(19)
(11)EP 2 663 980 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
11.03.2020 Bulletin 2020/11

(21)Application number: 12734635.1

(22)Date of filing:  12.01.2012
(51)International Patent Classification (IPC): 
G11C 16/34(2006.01)
G11C 11/56(2006.01)
G11C 16/26(2006.01)
G11C 16/04(2006.01)
G11C 16/28(2006.01)
(86)International application number:
PCT/US2012/021054
(87)International publication number:
WO 2012/097136 (19.07.2012 Gazette  2012/29)

(54)

METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES

VERFAHREN, VORRICHTUNGEN UND SYSTEME ZUR EINSTELLUNG DER SPANNUNGSERFASSUNG IN VORRICHTUNGEN

PROCÉDÉS, DISPOSITIFS, ET SYSTÈMES DE RÉGLAGE DE TENSIONS DE DÉTECTION DANS DES DISPOSITIFS


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 14.01.2011 US 201113007274

(43)Date of publication of application:
20.11.2013 Bulletin 2013/47

(73)Proprietor: Micron Technology, Inc.
Boise, ID 83716-9632 (US)

(72)Inventors:
  • RADKE, William, H.
    Los Gatos CA 95030 (US)
  • SHEN, Zhenlei
    Boise ID 83709 (US)
  • FEELEY, Peter
    Boise ID 83716 (US)

(74)Representative: Gill Jennings & Every LLP 
The Broadgate Tower 20 Primrose Street
London EC2A 2ES
London EC2A 2ES (GB)


(56)References cited: : 
US-A1- 2008 002 464
US-A1- 2008 192 541
US-A1- 2009 290 426
US-A1- 2010 165 730
US-A1- 2011 280 084
US-A1- 2008 144 388
US-A1- 2009 067 254
US-A1- 2009 310 404
US-A1- 2010 172 191
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    Technical Field



    [0001] The present disclosure relates generally to semiconductor memory devices, methods, and systems, and more particularly, to methods, devices, and systems for adjusting sensing voltages in devices.

    Background



    [0002] Memory devices are typically provided as internal, semiconductor, integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change random access memory (PCRAM), and flash memory, among others.

    [0003] Flash memory devices can be utilized as volatile and non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Uses for flash memory include memory for solid state drives (SSDs), personal computers, personal digital assistants (PDAs), digital cameras, cellular telephones, portable music players, e.g., MP3 players, and movie players, among other electronic devices. Data, such as program code, user data, and/or system data, such as a basic input/output system (BIOS), are typically stored in flash memory devices.

    [0004] Two common types of flash memory array architectures are the "NAND" and "NOR" architectures, so called for the logical form in which the basic memory cell configuration of each is arranged. A NAND array architecture arranges its array of memory cells in a matrix such that the control gates of each memory cell in a "row" of the array are coupled to (and in some cases form) an access line, which is commonly referred to in the art as a "word line". However each memory cell is not directly coupled to a data line (which is commonly referred to as a digit line, e.g., a bit line, in the art) by its drain. Instead, the memory cells of the array are coupled together in series.

    [0005] Memory cells in a NAND array architecture can be programmed to a target, e.g., desired, state. For example, electric charge can be placed on or removed from a charge storage structure of a memory cell to put the cell into one of a number of programmed states. For example, a single level cell (SLC) can represent two states, e.g., 1 or 0. Flash memory cells can also store more than two states, e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110. Such cells can be referred to as multilevel cells (MLCs). MLCs can allow the manufacture of higher density memories without increasing the number of memory cells since each cell can represent more than one digit, e.g., more than one bit. For example, a cell capable of representing four digits can have sixteen programmed states.

    [0006] Sensing operations, e.g., read and/or program verify operations, can use sensing voltages to determine the state of flash memory cells. However, a number of mechanisms, such as read disturb, program disturb, and/or charge loss, e.g., charge leakage, can cause the stored charge on the charge storage structure, e.g., the threshold voltage (Vt), of the memory cells, to change. As a result of the change in the stored charge, previously used sensing voltages, e.g., sensing voltages used prior to the change in the stored charge occurs, may no longer provide accurate and/or reliable sensing of the memory cells. That is, previously used sensing voltages may result in an erroneous sensing of the memory cells when used during subsequent sensing operations. For example, the use of previous sensing voltages may result in a determination that the memory cells are in a state other than the target state, e.g., a state different than the target state to which the cell was programmed.

    [0007] United States Patent Application Publication No. US 2010/172191 A1, to Chen et al., discloses a method for regulating a word line voltage corresponding to a set of memory cells. The method includes counting the amount of data in a set of data written to the memory cells that has a specific data value, and then counting the amount of data in a set of data read from the memory cells that also has the specific data value. A regulating adjustment to the word line voltage is then determined according to the difference between these two counted data amounts.

    [0008] United States Patent Application Publication No. US 2008/0002464 A1, to Maayan, discloses a method and system for determining a reference voltage. The method includes counting the number of memory cells in a set of memory cells that are to be programmed to each of one or more logical or program states, and then counting the number of memory cells in the set found to be at a given one of the logical or program states upon reading the set. The number of cells found to be at the given logical or program state during the reading is compared against the corresponding expected number from the programming, and that a read verify reference threshold value may be adjusted if there is a discrepancy in the comparison.

    [0009] United States Patent Application Publication No. US 2009/0310404 A1, to Cho et al., discloses an apparatus and method for controlling and optimizing a read level of a memory cell. The method includes counting a number of memory cells with a threshold voltage that is within a reference threshold voltage interval, comparing this number to a threshold value, and generating a new reference threshold voltage interval based on the result of the comparison.

    [0010] United States Patent Application Publication No.: US 2010/0165730 to Sommer et al., discloses a method of operating a memory device in which data stored in memory cells of the device are read by performing multiple read operations that compare output values of the memory cells to different read thresholds. Spacings between the different thresholds may be regular or irregular increments.

    Summary of the Invention



    [0011] The present invention provides memory devices and methods of operating the same as set out in the accompanying independent claims. The present invention is defined in the independent claims. Preferred aspects are defined in the dependent claims.

    Brief Description of the Drawings



    [0012] 

    Figure 1 is a schematic of a portion of a non-volatile memory array in accordance with one or more embodiments of the present disclosure.

    Figure 2 illustrates a diagram of a number of threshold voltage distributions and sensing voltages in accordance with one or more embodiments of the present disclosure.

    Figure 3 illustrates a diagram of a number of threshold voltage distributions and sensing voltages in accordance with one or more embodiments of the present disclosure.

    Figure 4 illustrates a diagram of a number of threshold voltage distributions and sensing voltages in accordance with one or more embodiments of the present disclosure.

    Figure 5 illustrates a block diagram of a memory device in accordance with one or more embodiments of the present disclosure.


    Detailed Description



    [0013] The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells.

    [0014] Embodiments of the present disclosure can be used to track and/or compensate for threshold voltage (Vt) change, e.g., shift, in memory devices and/or systems. Tracking and/or compensating for Vt changes can provide benefits such as increased accuracy and/or reliability, e.g., decreased error rate, and/or increased memory device and/or system life, among other benefits.

    [0015] In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how a number of embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure.

    [0016] As used herein, "a number of" something can refer to one or more such things. For example, a number of memory devices can refer to one or more memory devices.

    [0017] The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 100 may reference element "00" in Figure 1, and a similar element may be referenced as 400 in Figure 4. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate the embodiments of the present disclosure, and should not be taken in a limiting sense.

    [0018] Figure 1 is a schematic of a portion of a non-volatile memory array 100 in accordance with one or more embodiments of the present disclosure. The embodiment of Figure 1 illustrates a NAND architecture non-volatile memory array. However, embodiments described herein are not limited to this example. As shown in Figure 1, the memory array 100 includes access lines, e.g., word lines 105-1, ..., 105-N and intersecting data lines, e.g., local bit lines 107-1, 107-2, 107-3, ..., 107-M. For ease of addressing in the digital environment, the number of word lines 105-1, ..., 105-N and the number of local bit lines 107-1, 107-2, 107-3, ..., 107-M can be some power of two, e.g., 256 word lines by 4,096 bit lines.

    [0019] Memory array 100 includes NAND strings 109-1, 109-2, 109-3,. .., 109-M. Each NAND string includes non-volatile memory cells 111-1, ..., 111-N, each communicatively coupled to a respective word line 105-1, ..., 105-N. Each NAND string (and its constituent memory cells) is also associated with a local bit line 107-1, 107-2, 107-3, ..., 107-M. The non-volatile memory cells 111-1, ..., 111-N of each NAND string 109-1, 109-2, 109-3, ..., 109-M are connected in series source to drain between a source select gate (SGS), e.g., a field-effect transistor (FET) 113, and a drain select gate (SGD), e.g., FET 119.

    [0020] As shown in the embodiment illustrated in Figure 1, a source of source select gate 113 is connected to a common source line 123. The drain of source select gate 113 is connected to the source of the memory cell 111-1 of the corresponding NAND string 109-1. The drain of drain select gate 119 is connected to bit line 107-1 of the corresponding NAND string 109-1 at drain contact 121-1. The source of drain select gate 119 is connected to the drain of the last memory cell 111-N, e.g., a floating-gate transistor, of the corresponding NAND string 109-1.

    [0021] In one or more embodiments, construction of the non-volatile memory cells 111-1, ..., 111-N includes a source, a drain, a floating gate or other charge storage structure, and a control gate. The non-volatile memory cells 111-1, ..., 111-N have their control gates coupled to a word line, 105-1, .. ., 105-N respectively. A "column" of the non-volatile memory cells, 111-1, .. ., 111-N, make up the NAND strings 109-1, 109-2, 109-3, ..., 109-M, and are coupled to a given local bit line 107-1, 107-2, 107-3, ..., 107-M, respectively. A "row" of the non-volatile memory cells are those memory cells commonly coupled to a given word line 105-1, ..., 105-N. The use of the terms "column" and "row" is not meant to imply a particular linear, e.g., vertical and/or horizontal, orientation of the non-volatile memory cells. A NOR array architecture would be similarly laid out, except that the string of memory cells would be coupled in parallel between the select gates.

    [0022] As one of ordinary skill in the art will appreciate, subsets of cells coupled to a selected word line, e.g., 105-1, ..., 105-N, can be programmed and/or sensed, e.g., read, together as a group. A programming operation, e.g., a write operation, can include applying a number of program pulses, e.g., 16V-20V, to a selected word line in order to increase the threshold voltage (Vt) of selected cells coupled to that selected access line to a desired program voltage level corresponding to a target program state.

    [0023] A sensing operation, such as a read or program verify operation, can include sensing a voltage and/or current change of a bit line.

    [0024] Sensing the state of a selected cell can include providing a number of sensing voltages, e.g., read voltages, to a selected word line while providing a number of voltages, e.g., read pass voltages, to the word lines coupled to the unselected cells of the string sufficient to place the unselected cells in a conducting state independent of the threshold voltage of the unselected cells. The bit line corresponding to the selected cell being read and/or verified can be sensed to determine whether or not the selected cell conducts in response to the particular sensing voltage applied to the selected word line. For example, the state of a selected cell can be determined by the word line voltage at which the bit line current reaches a particular reference current associated with a particular state.

    [0025] As one of ordinary skill in the art will appreciate, in a sensing operation performed on a selected memory cell in a NAND string, the unselected memory cells of the string are biased so as to be in a conducting state. In such a sensing operation, the state of the selected cell can be determined based on the current and/or voltage sensed on the bit line corresponding to the string. For instance, the state of the selected cell can be determined based on whether the bit line current changes by a particular amount or reaches a particular level in a given time period.

    [0026] When the selected cell is in a conductive state, current flows between the source line contact at one end of the string and a bit line contact at the other end of the string. As such, the current associated with sensing the selected cell is carried through each of the other cells in the string, the diffused regions between cell stacks, and the select transistors.

    [0027] Figure 2 illustrates a diagram 201 of a number of threshold voltage distributions and sensing voltages in accordance with one or more embodiments of the present disclosure. The example shown in Figure 2 can represent, for example, memory cells 111-1, ..., 111-N.

    [0028] As shown in Figure 2, threshold voltage (Vt) distributions 225-0, 225-1, 225-2, and 225-3 represent four target states, e.g., L0, LI, L2, and L3, respectively, to which the memory cells can be programmed. In the example illustrated in Figure 2, Vt distribution 225-3 can be referred to as a maximum Vt, e.g., "Vtmax", to which a cell can be programmed because it is the range including the Vt with the largest magnitude. In operation, the memory cells in a selected block can be erased together such that they have a Vt level within Vt distribution 225-0 prior to being programmed. As such, distribution 225-0 can be referred to as an erased state and can represent a particular stored data state (target state L0), e.g., stored data such as binary "11". Target state LI can correspond to data 01, target state L2 can correspond to data 00, and target state L3 can correspond to data 10. However, embodiments are not limited to these data assignments.

    [0029] Vt distributions 225-0, 225-1, 225-2, and 225-3 can represent a number of memory cells that are programmed to the corresponding target states, where the height of a Vt distribution curve indicates a number of cells programmed to a particular voltage within the Vt distribution, on average. The width 227 of the Vt distribution curve indicates the range of voltages that represent a particular target state, e.g., the width of the Vt distribution curve 225-2 for L2 represents the range of voltages that correspond to data 00.

    [0030] A number of sensing voltages are illustrated in Figure 2. Such sensing voltages can include program verify voltages and/or read voltages, among other sensing voltages. For example, program verify voltages PV1, PV2, and PV3 are illustrated, as well as read voltages R1, R2, and R3. A program verify operation can be performed after one or more programming pulses to help determine whether a memory cell has been programmed within a desired Vt range to help prevent the memory cell from receiving further programming pulses, e.g., "over programming" the cell. For instance, memory cells to be programmed to the LI target state can be program verified with a voltage PV1.

    [0031] In the example illustrated in Figure 2, voltage levels R1, R2, and R3 represent sensing voltages, e.g., read voltages, that can be used to distinguish between states L0, L1, L2, and L3 during a sensing operation. In a sensing operation performed on a selected memory cell in a NAND string, the unselected memory cells of the string can be biased with a pass voltage "Vpass" 229 so as to be in a conducting state.

    [0032] The Vt of a memory cell can change, e.g., shift, over time due to a number of mechanisms. For example, the charge storage structure, e.g., floating gate, of the memory cell may lose charge over time. Such charge loss can cause the Vt of the cell to change, e.g., decrease. Additionally, as the memory cell undergoes programming and/or sensing operations over time, program disturb and/or read disturb mechanisms may cause the Vt of the cell to change, e.g., increase. Other mechanisms can also cause the Vt of the memory cell to change over time, as will be appreciated by one of ordinary skill in the art.

    [0033] In some instances, such a Vt change can alter the state of the memory cell. For example, if the memory cell were programmed to target state L2, e.g., data 00, charge loss could cause the Vt of the memory cell to decrease to a level less than R2, or possibly to a level within Vt 225-1 corresponding to state L1, e.g., data 01.

    [0034] Accordingly, such a Vt change can result in erroneous data being sensed during a sensing operation performed on the memory cell using the sensing voltages illustrated in Figure 2, e.g., read voltages R1, R2 and R3, and/or program verify voltages PV1, PV2, and PV3. For example, performing a sensing operation using the sensing voltages illustrated in Figure 2 may result in a determination that the memory cell represents a state other than the target state to which the cell was programmed. For instance, a sensing operation performed on a memory cell that was programmed to target state L2 and has undergone charge loss may determine that the cell represents state L1, if read voltage R2 is used in the sensing operation. That is, using read voltage R2 may result in a cell programmed to store data 00 being erroneously sensed as storing data 01.

    [0035] Figure 3 illustrates a diagram 301 of threshold voltage (Vt) distributions 325-1 and 325-2, and sensing voltages SO (327-0), S1 (327-1), S2 (327-2), S3 (327-3), and S4 (327-4), in accordance with one or more embodiments of the present disclosure. The example shown in Figure 3 can represent memory cells that have undergone a Vt change, e.g., shift, due to a mechanism such as charge loss, program disturb, and/or read disturb, for example. Vt distributions 325-1 and 325-2 can correspond to Vt distributions 225-1 and 225-2, respectively, previously described in connection with Figure 2, after the memory cells represented by Vt distributions 225-1 and 225-2 have undergone a Vt change. Further, although not shown in Figure 3 for simplicity, diagram 301 could also include additional Vt distributions corresponding to Vt distributions 225-0 and/or 225-3 previously described in connection with Figure 2 after the memory cells represented by Vt distributions 225-0 and/or 225-3 have undergone a Vt change.

    [0036] As shown in Figure 3, Vt distributions 325-1 and 325-2 have shifted relative to Vt distributions 225-1 and 225-2 shown in Figure 2, e.g., due to the Vt shifts of the memory cells represented therein. For example, portions of Vt distributions 325-1 and 325-2 overlap, as shown in Figure 3. Accordingly, sensing voltages used to determine the state of the memory cells before the Vt change occurred, e.g., the sensing voltages illustrated in Figure 2, may no longer provide accurate and/or reliable sensing of the memory cells, as previously described herein. For instance, a memory cell programmed to target state L2 may be sensed as being in state L1.

    [0037] However, adjusting the sensing voltages used to determine the state of the memory cells to different sensing voltages, e.g., to sensing voltages other than those illustrated in Figure 2, can be used to track and/or compensate for the Vt change, thereby providing accurate and/or reliable sensing.

    [0038] The sensing voltage(s) that will provide accurate and/or reliable sensing of the memory cells, e.g., the sensing voltage(s) that will sense the least amount of erroneous data, can be determined based, at least partially, on the quantity of memory cells having a Vt greater than the sensing voltage(s). That is, the adjustment of the sensing voltage used to determine the state of the memory cells can be based, at least partially, on the quantity of memory cells having a Vt greater than the sensing voltage.

    [0039] For instance, a number of sense operations, e.g., five, can be performed on the memory cells using a number of different sensing voltages, e.g., sensing voltages S0, S1, S2, S3, and/or S4, to determine a quantity of the memory cells having a Vt greater than each sensing voltage. The sensing voltage used to determine the state of the memory cells, e.g., read voltage R2 previously described in connection with Figure 2, can then be adjusted based, at least partially, on the determined quantities of memory cells.

    [0040] As an example, a sense operation performed on the memory cells using sensing voltage SO may determine that 7,000 cells have a Vt greater than sensing voltage S0, a sense operation performed on the memory cells using sensing voltage S1 may determine that 7,200 cells have a Vt greater than sensing voltage S1, sense operation performed using sensing voltage S2 may determine that 7,300 cells have a Vt greater than sensing voltage S2, a sense operation performed using sensing voltage S3 may determine that 7,400 cells have a Vt greater than sensing voltage S3, and a sense operation performed using sensing voltage S4 may determine that 7,600 cells have a Vt greater than sensing voltage S4.

    [0041] The sensing voltage used to determine the state of the memory cells can then be adjusted based, at least partially, on the determined quantities of memory cells having a Vt greater than each sensing voltage. For instance, differences between the determined quantities of memory cells having a Vt greater than each sensing voltage can be determined. As an example, the difference between the quantity of memory cells having a Vt greater than sensing voltage S1 and the quantity of memory cells having a Vt greater than sensing voltage S0 can be determined, the difference between the quantity of memory cells having a Vt greater than sensing voltage S2 and the quantity of memory cells having a Vt greater than sensing voltage S1 can be determined, the difference between the quantity of memory cells having a Vt greater than sensing voltage S3 and the quantity of memory cells having a Vt greater than sensing voltage S2 can be determined, and/or the difference between the quantity of memory cells having a Vt greater than sensing voltage S4 and the quantity of memory cells having a Vt greater than sensing voltage S3 can be determined. In this example, these differences are 200, 100, 100, and 200, respectively. The sensing voltage used to determine the state of the memory cells can then be adjusted based, at least partially, on the determined differences.

    [0042] For instance, a trend associated with the determined differences can be determined, and the sensing voltage used to determine the state of the memory cells can then be adjusted based, at least partially, on the trend.

    [0043] The sensing voltage used to determine the state of the memory cells can then be adjusted based, at least partially, on the point at which the minimal determined difference is crossed. That is, the sensing voltage used to determine the state of the memory cells can then be adjusted based, at least partially, on the determined minimum difference. For instance, the sensing voltage used to determine the state of the memory cells can be adjusted to a voltage between the sensing voltages between which the minimal determined difference is crossed. That is, the sensing voltage used to determine the state of the memory cells can be adjusted to a voltage between the sensing voltages associated with the determined minimum difference. In the previous example, the sensing voltage used to determine the state of the memory cells can be adjusted to a voltage between sensing voltages S1 and S3, e.g., sensing voltage S2.

    [0044] As an additional example, a first sense operation can be performed on the memory cells using a first sensing voltage, e.g., sensing voltage S0, to determine a first quantity of the memory cells having a Vt greater than the first sensing voltage. A second sense operation can also be performed on the memory cells using a second sensing voltage, e.g., sensing voltage S1, that is less than the first sensing voltage to determine a second quantity of the memory cells having a Vt greater than the second sensing voltage. A third sense operation can also be performed on the memory cells using a third sensing voltage, e.g., sensing voltage S2, that is less than the second sensing voltage to determine a third quantity of the memory cells having a Vt greater than the third sensing voltage.

    [0045] The difference between the third and second quantities of memory cells and the difference between the second and first quantities of memory cells can then be determined and compared.

    [0046] If the difference between the third and second quantities of memory cells is greater than the difference between the second and first quantities of memory cells, a fourth sense operation can be performed on the memory cells using a fourth sensing voltage that is greater than the first sensing voltage to determine a fourth quantity of memory cells having a Vt greater than the fourth sensing voltage. The difference between the first and fourth quantities of memory cells can then be determined and compared to the difference between the second and first quantities of memory cells. If the difference between the first and fourth quantities of memory cells is equal to the difference between the second and first quantities of memory cells, the sensing voltage used to determine a state of the memory cells, e.g., read voltage R2, can be adjusted to the first sensing voltage, e.g., from read voltage R2 to sensing voltage S0.

    [0047] If the difference between the first and fourth quantities of memory cells is greater than the difference between the second and first quantities of memory cells, the sensing voltage used to determine a state of the memory cells can be adjusted to a voltage between the first and second sensing voltages. As an example, one or more additional sensing operations can be performed to determine the adjusted voltage between the first and second sensing voltages, e.g., to further precision the adjusted voltage between the first and second sensing voltages. For instance, a fifth sense operation can be performed on the memory cells using a sensing voltage, e.g., a fifth sensing voltage, that is halfway between the first and second sensing voltages to determine a fifth quantity of memory cells having a Vt greater than the fifth sensing voltage. The difference between the second and fifth quantities of memory cells and the difference between the fifth and first quantities of memory cells can then be determined and compared. If the difference between the second and fifth quantities of memory cells is greater than the difference between the fifth and first quantities of memory cells, the sensing voltage used to determine a state of the memory cells can be adjusted .

    [0048] If the difference between the first and fourth quantities of memory cells is less than the difference between the second and first quantities of memory cells, a sixth sense operation can be performed on the memory cells using a sixth sensing voltage that is greater than the fourth sensing voltage to determine a sixth quantity of memory cells having a Vt greater than the sixth sensing voltage. The difference between the fourth and sixth quantities of memory cells can then be determined and compared to the difference between the first and fourth quantities of memory cells, and the sensing voltage used to determine a state of the memory cells can be adjusted, in a manner analogous to that previously described herein.

    [0049] If the difference between the third and second quantities of memory cells is less than the difference between the second and first quantities of memory cells, a fourth sense operation can be performed on the memory cells using a fourth sensing voltage, e.g., sensing voltage S3, that is less than the third sensing voltage to determine a fourth quantity of memory cells having a Vt greater than the fourth sensing voltage. The difference between the fourth and third quantities of memory cells can then be determined and compared to the difference between the third and second quantities of memory cells.

    [0050] If the difference between the fourth and third quantities of memory cells is greater than the difference between the third and second quantities of memory cells, the sensing voltage used to determine a state of the memory cells, e.g., read voltage R2, can be adjusted to a voltage between the second and third sensing voltages. As an example, one or more additional sensing operations can be performed using one or more additional sensing voltages, e.g., a sensing voltage that is halfway between the second and third sensing voltages, to determine the adjusted voltage between the second and third sensing voltages, e.g., to further precision the adjusted voltage between the second and third sensing voltages, in a manner analogous to that previously described herein.

    [0051] If the difference between the fourth and third quantities of memory cells is less than the difference between the third and second quantities of memory cells, a fifth sense operation can be performed on the memory cells using a fifth sensing voltage, e.g., sensing voltage S4, that is less than the fourth sensing voltage to determine a fifth quantity of memory cells having a Vt greater than the fifth sensing voltage. The difference between the fifth and fourth quantities of memory cells can then be determined and compared to the difference between the fourth and third quantities of memory cells, and the sensing voltage used to determine a state of the memory cells can be adjusted, in a manner analogous to that previously described herein.

    [0052] Figure 4 illustrates a diagram 401 of threshold voltage (Vt) distributions 425-1 and 425-2, and sensing voltages S0 (457-0), S1 (457-1), and S2 (457-2) in accordance with one or more embodiments of the present disclosure. The example shown in Figure 4 can represent memory cells that have undergone a Vt change, e.g., shift, due to a mechanism such as charge loss, program disturb, and/or read disturb, for example, in a manner analogous to that previously described in connection with Figure 3. That is, Vt distributions 425-1 and 425-2 can correspond to Vt distributions 225-1 and 225-2, respectively, previously described in connection with Figure 2, after the memory cells represented by Vt distributions 225-1 and 225-2 have undergone a Vt change.

    [0053] However, adjusting the sensing voltages used to determine the state of the memory cells to different sensing voltages, e.g., to sensing voltages other than those illustrated in Figure 2, can be used to track and/or compensate for the Vt change, thereby providing accurate and/or reliable sensing of the memory cells, as previously described herein. The sensing voltage(s) that will provide accurate and/or reliable sensing of the memory cells, e.g., the sensing voltage(s) that will sense the least amount of erroneous data, can be determined based, at least partially, on the quantity of memory cells having a Vt greater than the sensing voltage(s). That is, the adjustment of the sensing voltage used to determine the state of the memory cells can be based, at least partially, on the quantity of memory cells having a Vt greater than the sensing voltage.

    [0054] For instance, a number of sense operations, e.g., three, can be performed on the memory cells using a number of different sensing voltages, e.g., sensing voltages S0, S1, and/or S2, to determine a quantity of the memory cells having a Vt greater than each sensing voltage. The sensing voltage used to determine the state of the memory cells, e.g., read voltage R2 previously described in connection with Figure 2, can then be adjusted based, at least partially, on the determined quantities of memory cells.

    [0055] As an example, a sense operation performed on the memory cells using sensing voltage S0 may determine that 7,000 cells have a Vt greater than sensing voltage S0, a sense operation performed on the memory cells using sensing voltage S1 may determine that 7,400 cells have a Vt greater than sensing voltage S1, and a sense operation performed on the memory cells using sensing voltage S2 may determine that 7,300 cells have a Vt greater than sensing voltage S2.

    [0056] A determined quantity of memory cells having a Vt greater than a sensing voltage can include, for example, all memory cells having a Vt located to the right of the sensing voltage, e.g., all memory cells in diagram 401 whose Vt level is located to the right of the sensing voltage.

    [0057] The sensing voltage used to determine the state of the memory cells can be adjusted based, at least partially, on the determined quantities of memory cells. For instance, the determined quantities of memory cells can each be compared to a stored value. The stored value can correspond to a quantity of the memory cells programmed to a Vt within a defined Vt region. The defined Vt region can be, for example, a Vt distribution corresponding to a programmed state of the memory cells, e.g., Vt distributions 225-2 and/or 225-3 previously described in connection with Figure 2, a portion of a Vt distribution corresponding to a programmed state of the memory cells, or multiple Vt distributions corresponding to multiple programmed states of the memory cells. As an example, the stored value may be 7,315, e.g., 7,315 cells may have been programmed to a Vt within either Vt distributions 225-2 or Vt distribution 225-3 previously described in connection with Figure 2.

    [0058] The sensing voltage used to determine the state of the memory cells can then be adjusted based, at least partially, on the comparison. For instance, if a determined quantity of memory cells is within a particular range of the stored value, the sensing voltage used to determine the state of the memory cells can be adjusted to the sensing voltage used to perform the sensing operation that determined the quantity of memory cells that is within the particular range of the stored value. The particular range of the stored value can be, for example, a range associated with a passage of an error correction operation, e.g., a subsequent error correction operation to be performed on data subsequently sensed using the adjusted sensing voltage. That is, the particular range of the stored value can correspond to a quantity of bits, e.g., 60,

    [0059] In the previous example, the determined quantity of memory cells having a Vt greater than S0, e.g., 7,000, and the determined quantity of memory cells having a Vt greater than S1, e.g., 7,400, are not within the particular range, e.g., 60, of the stored value, e.g., 7,315. However, the determined quantity of memory cells having a Vt greater than S2, e.g., 7,300, is within the particular range of the stored value. Accordingly, the sensing voltage used to determine the state of the memory cells can be adjusted to sensing voltage S2.

    [0060] As an additional example, a first sense operation can be performed on the memory cells using a first sensing voltage, e.g., sensing voltage S0, to determine a first quantity of the memory cells having a Vt greater than the first sensing voltage. The first quantity of memory cells can then be compared to a stored value. The stored value can correspond to a quantity of the memory cells programmed to a Vt within a defined Vt region, as previously described herein.

    [0061] If the first quantity of memory cells is within a particular range of the stored value, the sensing voltage used to determine a state of the memory cells can be adjusted to the first sensing voltage. The particular range of the stored value can be, for example, a range associated with a passage of an error correction operation, as previously described herein.

    [0062] If the first quantity of memory cells is not within the particular range of the stored value, a second sense operation can be performed on the memory cells using a second sensing voltage, e.g., sensing voltage S1, to determine a second quantity of the memory cells having a Vt greater than the second sensing voltage. The second sensing voltage can be greater than the first sensing voltage if the first quantity of memory cells is greater than the stored value, and the second sensing voltage can be less than the first sensing voltage if the first quantity of memory cells is less than the stored value. Additionally, the voltage amount by which the second sensing voltage is spaced apart from the first sensing voltage can be based, at least partially, on the amount by which the first quantity of memory cells is outside the particular range of the stored value.

    [0063] The second quantity of memory cells can then be compared to the stored value. If the second quantity of memory cells is within the particular range of the stored value, the sensing voltage used to determine a state of the memory cells can be adjusted to the second sensing voltage. If the second quantity of memory cells is not within the particular range of the stored value, this process can be repeated using one or more additional sensing voltages, e.g., sensing voltage S3.

    [0064] Figure 5 illustrates a block diagram of a memory device 503 in accordance with one or more embodiments of the present disclosure. As shown in Figure 5, memory device 503 includes a memory array 500 and a controller 562 coupled to memory array 500. Memory array 500 can optionally include a counter 564, as shown in Figure 5. Counter 564 can be located at, for example, an end of one or more word lines in memory array 500.

    [0065] Memory array 500 can be, for example, memory array 100 previously described in connection with Figure 1. Although one memory array is shown in Figure 5, embodiments of the present disclosure are not so limited, e.g., memory device 503 can include more than one memory array coupled to controller 562. Controller 562 can include, for example, control circuitry and/or firmware, and can be included on the same physical device, e.g., the same die, as memory array 500, or can be included on a separate physical device that is communicatively coupled to the physical device that includes memory array 500.

    [0066] Controller 562 can track and/or compensate for a threshold voltage (Vt) change, e.g., shift, in the memory cells in memory array 500 by adjusting a sensing voltage, e.g., a read voltage, used to determine a state of the memory cells. The adjustment of the sensing voltage used to determine the state of the memory cells can be based, at least partially, on the quantity of memory cells having a Vt greater than a number of sensing voltages, as previously described herein.

    [0067] For example, controller 562 can perform a number of sense operations on a number of the memory cells in memory array 500 using a number of different sensing voltages to determine a quantity of the memory cells having a Vt greater than each respective sensing voltage.

    [0068] Controller 562 can then adjust a sensing voltage used to determine the state of the memory cells based, at least partially, on the determined quantities of memory cells, in a manner analogous to that previously described in connection with Figures 3 and/or 4. For example, controller 562 can determine differences between the determined quantities of memory cells, and adjust the sensing voltage used to determine the state of the memory cells based, at least partially, on the determined differences. Additionally and/or alternatively, controller 562 can compare the determined quantities of memory cells to a stored value, and adjust the sensing voltage used to determine the state of the memory cells based, at least partially, on the comparison.

    [0069] The stored value can correspond to a quantity of the memory cells programmed to a Vt within a defined Vt region, as previously described in connection with Figure 4. The quantity of memory cells programmed to the Vt within the defined Vt region can be determined by counter 564 located in memory array 500. For example, counter 564 can count the quantity of memory cells programmed to a Vt within the defined Vt region as the cells are being programmed. Additionally, the stored value can be stored in memory array 500. That is, one or more memory cells in memory array 500 can store data corresponding to the quantity of memory cells programmed to a Vt within the defined Vt region.

    [0070] Controller 562 can determine a state of a number of the memory cells in memory array 500 using the adjusted sensing voltage. For example, controller 562 can perform a sense operation on the memory cells using the adjusted sensing voltage to sense the state of the memory cells.

    [0071] Controller 562 can perform, e.g., automatically, the number of sense operations to determine the quantity of the memory cells having a Vt greater than each sensing voltage in response to a failure of an error correction operation performed on data associated with a determined, e.g., sensed, state of the memory cells. The failure of the error correction operation may be caused by, for example, a Vt shift of the memory cells, as previously described herein.

    [0072] The embodiment illustrated in Figure 5 can include additional circuitry that is not illustrated so as not to obscure embodiments of the present disclosure. For example, memory device 503 can include address circuitry to latch address signals provided over I/O connectors through I/O circuitry. Address signals can be received and decoded by a row decoder and a column decoder, to access memory array 500. It will be appreciated by those skilled in the art that the number of address input connectors can depend on the density and architecture of memory device 503 and/or memory array 500.

    Conclusion



    [0073] The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells.

    [0074] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of a number of embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of ordinary skill in the art upon reviewing the above description. The scope of a number of embodiments of the present disclosure includes other applications in which the above structures and methods are used.

    [0075] In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. The following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.


    Claims

    1. A memory device (503), comprising:

    memory cells (111-1, ..., 111-N); and

    a controller (562) configured to:

    perform a number of sense operations on the memory cells (111-1, ..., 111-N), wherein each sense operation is performed using a different sensing voltage (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2)

    determine, for each of the different sensing voltages (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2), a quantity of the memory cells (111-1, ..., 111-N) having a threshold voltage (Vt) greater than the respective sensing voltage (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2);

    determine differences between the determined quantities of memory cells (111-1, ..., 111-1);

    determine a trend associated with the determined differences; and

    adjust a sensing voltage used to determine a state of the memory cells (111-1, ..., 111-N) based, at least partially, on the determined trend.


     
    2. The memory device (503) of claim 1, wherein the controller (562) is configured to:

    compare the determined quantities of memory cells (111-1, ..., 111-N) to a stored value; and

    adjust the sensing voltage used to determine the state of the memory cells (111-1, ..., 111-N) based, at least partially, on the comparison.


     
    3. The memory device (503) of claim 2, wherein the stored value corresponds to a quantity of the number of memory cells (111-1, ..., 111-N) programmed to a Vt within a defined Vt region (225-1, 225-2).
     
    4. The memory device (503) of claim 2, wherein the stored value is stored in the memory cells (111-1, ..., 111-N).
     
    5. The memory device (503) of any one of claims 1-4, wherein the controller (562) is configured to perform the number of sense operations on the memory cells (111-1, ..., 111-N) in response to a failure of an error correction operation.
     
    6. A method of operating a memory device (503), comprising:

    performing a number of sense operations on a number of memory cells (111-1, .. ., 111-N) of the memory device, wherein each sense operation is performed using a different sensing voltage (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2);

    determining, for each of the different sensing voltages (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2), a quantity of the memory cells (111-1, ..., 111-N) having a threshold voltage (Vt) greater than the respective sensing voltage (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2);

    determining differences between the determined quantities of memory cells (111-, ..., 111-1);

    determining a trend associated with the determined differences; and

    adjusting a sensing voltage used to determine a state of the memory cells (111-1, ..., 111-N) based, at least partially, on the determined trend.


     
    7. A memory device (503), comprising:

    memory cells (111-1, ..., 111-N); and

    a controller (562) configured to:

    perform a number of sense operations on a number of the memory cells (111-1, ..., 111-N), wherein each sense operation is performed using a different sensing voltage (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2);

    determine, for each of the different sensing voltages (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2), a quantity of the number of the memory cells (111-1, ..., 111-N) having a threshold voltage (Vt) greater than the respective sensing voltage (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2);

    determine differences between the determined quantities of the memory cells (111-1, ..., 111-N);

    determine a minimum difference of the determined differences; and

    adjust a sensing voltage used to determine a state of the memory cells (111-1, ..., 111-N) based, at least partially, on the determined minimum difference.


     
    8. A method of operating a device (503), comprising:

    performing a number of sense operations on a number of memory cells (111-1, .. ., 111-N), wherein each sense operation is performed using a different sensing voltage (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2);

    determining, for each of the different sensing voltages (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2), a quantity of the number of memory cells (111-1, ..., 111-N) having a threshold voltage (Vt) greater than the respective sensing voltage (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2);

    determining differences between the determined quantities of memory cells (111-1, ..., 111-N);

    determining a minimum difference of the determined differences; and

    adjusting a sensing voltage used to determine a state of the number of memory cells (111-1, ..., 111-N) based, at least partially, on the determined minimum difference.


     
    9. The method of claim 8, wherein the method includes:

    comparing the determined quantities of memory cells (111-1, ..., 111-N); and

    adjusting the sensing voltage used to determine the state of the number of memory cells (111-1, ..., 111-N) based, at least partially, on the comparison.


     
    10. The method of either one of claims 8 & 9, wherein each sensing voltage (327-0, 327-1, 327-2, 327-3, 327-4) is spaced apart by a particular voltage amount.
     
    11. The method of either one of claims 8 & 9, wherein each sensing voltage (457-0, 457-1, 457-2) is spaced apart by a different voltage amount.
     
    12. The method of either one of claims 8 & 9, wherein the method includes determining the quantity of the number of memory cells (111-1, ..., 111-N) having a Vt greater than the respective sensing voltage (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2) used in the respective sense operation after each sense operation.
     


    Ansprüche

    1. Speichervorrichtung (503), Folgendes umfassend:

    Speicherzellen (111-1, ..., 111-N); und

    eine Steuerung (562), die für folgende Aufgaben konfiguriert ist:

    Durchführen einer Reihe von Abtastvorgängen an den Speicherzellen (111-1, ..., 111-N), wobei jeder Abtastvorgang mit einer anderen Abtastspannung durchgeführt wird (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2);

    Bestimmen für jede der verschiedenen Abtastspannungen (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2) eine Menge der Speicherzellen (111-1, ..., 111-N) mit einer Schwellenspannung (Vt), die größer ist als die jeweilige Abtastspannung (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2);

    Bestimmen der Unterschiede zwischen den ermittelten Mengen von Speicherzellen (111-1, ..., 111-1);

    Bestimmen einer Tendenz, die mit den ermittelten Unterschieden in Zusammenhang steht; und

    Anpassen einer Abtastspannung, die zur Bestimmung eines Status der Speicherzellen (111-1, ..., 111-N) verwendet wird, zumindest teilweise auf der Grundlage der festgestellten Tendenz.


     
    2. Die Speichervorrichtung (503) nach Anspruch 1, in der die Steuerung (562) für folgende Aufgaben konfiguriert ist:

    Vergleichen der bestimmten Mengen von Speicherzellen (111-1, ..., 111-N) mit einem gespeicherten Wert; und

    Anpassen der Abtastspannung, die zum Bestimmen des Status der Speicherzellen (111-1, ..., 111-N) verwendet wird, zumindest teilweise basierend auf dem Vergleich.


     
    3. Speichervorrichtung (503) nach Anspruch 2, wobei der gespeicherte Wert einer Menge der Anzahl von Speicherzellen (111-1, ..., 111-N) entspricht, die mit einer Vt innerhalb eines definierten Vt-Bereichs (225-1, 225-2) programmiert sind.
     
    4. Speichervorrichtung (503) nach Anspruch 2, wobei der gespeicherte Wert in den Speicherzellen (111-1, ..., 111-N) gespeichert wird.
     
    5. Speichervorrichtung (503) nach einem der Ansprüche 1-4, wobei die Steuerung (562) dafür konfiguriert ist, die Anzahl der Abtastvorgänge an den Speicherzellen (111-1, ..., 111-N) als Reaktion auf einen Ausfall einer Fehlerkorrekturvorgangs durchzuführen.
     
    6. Verfahren zum Betreiben einer Speichervorrichtung (503), Folgendes umfassend:

    Durchführen einer Anzahl von Abtastvorgängen an einer Anzahl von Speicherzellen (111-1, ..., 111-N) der Speichervorrichtung, wobei jeder Abtastvorgang unter Verwendung einer anderen Abtastspannung (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2) durchgeführt wird;

    Bestimmen, für jede der verschiedenen Abtastspannungen (327-0, 327-1, 327-2, 327- 3, 327-4, 457-0, 457-1, 457-2), einer Menge der Speicherzellen (111-1, ..., 111-N) mit einer Schwellenspannung (Vt), die größer ist als die jeweilige Abtastspannung (327-0, 327-1, 327- 2, 327-3, 327-4, 457-0, 457-1, 457-2);

    Bestimmen der Unterschiede zwischen den ermittelten Mengen von Speicherzellen (111-, ..., 111-1);

    Bestimmen einer Tendenz, die mit den ermittelten Unterschieden in Zusammenhang steht; und Anpassen einer Abtastspannung, die zur Bestimmung eines Status der Speicherzellen (111-1, ..., 111-N) verwendet wird, zumindest teilweise auf der Grundlage der festgestellten Tendenz.


     
    7. Speichervorrichtung (503), Folgendes umfassend:

    Speicherzellen (111-1, ..., 111-N); und

    eine Steuerung (562), die für folgende Aufgaben konfiguriert ist:

    Durchführen einer Anzahl von Abtastvorgängen an einer Anzahl der Speicherzellen (111-1, ..., 111-N), wobei jeder Abtastvorgang mit einer anderen Abtastspannung durchgeführt wird (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2);

    Bestimmen für jede der verschiedenen Abtastspannungen (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2) eine Menge der Anzahl der Speicherzellen (111-1, ..., 111-N) mit einer Schwellenspannung (Vt), die größer ist als die jeweilige Abtastspannung (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2);

    Bestimmen der Unterschiede zwischen den ermittelten Mengen der Speicherzellen (111-1, .., 111-N);

    Bestimmen eines Mindestunterschieds der ermittelten Unterschiede; und

    Anpassen einer Abtastspannung, die zur Bestimmung eines Status der Speicherzellen (111-1, ..., 111-N) verwendet wird, zumindest teilweise auf der Grundlage der ermittelten Mindestdifferenz.


     
    8. Verfahren zum Betreiben einer Vorrichtung (503), Folgendes umfassend:

    Durchführen einer Anzahl von Abtastvorgängen an einer Anzahl von Speicherzellen (111-1, ..., 111-N), wobei jeder Abtastvorgang mit einer anderen Abtastspannung durchgeführt wird (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2);

    Bestimmen, für jede der verschiedenen Abtastspannungen (327-0, 327-1, 327-2, 327- 3, 327-4, 457-0, 457-1, 457-2), einer Menge der Anzahl von Speicherzellen (111-1, ..., 111-N) mit einer Schwellenspannung (Vt), die größer ist als die jeweilige Abtastspannung (327- 0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2);

    Bestimmen der Unterschiede zwischen den ermittelten Mengen von Speicherzellen (111-1, ..., 111-N);

    Bestimmen eines Mindestunterschieds der ermittelten Unterschiede; und

    Anpassen einer Abtastspannung, die zur Bestimmung eines Status der Anzahl der Speicherzellen (111-1, ..., 111-N) verwendet wird, zumindest teilweise auf der Grundlage des ermittelten Mindestunterschieds.


     
    9. Verfahren nach Anspruch 8, das Verfahren Folgendes umfassend:

    Vergleichen der bestimmten Mengen von Speicherzellen (111-1, ..., 111-N); und

    Anpassen der Abtastspannung, die zur Bestimmung des Status der Anzahl von Speicherzellen (111-1, ..., 111-N) verwendet wird, zumindest teilweise auf der Grundlage des Vergleichs.


     
    10. Verfahren nach einem der Ansprüche 8 und 9, wobei jede Abtastspannung (327-0, 327-1, 327-2, 327-3, 327-4) um einen bestimmten Spannungsbetrag beabstandet ist.
     
    11. Verfahren nach einem der Ansprüche 8 und 9, wobei jede Abtastspannung (457-0, 457-1, 457-2) um einen unterschiedlichen Spannungsbetrag beabstandet ist.
     
    12. Verfahren nach einem der Ansprüche 8 und 9, wobei das Verfahren das Bestimmen der Menge der Anzahl von Speicherzellen (111-1, ..., 111-N) umfasst, deren Vt größer ist als die jeweilige Abtastspannung (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2), die in dem jeweiligen Abtastvorgang nach jedem Abtastvorgang verwendet wird.
     


    Revendications

    1. Dispositif de mémoire (503), comprenant :

    des cellules de mémoire (111-1, ..., 111-N) ; et

    un dispositif de commande (562) configuré pour :

    réaliser un certain nombre d'opérations de détection sur les cellules de mémoire (111-1, ..., 111-N), chaque opération de détection étant réalisée à l'aide d'une tension de détection différente (327-0, 327-1, 327-2, 327- 3, 327-4, 457-0, 457-1, 457-2) ;

    déterminer, pour chacune des différentes tensions de détection (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2), une quantité des cellules de mémoire (111-1, ..., 111-N) ayant une tension de seuil (Vt) supérieure à la tension de détection respective (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2) ;

    déterminer des différences entre les quantités déterminées de cellules de mémoire (111-1, ..., 111-1) ;

    déterminer une tendance associée aux différences déterminées ; et

    régler une tension de détection utilisée pour déterminer un état des cellules de mémoire (111-1, ..., 111-N) sur la base, au moins partiellement, de la tendance déterminée.


     
    2. Dispositif de mémoire (503) selon la revendication 1, dans lequel le dispositif de commande (562) est configuré pour :

    comparer les quantités déterminées de cellules de mémoire (111-1, ..., 111-N) à une valeur stockée ; et

    régler la tension de détection utilisée pour déterminer l'état des cellules de mémoire (111-1, ..., 111-N) sur la base, au moins partiellement, de la comparaison.


     
    3. Dispositif de mémoire (503) selon la revendication 2, dans lequel la valeur stockée correspond à une quantité du nombre de cellules de mémoire (111-1, ..., 111-N) programmées pour une Vt dans une région de Vt définie (225-1, 225-2).
     
    4. Dispositif de mémoire (503) selon la revendication 2, dans lequel la valeur stockée est stockée dans les cellules de mémoire (111-1, ..., 111-N).
     
    5. Dispositif de mémoire (503) selon l'une quelconque des revendications 1 à 4, dans lequel le dispositif de commande (562) est configuré pour réaliser le nombre d'opérations de détection sur les cellules de mémoire (111-1, ..., 111-N) en réponse à l'échec d'une opération de correction d'erreur.
     
    6. Procédé de fonctionnement de dispositif de mémoire (503), comprenant :

    la réalisation d'un certain nombre d'opérations de détection sur un certain nombre de cellules de mémoire (111-1, ..., 111-N) du dispositif de mémoire, chaque opération de détection étant réalisée à l'aide d'une tension de détection différente (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2) ;

    la détermination, pour chacune des différentes tensions de détection (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2), d'une quantité des cellules de mémoire (111-1, ..., 111-N) ayant une tension de seuil (Vt) supérieure à la tension de détection respective (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2) ;

    la détermination de différences entre les quantités déterminées de cellules de mémoire (111-, ..., 111-1) ;

    la détermination d'une tendance associée aux différences déterminées ; et

    le réglage d'une tension de détection utilisée pour déterminer un état des cellules de mémoire (111-1, ..., 111-N) sur la base, au moins partiellement, de la tendance déterminée.


     
    7. Dispositif de mémoire (503), comprenant :

    des cellules de mémoire (111-1, ..., 111-N) ; et

    un dispositif de commande (562) configuré pour :

    réaliser un certain nombre d'opérations de détection sur un certain nombre de cellules de mémoire (111-1, ..., 111-N), chaque opération de détection étant réalisée à l'aide d'une tension de détection différente (327-0, 327-1, 327-2 , 327-3, 327-4, 457-0, 457-1, 457-2) ;

    déterminer, pour chacune des différentes tensions de détection (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2), une quantité du nombre des cellules de mémoire (111-1, ..., 111-N) ayant une tension de seuil (Vt) supérieure à la tension de détection respective (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2) ;

    déterminer des différences entre les quantités déterminées des cellules de mémoire (111-1, ..., 111-N) ;

    déterminer une différence minimale des différences déterminées ; et

    régler une tension de détection utilisée pour déterminer un état des cellules de mémoire (111-1, ..., 111-N) sur la base, au moins partiellement, de la différence minimale déterminée.


     
    8. Procédé de fonctionnement d'un dispositif (503), comprenant :

    la réalisation d'un certain nombre d'opérations de détection sur un certain nombre de cellules de mémoire (111-1, ..., 111-N), chaque opération de détection étant réalisée à l'aide d'une tension de détection différente (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2) ;

    la détermination, pour chacune des différentes tensions de détection (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2), d'une quantité du nombre de cellules de mémoire (111-1, ..., 111-N) ayant une tension de seuil (Vt) supérieure à la tension de détection respective (327-0, 327-1, 327-2, 327-3, 327-4, 457- 0, 457-1, 457-2) ;

    la détermination de différences entre les quantités déterminées de cellules de mémoire (111-1, ..., 111-N) ;

    la détermination d'une différence minimale des différences déterminées ; et

    le réglage d'une tension de détection utilisée pour déterminer un état du nombre de cellules de mémoire (111-1, ..., 111-N) sur la base, au moins partiellement, de la différence minimale déterminée.


     
    9. Procédé selon la revendication 8, dans lequel le procédé comporte :

    la comparaison des quantités déterminées de cellules de mémoire (111-1, ..., 111-N) ; et

    le réglage de la tension de détection utilisée pour déterminer l'état du nombre de cellules de mémoire (111-1, ..., 111-N) sur la base, au moins partiellement, de la comparaison.


     
    10. Procédé selon l'une quelconque des revendications 8 ou 9, dans lequel chaque tension de détection (327-0, 327-1, 327-2, 327-3, 327-4) est espacée d'une quantité de tension particulière.
     
    11. Procédé selon l'une quelconque des revendications 8 ou 9, dans lequel chaque tension de détection (457-0, 457-1, 457-2) est espacée d'une quantité de tension différente.
     
    12. Procédé selon l'une quelconque des revendications 8 ou 9, dans lequel le procédé comporte la détermination de la quantité du nombre de cellules de mémoire (111-1, ..., 111-N) ayant une Vt supérieure à la tension de détection respective (327-0, 327-1, 327-2, 327-3, 327-4, 457-0, 457-1, 457-2) utilisée dans l'opération de détection respective après chaque opération de détection.
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description