(19)
(11)EP 2 684 191 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
04.12.2019 Bulletin 2019/49

(21)Application number: 12713430.2

(22)Date of filing:  07.03.2012
(51)International Patent Classification (IPC): 
G11C 11/00(2006.01)
H01L 27/105(2006.01)
G11C 5/14(2006.01)
H03K 19/00(2006.01)
H01L 27/092(2006.01)
(86)International application number:
PCT/US2012/027985
(87)International publication number:
WO 2012/122221 (13.09.2012 Gazette  2012/37)

(54)

USING LOW VOLTAGE REGULATOR TO SUPPLY POWER TO A SOURCE-BIASED POWER DOMAIN

STROMVERSORGUNG EINES STROMBEREICHS MIT VORGESPANNTER QUELLE ANHAND EINES NIEDRIGERSPANNUNGSREGLERS

UTILISATION D'UN RÉGULATEUR PAR BASSE TENSION POUR ALIMENTER UN DOMAINE DE PUISSANCE POLARISÉ PAR UNE SOURCE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 10.03.2011 US 201161451202 P
01.03.2012 US 201213409440

(43)Date of publication of application:
15.01.2014 Bulletin 2014/03

(73)Proprietor: Microchip Technology Incorporated
Chandler, AZ 85224-6199 (US)

(72)Inventors:
  • MUHA, James
    Phoenix, AZ 85044 (US)
  • WILSON, Tim
    Chandler, AZ 85226 (US)
  • SESSIONS, DC
    Phoenix, AZ 85032 (US)
  • YUENYONGSGOOL, Yong
    Gilbert, AZ 85297 (US)

(74)Representative: sgb europe 
Lechnerstraße 25a
82067 Ebenhausen
82067 Ebenhausen (DE)


(56)References cited: : 
WO-A1-02/29893
US-A- 5 726 946
JP-A- 10 229 165
US-A1- 2001 048 319
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description


    [0001] The present disclosure relates to voltage regulators, and, more particularly, to using a low voltage regulator to significantly reduce standby, sleep mode current draw in source-biased power domains of an integrated circuit device.

    [0002] An integrated circuit device may electrically alter the threshold voltage of its NMOS transistors by raising the Vss power rail voltage above the bulk (e.g., well, tub, or substrate) voltage of the integrated circuit substrate (sometimes referred to as a "virtual ground"). This technique is commonly used to reduce the power consumption of the integrated circuit device due to sub-threshold leakage. Generally, the integrated circuit device will have two or more independent voltage domains to service respective core logic circuits that have signal paths therebetween; some of these voltage domains may operate on the virtual ground, and other voltage domains may operate on true ground.

    [0003] Separate voltage supplies may be used to connect to N-MOS and P-MOS bulk regions in multiple well CMOS technologies. Modification of these voltages with respect to the primary power and ground supplies is called well-biasing. These supplies can be modulated to provide a back-bias voltage which causes an increase in the MOS device threshold voltage, Vth, thereby reducing the sub-threshold leakage. Back-bias tap cells have a basic function to provide access to the wells and/or substrate independent of the source connected transistors therein. Back bias tap cells provide power for wells of always-on cells while power is gated for retention of flip-flops states, power gates with buffers and always-on buffers. They also provide well access such that back biasing can be used for leakage optimization.

    [0004] One way to dramatically lower the current of an integrated circuit device in a sleep state is to raise the ground rail voltage used by standard cells above the substrate voltage, commonly referred to as back-biasing. This reduces leakage current. Another way to reduce current while in a sleep state is to utilize a low voltage regulator since a loosely regulated, lower voltage is sufficient to maintain the logic cell states. This reduces bias current of not only the voltage regulator but of supporting macro cells like a band gap voltage reference. The aforementioned two techniques cannot be combined since the low voltage regulator does not provide a high enough voltage to maintain adequate noise margin when standard cells are in a back-biased state. A normal voltage regulator must be used to maintain adequate noise margin.

    [0005] One problem with implementing source back-biasing is that the effective voltage across the biased circuits decreases due to the ground (common source) voltage rising which in turn reduces the reliability of the biased circuits. For example, in a source-biased power domain in 180 nanometer technology, the ground rail, called virtual ground, is raised to approximately 0.6 volts, so it is necessary to supply 1.8 volts to the power rail to allow for 1.2 volts of noise margin. Presently, that requires that the main voltage regulator be in operation since the output voltage of a low voltage regulator in 180 nanometer technology, for example, is only 1.2 volts, leaving just 0.6 volts of noise margin which is insufficient.

    [0006] US 5,726,946 discloses a semiconductor integrated circuit device having hierarchical power source arrangement. JP 10229165 discloses a CMOS inverter circuit with a first and second operating mode with variable threshold voltages.

    [0007] Therefore it would be desirable for source back-biased circuits to retain the same effective voltage for noise margin when being powered by a low voltage regulator as when these circuits are not being back-biased. This and other objects can be achieved by the integrated circuit device and method for operating an integrated circuit device as defined in the independent claims. Further enhancements are characterized in the dependent claims.

    [0008] According to an embodiment, a low voltage regulator coupled to source back-biased capable power domains may comprise: a low voltage regulator having a common thereof coupled to a virtual ground of at least one power domain in an integrated circuit die that is capable of being back-biased, an input coupled to a supply voltage, and an output coupled to and supplying a regulated voltage to transistors in the at least one power domain; and a true ground is coupled to a substrate of the integrated circuit die, wherein when the virtual ground is back-biased relative to the true ground sufficient to reduce leakage current to an acceptable level in a given process technology, the output voltage of the low voltage regulator rises with the virtual ground voltage so as to maintain substantially the same voltage to the transistors in the at least one power domain during back-biasing thereof.

    [0009] According to a further embodiment, the regulated voltage from the low voltage regulator is approximately the normal operating voltage for logic minus an offset voltage at the virtual ground sufficient to reduce the leakage current to the acceptable level in the given process technology. According to a further embodiment, the regulated voltage from the low voltage regulator is approximately 1.2 volts for 180 nanometer process technology. According to a further embodiment, the at least one power domain is back-biased with a ground offset voltage relative to the true ground sufficient to reduce leakage current to an acceptable level in the given process technology.

    [0010] According to a further embodiment, the ground offset voltage is about 0.6 volts for 180 nanometer process technology. According to a further embodiment, the true ground is at substantially zero (0) volts. According to a further embodiment, bias current of the low voltage regulator is about 100 nanoamperes which is typical for 180 nanometer process technology. According to a further embodiment, the substrate is a p-substrate having holes as majority carriers. According to a further embodiment, the virtual ground is coupled to sources of n-mos transistors fabricated in the p-substrate. According to a further embodiment, the low voltage regulator is used to power the at least one power domain during back-biasing thereof.

    [0011] According to another embodiment, a method for powering a source back-biased capable power domain with a low voltage regulator may comprise the steps of: providing a low voltage regulator having a common thereof coupled to a virtual ground of at least one power domain in an integrated circuit die that is capable of being back-biased, an input coupled to a supply voltage, and an output coupled to and supplying a regulated voltage to transistors in the at least one power domain; coupling a true ground to a substrate of the integrated circuit die; and back-biasing the virtual ground relative to the true ground sufficient to reduce leakage current to an acceptable level in a given process technology, wherein the output voltage of the low voltage regulator rises with the virtual ground voltage so as to maintain substantially the same voltage to the transistors in the at least one power domain during the step of back-biasing thereof.

    [0012] According to a further embodiment of the method, the regulated voltage from the low voltage regulator is approximately the normal operating voltage for logic minus an offset voltage at the virtual ground sufficient to reduce the leakage current to the acceptable level in the given process technology. According to a further embodiment of the method, during the step of back-biasing the virtual ground voltage there is a ground offset voltage sufficient to reduce leakage current to an acceptable level in the given process technology. According to a further embodiment of the method, the true ground is at substantially zero (0) volts.

    [0013] According to a further embodiment of the method, bias current of the low voltage regulator is about 100 nanoamperes which is typical for 180 nanometer process technology. According to a further embodiment of the method, the substrate is a p-substrate having holes as majority carriers. According to a further embodiment of the method, the virtual ground comprises the step of coupling sources of n-mos transistors fabricated in the p-substrate to the virtual ground. According to a further embodiment of the method, the step of powering the at least one power domain during back-biasing thereof is done with the low voltage regulator.

    [0014] A more complete understanding of the present disclosure may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein:

    Figure 1 illustrates a schematic elevational view of a portion of an integrated circuit device showing separate substrate and source common (ground) connections that are used to source back-bias transistors in the integrated circuit device, according to a specific example embodiment of this disclosure;

    Figure 2 illustrates a greatly simplified schematic diagram of a standard voltage regulator;

    Figure 3 illustrates a greatly simplified schematic diagram of a low voltage regulator;

    Figure 4 illustrates a greatly simplified schematic diagram of a low voltage regulator, modified according to a specific example embodiment of this disclosure;

    Figure 5 illustrates a schematic diagram of a low voltage regulator for source-biased power domains, according to a specific example embodiment of this disclosure; and

    Figure 6 illustrates a schematic block diagram of an integrated voltage regulator comprising switchable main and low voltage regulators, according to a specific example embodiment of this disclosure.



    [0015] While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims.

    [0016] If the common (ground) of a low voltage regulator is connected to a virtual ground of the integrated circuit die, the regulated output voltage from the low voltage regulator is raised by approximately the same amount that the back-biased virtual ground voltage is raised. Therefore, the output of the low voltage regulator will be approximately the normal operating voltage for logic minus the ground offset voltage. For example, in 180 nanometer process technology, this voltage level is approximately 1.8 volts which is about 1.2 volts above a 0.6 volt virtual ground.

    [0017] Since the bias current of the main voltage regulator is in the one to two microampere range while the bias current of the low voltage regulator may be 100 nanoamperes for typical 180 nanometer process technology. Therefore significant power savings may be realized without sacrificing adequate noise margin for standard cells by replacing the main voltage regulator with a low voltage regulator, modifying the integrated circuit design such that transistors that previously were connected to true ground are now connected to virtual ground, and substrate taps are connected to true ground. Several microamperes of current may thereby be eliminated in a sleep or deep sleep state while maintaining adequate noise margin. Additionally, the bias current of a band gap voltage reference can be eliminated, thereby saving several more microamperes.

    [0018] Referring now to the drawings, the details of a specific example embodiment is schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix.

    [0019] Referring to Figure 1, depicted is a schematic elevational view of a portion of an integrated circuit device showing separate substrate and source common (ground) connections that are used to source back-bias transistors in the integrated circuit device, according to a specific example embodiment of this disclosure. An integrated circuit die may comprise a p-substrate 102 having n-mos and p-mos transistors formed therein. A typical n-mos transistor comprises an n+ source 106, a gate 108 and an n+ drain 110. A typical p-mos transistor comprises p+ drain 112, a gate 114 and a p+ source 116. The p-mos transistor is fabricated in an n-well 120 formed in the p-substrate 102. An n+ tap 122 is formed in the n-well 120 and is coupled to VDD and the p+ source 116 with a metal connection 118. A p+ tap 104 separate from the n+ source 106 of the n-mos transistor couples the p-substrate 102 to a true ground 128, TGND, connection, and the n+ source 106 is therefore independently connected to a virtual ground 130, VGND, connection. Insulating oxides are not shown for illustrative clarity.

    [0020] Referring to Figure 2, depicted is a greatly simplified schematic diagram of a standard voltage regulator. A standard (main) voltage regulator 232 has a common rail connected to the same true ground, TGND, connection 128 that is also coupled to the p+ (substrate) ties 104. The regulated output voltage of the regulator 232 has to be the normal operating voltage for logic in a given process technology, for example, in 180 nanometer process technology, this voltage level is approximately 1.8 volts to maintain logic circuits that have been source back-biased to reduce current therein. The voltage regulator 232 uses significant current for its own operation, thus limiting battery life.

    [0021] Referring to Figure 3, depicted is a greatly simplified schematic diagram of a low voltage regulator. A low voltage regulator 334 has a common rail connected to the same true ground, TGND, connection 128 that is also coupled to the p+ (substrate) ties 104. The low voltage regulator 334 has only an output voltage that is insufficient to maintain logic circuits that have been source back-biased to reduce current therein.

    [0022] Referring to Figure 4, depicted is a greatly simplified schematic diagram of a low voltage regulator, modified according to a specific example embodiment of this disclosure. The low voltage regulator 436 has a common rail connected to the virtual ground, VGND, connection 130 that is only coupled to the n+ source 106. The low voltage regulator 436 has an output voltage that is substantially the normal operating voltage for the logic minus the ground offset voltage, e.g., 1.2 volts for 180 nanometer process technology. Since the output voltage of the low voltage regulator 436 is referenced to the virtual ground, VGND, connection 130 and not the true ground, TGND, connection 128, it can maintain an output voltage providing substantially the normal operating voltage referenced to true ground, TGND, with reference to the n+ source 106, thereby maintaining logic circuits that have been source back-biased to reduce current therein.

    [0023] Referring to Figure 5, depicted is a schematic diagram of a low voltage regulator for source-biased power domains, according to the teachings of this disclosure. There are two GND inputs to the voltage regulator, "true ground" called TGND and "virtual ground" called VGND. The TGND connection 128 is connected to only substrate ties to keep the substrate as close to zero (0) volts as possible. The VGND connection 130 is connected to various transistor drains, gates, or sources, as dictated by the voltage regulator design, the design of which is not covered herein. The output voltage VOUT is relative to VGND since the circuitry of the regulator 436 connects only to VGND and not TGND. Thus as VGND rises above zero (0) volts the output voltage, VOUT, will rise similarly.

    [0024] Referring to Figure 6, depicted is a schematic block diagram of an integrated voltage regulator comprising switchable main and low voltage regulators, according to a specific example embodiment of this disclosure. An integrated voltage regulator 640 may comprise the main voltage regulator 232 and the low voltage regulator 436 previously described hereinabove, and voltage steering switches 642 and 644, e.g., field effect transistor (FET) switches. A direct current voltage (power) source 646, e.g., 3 volt supply, battery, etc., is coupled to the voltage steering switch 642 and supplies either the main voltage regulator 232 or the low voltage regulator 436 when in normal operation or low power back-biased standby, respectively. The other voltage steering switch 644 couples either the main voltage regulator 232 or the low voltage regulator 436 to VDD for the integrated circuit transistors when in normal operation or low power back-biased standby, respectively. It is contemplated and within the scope of this disclosure that the main voltage regulator 232, the low voltage regulator 436, and the voltage steering switches 642 and 644 may be separate or integrated into the integrated voltage regulator 640.

    [0025] While embodiments of this disclosure have been depicted, described, and are defined by reference to example embodiments of the disclosure, such references do not imply a limitation on the disclosure, and no such limitation is to be inferred. The subject matter disclosed is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent art and having the benefit of this disclosure. The depicted and described embodiments of this disclosure are examples only.


    Claims

    1. An integrated circuit device comprising a low voltage regulator (436) and driver circuitry, wherein
    the driver circuitry comprises drivers having a low side transistor (106, 108, 110) connected in series with a high side transistor (112, 114, 116, 122) coupled between a first voltage node (130) and a second voltage node (118) and configured to drive a signal according to an input signal (124),
    the low voltage regulator (436) having a common connection coupled to a virtual ground (VGND) of at least one power domain in the integrated circuit die, wherein the virtual ground is configurable to be back-biased with respect to a true ground, an input coupled to a supply voltage (VDD), and an output coupled to and supplying a regulated voltage to transistors in the at least one power domain;
    wherein the first voltage node (130; 106) of all low side transistors of all drivers of the driver circuitry are connected to the virtual ground (VGND) and the respective second voltage node (118) is coupled through a first switch (644) either with an output of the low voltage regulator (232) or another supply voltage node receiving an operating voltage, and
    wherein the true ground (TGND) is coupled to a substrate (102) of the integrated circuit die, wherein when the virtual ground (VGND) is back-biased relative to the true ground (TGND) sufficient to reduce leakage current to a predefined level in a given process technology, the output voltage of the low voltage regulator rises with the virtual ground voltage to approximately the same voltage as the operating voltage.
     
    2. The integrated circuit device according to claim 1, wherein the regulated voltage from the low voltage regulator (436) is approximately the operating voltage for logic minus an offset voltage at the virtual ground (VGND) sufficient to reduce the leakage current to the predefined level in the given process technology.
     
    3. The integrated circuit device according to claim 2, wherein the regulated voltage from the low voltage regulator (436) is approximately 1.2 volts for 180 nanometer process technology.
     
    4. The integrated circuit device according to one of the preceding claims, wherein the at least one power domain is back-biased with a ground offset voltage relative to the true ground (TGND) sufficient to reduce leakage current to the predefined level in the given process technology.
     
    5. The integrated circuit device according to claim 4, wherein the ground offset voltage is 0.6 volts for 180 nanometer process technology.
     
    6. The integrated circuit device one of the preceding claims, a substrate (102) of a first conductivity comprising a first diffusion (104) of the first conductivity for providing a connection for said true ground (TGND) and a second diffusion (106) of a second conductivity type providing a connection for said virtual ground (VGND) wherein the second diffusion forms part of a low side transistor.
     
    7. The integrated circuit device according to one of the preceding claims, wherein the substrate (102) is a p-substrate having holes as majority carriers.
     
    8. The integrated circuit device according to one of the preceding claims, wherein the virtual ground is coupled to sources of n-mos transistors fabricated in the p-substrate.
     
    9. The integrated circuit device according to one of the preceding claims, wherein the low voltage regulator (436) is used to power the at least one power domain during back-biasing thereof.
     
    10. The integrated circuit device according to any of the preceding claims, further comprising a main voltage regulator (232) having an input operable to be coupled with a power supply voltage (646), an output providing a regulated voltage to said another supply voltage node and a common connection coupled with the true ground, and
    a second switch (642) operable to either connect the input of the main voltage regulator (232) or the input of the low voltage regulator (436) with said power supply voltage.
     
    11. A method for powering an integrated circuit device with a low voltage regulator (436), said method comprising the steps of:

    coupling a common connection of the low voltage regulator (436) to a virtual ground (VGND) of at least one power domain in the integrated circuit device, wherein the virtual ground is configurable to be back-biased with respect to a true ground (TGND), coupling an input of the low voltage regulator (436) to a supply voltage, and supplying a regulated voltage through an output of the low voltage regulator (436) to transistors in the at least one power domain;

    coupling all low side transistors (106, 108, 110) connected in series with associated high side transistors (112, 114, 116, 122) of driver circuitry of the integrated circuit device with said virtual ground (VGND);

    coupling the true ground (TGND) to a substrate of the integrated circuit device; and

    in a low power mode, back-biasing the virtual ground (VGND) relative to the true ground (TGND) sufficient to reduce leakage current to a predefined level in a given process technology, wherein the output voltage of the low voltage regulator (436) rises with the virtual ground voltage to approximately the same voltage as the operating voltage and coupling all high side transistors to said output of the low voltage regulator (436), and

    in an operating power mode, coupling all high side transistors to another supply voltage node and not back-biasing the virtual ground (VGND).


     
    12. The method according to claim 11, wherein the regulated voltage from the low voltage regulator (436) is approximately a predefined operating voltage for logic minus an offset voltage at the virtual ground sufficient to reduce the leakage current to the predefined level in the given process technology.
     
    13. The method according to claim 11 or 12, wherein during the step of back-biasing the virtual ground voltage is a ground offset voltage sufficient to reduce leakage current to the predefined level in the given process technology.
     
    14. The method according to one of the preceding claims 11-13, wherein the low voltage regulator (436) provides a bias current, wherein the substrate (102) is a p-substrate having holes as majority carriers, and wherein the virtual ground (VGND) comprises the step of coupling sources of n-mos transistors fabricated in the p-substrate to the virtual ground.
     
    15. The method according to one of the preceding claims 11-14, further comprising the step of powering the at least one power domain during back-biasing thereof with the low voltage regulator (436).
     


    Ansprüche

    1. Integrierte Schaltungsanordnung, die einen Niederspannungsregler (436) und eine Treiberschaltung aufweist, wobei
    die Treiberschaltung Treiber aufweist, die einen Low-Side-Transistor (106, 108, 110) aufweisen, die mit einem High-Side-Transistor (112, 114, 116, 122) in Reihe verbunden sind, der zwischen einen ersten Spannungsknoten (130) und einen zweiten Spannungsknoten (118) gekoppelt ist und konfiguriert ist, um ein Signal gemäß einem Eingangssignal (124) zu steuern,
    der Niederspannungsregler (436) eine gemeinsame Verbindung aufweist, die mit einer virtuellen Masse (VGND) von zumindest einem Strombereich in dem integrierten Schaltkreischip gekoppelt ist, wobei die virtuelle Masse so konfiguriert werden kann, dass sie in Bezug auf eine wahre Masse rückwärtsvorgespannt ist, einen mit einer Versorgungsspannung (VDD) gekoppelten Eingang und einen mit Transistoren in dem zumindest einen Strombereich gekoppelten und diesen eine geregelte Spannung zuführenden Ausgang aufweist;
    wobei der erste Spannungsknoten (130; 106) aller Low-Side-Transistoren aller Treiber der Treiberschaltung mit der virtuellen Masse (VGND) verbunden ist und der entsprechende zweite Spannungsknoten (118) über einen ersten Schalter (644) entweder mit einem Ausgang des Niederspannungsreglers (232) oder einem anderen Versorgungsspannungsknoten gekoppelt ist, der eine Betriebsspannung empfängt, und
    wobei die wahre Masse (TGND) mit einem Substrat (102) des integrierten Schaltkreischips gekoppelt ist, wobei, wenn die virtuelle Masse (VGND) in Bezug auf die wahre Masse (TGND) ausreichend rückwärtsvorgespannt ist, um den Leckstrom in einer gegebenen Prozesstechnologie auf einen vorgegebenen Pegel zu reduzieren, die Ausgangsspannung des Niederspannungsreglers mit der virtuellen Massespannung auf ungefähr die gleiche Spannung wie die Betriebsspannung steigt.
     
    2. Integrierte Schaltungsanordnung gemäß Anspruch 1, wobei die geregelte Spannung von dem Niederspannungsregler (436) ungefähr die Betriebsspannung für die Logik minus einer Offset-Spannung an der virtuellen Masse (VGND) ist, die ausreicht, um den Leckstrom in der gegebenen Prozesstechnologie auf den vorgegebenen Pegel zu reduzieren.
     
    3. Integrierte Schaltungsanordnung gemäß Anspruch 2, wobei die geregelte Spannung von dem Niederspannungsregler (436) für 180-Nanometer-Prozesstechnologie ungefähr 1,2 Volt beträgt.
     
    4. Integrierte Schaltungsanordnung gemäß einem der vorhergehenden Ansprüche, wobei der zumindest eine Strombereich mit einer Masseoffsetspannung relativ zur wahren Masse (TGND) rückwärtsvorgespannt ist, die ausreicht, um den Leckstrom in der gegebenen Prozesstechnologie auf den vorgegebenen Pegel zu reduzieren.
     
    5. Integrierte Schaltungsanordnung gemäß Anspruch 4, wobei die Masseoffsetspannung für die 180-Nanometer-Prozesstechnologie 0,6 Volt beträgt.
     
    6. Integrierte Schaltungsanordnung gemäß einem der vorhergehenden Ansprüche, die ein Substrat (102) einer ersten Leitfähigkeit aufweist, das eine erste Diffusion (104) der ersten Leitfähigkeit zum Bereitstellen einer Verbindung für die wahre Masse (TGND) und eine zweite Diffusion (106) eines zweiten Leitfähigkeitstyps aufweist, die eine Verbindung für die virtuelle Masse (VGND) bereitstellt, wobei die zweite Diffusion einen Teil eines Low-Side-Transistors ausbildet.
     
    7. Integrierte Schaltungsanordnung gemäß einem der vorhergehenden Ansprüche, wobei das Substrat (102) ein p-Substrat mit Defektelektronen als Majoritätsträger ist.
     
    8. Integrierte Schaltungsanordnung gemäß einem der vorhergehenden Ansprüche, wobei die virtuelle Masse mit Source-Anschlüssen von in dem p-Substrat hergestellten n-MOS-Transistoren gekoppelt ist.
     
    9. Integrierte Schaltungsanordnung gemäß einem der vorhergehenden Ansprüche, wobei der Niederspannungsregler (436) verwendet wird, um den zumindest einen Strombereich während dessen Rückwärtsvorspannens mit Spannung zu versorgen.
     
    10. Integrierte Schaltungsanordnung gemäß einem der vorhergehenden Ansprüche, die weiterhin einen Hauptspannungsregler (232) aufweist, der einen Eingang aufweist, der mit einer Energieversorgungsspannung (646) gekoppelt werden kann, einen Ausgang aufweist, der eine geregelte Spannung an den anderen Versorgungsspannungsknoten bereitstellt und eine gemeinsame Verbindung aufweist, die mit der wahren Masse verbunden ist, und
    einen zweiten Schalter (642), der betreibbar ist, um entweder den Eingang des Hauptspannungsreglers (232) oder den Eingang des Niederspannungsreglers (436) mit der Versorgungsspannung zu koppeln.
     
    11. Verfahren zum Versorgen einer integrierten Schaltungsanordnung mit Energie mit einem Niederspannungsregler (436), wobei das Verfahren die folgenden Schritte aufweist:

    Koppeln einer gemeinsamen Verbindung des Niederspannungsreglers (436) mit einer virtuellen Masse (VGND) von zumindest einem Strombereich in der integrierten Schaltungsanordnung, wobei die virtuelle Masse so konfiguriert werden kann, dass sie in Bezug auf eine wahre Masse (TGND) rückwärtsvorgespannt ist, Koppeln eines Eingangs des Niederspannungsreglers (436) mit einer Versorgungsspannung und Bereitstellen einer geregelten Spannung über einen Ausgang des Niederspannungsreglers (436) an Transistoren in dem zumindest einen Strombereich;

    Koppeln aller Low-Side-Transistoren (106, 108, 110), die mit zugeordneten High-Side-Transistoren (112, 114, 116, 122) der Treiberschaltung der integrierten Schaltungsanordnung in Reihe verbunden sind, mit der virtuellen Masse (VGND);

    Koppeln der wahren Masse (TGND) an ein Substrat der integrierten Schaltungsanordnung; und

    in einem Niedrigenergiemodus, Rückwärtsvorspannen der virtuellen Masse (VGND) in Bezug auf die wahre Masse (TGND), ausreichend, um den Leckstrom auf einen vorgegebenen Pegel in einer gegebenen Prozesstechnologie zu reduzieren, wobei die Ausgangsspannung des Niederspannungsreglers (436) mit der virtuellen Massespannung auf ungefähr die gleiche Spannung wie die Betriebsspannung ansteigt und Koppeln aller High-Side-Transistoren mit dem Ausgang des Niederspannungsreglers (436), und

    in einem Betriebsenergiemodus, Koppeln aller High-Side-Transistoren mit einem anderen Versorgungsspannungsknoten und kein Rückwärtsvorspannen der virtuellen Masse (VGND).


     
    12. Verfahren gemäß Anspruch 11, wobei die geregelte Spannung von dem Niederspannungsregler (436) annähernd eine vorgegebene Betriebsspannung für die Logik abzüglich einer Offset-Spannung an der virtuellen Masse ist, die ausreicht, um den Leckstrom in der gegebenen Prozesstechnologie auf das vorgegebene Maß zu reduzieren.
     
    13. Verfahren gemäß Anspruch 11 oder 12, bei dem während des Schritts des Rückwärtsvorspannens die virtuelle Massespannung eine Masseoffsetspannung ist, die ausreicht, um den Leckstrom in der gegebenen Prozesstechnologie auf den vorgegebenen Pegel zu reduzieren.
     
    14. Verfahren gemäß einem der vorhergehenden Ansprüche 11 bis 13, wobei der Niederspannungsregler (436) einen Vorspannungsstrom liefert, wobei das Substrat (102) ein p-Substrat mit Defektelektronen als Majoritätsträger ist und wobei die virtuelle Masse (VGND) den Schritt des Koppelns von Source-Anschlüssen von in dem p-Substrat hergestellten n-MOS-Transistoren mit der virtuellen Masse aufweist.
     
    15. Verfahren gemäß einem der vorhergehenden Ansprüche 11 bis 14, das weiterhin den Schritt des Versorgens des zumindest einen Leistungsbereichs mit Energie während dessen Rückwärtsvorspannens mit dem Niederspannungsregler (436) aufweist.
     


    Revendications

    1. Dispositif à circuit intégré comprenant un régulateur basse tension (436) et des éléments de circuit de commande, dans lequel
    les éléments de circuit de commande comprennent des dispositifs de commande ayant un transistor côté bas (106, 108, 110) connecté en série avec un transistor côté haut (112, 114, 116, 122) couplé entre un premier nœud de tension (130) et un deuxième nœud de tension (118) et configuré pour commander un signal conformément à un signal d'entrée (124),
    le régulateur basse tension (436) ayant une connexion commune couplée à une masse virtuelle (VGND) d'au moins un domaine de puissance dans la puce de circuit intégré, dans lequel la masse virtuelle peut être configurée pour être rétro polarisée par rapport à une masse vraie, une entrée couplée à une tension d'alimentation (VDD), et une sortie couplée et fournissant une tension régulée à des transistors dans ledit au moins un domaine de puissance ;
    dans lequel le premier nœud de tension (130 ; 106) de tous les transistors côté bas de tous les dispositifs de commande des éléments de circuit de commande est connecté à la masse virtuelle (VGND) et le deuxième nœud de tension (118) respectif est couplé par l'intermédiaire d'un premier commutateur (644) soit à une sortie du régulateur basse tension (232), soit à un autre nœud de tension d'alimentation recevant une tension de fonctionnement, et
    dans lequel la masse vraie (TGND) est couplée à un substrat (102) de la puce de circuit intégré, dans lequel, lorsque la masse virtuelle (VGND) est rétro polarisée par rapport à la masse vraie (TGND) suffisamment pour réduire un courant de fuite à un niveau prédéfini dans une technologie de processus donnée, la tension de sortie du régulateur basse tension augmente avec la tension de masse virtuelle à peu près à la même tension que la tension de fonctionnement.
     
    2. Dispositif à circuit intégré selon la revendication 1, dans lequel la tension régulée provenant du régulateur basse tension (436) est à peu près égale à la tension de fonctionnement pour la logique moins une tension de décalage au niveau de la masse virtuelle (VGND) suffisante pour réduire le courant de fuite au niveau prédéfini dans la technologie de processus donnée.
     
    3. Dispositif à circuit intégré selon la revendication 2, dans lequel la tension régulée provenant du régulateur basse tension (436) est à peu près égale à 1,2 volt pour une technologie de processus de 180 nanomètres.
     
    4. Dispositif à circuit intégré selon l'une des revendications précédentes, dans lequel ledit au moins un domaine de puissance est rétro polarisé avec une tension de décalage de masse par rapport à la masse vraie (TGND) suffisante pour réduire un courant de fuite au niveau prédéfini dans la technologie de processus donnée.
     
    5. Dispositif à circuit intégré selon la revendication 4, dans lequel la tension de décalage de masse est égale à 0,6 volt pour une technologie de processus de 180 nanomètres.
     
    6. Dispositif à circuit intégré l'une des revendications précédentes, dans lequel un substrat (102) d'une première conductivité comprend une première diffusion (104) de la première conductivité pour fournir une connexion pour ladite masse vraie (TGND) et une deuxième diffusion (106) d'un deuxième type de conductivité fournissant une connexion pour ladite masse virtuelle (VGND), dans lequel la deuxième diffusion forme une partie d'un transistor côté bas.
     
    7. Dispositif à circuit intégré selon l'une des revendications précédentes, dans lequel le substrat (102) est un substrat p comportant des trous en tant que porteurs majoritaires.
     
    8. Dispositif à circuit intégré selon l'une des revendications précédentes, dans lequel la masse virtuelle est couplée aux sources des transistors n-mos fabriqués dans le substrat p.
     
    9. Dispositif à circuit intégré selon l'une des revendications précédentes, dans lequel le régulateur basse tension (436) est utilisé pour alimenter ledit au moins un domaine de puissance pendant la rétro polarisation de celui-ci.
     
    10. Dispositif à circuit intégré selon l'une quelconque des revendications précédentes, comprenant en outre un régulateur de tension principal (232) ayant une entrée pouvant être utilisée pour être couplée à une tension d'alimentation (646), une sortie fournissant une tension régulée audit un autre nœud de tension d'alimentation et une connexion commune couplée à la masse vraie, et
    un deuxième commutateur (642) pouvant être utilisé pour connecter soit l'entrée du régulateur de tension principal (232), soit l'entrée du régulateur basse tension (436) à ladite tension d'alimentation.
     
    11. Procédé pour alimenter un dispositif à circuit intégré avec un régulateur basse tension (436), ledit procédé comprenant les étapes :

    de couplage d'une connexion commune du régulateur basse tension (436) à une masse virtuelle (VGND) d'au moins un domaine de puissance dans le dispositif à circuit intégré, dans lequel la masse virtuelle peut être configurée pour être rétro polarisée par rapport à une masse vraie (TGND), de couplage d'une entrée du régulateur basse tension (436) à une tension d'alimentation, et de fourniture d'une tension régulée par l'intermédiaire d'une sortie du régulateur basse tension (436) à des transistors dans ledit au moins un domaine de puissance ;

    de couplage de tous les transistors côté bas (106, 108, 110) connectés en série avec les transistors côté haut (112, 114, 116, 122) associés des éléments de circuit de commande du dispositif à circuit intégré avec ladite masse virtuelle (VGND) ;

    de couplage de la masse vraie (TGND) à un substrat du dispositif à circuit intégré ; et

    dans un mode de faible puissance, de rétro polarisation de la masse virtuelle (VGND) par rapport à la masse vraie (TGND) suffisamment pour réduire un courant de fuite à un niveau prédéfini dans une technologie de processus donnée, dans lequel la tension de sortie du régulateur basse tension (436) augmente avec la tension de masse virtuelle à peu près à la même tension que la tension de fonctionnement, et de couplage de tous les transistors côté haut à ladite sortie du régulateur basse tension (436), et

    dans un mode de puissance de fonctionnement, de couplage de tous les transistors côté haut à un autre nœud de tension d'alimentation et de non rétro polarisation de la masse virtuelle (VGND).


     
    12. Procédé selon la revendication 11, dans lequel la tension régulée provenant du régulateur basse tension (436) est à peu près égale à une tension de fonctionnement prédéfinie pour la logique moins une tension de décalage au niveau de la masse virtuelle suffisante pour réduire le courant de fuite au niveau prédéfini dans la technologie de processus donnée.
     
    13. Procédé selon la revendication 11 ou 12, dans lequel, pendant l'étape de rétro polarisation de la masse virtuelle, la tension est une tension de décalage de masse suffisante pour réduire un courant de fuite au niveau prédéfini dans la technologie de processus donnée.
     
    14. Procédé selon l'une des revendications 11 à 13 précédentes, dans lequel le régulateur basse tension (436) fournit un courant de polarisation, dans lequel le substrat (102) est un substrat p comportant des trous en tant que porteurs majoritaires, et dans lequel la masse virtuelle (VGND) comprend l'étape de couplage des sources des transistors n-mos fabriqués dans le substrat p à la masse virtuelle.
     
    15. Procédé selon l'une des revendications 11 à 14 précédentes, comprenant en outre l'étape d'alimentation dudit au moins un domaine de puissance pendant la rétro polarisation de celui-ci avec le régulateur basse tension (436).
     




    Drawing























    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description