(19)
(11)EP 2 700 089 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
23.01.2019 Bulletin 2019/04

(21)Application number: 12774630.3

(22)Date of filing:  28.03.2012
(51)International Patent Classification (IPC): 
H01L 29/86(2006.01)
H01L 21/328(2006.01)
(86)International application number:
PCT/US2012/030904
(87)International publication number:
WO 2012/145130 (26.10.2012 Gazette  2012/43)

(54)

SELECT DEVICES

AUSWAHLVORRICHTUNGEN

DISPOSITIFS DE SÉLECTION


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 19.04.2011 US 201113089648

(43)Date of publication of application:
26.02.2014 Bulletin 2014/09

(73)Proprietor: Micron Technology, Inc.
Boise, ID 83716-9632 (US)

(72)Inventors:
  • RAMASWAMY, D.V. Nirmal
    Boise, Idaho 83706 (US)
  • SANDHU, Gurtej S.
    Boise, Idaho 83706 (US)

(74)Representative: Beresford, Keith Denis Lewis et al
Beresford Crump LLP 16 High Holborn
London WC1V 6BX
London WC1V 6BX (GB)


(56)References cited: : 
KR-A- 20100 005 986
US-A1- 2007 170 446
US-A1- 2008 150 425
US-A1- 2007 001 201
US-A1- 2007 170 446
US-A1- 2010 264 397
  
  • KRINGHOJ P ET AL: "Solid-phase epitaxial crystallization of strain-relaxed Si1-xGex alloy layers", PHYSICAL REVIEW LETTERS, AMERICAN PHYSICAL SOCIETY, US, vol. 73, no. 6, 8 August 1994 (1994-08-08) , pages 858-861, XP009129829, ISSN: 0031-9007
  • VANHELLEMONT JAN ET AL: "On the impact of germanium doping on the vacancy formation energy in Czochralski-grown silicon", JOURNAL OF APPLIED PHYSICS, AMERICAN INSTITUTE OF PHYSICS, US, vol. 108, no. 1, 13 July 2010 (2010-07-13) , pages 16105-16105, XP012141840, ISSN: 0021-8979, DOI: 10.1063/1.3449080
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

Technical Field



[0001] The present disclosure relates generally to semiconductor electronic devices and methods, and more particularly, select devices.

Background



[0002] Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its information and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent information by retaining stored information when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.

[0003] Select devices can be coupled to memory cells. Select devices can be used as a switch, in which the transistor is either fully-on or fully-off. Fully-on has a voltage across the transistor of almost zero and the transistor is "saturated" as it cannot pass any more current. Examples of select devices include thin film transistors (TFTs). TFTs commonly use silicon film. Generally, polycrystalline silicon materials have been widely used as semiconductor materials for TFTs because they have a high field-effect mobility and can be applied to high speed circuits and constitute complementary metal oxide semiconductor (CMOS) circuits. TFTs using polycrystalline silicon materials can be used as active elements of active-matrix liquid crystal display (AMLCD) devices and switching and driving elements of organic light emitting diodes (OLEDs).

[0004] Methods of crystallizing an amorphous silicon material into a polycrystalline silicon material include solid phase crystallization (SPC), excimer laser crystallization (ELC), metal induced crystallization (MIC) and metal induced lateral crystallization (MILC). SPC is a method of annealing an amorphous silicon material for several to several tens of hours at a temperature at or below the transition temperature of the glass used as a substrate of a display device employing a thin film transistor (typically, about 700° C or less). ELC is a method of crystallizing an amorphous silicon material by irradiating the amorphous silicon material with an excimer laser and locally heating the amorphous silicon material to a high temperature for a very short time. MIC is a method of using phase transfer induction from amorphous silicon to polysilicon by contacting the amorphous silicon material with metals such as nickel (Ni), palladium (Pd), gold (Au), and aluminium (Al), or implanting such metals into the amorphous silicon material. MILC is a method of inducing sequential crystallization of an amorphous silicon material by lateral diffusion of silicide formed by reacting metal with silicon.

[0005] However, SPC has disadvantages of long processing time and a risk of transformation of the substrate due to the long processing time and high temperature used for the annealing. ELC has disadvantages in the expensive laser equipment is required and interfacial characteristics between a semiconductor material and a gate insulating material may be poor due to protrusions generated on the created polycrystallized surface. MIC and MILC have disadvantages in that a large amount of crystallization-inducing metal remains on the crystallized polycrystalline silicon material to increase the leakage current of a semiconductor material of a TFT.

[0006] United States Patent Application Publication No. US 2010/264397 A1 to Xia et al., concerns two-terminal memristive switches including a memristive matrix. The memristive matrix includes two regions: a non-doped semiconducting region and a highly doped semiconducting region. The memristive matrix is a thin film, that may be nanocrystalline or amorphous, having a thickness less than 100 nm, which can be made of Ga semiconductor material with a 3.3 eV bandgap, with an upper and a lower electrode.

[0007] United States Patent Application Publication No. US 2007/170446 A1 to Cho et al., discloses a semiconductive stack form between two electrodes, the stack comprising nanocrystalline line layers and amorphous layer, and is made of a semiconductor material with less than 4 eV bandgap.

[0008] Article entitled: "Phase Epitaxial Crystallisation of Strain Relaxed Si1-xGex Alloy Layers", Physical Review Letters, American Physical Society, US, Vol. 73, No. 6, 8 August 1994, pages 858-861, XP 009129829 by Kringhoj, P., et al., discloses the use of active impurities promoting or retarding crystallisation of a semiconductor.

[0009] Article entitled: "On the impact of germanium doping on the vacancy formation energy in Czochralski-grown silicon" Journal of Applied Physics, American Institute of Physics, US, vol. 108, number 1, 13 July 2010, page 16105, XP 012141840 by Vanhellemont, Jan et al., concerns an electroluminescent diode and methods of fabricating the same. The electroluminescent diode includes: a first electrode; an inorganic hole transport layer; a semiconductor nanocrystal layer; an inorganic electron transport layer; and a second electrode. The inorganic hole transport layer and/or the inorganic electron transport layer can be amorphous. The semiconductor nanocrystal layer is a monolayer or combination of monolayers of semiconductor nanocrystals. When the holes and electrons collide in the semiconductor nanocrystal layer, they bind to form excitations which subsequently recombine, thereby emitting light. The semiconductor nanocrystal layer is located between the inorganic hole transport layer and the inorganic electron transport layer to provide for emitting light. During production the semiconductor layer is annealed at 450° C.

Summary of the Invention



[0010] The present invention is defined in the appended independent claims to which reference should be made. Advantageous features are set out in the appended dependent claims.

Brief Description of the Drawings



[0011] 

Figure 1 illustrates an example of a select device having a semiconductor stack in accordance with one or more embodiments of the present disclosure.

Figure 2 illustrates an example of a select device having a semiconductor stack in accordance with one or more embodiments of the present disclosure.

Figure 3 illustrates an example of a select device having a semiconductor stack in accordance with one or more embodiments of the present disclosure.

Figure 4 illustrates an example of a cross-point memory array including at least one select device in accordance with one or more embodiments of the present disclosure.


Detailed Description



[0012] Methods, devices, and systems associated with select devices are described herein. One or more select devices can include a semiconductive stack of at least one semiconductive material formed on a first electrode. The semiconductive stack can have a thickness of from about 700 angstroms (Å) or less, and each of the at least one semiconductive material can have an associated band gap of about 4 electron volts (eV) or less. A second electrode can be formed on the semiconductive stack.

[0013] Embodiments of the present disclosure can provide select devices capable of supporting increased current densities compared to prior select devices. In various embodiments, the structure of the select device can include a semiconductive stack tunable to accommodate different memory cell characteristics, such as symmetric or asymmetric current versus voltage signature, for instance. In one or more embodiments, the select devices provided can be subjected to a large number of loading cycles (e.g., 106) without experiencing a premature fatigue failure.

[0014] In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more examples of the disclosure may be practiced. These examples are described in sufficient detail to enable those of ordinary skill in the art to practice the examples of this disclosure, and it is to be understood that other examples may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure.

[0015] The figures herein follow a numbering convention in which the first digit corresponds to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 203 may reference element "03" in Figure 2, and a similar element may be referenced as 303 in Figure 3. As will be appreciated, elements shown in the various examples herein can be added, exchanged, and/or eliminated so as to provide a number of additional examples of the present disclosure. In addition, the proportion and the relative scale of the elements provided in the figures are intended to illustrate various examples of the present invention and are not to be used in a limiting sense.

[0016] Examples of a select device can include, but are not so limited to, bipolar select devices, Esaki diodes (e.g., tunnel diodes), and Schottky diodes, among others. For ease of description and by way of example, the select devices illustrated in the figures will be described in terms of a bipolar select device, though embodiments according to the present disclosure are not so limited.

[0017] Figure 1 illustrates an example of a bipolar select device 100 formed in accordance with one or more embodiments of the present disclosure. In this example, the bipolar select device 100 includes a semiconductive stack 105 formed on a first electrode 101. As used herein, a semiconductive stack (e.g., 105) includes one or more semiconductive materials formed in a stacked configuration (e.g., in a number of layers or otherwise). As used herein, semiconductive materials can include semi-insulative materials. In one or more embodiments, the bipolar select device 100 can serve as a select device for a memory cell such as a resistive random access memory (RRAM) cell. Although embodiments are not so limited, the select device 100 can be a diode, for instance.

[0018] In the example illustrated in Figure 1 which does not fall under the scope of the independent claims, the semiconductive stack 105 includes a single semiconductive material 105 having a thickness (t) formed on a first electrode 101. A second electrode 103 is formed on the semiconductive stack 105. The first electrode 101 and/or the second electrode 103 can include a metal material, for example. The metal material can include titanium, titanium nitride (TiN), platinum (Pt), tungsten (W), tungsten nitride (WN), ruthenium (Ru), and/or iridium (Ir), and/or combinations thereof, among other metal materials. The first electrode 101 and second electrode 103 can be made of the same or different materials and can have the same or different physical configuration. That is, the electrodes 101 and 103 can be symmetric or asymmetric. In one example, the first electrode 101 can be TiN and the second electrode 103 can be ruthenium (Ru). The first and/or second electrodes 101 and 103 can be formed as a plug within a dielectric material such as silicon nitride (SiN), for example. Embodiments are not limited to electrodes comprising particular materials or to electrodes having a particular physical configuration. For instance, the particular materials and or physical configuration of the electrodes can depend on factors such as the characteristics of the semiconductive stack 105 and/or a desired current density through the select device 100, among other factors.

[0019] The semiconductive material 105 formed on the first electrode 101 can be various semiconductive materials, such as silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), indium gallium nitride (InGaN), and/or aluminum gallium nitride (AlGaN), among others. The semiconductive material 105 can comprise, for example, an amorphous semiconductive material. An amorphous semiconductive material can refer to a semiconductive material that lacks the long-range order characteristics of a crystal.

[0020] In one or more embodiments, the semiconductive material 105 has a thickness (t) of about 700 angstroms or less and can have an associated band gap of about 4 eV or less. As used herein, a band gap (e.g., energy band gap) refers to the energy difference between a top of the valence band and a bottom of the conduction band associated with a particular material.

[0021] Figure 2 illustrates an example of a bipolar select device 200 which does not fall under the scope of the independent claims. In this example, the bipolar select device 200 includes a semiconductive stack having a thickness (t) that includes two semiconductive materials 207 and 209, where semiconductive material 207 is formed on a first electrode 201. The semiconductive material 209 is formed on the semiconductive material 207, and a second electrode 203 is formed on the semiconductive material 209. In various embodiments, the electrodes 201, 203 are metal electrodes.

[0022] In one or more embodiments, the material 209 of the semiconductive stack can be an amorphous semiconductive material 209 and the semiconductive material 207 can be a partially nanocrystallized semiconductive material 207. The term nanocrystallized includes materials that have small grains of crystalline material within the amorphous phase of the material, including materials around the transition region from amorphous to microcrystalline phase of the material. Alternatively, the material 209 of the semiconductive stack of the bipolar select device 200 can be a partially nanocrystallized semiconductive material 209 and the material 207 can be an amorphous semiconductive material 207. For example, in one or more embodiments the percentage crystallized of the partially nanocrystallized semiconductive material can be between 0% and 50% nanocrystallized.

[0023] As an example, the two semiconductive materials 207, 209 can have the same thickness (e.g., each of the materials 207, 209 can have a thicknesses of t/2). However, embodiments are not limited to particular thicknesses of materials 207 and 209. The particular materials 207 and 209 of the semiconductive stack, as well as their respective thicknesses, can depend on various factors, for example the desired current density through the select device 200 and/or a memory cell associated therewith. Similarly, the particular materials and/or physical configuration of the electrodes 201 and 203 can depend on various factors, for example the desired current density through the select device 200 and/or a memory cell associated therewith.

[0024] As such, one or more bipolar select devices (e.g., 100, 200, 300) according to the present disclosure can be "tunable" to accommodate particular characteristics. As an example, factors of the bipolar select device 200 that can effect its associated current density can include the barrier height (e.g., Schottky barrier height) between the semiconductive materials 207, 209 and the electrodes 201, 203, the work function of the metal electrodes 201, 203, the dielectric constants of the semiconductive materials 207, 209, and the effective electron mass of the materials 207, 209, among other factors. Therefore, the configuration of bipolar select devices can be tuned to achieve desired current density and/or leakage current characteristics, for instance.

[0025] In one or more embodiments, the bipolar select device can be tuned by adjusting the thickness of the semiconductive stack within in a range of from about 100 Å to about 500 Å. For example, a semiconductive stack of about 500 Å can have an amorphous semiconductive material of about 200 Å and a partially nanocrystallized semiconductive material of about 300 Å. In various embodiments, the anneal can be performed at low temperature processes in a range of from about 500° C to about 700° C to tune the bipolar select device. Such embodiments can provide benefits associated with Schottky barriers formed at a metal-semiconductor junction. In one or more embodiments, the bipolar select device can be a tunneling based diode (e.g., Esaki diode), and can have the numerous characteristics of such devices as are commonly known in the art.

[0026] Figure 3 illustrates an example of a bipolar select device 300 formed in accordance with one or more embodiments of the present disclosure. In this example, the bipolar select device 300 includes a semiconductive stack having a thickness (t) and including three semiconductive materials 311, 313, and 315 formed on a first electrode 301. The semiconductive material 313 is formed on semiconductive material 311, semiconductive material 315 is formed on semiconductive material 313, and a second electrode 303 is formed on the semiconductive material 315. Select devices of more than three semiconductive materials are contemplated.

[0027] As an example, semiconductive material 311 can be a first partially nanocrystallized semiconductive material, semiconductive material 313 can be an amorphous semiconductive material, and semiconductive material 315 can be a second partially nanocrystallized semiconductive material. In another example, semiconductive material 311 can be a first amorphous semiconductive material, semiconductive material 313 can be a partially nanocrystallized semiconductive material, and semiconductive material 315 can be a second amorphous semiconductive material. Other stack arrangements are contemplated. In the example shown in Figure 3, the bipolar select device 300 can be referred to as a symmetrical bipolar select device since the semiconductive materials (e.g., 311 and 315) abutting the electrodes 301 and 303 are the same material (e.g., amorphous semiconductive material or partially nanocrystallized semiconductive material). Symmetrical bipolar select devices can create a symmetrical current density versus voltage curve, which can be beneficial in their predictability during operation, among other benefits.

[0028] In various embodiments, the bipolar select device 100, 200, 300 can be formed at a temperature of about 500° C or less. The semiconductive materials 105 in Figure 1, 207 and 209 in Figure 2, and 311, 313, 315 in Figure 3 can be formed via various techniques such as, but not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), microwave CVD, anneal, and atomic layer deposition (ALD).

[0029] Forming the semiconductive stack of the bipolar select device 200, 300 can include doping at least one of the semiconductive materials (e.g., 207, 209 in Figure 2, and 311, 313, 315 in Figure 3) of the semiconductive stack with a crystallization retardant such as carbon (C), oxygen (O), and/or nitrogen (N), for instance. Forming the semiconductive stack can also include doping at least one of the semiconductive materials (e.g., 207, 209 in Figure 2, and 311, 313, 315 in Figure 3) of the semiconductive stack with a material such as germanium (Ge), for instance, to promote crystallinity. Other examples of crystallinity promoters include nickel (Ni), palladium (Pd), silver (Ag), gold (Au), aluminum (Al), tin (Sn), antimony (Sb), copper (Cu), terbium (Tb), and cadmium (Cd). In one or more embodiments, the doping of the semiconductive stack with a crystallization retardant and a crystallinity promoter can occur simultaneously or substantially simultaneously. For instance, in an example in which material 313 is a partially crystallized semiconductive material and the materials 311 and 315 are amorphous semiconductive materials, the material 313 can be doped with a crystallization promoter and the materials 311 and 315 can be doped with a crystallization retardant.

[0030] In various embodiments, forming the semiconductive stack can include performing an anneal prior to forming the second electrode (e.g, 103, 203, 303). The anneal can alter at least one of the semiconductor materials. For example, the anneal can alter the at least one semiconductive material doped with the crystallinity promoter to a partially nanocrystallized semiconductive material. Further, because at least one semiconductive material has been doped with the crystallization retardant, at least one semiconductive material will remain an amorphous semiconductive material. Lowering the concentrations of the crystallinity promoter can increase the grain size of the crystalline semiconductor material produced (e.g., by spacing out the sites from which crystallization proceeds). In an example, the anneal can be done at a temperature of about 500° C or less; however, embodiments are not so limited. For example, in one or more embodiments of the present disclosure the anneal can be done at a temperature in a range of from about 500° C to about 700° C for a range of from 1 millisecond to 20 minutes.

[0031] In operation, one or more bipolar select devices in accordance with embodiments described herein can be operated by application of a voltage across the semiconductive stack formed between the first electrode and the second electrode. The applied voltage across the semiconductive stack can, in an example, produce a current density of at least about 1.0 x 106 J·A/cm2 across the bipolar select device. In one or more embodiments, a current density of at least about 1.0 x 106 J·A/cm2 is achieved responsive to an applied voltage of about 3 volts of less.

[0032] Figure 4 is illustrates an example of a cross-point memory array 420 including at least one bipolar select device in accordance with one or more embodiments of the present disclosure. The cross-point memory array 420 can include a first number of conductive lines 423-1, 423-2 and a second number of conductive lines 425-1, 425-2 that intersect the first number of conductive lines 423-1, 423-2. Although Figure 4 shows two conductive lines 423-1, 423-2 and two conductive lines 425-1, 425-2, examples are not limited to a particular number of conductive lines. The first number of conductive lines 423-1, 423-2 can, in an example, be access lines (e.g., word lines) and the second number of conductive lines 425-1, 425-2 can be data lines (e.g., bit lines). The first number of conductive lines 423-1, 423-2 and/or the second number of conductive lines 425-1, 425-2 can be comprised of copper, among various other conductive materials. The cross-point memory array 420 can be an RRAM array, for example, and can be constructed on a bulk silicon integrated circuit (IC). In an example, one or more additional crosspoint memory arrays can be stacked on the cross-point memory array 420.

[0033] As illustrated in Figure 4, the array 420 includes a number of bipolar select devices 400-1, 400-2, 400-3, ... 400-N located at each of the number of intersections of the conductive lines 423-1, 423-2 and the conductive lines 425-1, 425-2. Each of the number of bipolar select devices 400-1, 400-2, 400-3, ... 400-N is connected to a variable resistance element 429-1, 429-2, 429-3, ... 429-N. The variable resistance elements 429-1, 429-2, 429-3, ... 429-N can include various types of resistance variable including transition metal oxides, chalcogenides, and perovskites, among other resistance variable materials. The bipolar select devices 400-1, 400-2, 400-3, ... 400-N can be select devices such as described above in connection with Figures 1-3.

[0034] Although specific examples have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific examples shown. This disclosure is intended to cover adaptations or variations of one or more examples of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above examples, and other examples not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the one or more examples of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of one or more examples of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

[0035] Throughout the specification and claims, the meanings identified below do not necessarily limit the terms, but merely provide illustrative examples for the terms. The meaning of "a," "an," and "the" includes plural reference, and the meaning of "in" includes "in" and "on." The term "a number of" is meant to be understood as including at least one but not limited to one. The phrase "in an example," as used herein does not necessarily refer to the same example, although it can.

[0036] In the foregoing Detailed Description, various features are grouped together in a single example for the purpose of streamlining the disclosure.


Claims

1. A select device (100, 200, 300, 400-1, 400-2, 400-3, ..., 400-N), comprising:

a semiconductive stack (105) including at least one semiconductive material (207, 209, 311, 313, 315) on a first electrode (101, 201, 301), wherein the semiconductive stack (105) has a thickness of 70 nm (700 Ängstroms) or less, and wherein each of the at least one semiconductive material (207, 209, 311, 313, 315) has an associated band gap of 4 electron volts or less, and wherein the at least one semiconductive material (311) comprises:

a first partially nanocrystallized semiconductive material (311);

an amorphous semiconductive material (313) on the first partially nanocrystallized semiconductive material; and

a second partially nanocrystallized semiconductive material (315) on the amorphous semiconductive material; and

a second electrode (103, 203, 303) formed on the semiconductive stack (105).


 
2. The select device (100, 200, 300, 400-1, 400-2, 400-3, ... 400-N) of claim 1, wherein the semiconductive stack (105) includes a single amorphous material.
 
3. The select device (100, 200, 300, 400-1, 400-2, 400-3, ... 400-N) of claim 1, wherein the first partially nanocrystallized semiconductive material has a first thickness and the amorphous semiconductive material (311 has a second thickness.
 
4. The select device (100, 200, 300, 400-1, 400-2, 400-3, ..., 400-N) of claim 1, wherein the second partially nanocrystallized semiconductive material (315) on the amorphous semiconductive material (313) has a third thickness and the first thickness, the second thickness, and the third thickness have a combined thickness of 70 nm (700 Ängstroms) or less.
 
5. The select device (100, 200, 300, 400-1, 400-2, 400-3, ..., 400-N) of claim 1, wherein the first partially nanocrystallized semiconductive material (207, 209, 311, 313, 315) is on the first electrode (101, 201, 301), the amorphous semiconductive material (207, 209, 311, 313, 315) is on the first partially nanocrystallized semiconductive material (207, 209, 311, 313, 315), and the second partially nanocrystallized semiconductive material (207, 209, 311, 313, 315) is on the amorphous semiconductive material (207, 209, 311, 313, 315).
 
6. The select device (100, 200, 300, 400-1, 400-2, 400-3, ..., 400-N) of any one of claims 1-5, wherein at least one semiconductive material (207, 209, 311, 313, 315) of the semiconductive stack (105) is doped with a crystallization retardant.
 
7. The select device (100, 200, 300, 400-1, 400-2, 400-3, ..., 400-N) of any one of claims 1-5, wherein at least one semiconductive material (207, 209, 311, 313, 315) of the semiconductive stack (105) is doped with Ge to promote crystallinity.
 
8. A method of forming a bipolar select device (100, 200, 300, 400-1, 400-2, 400-3,..., 400-N), comprising:

forming a semiconductive stack (105) having a thickness of 70 nm (700 Ängstroms) or less on a first electrode (101, 201, 301), wherein each material (207, 209, 311, 313, 315) of the semiconductive stack (105) has an associated band gap of 4 electron volts or less;

doping at least one semiconductive material (207, 209, 311, 313, 315) of the semiconductive stack (105) with a crystallization retardant;

doping at least one semiconductive material (207, 209, 311, 313, 315) of the semiconductive stack (105) to promote crystallinity;

performing an anneal of the semiconductive stack (105) at an anneal temperature of 500° C or less before forming a second electrode on the semiconductive stack; and

forming the second electrode (103, 203, 303) on the semiconductive stack (105).


 
9. The method of claim 8, wherein doping the at least one semiconductive material (207, 209, 311, 313, 315) of the semiconductive stack (105) with a crystallization retardant includes at least one dopant of C, O, and N.
 
10. The method of claim 8, wherein the select device (100, 200, 300, 400-1, 400-2, 400-3, ..., 400-N) is formed at a temperature of 700° C or less.
 


Ansprüche

1. Auswahlvorrichtung (100, 200, 300, 4001, 400-2, 400-3, 400-3, ..., 400-N), umfassend:

einen Halbeiterstapel (105) mit mindestens einem Halbleitermaterial (207, 209, 311, 313, 315) an einer ersten Elektrode (101, 201, 301), wobei der Halbleiterstapel (105) eine Dicke von 70 nm (700 Ångström) oder weniger aufweist, und wobei jedes der mindestens einen Halbleitermaterialien (207, 209, 311, 313, 315) eine zugehörige Bandlücke von 4 Elektronenvolt oder weniger aufweist, und wobei das mindestens eine Halbleitermaterial (311) umfasst:

ein erstes teilweise nanokristallines Halbleitermaterial (311); ein amorphes Halbleitermaterial (313) auf dem ersten teilweise nanokristallinen Halbleitermaterial; und

ein zweites teilweise nanokristallines Halbleitermaterial (315) auf dem amorphen Halbleitermaterial; und

eine zweite Elektrode (103, 203, 303), die auf Halbleiterstapel (105) ausgebildet ist.


 
2. Auswahlvorrichtung (100, 200, 300, 400-1, 400-2, 400-3, 400-3, ... 400-N) nach Anspruch 1,
wobei der Halbleiterstapel (105) ein einziges amorphes Material umfasst.
 
3. Auswahlvorrichtung (100, 200, 300, 400-1, 400-2, 400-2, 400-3, ... 400-N) nach Anspruch 1, wobei das erste teilweise nanokristalline Halbleitermaterial eine erste Dicke und das amorphe Halbleitermaterial (311) eine zweite Dicke aufweisen.
 
4. Auswahlvorrichtung (100, 200, 300, 400-1, 400-2, 400-3, 400-3, ... , 400-N) nach Anspruch 1, wobei das zweite teilweise nanokristalline Halbleitermaterial (315) auf dem amorphen Halbleitermaterial (313) eine dritte Dicke aufweist und die erste Dicke, die zweite Dicke und die dritte Dicke eine kombinierte Dicke von 70 nm (700 Ångström) oder weniger haben.
 
5. Die Auswahlvorrichtung (100, 200, 300, 400-1, 400-2, 400-3, 400-3, ... , 400-N) nach Anspruch 1, wobei sich das erste teilweise nanokristalline Halbleitermaterial (207, 209, 311, 313, 315) auf der ersten Elektrode (101, 201, 301) befindet, das amorphe Halbleitermaterial (207, 209, 311, 313, 315) sich auf dem ersten teilweise nanokristallinen Halbleitermaterial (207, 209, 311, 313, 315) befindet und das zweite teilweise nanokristalline Halbleitermaterial (207, 209, 311, 313, 315) sich auf dem amorphen Halbleitermaterial (207, 209, 311, 313, 315) befindet.
 
6. Auswahlvorrichtung (100, 200, 300, 400-1, 400-2, 400-3, 400-3, ... , 400-N) nach einem der Ansprüche 1 - 5, wobei mindestens ein Halbleitermaterial (207, 209, 311), 313, 315) des Halbleiterstapels (105) mit einem Kristallisationsverzögerer dotiert ist.
 
7. Auswahlvorrichtung (100, 200, 300, 400-1, 400-2, 400-3, 400-3, ... , 400-N) nach einem der Ansprüche 1 - 5, wobei mindestens ein Halbleitermaterial (207, 209, 311, 313, 315) des Halbleiters (105) mit Ge dotiert ist, um die Kristallinität zu fördern.
 
8. Verfahren zum Bilden einer bipolaren Auswahlvorrichtung (100, 200, 300, 400-1, 400-2, 400 - 3, ... , 400-N), umfassend:

Bilden eines Halbleiterstapels (105) mit einer Dicke von 70 nm (700 Ångström) oder weniger auf einer ersten Elektrode (101, 201, 301), wobei jedes der Materialien (207, 209, 311, 313, 315) des Halbleiterstapels (105) eine zugehörige Bandlücke von 4 Elektronenvolt oder weniger aufweist;

Dotieren mindestens eines Halbleitermaterials (207, 209, 311, 313, 315) des Halbleiterstapels (105) mit einem Kristallisationsverzögerer;

Dotieren mindestens eines Halbleitermaterials (207, 209, 311, 313, 315) des Halbleiterstapels (105), um die Kristallinität zu fördern;

Durchführen eines Temperns des Halbleiterstapels (105) bei einer Tempertemperatur von 500° C oder weniger, bevor eine zweite Elektrode auf dem Halbleiterstapel gebildet wird; und

Bilden der zweiten Elektrode (103, 203, 303) auf dem Halbleiterstapel (105).


 
9. Verfahren nach Anspruch 8, wobei die Dotierung des mindestens einen Halbleitermaterials (207, 209, 311, 313, 315) des Halbleiterstapels (105) mit einem Kristallisationsverzögerer mindestens ein Dotierungsmittel aus C, 0 und N enthält.
 
10. Verfahren nach Anspruch 8, worin die Auswahlvorrichtung (100, 200, 300, 400-1, 400-2, 400-2, 400-3, ... , 400-N) bei einer Temperatur von 700°C oder weniger gebildet wird.
 


Revendications

1. Dispositif de sélection (100, 200, 300, 400-1, 400-2, 400 - 3, ... , 400-N), comprenant :

une pile semi-conductrice (105) comprenant au moins un matériau semi-conducteur (207, 209, 311, 313, 315) sur une première électrode (101, 201, 301), dans lequel la pile semi-conductrice (105) possède une épaisseur de 70 nm (700 Angstrôm) ou moins, et dans lequel chacun du au moins un matériau semi-conducteur (207, 209, 311, 313, 315) possède une bande interdite associée de 4 électrons-volts ou moins, et dans lequel le au moins un matériau semi-conducteur (311) comprend :

un premier matériau semi-conducteur partiellement nano-cristallisé (311) ;

un matériau semi-conducteur amorphe (313) sur le premier matériau semi-conducteur partiellement nano-cristallisé ; et

un second matériau semi-conducteur partiellement nano-cristallisé (315) sur le matériau semi-conducteur amorphe ; et

une seconde électrode (103, 203, 303) formée sur la pile semi-conductrice (105).


 
2. Dispositif de sélection (100, 200, 300, 400-1, 400-2, 400 - 3, ... , 400-N) selon la revendication 1, dans lequel la pile semi-conductrice (105) comprend un seul matériau amorphe.
 
3. Dispositif de sélection (100, 200, 300, 400-1, 400-2, 400 - 3, ... , 400-N) selon la revendication 1, dans lequel le premier matériau semi-conducteur partiellement nano-cristallisé possède une première épaisseur et le matériau semi-conducteur amorphe (311 possède une seconde épaisseur.
 
4. Dispositif de sélection (100, 200, 300, 400-1, 400-2, 400-3,..., 400-N) selon la revendication 1, dans lequel le second matériau semi-conducteur partiellement nano-cristallisé (315) sur le matériau semi-conducteur amorphe (313) possède une troisième épaisseur et la première épaisseur, la seconde épaisseur, et la troisième épaisseur possèdent une épaisseur combinée de 70 nm (700 Angström) ou moins.
 
5. Dispositif de sélection (100, 200, 300, 400-1, 400-2, 400-3,..., 400-N) selon la revendication 1, dans lequel le premier matériau semi-conducteur partiellement nano-cristallisé (207, 209, 311, 313, 315) se trouve sur la première électrode (101, 201, 301), le matériau semi-conducteur amorphe (207, 209, 311, 313, 315) se trouve sur le premier matériau semi-conducteur partiellement nano-cristallisé (207, 209, 311, 313, 315), et le second matériau semi-conducteur partiellement nano-cristallisé (207, 209, 311, 313, 315) se trouve sur le matériau semi-conducteur amorphe (207, 209, 311, 313, 315).
 
6. Dispositif de sélection (100, 200, 300, 400-1, 400-2, 400-3,..., 400-N) selon l'une quelconque des revendications 1 à 5, dans lequel au moins un matériau semi-conducteur (207, 209, 311, 313, 315) de la pile semi-conductrice (105) est dopé avec un retardateur de cristallisation.
 
7. Dispositif de sélection (100, 200, 300, 400-1, 400-2, 400-3,..., 400-N) selon l'une quelconque des revendications 1 à 5, dans lequel au moins un matériau semi-conducteur (207, 209, 311, 313, 315) de la pile semi-conductrice (105) est dopé avec du Ge afin de promouvoir la cristallinité.
 
8. Procédé de formation d'un dispositif de sélection bipolaire (100, 200, 300, 400-1, 400-2, 400-3,..., 400-N), comprenant :

la formation d'une pile semi-conductrice (105) ayant une épaisseur de 70 nm (700 Angström) ou moins sur une première électrode (101, 201, 301), dans lequel chaque matériau (207, 209, 311, 313, 315) de la pile semi-conductrice (105) possède une bande interdite associée de 4 électrons-volts ou moins ;

le dopage d'au moins un matériau semi-conducteur (207, 209, 311, 313, 315) de la pile semi-conductrice (105) avec un retardateur de cristallisation ;

le dopage d'au moins un matériau semi-conducteur (207, 209, 311, 313, 315) de la pile semi-conductrice (105) afin de promouvoir la cristallinité ;

la réalisation d'un recuit de la pile semi-conductrice (105) à une température de recuit de 500°C ou moins avant de former une seconde électrode sur la pile semi-conductrice ; et

la formation de la seconde électrode (103, 203, 303) sur la pile semi-conductrice (105).


 
9. Procédé selon la revendication 8, dans lequel le dopage du au moins un matériau semi-conducteur (207, 209, 311, 313, 315) de la pile semi-conductrice (105) avec un retardateur de cristallisation comprend au moins un dopant de C, O et N.
 
10. Procédé selon la revendication 8, dans lequel le dispositif de sélection (100, 200, 300, 400-1, 400-2, 400-3, ..., 400-N) est formé à une température de 700°C ou moins.
 




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Cited references

REFERENCES CITED IN THE DESCRIPTION



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