(19)
(11)EP 2 743 984 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
06.05.2020 Bulletin 2020/19

(21)Application number: 13196720.0

(22)Date of filing:  11.12.2013
(51)Int. Cl.: 
H01L 27/12  (2006.01)
H01L 29/45  (2006.01)
G02F 1/1368  (2006.01)
H01L 29/786  (2006.01)
H01L 29/66  (2006.01)

(54)

ARRAY SUBSTRATE AND THE METHOD FOR MANUFACTURING THE SAME, AND LIQUID CRYSTAL DISPLAY DEVICE

ARRAY-SUBSTRAT UND VERFAHREN ZUR HERSTELLUNG DAVON UND FLÜSSIGKRISTALLANZEIGEVORRICHTUNG

SUBSTRAT DE RÉSEAU ET SON PROCÉDÉ DE FABRICATION ET DISPOSITIF D'AFFICHAGE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 14.12.2012 CN 201210544983

(43)Date of publication of application:
18.06.2014 Bulletin 2014/25

(73)Proprietor: BOE Technology Group Co., Ltd.
Beijing 100015 (CN)

(72)Inventor:
  • Liu, Xiang
    Beijing 100176 (CN)

(74)Representative: Isarpatent 
Patent- und Rechtsanwälte Behnisch Barth Charles Hassa Peckmann & Partner mbB Friedrichstrasse 31
80801 München
80801 München (DE)


(56)References cited: : 
US-A1- 2008 142 797
US-A1- 2010 148 169
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description


    [0001] The present invention relates to an array substrate, a corresponding manufacturing method, and a liquid crystal display device.

    [0002] US 2010/0148169A1 discloses an array substrate, comprising: a gate electrode, a gate insulating layer, a barrier layer pattern and an active semiconductor layer pattern formed by a metal oxide semiconductor, the barrier layer pattern and the active semiconductor layer pattern being located on the gate insulating layer, a semiconductor protecting layer, configured to cover the barrier layer pattern and the active semiconductor layer pattern, a data wire, a source electrode and a drain electrode made of metal Cu, wherein, the data wire connects the barrier layer pattern, the source electrode and the drain electrode connect the active semiconductor layer pattern.

    DESCRIPTION OF THE PRIOR ART



    [0003] Thin film transistor liquid crystal display (TFT-LCD) has the advantages of small size, low energy consumption, no radiation, etc. As the size of the TFT-LCD increases and resolution improves, a drive circuit of higher frequency is used to improve the display quality, which leads to a more severe image signal delay of large size, high resolution TFT-LCD. The delay of the TFT-LCD signal is mainly decided by T=RC, wherein R is the signal resistance and C is the relative capacitance. Nowadays, the gate electrode, the gate electrode scanning line and data wire of the TFT-LCD are usually made by using metals such as Ta, Cr, Mo, etc. or the alloys thereof having stable chemical properties and high resistivity as the material of metal electrode. With the size and resolution of TFT-LCD increasing, the length of the gate electrode scanning line also increases, and the signal delay time also increases. Once the signal delay increases to certain level, some pixels will be inadequately charged, which leads to unevenness in the brightness, decrease in the contrast of the TFT-LCD, and affects the image display quality greatly.

    [0004] As the size of the liquid crystal display increases, the frequency of the drive circuit also has to be increased. The mobility of the amorphous-silicon TFT(thin film transistor) is about 0.5 cm2/V·S. However, when the size of the liquid crystal display exceeds 80 inch and the drive frequency is 120Hz, a mobility of no less than 1cm2/V·S is necessary.

    [0005] Metal oxide TFT (amorphous IGZO) is large in mobility, good in evenness, transparent and simple in manufacture process, can meet the requirement of the large size liquid crystal display and organic active electroluminescence and meet the requirement of large size, high refresh frequency LCD and OLED for high mobility. When metal Cu is used to form the drain electrode and the source electrode of TFT, Cu diffuses to the semiconductor layer, the gate insulating layer and the semiconductor protecting layer, which will affect the performance of TFT greatly. Therefore, before depositing the metal Cu thin film, barrier layer has to be deposited first.

    [0006] The prior art has the following problems: when using amorphous IGZO to make TFT, a barrier layer is usually formed on the amorphous IGZO (semiconductor layer) to avoid that the amorphous IGZO is damaged when forming the Cu source electrode and drain electrode. However, this will add another patterning process, and when wet-etching metal Cu, since the etching rate of the metal Cu and that of the barrier layer are of great difference, the barrier layer will remain a bit after being etched and other thin films deposited thereupon will be badness in covering.

    SUMMARY OF THE INVENTION



    [0007] The technical problem the present invention intend to solve is providing an array substrate and the method for manufacturing the same, and a liquid crystal display device, to solve the problem of the prior art that when metal Cu is used to make the drain electrode and the source electrode of TFT, the metal Cu diffuses to the semiconductor layer, the gate insulating layer and the semiconductor protecting layer to affect the performance of TFT.

    [0008] To solve the problem mentioned above, the present invention provides an array substrate as defined in independent claim 1.

    [0009] Of the array substrate, the gate insulating layer includes two layers, the first layer is a silicon nitride layer and the second layer is a silicon oxide layer which contacts the active semiconductor layer pattern or the semiconductor protecting layer directly

    [0010] Of the array substrate, the semiconductor protecting layer includes two layers, the first layer is a silicon nitride layer, the second layer is an oxide layer, and the oxide is metal oxide or silicone oxide, the first layer contacts the active semiconductor layer pattern directly.

    [0011] Of the array substrate, a transparent conductive material is used to form a connecting wire between data wire and source electrode, the connecting wire between data wire and source electrode connects the data wire and the source electrode at a connecting via hole of data wire and source electrode.

    [0012] Of the array substrate, a thin film is formed by a transparent conductive material at a source electrode via hole, to cover the source electrode at the source electrode via hole.

    [0013] Of the array substrate, a thin film is formed by a transparent conductive material at a drain electrode via hole, to cover the drain electrode at the drain electrode via hole.

    [0014] A method for manufacturing an array substrate according to the present invention is defined in independent claim 7.

    [0015] Of the method for manufacturing an array substrate, via holes are formed at positions corresponding to the barrier layer pattern and the active semiconductor layer pattern.

    [0016] Of the method for manufacturing an array substrate, the step of "forming a connecting wire between data wire and source electrode, and a transparent pixel electrode through a patterning process" further comprising:
    a transparent conductive material being used to form the connecting wire between data wire and source electrode, the connecting wire between data wire and source electrode connecting the data wire and the source electrode at a connecting via hole of data wire and source electrode.

    [0017] A liquid crystal display device is defined in independent claim 10..

    [0018] The effects achieved by the technical solution of the present invention are as follows: metal Cu is used to form the data wire, the source electrode and the drain electrode, and the metal oxide semiconductor is used as the barrier layer for the metal Cu, and as a result, the diffusion of metal Cu to the layers such as the gate insulating layer is prevented in the manufacturing process of TFT.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0019] 

    Figure 1 is the structural plan diagram of an array substrate of the present invention.

    Figure 2 is the cross-section diagram of forming the gate electrode and the gate electrode scanning line of an array substrate of the present invention through a one-time patterning process.

    Figure 3 is the plan diagram of forming the gate electrode and the gate electrode scanning line of an array substrate of the present invention through a one-time patterning process.

    Figure 4 is the cross-section diagram of forming the barrier layer pattern and the active semiconductor layer pattern of an array substrate of the present invention through a one-time patterning process.

    Figure 5 is the plan diagram of forming the barrier layer pattern and the active semiconductor layer pattern of an array substrate of the present invention through a one-time patterning process.

    Figure 6 is the cross-section diagram of forming the semiconductor protecting layer of an array substrate of the present invention through a one-time patterning process.

    Figure 7 is the plan diagram of forming the semiconductor protecting layer of an array substrate of the present invention through a one-time patterning process.

    Figure 8 is the cross-section diagram of forming the data wire, the source electrode and the drain electrode of an array substrate of the present invention through a one-time patterning process.

    Figure 9 is the plan diagram of forming the data wire, the source electrode and the drain electrode of an array substrate of the present invention through a one-time patterning process.

    Figure 10 is the cross-section diagram of forming the transparent pixel electrode, and the connecting wire between data wire and source electrode of an array substrate of the present invention through a one-time patterning process.

    Figure 11 is the plan of forming the transparent pixel electrode, and the connecting wire between data wire and source electrode of an array substrate of the present invention through a one-time patterning process.

    Figure 12 is the structural diagram of the connecting wire between data wire and source electrode covering part of the data wire of an array substrate of the present invention.



    [0020] 1: glass substrate; 2: gate electrode; 3: gate insulating layer; 4: active semiconductor layer pattern; 5: semiconductor protecting layer; 6: source electrode; 7: drain electrode; 8: transparent pixel electrode; 9: connecting wire between data wire and source electrode; 10: connecting via hole of data wire and source electrode; 11: barrier layer pattern; 12: data wire; 13: gate electrode scanning line; 14:source electrode via hole; 15:drain electrode via hole.

    DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS



    [0021] In order to make clearer of the technical problem intended to solve, technical solution and advantages of the present invention, the specific description is provided below with reference to the drawings and embodiments.

    [0022] In the present invention, metal Cu with low resistance is used to form the source electrode 6 and the drain electrode 7, the gate electrode scanning line 13 and the data wire 12, to improve the condition of the metal Cu wiring in the array substrate.

    [0023] An embodiment of the present invention provides an array substrate, as shown in Figure 1 and 10, comprising:

    a gate electrode 2;

    a gate insulating layer 3;

    a barrier layer pattern 11 for Cu and an active semiconductor layer pattern 4 made of metal oxide semiconductor, which were located on the gate insulating layer 3,

    a semiconductor protecting layer 5 which covered the barrier layer pattern 11 for Cu and the active semiconductor layer pattern 4, and had via holes at positions corresponding to the barrier layer pattern 11 and the active semiconductor layer pattern 4;

    a data wire 12, a source electrode 6 and a drain electrode 7 made of metal Cu, the data wire 12 connected the barrier layer pattern 11 through the corresponding via hole, and the source electrode 6 and the drain electrode 7 connected the active semiconductor layer pattern 4 through the corresponding via holes respectively.



    [0024] Of the provided technology, metal Cu was used to form the data wire 12, the source electrode 6 and the drain electrode 7, and the metal oxide semiconductor was used as the barrier layer for the metal Cu, and as a result, the diffusion of metal Cu to the layers such as the gate insulating layer 3 was prevented in the manufacturing process of TFT.

    [0025] In one preferred embodiment, the gate insulating layer 3 included two layers, the first layer is a silicon nitride layer (SiNx) and the second layer is a silicon oxide layer (SiOx) which contacted the active semiconductor layer pattern 4 or the semiconductor protecting layer 5 directly.

    [0026] In one preferred embodiment, via holes included:

    the first via hole, namely the connecting via hole of data wire and source electrode 10,

    the second via hole, namely the source electrode via hole 14 ,

    the third via hole, namely the drain electrode via hole 15.



    [0027] Each via hole served as the contacting area of metal Cu with the metal oxide semiconductor, as shown in Figure 6.

    [0028] In one preferred embodiment, transparent conductive material was used to form a connecting wire 9 between the data wire and the source electrode which connected the data wire 12 and the source electrode 6 at the via hole for connecting the data wire and the source electrode.

    [0029] As shown in Figure 11, the transparent conductive material covered the whole data wire 12, or as shown in Figure 12, part of the data wire 12. The transparent conductive material specifically was indium tin oxide (ITO) or indium zinc oxide (IZO).

    [0030] In one preferred embodiment, transparent conductive material was used to form a thin film at the source electrode via hole, to cover the source electrode 6 at the source electrode via hole. The transparent conductive material specifically was ITO or IZO.

    [0031] In one preferred embodiment, transparent conductive material was used to form a thin film at the drain electrode via hole, to cover the drain electrode 7 at the drain electrode via hole. The transparent conductive material specifically was ITO or IZO.

    [0032] In one preferred embodiment, the semiconductor protecting layer 5 included two layers, the first layer was a silicon nitride layer, the second layer was an oxide layer, and the oxides is metal oxides or silicon oxides. The first layer contacted the active semiconductor layer pattern 4 directly.

    [0033] The semiconductor protecting layer 5 included two layers, the first layer was a silicon nitride layer and the second layer was an oxide layer, and the oxide could be a metal oxide insulator such as Al2O3, or silicon oxides, such as silica or silicon oxynitride. The function of semiconductor protecting layer 5 lied in preventing the active semiconductor layer pattern 4 from etching off during the process of etching the source electrode 6 and drain electrode 7.

    [0034] Applying the technology provided by an embodiment, in an array substrate manufacturing situation, metal oxide semiconductor was used to form the barrier layer pattern 11 for Cu and the active semiconductor pattern 4, and the metal Cu was used to form the data wire 12, the source electrode 6 and the drain electrode 7. The method specifically comprised:

    [0035] Step 1: depositing a gate metal thin film with a thickness of 4000Å∼15000Å on a glass substrate or a quartz substrate by sputtering or thermal evaporation, wherein the gate metal thin film was formed by metal or alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., or composite gate metal thin film formed by multiple metal layers.

    [0036] In the first one-time patterning process, a gate electrode 2 and a gate electrode scanning line 13 were formed. Figure 2 and 3 shows respectively the cross-section diagram and the plan diagram of the array substrate after this one-time patterning process.

    [0037] Step 2: Depositing continuously a gate insulating layer 3 with a thickness of 2000Å∼ 5000Å by PECVD. The gate insulating layer could be formed by oxides, nitrides or oxynitrides, for example, the gate insulating layer could be formed by silicon oxide, silicon nitride or silicon oxynitride.

    [0038] In order to improve the performance of the TFT, the gate insulating layer 3 included two layers, the first layer was SiNx, the second layer was SiOx which contacted the active semiconductor layer pattern 4 and the semiconductor protecting layer 5 directly.

    [0039] Step 3: Depositing continuously a metal oxide semiconductor layer with a thickness of 50Å∼1000Å by sputtering on the gate insulating layer 3. Specifically, amorphous IGZO, HIZO, IZO, a-InZnO, a-InZnO, ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:AL, TiO2:Nb, Cd-Sn-O or other metal oxides could be used.

    [0040] In the second one-time patterning process, a barrier layer pattern 11 and an active semiconductor layer pattern 4 were formed. Figure 4 and 5 shows respectively the cross-section diagram and the plan diagram of the array substrate after this one-time patterning process.

    [0041] The barrier layer pattern 11 functioned as the barrier layer and increased the adhesion of the relevant electrodes and the metal Cu thin film, and further prevented the metal Cu ion diffusing to the relevant layers such as the gate insulating layer 3.

    [0042] Step 4: depositing a semiconductor protecting layer 5 with a thickness of 500Å∼ 3000Å by PEVCD onto the array substrate. The semiconductor protecting layer 5 could be oxides or nitrides, and oxides could be a metal oxide insulator such as Al2O3, or silicon oxides, such as silica or silicon oxynitride, and nitrides could be silicon nitride. As regarding to the semiconductor protecting layer 5, a double layer barrier structure could be used. And in the double layer barrier structure, the first layer was silicon nitride and the second layer was oxides which could be an insulator of the metal oxide such as Al2O3, or silicon oxide such as silica or silicon oxynitride. The first layer contacted the active semiconductor layer pattern directly.

    [0043] In the third one-time patterning process, the first via hole, the second via hole and the third via hole were formed, wherein the first via hole was a connecting via hole of data wire and source electrode 10, the second via hole was a source electrode via hole 14, and the third via hole was a drain electrode via hole 15.

    [0044] The cross sectional diagram and the plan diagram are shown in Figure 6 and 7. Each via hole served as the contacting area of metal Cu and metal oxide semiconductor.

    [0045] Step 5: depositing a source/drain metal layer with a thickness of 2000Å∼4000 Å by sputtering or thermal evaporation on the array substrate wherein metal Cu was used specifically.

    [0046] In the fourth one-time patterning process, patterns of a data wire 12, a source electrode 6 and a drain electrode 7 were formed. The cross-section diagram and the plan diagram are shown in Figure 8 and 9 respectively.

    [0047] Step 6: depositing a transparent conductive layer with a thickness of 300Å∼1500Å by sputtering and thermal evaporation on the array substrate. The material of the transparent conductive layer could be ITO, IZO, or other transparent metal oxides.

    [0048] In the fifth one-time patterning process, the transparent pixel electrode 8, the connecting wire between data wire and source electrode 9 were formed. The cross-section diagram is shown in Figure 10. The ITO or IZO used in the transparent pixel electrode 8 could cover the whole drain electrode 7 to reduce the poor contact between drain electrode 7 and the transparent pixel electrode 8, to guarantee the adequate contact of the drain electrode 7 and the transparent pixel electrode 8, and to protect the Cu thin film that forms the drain electrode 7. The ITO or IZO used in transparent pixel electrode 8 also can partly cover the drain electrode 7.

    [0049] As shown in Figure 11, transparent conductive material (specifically, ITO or IZO) was used in the connecting wire between data wire and drain electrode 9, which covered the whole data wire 12. Or as shown in Figure 12, the connecting wire between data wire and drain electrode 9 could also cover part of the data wire 12.

    [0050] Applying the technology provided by an embodiment, in an array substrate manufacturing situation, the method comprised:

    forming a gate electrode 2 and a gate electrode scanning line 13 through the first one-time patterning process,

    forming the semiconductor protecting layer 5 with via holes through the third one-time patterning process, wherein the via holes were formed at area corresponding to the barrier layer pattern 11 and the active semiconductor pattern 4. Contacting areas of Cu on metal oxide semiconductor of the barrier layer pattern 11 and the active semiconductor pattern 4 were formed in the semiconductor protecting layer 5, including: contacting area of the data wire through the first via hole, contacting area of the source electrode through the second via hole, contacting area of the drain electrode through the third via hole. The semiconductor protecting layer 5 now served as the protecting layer for the active semiconductor layer pattern 4 to improve the stability of the metal oxide TFT.



    [0051] In the forth one-time patterning process, patterns of a data wire 12, a source electrode 6 and a drain electrode 7 were formed.

    [0052] In the fifth one-time patterning process, a connecting wire between data wire and source electrode 9, and a transparent pixel electrode 8 were formed. The transparent conductive material was used to form the connecting wire between data wire and source electrode 9 which connects the data wire 12 and the source electrode 6 at the first via hole. The transparent conductive material (specifically ITO or IZO) could cover the whole metal Cu thin film to ensure the adequate contact of drain electrode 7 and transparent pixel electrode 8 and to protect the metal Cu thin film. The transparent conductive material could also partly cover the metal Cu thin film, for example, the connecting wire between data wire and source electrode 9 also could cover part of the metal Cu thin film.

    [0053] The one-time patterning process included technological process such as photoresist coating, exposing, developing, etching, stripping, etc., and finally a pattern was formed in the thin film in the one-time patterning process.

    [0054] In the one-time patterning process, since the barrier layer pattern 11 formed by metal oxide semiconductor was used as the barrier layer for metal Cu, the diffusion of metal Cu into layers such as the gate insulating layer 3 was prevented in the manufacturing process the TFT. Moreover, the semiconductor protecting layer 5, the function of which was to prevent the active semiconductor layer 4 being etched off during the etching of the source electrode 6 and the drain electrode 7, was used to protect the active semiconductor layer pattern 4.

    [0055] The advantages acquired by applying the present solution are: metal Cu is used to form the data wire 12, the source electrode 6 and the drain electrode 7, and the metal oxide semiconductor is used as the barrier layer pattern 11 for the metal Cu, and as a result, the diffusion of metal Cu into the layers such as the gate insulating layer 3, the active semiconductor layer pattern 4, etc., is prevented in the manufacturing process of TFT. Since the metal oxide TFT (amorphous IGZO) is large in mobility, good in evenness, transparent and simple in manufacture process, it can meet the requirement of the large size liquid crystal display and the organic active electroluminescence and meet the requirement of large size, high refresh frequency LCD and OLED for high mobility.


    Claims

    1. An array substrate, comprising:

    a gate electrode (2),

    a gate insulating layer (3),

    a barrier layer pattern (11) and an active semiconductor layer pattern (4), both of which are formed by a metal oxide semiconductor, the barrier layer pattern (11) and the active semiconductor layer pattern (4) being located on the gate insulating layer (3),

    a semiconductor protecting layer (5), configured to cover the barrier layer pattern (11) and the active semiconductor layer pattern (4), and via holes being formed at positions corresponding to the barrier layer pattern (11) and the active semiconductor layer pattern (4), wherein the via holes include a connecting via hole (10) of a data wire (12) and a source electrode (6), a source electrode via hole (14), and a drain electrode via hole (15);

    wherein the data wire (12), a source electrode (6) and a drain electrode (7) are made of metal Cu, wherein the data wire (12) connects the barrier layer pattern (11) through the connecting via hole (10) of the data wire (12) and the source electrode (6), the source electrode (6) and the drain electrode (7) connect the active semiconductor layer pattern (4) through the source electrode via hole (14) and the drain electrode via hole (15), respectively, and each via hole serves as the contacting area of metal Cu with the metal oxide semiconductor.


     
    2. The array substrate according to claim 1, wherein, the gate insulating layer (3) includes two layers, the first layer is a silicon nitride layer and the second layer is a silicon oxide layer which contacts the active semiconductor layer pattern (4) or the semiconductor protecting layer (5) directly.
     
    3. The array substrate according to claim 1 or claim 2, wherein, the semiconductor protecting layer (5) includes two layers, the first layer is a silicon nitride layer and the second layer is an oxide layer, the oxide layer is a metal oxide layer or a silicon oxide layer, the first layer contacts the active semiconductor layer pattern (4) directly.
     
    4. The array substrate according to any one of claims 1-3, wherein, a transparent conductive material is used to form a connecting wire between the data wire (12) and the source electrode (6), the connecting wire between the data wire (12) and the source electrode (6) connects the data wire (12) and the source electrode (6) at the connecting via hole (10) of the data wire (12) and the source electrode (6).
     
    5. The array substrate according to any one of claims 1-4, wherein,
    a thin film is formed by a transparent conductive material at the source electrode via hole (14), to cover the source electrode (6) at the source electrode via hole (14).
     
    6. The array substrate according to any one of claims 1-5, characterized in that,
    a thin film is formed by a transparent conductive material at the drain electrode via hole (15), to cover the drain electrode (7) at the drain electrode via hole (15).
     
    7. A method for manufacturing an array substrate, comprising:

    forming a gate electrode (2) and a gate electrode scanning line (13) through a one-time patterning process,

    forming a gate insulating layer (3),

    forming a barrier layer pattern (11) and an active semiconductor layer pattern (4) of a metal oxide semiconductor through a one-time patterning process,

    forming a semiconductor protecting layer (5) with via holes through a one-time patterning process, the via holes include a connecting via hole (10) of data wire (12) and source electrode (6), a source electrode via hole (14), and a drain electrode via hole (15),

    forming patterns of a data wire (12), the source electrode (16) and a drain electrode (7) made of metal Cu through a one-time patterning process, wherein, the data wire (12) connects the barrier layer pattern (11) through the connecting via hole (10) of the data wire (12) and source electrode (6), and the source electrode (6) and the drain electrode (7) connect the active semiconductor layer pattern (4) through the source electrode via hole (14) and the drain electrode via hole (15), respectively, and each via hole serves as the contacting area of metal Cu with the metal oxide semiconductor,

    forming a connecting wire (9) between the data wire (12) and source electrode (6), and a transparent pixel electrode through a one-time patterning process.


     
    8. The method according to claim 7, wherein, said via holes are formed at positions corresponding to the barrier layer pattern (11) and the active semiconductor layer pattern (4).
     
    9. The method according to claim 7 or claim 8, the step of forming a connecting wire (9) between the data wire (12) and source electrode (6), and a transparent pixel electrode through a patterning process further comprising:
    a transparent conductive material being used to form the connecting wire (9) between the data wire (12) and source electrode (6), the connecting wire (9) between the data wire (12) and source electrode (6) connecting the data wire (12) and the source electrode (6) at a connecting via hole (10) of the data wire and the source electrode (6).
     
    10. A liquid crystal display device, comprising the array substrate of any one of claims 1-6.
     
    11. The array substrate of claim 1,
    wherein the semiconductor protecting layer (5) does not completely surround or cover the data wire (12), the source electrode (6) and the drain electrode (7).
     
    12. The method according to claim 7,
    wherein the semiconductor protecting layer (5) does not completely surround or cover the data wire (12), the source electrode (6) and the drain electrode (7).
     


    Ansprüche

    1. Arraysubstrat, das Folgendes umfasst:

    eine Gate-Elektrode (2),

    eine Gate-Isolationsschicht (3),

    eine Barriereschichtstruktur (11) und eine aktive Halbleiterschichtstruktur (4), die beide durch einen Metall-Oxid-Halbleiter gebildet sind, wobei sich die

    Barriereschichtstruktur (11) und die aktive

    Halbleiterschichtstruktur (4) auf der Gate-Isolationsschicht (3) befinden,

    eine Halbleiterschutzschicht (5), die zum Bedecken der Barriereschichtstruktur (11) und der aktiven

    Halbleiterschichtstruktur (4) konfiguriert ist, und Via-Löcher,

    die in Positionen gebildet sind, die der

    Barriereschichtstruktur (11) und der aktiven

    Halbleiterschichtstruktur (4) entsprechen, wobei die Via-Löcher ein Verbindungs-Via-Loch (10) eines Datendrahts (12) und einer Source-Elektrode (6), ein Source-Elektrode-Via-Loch (14) und

    ein Drain-Elektrode-Via-Loch (15) beinhalten;

    wobei der Datendraht (12), eine Source-Elektrode (6) und eine Drain-Elektrode (7) aus einem Metall Cu gefertigt sind, wobei der Datendraht (12) die Barriereschichtstruktur (11) durch das Verbindungs-Via-Loch (10) des Datendrahts (12) und die Source-Elektrode (6) verbindet, wobei die Source-Elektrode (6) und die Drain-Elektrode (7) die aktive Halbleiterschichtstruktur (4) durch das Source-Elektrode-Via-Loch (14) bzw. das Drain-Elektrode-Via-Loch (15) verbinden und wobei jedes Via-Loch als der Kontaktierungsbereich des Metalls Cu mit dem Metall-Oxid-Halbleiter dient.


     
    2. Arraysubstrat nach Anspruch 1, wobei die Gate-Isolationsschicht (3) zwei Schichten beinhaltet, wobei die erste Schicht eine Siliciumnitridschicht ist und die zweite Schicht eine Siliciumoxidschicht ist, die die aktive Halbleiterschichtstruktur (4) oder die Halbleiterschutzschicht (5) direkt kontaktiert.
     
    3. Arraysubstrat nach Anspruch 1 oder Anspruch 2, wobei die Halbleiterschutzschicht (5) zwei Schichten beinhaltet, wobei die erste Schicht eine Siliciumnitridschicht ist und die zweite Schicht eine Oxidschicht ist, wobei die Oxidschicht eine Metalloxidschicht oder eine Siliciumoxidschicht ist, wobei die erste Schicht die aktive Halbleiterschichtstruktur (4) direkt kontaktiert.
     
    4. Arraysubstrat nach einem der Ansprüche 1-3, wobei ein transparentes leitfähiges Material verwendet wird, um einen Verbindungsdraht zwischen dem Datendraht (12) und der Source-Elektrode (6) zu bilden, wobei der Verbindungsdraht zwischen dem Datendraht (12) und der Source-Elektrode (6) den Datendraht (12) und die Source-Elektrode (6) an dem Verbindungs-Via-Loch (10) des Datendrahts (12) und der Source-Elektrode (6) verbindet.
     
    5. Arraysubstrat nach einem der Ansprüche 1-4, wobei ein Dünnfilm durch ein transparentes leitfähiges Material an dem Source-Elektrode-Via-Loch (14) gebildet ist, um die Source-Elektrode (6) an dem Source-Elektrode-Via-Loch (14) zu bedecken.
     
    6. Arraysubstrat nach einem der Ansprüche 1-5, dadurch gekennzeichnet, dass
    ein Dünnfilm durch ein transparentes leitfähiges Material an dem Drain-Elektrode-Via-Loch (15) gebildet ist, um die Drain-Elektrode (7) an dem Drain-Elektrode-Via-Loch (15) zu bedecken.
     
    7. Verfahren zum Herstellen eines Arraysubstrats, das Folgendes umfasst:

    Bilden einer Gate-Elektrode (2) und einer Gate-Elektrode-Scanleitung (13) durch einen einmaligen Strukturierungsprozess,

    Bilden einer Gate-Isolationsschicht (3),

    Bilden einer Barriereschichtstruktur (11) und einer aktiven Halbleiterschichtstruktur (4) aus einem Metall-Oxid-Halbleiter durch einen einmaligen Strukturierungsprozess,

    Bilden einer Halbleiterschutzschicht (5) mit Via-Löchern durch einen einmaligen Strukturierungsprozess, wobei die Via-Löcher ein Verbindungs-Via-Loch (10) eines Datendrahts (12) und einer Source-Elektrode (6), ein Source-Elektrode-Via-Loch (14) und

    ein Drain-Elektrode-Via-Loch (15) beinhalten;

    Bilden von Strukturen aus einem Datendraht (12), der Source-Elektrode (16) und einer Drain-Elektrode (7), die aus einem Metall Cu gefertigt sind, durch einen einmaligen Strukturierungsprozess, wobei der Datendraht (12) die Barriereschichtstruktur (11) durch das Verbindungs-Via-Loch (10) des Datendrahts (12) und die Source-Elektrode (6) verbindet, und die Source-Elektrode (6) und die Drain-Elektrode (7) die aktive Halbleiterschichtstruktur (4) durch das Source-Elektrode-Via-Loch (14) bzw. das Drain-Elektrode-Via-Loch (15) verbinden und jedes Via-Loch als der Kontaktierungsbereich des Metalls Cu mit dem Metall-Oxid-Halbleiter dient,

    Bilden eines Verbindungsdrahts (9) zwischen dem Datendraht (12) und der Source-Elektrode (6) und einer transparenten Pixelelektrode durch einen einmaligen Strukturierungsprozess.


     
    8. Verfahren nach Anspruch 7, wobei die Via-Löcher in Positionen gebildet sind, die der Barriereschichtstruktur (11) und der aktiven Halbleiterschichtstruktur (4) entsprechen.
     
    9. Verfahren nach Anspruch 7 oder Anspruch 8, wobei der Schritt des Bildens eines Verbindungsdrahts (9) zwischen dem Datendraht (12) und der Source-Elektrode (6) und einer transparenten Pixelelektrode durch einen Strukturierungsprozess ferner Folgendes umfasst:
    ein transparentes leitfähiges Material, das verwendet wird, um den Verbindungsdraht (9) zwischen dem Datendraht (12) und der Source-Elektrode (6) zu bilden, wobei der Verbindungsdraht (9) zwischen dem Datendraht (12) und der Source-Elektrode (6) den Datendraht (12) und die Source-Elektrode (6) an einem Verbindungs-Via-Loch (10) des Datendrahts und der Source-Elektrode (6) verbindet.
     
    10. Flüssigkristallanzeigevorrichtung, die das Arraysubstrat nach einem der Ansprüche 1-6 umfasst.
     
    11. Arraysubstrat nach Anspruch 1,
    wobei die Halbleiterschutzschicht (5) den Datendraht (12), die Source-Elektrode (6) und die Drain-Elektrode (7) nicht vollständig umgibt oder bedeckt.
     
    12. Verfahren nach Anspruch 7,
    wobei die Halbleiterschutzschicht (5) den Datendraht (12), die Source-Elektrode (6) und die Drain-Elektrode (7) nicht vollständig umgibt oder bedeckt.
     


    Revendications

    1. Substrat-réseau, comprenant :

    une électrode de grille (2),

    une couche isolante de grille (3),

    un motif de couche barrière (11) et un motif de couche semi-conductrice active (4), tous deux étant formés par un semi-conducteur à oxyde métallique, le motif de couche barrière (11) et le motif de couche semi-conductrice active (4) étant situés sur la couche isolante de grille (3),

    une couche de protection de semi-conducteur (5), configurée pour recouvrir le motif de couche barrière (11) et le motif de couche semi-conductrice active (4), et des trous traversants étant formés à des positions correspondant au motif de couche barrière (11) et au motif de couche semi-conductrice active (4), les trous traversants comportant un trou traversant de connexion (10) d'un fil de données (12) et d'une électrode de source (6), un trou traversant d'électrode de source (14),
    et un trou traversant d'électrode de drain (15) ;

    dans lequel le fil de données (12), une électrode de source (6) et une électrode de drain (7) sont constitués de Cu métallique, dans lequel le fil de données (12) se connecte au motif de couche barrière (11) par le biais du trou traversant de connexion (10) du fil de données (12) et de l'électrode de source (6), l'électrode de source (6) et l'électrode de drain (7) se connectent au motif de couche semi-conductrice active (4) par le biais du trou traversant d'électrode de source (14) et du trou traversant d'électrode de drain (15), respectivement,
    et chaque trou traversant sert de zone de contact de Cu métallique avec le semi-conducteur à oxyde métallique.


     
    2. Substrat-réseau selon la revendication 1, dans lequel la couche isolante de grille (3) comporte deux couches, la première couche est une couche de nitrure de silicium et la deuxième couche est une couche d'oxyde de silicium qui est en contact direct avec le motif de couche semi-conductrice active (4) ou la couche de protection de semi-conducteur (5).
     
    3. Substrat-réseau selon la revendication 1 ou la revendication 2, dans lequel la couche de protection de semi-conducteur (5) comporte deux couches, la première couche est une couche de nitrure de silicium et la deuxième couche est une couche d'oxyde, la couche d'oxyde est une couche d'oxyde métallique ou une couche d'oxyde de silicium, la première couche est en contact direct avec le motif de couche semi-conductrice active (4).
     
    4. Substrat-réseau selon l'une quelconque des revendications 1 à 3, dans lequel un matériau conducteur transparent est utilisé pour former un fil de connexion entre le fil de données (12) et l'électrode de source (6), le fil de connexion entre le fil de données (12) et l'électrode de source (6) connecte le fil de données (12) et l'électrode de source (6) au niveau du trou traversant de connexion (10) du fil de données (12) et de l'électrode de source (6).
     
    5. Substrat-réseau selon l'une quelconque des revendications 1 à 4, dans lequel
    un film mince est formé par un matériau conducteur transparent au niveau du trou traversant d'électrode de source (14), pour recouvrir l'électrode de source (6) au niveau du trou traversant d'électrode de source (14).
     
    6. Substrat-réseau selon l'une quelconque des revendications 1 à 5, caractérisé en ce que
    un film mince est formé par un matériau conducteur transparent au niveau du trou traversant d'électrode de drain (15), pour recouvrir l'électrode de drain (7) au niveau du trou traversant d'électrode de drain (15).
     
    7. Procédé de fabrication d'un substrat-réseau, comprenant :

    la formation d'une électrode de grille (2) et d'une ligne de balayage d'électrode de grille (13) par un traitement de gravure en une seule passe,

    la formation d'une couche isolante de grille (3),

    la formation d'un motif de couche barrière (11) et d'un motif de couche semi-conductrice active (4) en semi-conducteur à oxyde métallique par un traitement de gravure en une seule passe,

    la formation d'une couche de protection de semi-conducteur (5) avec des trous traversants par un traitement de gravure en une seule passe, les trous traversants comportant un trou traversant de connexion (10) d'un fil de données (12) et d'une électrode de source (6), un trou traversant d'électrode de source (14), et un trou traversant d'électrode de drain (15),

    la formation de motifs d'un fil de données (12), de l'électrode de source (16) et d'une électrode de drain (7) constitués de Cu métallique par un traitement de gravure en une seule passe, le fil de données (12) se connectant au motif de couche barrière (11) par le biais du trou traversant de connexion (10) du fil de données (12) et de l'électrode de source (6), et l'électrode de source (6) et l'électrode de drain (7) se connectant au motif de couche semi-conductrice active (4) par le biais du trou traversant d'électrode de source (14) et du trou traversant d'électrode de drain (15), respectivement, et chaque trou traversant servant de zone de contact de Cu métallique avec le semi-conducteur à oxyde métallique,

    la formation d'un fil de connexion (9) entre le fil de données (12) et l'électrode de source (6), et d'une électrode de pixel transparente par un processus de gravure en une seule passe.


     
    8. Procédé selon la revendication 7, dans lequel lesdits trous traversants sont formés à des positions correspondant au motif de couche barrière (11) et au motif de couche semi-conductrice active (4).
     
    9. Procédé selon la revendication 7 ou la revendication 8, l'étape de formation d'un fil de connexion (9) entre le fil de données (12) et l'électrode de source (6), et d'une électrode de pixel transparente par un traitement de gravure en une seule passe comprenant en outre :

    l'utilisation d'un matériau conducteur transparent pour former le fil de connexion (9) entre le fil de données (12) et l'électrode de source (6), le fil de connexion (9) entre le fil de données (12) et l'électrode de source (6) connectant le fil de données (12) et l'électrode de source (6) au niveau d'un trou traversant de connexion (10) du fil de données et de l'électrode de source (6).


     
    10. Dispositif d'affichage à cristaux liquides, comprenant le substrat-réseau de l'une quelconque des revendications 1 à 6.
     
    11. Substrat-réseau de la revendication 1,
    dans lequel la couche de protection de semi-conducteur (5) n'entoure ou ne recouvre pas entièrement le fil de données (12), l'électrode de source (6) et l'électrode de drain (7).
     
    12. Procédé selon la revendication 7,
    dans lequel la couche de protection de semi-conducteur (5) n'entoure ou ne recouvre pas entièrement le fil de données (12), l'électrode de source (6) et l'électrode de drain (7).
     




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    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description