(19)
(11)EP 2 815 427 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
06.05.2020 Bulletin 2020/19

(21)Application number: 13706105.7

(22)Date of filing:  24.01.2013
(51)Int. Cl.: 
B82Y 30/00  (2011.01)
C23C 16/26  (2006.01)
H01L 23/532  (2006.01)
C23C 16/02  (2006.01)
H01L 21/768  (2006.01)
(86)International application number:
PCT/US2013/022885
(87)International publication number:
WO 2013/122724 (22.08.2013 Gazette  2013/34)

(54)

METHOD OF MANUFACTURING ELECTRICAL CONDUCTORS

VERFAHREN ZUR HERSTELLUNG ELEKTRISCHER LEITER

PROCÉDÉ DE FABRICATION DE CONDUCTEURS ÉLECTRIQUES


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 13.02.2012 US 201213372155

(43)Date of publication of application:
24.12.2014 Bulletin 2014/52

(73)Proprietor: TE Connectivity Corporation
Berwyn, PA 19312 (US)

(72)Inventors:
  • SULLIVAN MALERVY, Mary, Elizabeth
    Downingtown, Pennsylvania 19335 (US)
  • HILTY, Robert, Daniel
    Sunnyvale, California 94087 (US)
  • MARTENS, Rodney, Ivan
    Mechanicsburg, Pennsylvania 17050 (US)
  • ZHENG, Min
    San Francisco, California 94107 (US)
  • HEMOND, Jessica, Henderson, Brown
    Mifflintown, Pennsylvania 17059 (US)
  • LIU, Zhengwei
    Sugar Land, Texas 77479 (US)

(74)Representative: Bankes, Stephen Charles Digby et al
Baron Warren Redfern 1000 Great West Road
Brentford TW8 9DW
Brentford TW8 9DW (GB)


(56)References cited: : 
WO-A1-2011/074987
US-A1- 2011 006 425
US-A1- 2010 203 340
US-A1- 2011 198 558
  
  • LOYD ET AL.: "A Preliminary Investigation of Graphite, Graphene and Carbon Nanotubes as Solid State Lubricants", PROCEEDINGS OF THE 2011 IEEE 57TH HOLM CONFERENCE ON ELECTRICAL CONTACTS, 11 September 2011 (2011-09-11), - 14 September 2011 (2011-09-14), pages 1-9, XP002695919, DOI: 10.1109/HOLM.2011.6034776 ISBN: 978-1-61284-650-7
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description


[0001] The subject matter herein relates generally to methods of manufacturing electrical conductors.

[0002] Electrical conductors have many forms, such as a contact, a terminal, a pin, a socket, an eye-of-needle pin, a micro-action pin, a compliant pin, a wire, a cable braid, a trace, a pad and the like. Such electrical conductors are used in many different types of products or devices, including electrical connectors, cables, printed circuit boards, and the like. The metals used in the electrical conductors are susceptible to corrosion, diffusion or other reactions, limiting their use or requiring protective coatings. For example, when copper or copper alloy electrical conductors are used, such conductors are susceptible to corrosion. A gold surface layer is typically applied to the copper as a corrosion inhibitor. However, the gold and copper materials suffer from diffusion and typically a diffusion barrier, such as nickel is deposited between the copper and gold layers.

[0003] Corrosion of base metals is detrimental to the conductor interface and signal integrity. Current plating methods used to mitigate corrosion often leave a porous surface, resulting in oxidation and corrosion of the underlying surface. Additionally, some surface layers suffer from problems associated with friction, stiction and other contact forces, limiting application of the conductors.

[0004] The publication "A Preliminary Investigation of Graphite, Graphene and Carbon Nanotubes as Solid State Lubricants" by Loyd et al. discloses the use of graphene as surface coating and lubricant on standard contact finishes.

[0005] A need remains for an electrical conductor that addresses the aforementioned problems and other shortcomings associated with traditional electrical conductors.

[0006] According to the present invention, a method of manufacturing an electrical conductor is provided including providing an electrically conductive substrate layer, depositing a surface layer on the substrate layer and depositing a graphene layer on the substrate layer characterized in that the surface layer includes pores that expose the substrate layer and the graphene layer is deposited within the pores thereby to plug said pores, after the surface layer is deposited on the substrate layer.

[0007] Optionally, the formed graphene deposits may include processing the electrical conductor using a chemical vapor deposition (CVD) process using an organic compound precursor and heat of sufficient temperature to facilitate graphene growth on the metal compound comprising the substrate layer. The chemical vapor deposition process may use methane at a temperature that promotes graphene growth on the exposed substrate layer. The forming of the graphene deposits may include subjecting the electrical conductor to conditions having a preference for graphene growth on the substrate layer as compared to the surface layer. The forming of the graphene deposits may include depositing a graphene layer between the substrate layer and the surface layer that spans across the pores.

[0008] The invention will now be described by way of example with reference to the accompanying drawings wherein:

Figure 1 is a cross sectional view of a portion of an electrical conductor formed in accordance with an exemplary embodiment.

Figure 2 is a cross sectional view of a portion of the electrical conductor with graphene barriers.

Figure 3 is a cross sectional view of a portion of the electrical conductor with graphene barriers.

Figure 4 illustrates the electrical conductor having graphene barriers.

Figure 5 illustrates the electrical conductor having graphene barriers.

Figure 6 illustrates the electrical conductor having graphene barriers.

Figure 7 is a flow chart showing an exemplary method of manufacture of an electrical conductor.



[0009] Figure 1 is a cross sectional view of a portion of an electrical conductor 100 formed in accordance with an exemplary embodiment. The electrical conductor 100 may be any type of electrical conductor, such as a contact, a terminal, a pin, a socket, an eye-of-the-needle pin, a micro-action pin, a compliant pin, a wire, a cable braid, a trace, a pad and the like. The electrical conductor 100 may form part of an electrical connector, a cable, a printed circuit board and the like.

[0010] In an exemplary embodiment, the electrical conductor 100 is a multi-layered structure having a substrate layer 102 and a surface layer 104 that together define a workpiece 105. The workpiece 105 is processed to form graphene on select layers and/or at select locations of the workpiece 105 to enhance the performance of the electrical conductor. The surface layer 104 provides a corrosion-resistant electrically conductive layer on the substrate layer 102. For example, the surface layer 104 may include a metal compound such as gold, silver, tin, palladium, nickel, palladium-nickel, platinum and the like. The surface layer 104 is generally a thin layer. The surface layer 104 may be deposited on the substrate layer 102 by any known process, such as plating. Optionally, the surface layer 104 may be deposited directly on the underlying substrate layer 102. Alternatively, one or more other layers may be provided between the surface layer 104 and the substrate layer 102, such as a graphene layer.

[0011] The substrate layer 102 may be a multi-layered structure. In the illustrated embodiment, the substrate layer 102 includes a base substrate layer 106 and a barrier substrate layer 108 deposited on the base substrate layer 106. Optionally, the base substrate layer 106 and/or the barrier substrate layer 108 may be a multi-layered structure. The surface layer 104 and the substrate layers 102 together define a stackup of layers. The graphene may be provided at any or all interfaces between the layers and/or at select locations of the stackup to enhance the performance of the electrical conductor.

[0012] In an exemplary embodiment, the base substrate layer 106 is electrically conductive and includes a metal compound, such as a copper or a copper alloy. Other metal compounds for the base substrate layer 106 may include nickel, nickel alloy, steel, steel allow, aluminum, aluminum alloy, palladium-nickel, tin, tin alloy, cobalt, carbon, graphite, graphene, carbon-based fabric, or any other conductive material. The barrier substrate layer 108 is electrically conductive and includes a metal compound, such as nickel or a nickel alloy. Other metal compounds for the barrier substrate layer 108 include other metal or conductive material such as copper, gold, silver, cobalt, tungsten, platinum, palladium, or alloys of such. The barrier substrate layer 108 provides a diffusion barrier between the base substrate layer 106 and the surface layer 104, such as when such layers are copper and gold or other metal compounds that have diffusion problems. The barrier substrate layer 108 provides mechanical backing for the surface layer 104, which may be relatively thin, improving its wear resistance. The barrier substrate layer 108 reduces the impact of pores present in the surface layer 104. The barrier substrate layer 108 may be deposited on the base substrate layer 106 by any known process, such as plating. Optionally, the barrier substrate layer 108 may be deposited directly on the underlying base substrate layer 106. Alternatively, one or more other layers may be provided between the barrier substrate layer 108 and the base substrate layer 106, such as a graphene layer.

[0013] The barrier substrate layer 108 may include pores 110 that expose the base substrate layer 106. The pores 110 are formed during the depositing process. For example, the pores 110 may form at triple points or grain boundaries of the base substrate layer 106. The pores 110 expose the base substrate layer 106, which may lead to corrosion of the base substrate layer 106 if left exposed. The pores 110 have a bottom 112, exposing the base substrate layer 106, and sides 114 extending from the bottom 112 to a top 116 of the barrier substrate layer 108 (the terms bottom and top are relative to a particular orientation of the electrical conductor and more generally constitute interior and exterior, respectively). The sides 114 are exposed within the pores 110. While the pores 110 are represented graphically in Figure 1 as being rectangular, it is realized that the pores 110 may have any shape. For example, the sides 114 may be non-planar and may be irregular in shape.

[0014] The surface layer 104 may include pores 120 that expose the substrate layer 102. The pores 120 may be formed during the depositing process. For example, the pores 120 may form at the pores 110. The pores 120 expose the substrate layer 102, which may lead to corrosion if left exposed. The pores 120 have an open bottom 122 along the interface between the surface layer 104 and the substrate layer 102. The pores 120 have sides 124 extending from the bottom 122 to a top 126 of the surface layer 104. The sides 124 are exposed within the pores 120.

[0015] Figure 2 is a cross sectional view of a portion of the electrical conductor 100 with graphene barriers 130 to inhibit corrosion. The graphene barriers 130 may be electrically conductive. The graphene barriers 130 are deposited on the substrate layer 102. In the illustrated embodiment, the graphene barriers 130 are provided on the base substrate layer 106 to inhibit corrosion of the base substrate layer 106 (e.g. copper layer). In an exemplary embodiment, the graphene barriers 130 are grown on the exposed portion of the base substrate layer 106. For example, the electrical conductor 100 is processed to grow the graphene barriers 130 in select locations (e.g. on the exposed base substrate layer 106). The graphene barriers 130 constitute graphene deposits, generally indicated by reference numeral 132. The graphene deposits 132 plug the pores 110, 120. The graphene deposits 132 cover the bottoms 112 of the pores 110 below the pores 120. The graphene deposits 132 may constitute plugs for the pores and may be referred to hereinafter as plugs 132.

[0016] In an exemplary embodiment, the graphene barriers 130 may be formed during a chemical vapor deposition (CVD) process in the presence of an organic compound, such as gaseous methane, at a high temperature, such as approximately 800°C. Deposition mechanisms may also include electron beam, microwave or other process within the vaporous atmosphere. Other processes may be used to deposit the graphene barriers 130, such as laser deposition, plasma deposition or other techniques or processes. Optionally, the graphene barriers 130 may be 1 atomic layer thick on the base substrate layer 106. Alternatively, the graphene barriers 130 may be thicker. The graphene barriers 130 provide corrosion resistance.

[0017] The graphene barriers 130 may be deposited only on the exposed portions of the base substrate layer 106. For example, the metal compound of the base substrate layer 106 may be used as a catalyst during the CVD process (or other process) to promote graphene growth at the interface with the base substrate layer 106 as compared to other layers, such as the barrier substrate layer 108 or the surface layer 104. Optionally, the CVD process may be controlled to promote graphene growth at such interface as opposed to interfaces with other metal compounds. For example, the type of organic compound or gas precursor used, the pressure of the gas precursor used, the flow rate of the gas precursor, the temperature of the process, or other factors may promote graphene growth on one metal as compared to other metals. As such, the graphene barriers 130 may be selectively deposited on the electrical conductor 100 as opposed to a blanket covering of the entire electrical conductor 100, or particular layer of the electrical conductor 100.

[0018] In alternative embodiments, the CVD process may be controlled to promote graphene growth on more than one type of metal as compared to other types of metals. For example, the CVD process may be controlled to promote graphene growth on copper and nickel, but not gold, such that the exposed portions of the barrier substrate layer 108 and the base substrate layer 106 in the pores 110 are covered by graphene, but the surface layer 104 is not covered by graphene. Such embodiment is shown in more detail in Figure 3.

[0019] Figure 3 is a cross sectional view of a portion of the electrical conductor 100 with graphene barriers 140 to inhibit corrosion. The graphene barriers 140 may be electrically conductive. The graphene barriers 140 are deposited on the substrate layer 102. In the illustrated embodiment, the graphene barriers 140 are provided on the base substrate layer 106 and/or the barrier substrate layer 108 to inhibit corrosion. The graphene barriers 140 are grown on the exposed portion of the base substrate layer 106 and the barrier substrate layer 108. For example, the graphene barriers 140 are grown on the sides 114 of the pores 110 and the bottom 122 of the pores 120 along the barrier substrate layer 108 to grow the graphene barriers 140 in select locations. The graphene barriers 140 constitute graphene deposits, generally indicated by reference numeral 142. The graphene deposits 142 plug the pores 110. The graphene deposits 142 cover the bottoms 112 of the pores 110. The graphene deposits 142 may be formed in a similar manner as the graphene deposits 132 (shown in Figure 2). Optionally, the graphene deposits 142 may entirely fill the pores 110 and/or 120. The graphene deposits 142 may constitute plugs for the pores and may be referred to hereinafter as plugs 142.

[0020] In alternative embodiments, the electrical conductor 100 may include graphene layers that cover the entire surfaces of one or more layers in addition to having the graphene deposits 132 or 142 or as an alternative to having the graphene deposits 132 or 142. Figure 4 illustrates the electrical conductor 100 having a graphene layer 150 deposited on the base substrate layer 106 between the base substrate layer 106 and the barrier substrate layer 108. Figure 5 illustrates the electrical conductor 100 having a graphene layer 152 deposited on the barrier substrate layer 108 between the barrier substrate layer 108 and the surface layer 104. Figure 6 illustrates the electrical conductor having a graphene layer 154 deposited on the surface layer 104. The graphene layers 150, 152, 154 define graphene barriers. Optionally, the electrical conductor 100 may include more than one graphene layer, such as the graphene layers 150 and 152, the graphene layers 150 and 154, the graphene layers 152 and 154 or the graphene layers 150, 152 and 154.

[0021] In an exemplary embodiment, the graphene layers 150, 152, 154 entirely cover the top surfaces of the base substrate layer 106, the barrier substrate layer 108 and the surface layer 104, respectively. The pores 110 in the barrier substrate layer 108 expose the graphene layer 150. The pores 120 in the surface layer 104 expose the graphene layers 150 and/or 152. The graphene layer 154 covers the pores 120 and/or 110. The exposed portions of the graphene layers operate as corrosion barriers for the electrical conductor 100 by providing a barrier between the base substrate layer 106 and the environment to inhibit oxygen atoms from interacting with the metal compounds of the base substrate layer 106.

[0022] In an exemplary embodiment, the graphene layers 150, 152 operate as diffusion barriers to inhibit diffusion between the base substrate layer 106 and the surface layer 104. Optionally, the graphene layer 150 may replace the barrier substrate layer 108, acting as the diffusion barrier between the base substrate layer 106 and the surface layer 104.

[0023] In an exemplary embodiment, the graphene layer 154 is the outermost layer of the electrical conductor 100. The graphene layer 154 may reduce friction on the outermost surface of the electrical conductor 100, which may make mating of the electrical conductor 100 easier. The graphene layer 154 may reduce stiction of the surface layer 104. The reduction in stiction may allow use of the electrical conductor 100 in fields or devices that previously were unsuitable for electrical conductors 100 having problems with stiction and/or cold welds, such as electrical conductors having the outermost layer being a gold layer. For example, in microelectromechanical systems (MEMS) switches, stiction is a problem when a gold layer is the outermost layer of the electrical conductor. Coating the surface layer 104 with the graphene layer 154 reduces the stiction of the electrical conductor 100, making the electrical conductor suitable for use in MEMS switches.

[0024] The graphene layers 152, 154 cover the pores 110, 120, respectively. Optionally, the graphene layers 152, 154 may at least partially fill the pores 110 and/or 120. The graphene layers 152, 154 may define graphene deposits that at least partially plug the pores 110 and/or 120.

[0025] Figure 7 is a flow chart showing an exemplary method of manufacture of an electrical conductor, such as the electrical conductor 100. The method includes providing 200 a base substrate layer, such as the base substrate layer 106. The base substrate layer may be a copper or copper alloy layer.

[0026] Optionally, the method may include forming 202 a graphene layer, such as the graphene layer 150, on the base substrate layer. The graphene layer may be formed by a CVD process or another process. The graphene layer may completely cover the base substrate layer or may selectively cover portions of the base substrate layer. The graphene layer may be formed by growing or depositing one or more graphene layers on the base substrate layer. The base substrate layer may act as a catalyst to promote selective growth of the graphene thereon.

[0027] The method includes depositing 204 a barrier substrate layer, such as the barrier substrate layer 108, on the base substrate layer. The barrier substrate layer may be directly deposited on the base substrate layer. Alternatively, one or more other layers, such as the graphene layer, may be layered between the barrier substrate layer and the base substrate layer. The barrier substrate layer may be deposited by plating or by other known processes that apply the barrier substrate layer on the base substrate layer.

[0028] Optionally, the method may include forming 206 a graphene layer, such as the graphene layer 152, on the barrier substrate layer. The graphene layer may be formed by a CVD process or another process. The graphene layer may completely cover the barrier substrate layer or may selectively cover portions of the barrier substrate layer. The graphene layer may cover any pores in the barrier substrate layer. The graphene layer may at least partially fill any pores in the barrier substrate layer. The graphene layer may be formed by growing or depositing one or more graphene layers on the barrier substrate layer. The barrier substrate layer may act as a catalyst to promote growth of the graphene thereon.

[0029] The method includes depositing 208 a surface layer, such as the surface layer 104, on the barrier substrate layer. The surface layer may be directly deposited on the surface layer. Alternatively, one or more other layers, such as the graphene layer 152, may be layered between the barrier substrate layer and the surface layer. The surface layer may be deposited by plating or by other known processes that apply the surface layer on the barrier substrate layer.

[0030] Optionally, the method may include forming 210 a graphene layer, such as the graphene layer 154, on the surface layer. The graphene layer may be formed by a CVD process or another process. The graphene layer may completely cover the surface layer or may selectively cover portions of the surface layer. The graphene layer may cover any pores in the surface layer. The graphene layer may at least partially fill any pores in the surface layer. The graphene layer may be formed by growing one or more graphene layers on the surface layer. The surface layer may act as a catalyst to promote growth of the graphene thereon.

[0031] The method includes forming 212 graphene deposits, such as the graphene deposits 132 and/or 142, in the pores in the barrier substrate layer and/or the pores in the surface layer. The graphene deposits may be formed by a CVD process or another process. For example, the workpiece defined by the various layers of the electrical conductor is processed to form the graphene in select areas. The graphene deposits may be formed on the exposed metal of the barrier substrate layer and/or the base substrate layer in the pores in the barrier substrate layer. The graphene deposits may completely cover the exposed portion of the base substrate layer and/or the sides of the pores in the barrier substrate layer. The graphene deposits may at least partially fill any pores in the barrier substrate layer. The graphene deposits may be formed by growing one or more graphene layers on the exposed metal of the substrate layer(s). The exposed metal may act as a catalyst to promote growth of the graphene thereon as compared to the exposed metal of the surface layer.

[0032] In an exemplary embodiment, the graphene of the layers or the deposits are formed during a CVD process in the presence of an organic compound, such as gaseous methane, at a high temperature, such as approximately 800°C. The location of the graphene growth may be controlled, such as by using certain metals as catalysts to promote growth where such metals are exposed. For example, the metal exposed in the pores may be used as the catalyst to promote graphene growth at such interfaces as compared to other layers that do not have such metals exposed. The type of organic compound or gas precursor used, the pressure of the gas precursor used, the flow rate of the gas precursor, the temperature of the process, or other factors may promote graphene growth on one metal as compared to other metals.


Claims

1. A method of manufacturing an electrical conductor (106), the method comprising:

providing an electrically conductive substrate layer (102);

depositing a surface layer (104) on the substrate layer, and

depositing a graphene layer (130 or 140) on the substrate layer

characterized in that the surface layer (104) includes pores (120) that expose the substrate layer (102) and the graphene layer (130 or 140) is deposited within the pores (120) thereby to plug said pores (120), after the surface layer (104) is deposited on the substrate layer.


 
2. The method of claim 1, wherein a graphene layer (152) is deposited directly on the substrate layer (102) prior to the deposit of the surface layer (104).
 
3. The method of claim 1, wherein a graphene layer (154) is deposited directly on the surface layer (104).
 
4. The method of claim 1. wherein the substrate layer (102) includes a base substrate layer (106) and a barrier substrate layer (108) deposited on the base substrate layer, the surface layer (104) being deposited on the barrier substrate layer, wherein a graphene layer (152) is deposited directly on the barrier substrate layer prior to the deposit of the surface layer on the barrier substrate layer.
 
5. The method of claim 1, wherein the substrate layer (102) includes a base substrate layer (106) and a barrier substrate layer (108) deposited on the base substrate layer, the surface layer (104) being deposited directly on the barrier substrate layer, wherein a graphene layer (150) is deposited directly on the base substrate layer prior to the deposit of the barrier substrate layer on the base substrate layer.
 
6. The method of claim 1, wherein the substrate layer (102) includes a base substrate layer (106) and a barrier substrate layer (108) deposited on the base substrate layer, the surface layer (104) being deposited on the barrier substrate layer, wherein the graphene layer (140) is deposited directly on at least one of the barrier substrate layer (108) and the base substrate layer (106) after the surface layer (104) is deposited on the barrier substrate layer (108).
 
7. The method of claim 1, wherein the substrate layer (102) includes a base substrate layer (106) and a barrier substrate layer (108) deposited on the base substrate layer, the surface layer (104) being deposited on the barrier substrate layer, the layers forming a stackup, the graphene layer (150, 152, 154) being deposited at any or all interfaces between the layers of the stackup.
 
8. The method of claim 1, wherein said depositing a graphene layer (140) comprises depositing graphene plugs (142) in pores (120) of the surface layer (104) by processing the electrical conductor (100) using a chemical vapor deposition process using an organic compound precursor and heat of sufficient temperature to facilitate graphene growth on the metal compound comprising the substrate layer (102).
 


Ansprüche

1. Verfahren zur Herstellung eines elektrischen Leiters (106), wobei das Verfahren Folgendes beinhaltet:

Bereitstellen einer elektrisch leitfähigen Substratschicht (102);

Absetzen einer Oberflächenschicht (104) auf die Substratschicht; und

Absetzen einer Graphenschicht (130 oder 140) auf die Substratschicht,

dadurch gekennzeichnet, dass die Oberflächenschicht (104) Poren (120) aufweist, die die Substratschicht (102) exponieren, und die Graphenschicht (130 oder 140) in die Poren (120) abgesetzt wird, um dadurch die genannten Poren (120) zu verschließen, nachdem die Oberflächenschicht (104) auf die Substratschicht abgesetzt wurde.


 
2. Verfahren nach Anspruch 1, wobei eine Graphenschicht (152) vor dem Absetzen der Oberflächenschicht (104) direkt auf die Substratschicht (102) abgesetzt wird.
 
3. Verfahren nach Anspruch 1, wobei eine Graphenschicht (154) direkt auf die Oberflächenschicht (104) abgesetzt wird.
 
4. Verfahren nach Anspruch 1, wobei die Substratschicht (102) eine Basissubstratschicht (106) und eine auf die Basissubstratschicht abgesetzte Barrierensubstratschicht (108) beinhaltet, wobei die Oberflächenschicht (104) auf die Barrierensubstratschicht abgesetzt wird, wobei eine Graphenschicht (152) vor dem Absetzen der Oberflächenschicht auf die Barrierensubstratschicht direkt auf die Barrierensubstratschicht abgesetzt wird.
 
5. Verfahren nach Anspruch 1, wobei die Substratschicht (102) eine Basissubstratschicht (106) und eine auf die Basissubstratschicht abgesetzte Barrierensubstratschicht (108) beinhaltet, wobei die Oberflächenschicht (104) direkt auf die Barrierensubstratschicht abgesetzt wird, wobei eine Graphenschicht (150) vor dem Absetzen der Barrierensubstratschicht auf die Basissubstratschicht direkt auf die Basissubstratschicht abgesetzt wird.
 
6. Verfahren nach Anspruch 1, wobei die Substratschicht (102) eine Basissubstratschicht (106) und eine auf die Basissubstratschicht abgesetzte Barrierensubstratschicht (108) beinhaltet, wobei die Oberflächenschicht (104) auf die Barrierensubstratschicht abgesetzt wird, wobei die Graphenschicht (140) nach dem Absetzen der Oberflächenschicht (104) auf die Barrierensubstratschicht (108) direkt auf die Barrierensubstratschicht (108) und/oder die Basissubstratschicht (106) abgesetzt wird.
 
7. Verfahren nach Anspruch 1, wobei die Substratschicht (102) eine Basissubstratschicht (106) und eine auf die Basissubstratschicht abgesetzte Barrierensubstratschicht (108) beinhaltet, wobei die Oberflächenschicht (104) auf die Barrierensubstratschicht abgesetzt wird, wobei die Schichten einen Stapel bilden, wobei die Graphenschicht (150, 152, 154) auf beliebige oder alle Grenzflächen zwischen den Schichten des Stapels abgesetzt wird.
 
8. Verfahren nach Anspruch 1, wobei das genannte Absetzen einer Graphenschicht (140) das Absetzen von Graphenpropfen (142) in Poren (120) der Oberflächenschicht (104) durch Verarbeiten des elektrischen Leiters (100) mit einem chemischen Gasabscheidungsprozess mit einem organischen Verbindungsvorläufer und Wärme von ausreichender Temperatur beinhaltet, um Graphenwachstum auf der Metallverbindung mit der Substratschicht (102) zu fördern.
 


Revendications

1. Procédé de fabrication d'un conducteur électrique (106), le procédé comprenant :

la mise à disposition d'une couche de substrat électriquement conductrice (102) ;

le dépôt d'une couche superficielle (104) sur la couche de substrat ; et

le dépôt d'une couche de graphène (130 ou 140) sur la couche de substrat ;

caractérisé en ce que la couche superficielle (104) inclut des pores (120) qui exposent la couche de substrat (102) et la couche de graphène (130 ou 140) est déposée au sein des pores (120) bouchant ainsi lesdits pores (120), une fois que la couche superficielle (104) est déposée sur la couche de substrat.


 
2. Procédé de la revendication 1, dans lequel une couche de graphène (152) est déposée directement sur la couche de substrat (102) avant le dépôt de la couche superficielle (104) .
 
3. Procédé de la revendication 1, dans lequel une couche de graphène (154) est déposée directement sur la couche superficielle (104).
 
4. Procédé de la revendication 1, dans lequel la couche de substrat (102) inclut une couche de substrat de base (106) et une couche de substrat barrière (108) déposée sur la couche de substrat de base, la couche superficielle (104) étant déposée sur la couche de substrat barrière, dans lequel une couche de graphène (152) est déposée directement sur la couche de substrat barrière avant le dépôt de la couche superficielle sur la couche de substrat barrière.
 
5. Procédé de la revendication 1, dans lequel la couche de substrat (102) inclut une couche de substrat de base (106) et une couche de substrat barrière (108) déposée sur la couche de substrat de base, la couche superficielle (104) étant déposée directement sur la couche de substrat barrière, dans lequel une couche de graphène (150) est déposée directement sur la couche de substrat de base avant le dépôt de la couche de substrat barrière sur la couche de substrat de base.
 
6. Procédé de la revendication 1, dans lequel la couche de substrat (102) inclut une couche de substrat de base (106) et une couche de substrat barrière (108) déposée sur la couche de substrat de base, la couche superficielle (104) étant déposée sur la couche de substrat barrière, dans lequel la couche de graphène (140) est déposée directement sur au moins une couche parmi la couche de substrat barrière (108) et la couche de substrat de base (106) une fois que la couche superficielle (104) est déposée sur la couche de substrat barrière (108).
 
7. Procédé de la revendication 1, dans lequel la couche de substrat (102) inclut une couche de substrat de base (106) et une couche de substrat barrière (108) déposée sur la couche de substrat de base, la couche superficielle (104) étant déposée sur la couche de substrat barrière, les couches formant un empilement, la couche de graphène (150, 152, 154) étant déposée sur l'une quelconque ou toutes les interfaces entres les couches de l'empilement.
 
8. Procédé de la revendication 1, dans lequel ledit dépôt d'une couche de graphène (140) comprend le dépôt de bouchons en graphène (142) dans des pores (120) de la couche superficielle (104) en traitant le conducteur électrique (100) grâce à l'utilisation d'un processus de dépôt chimique en phase vapeur en utilisant un précurseur de composé organique et une chaleur d'une température suffisante pour faciliter la croissance du graphène sur le composé métallique comprenant la couche de substrat (102).
 




Drawing












REFERENCES CITED IN THE DESCRIPTION



This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Non-patent literature cited in the description