(19)
(11)EP 2 837 000 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
25.03.2020 Bulletin 2020/13

(21)Application number: 13775893.4

(22)Date of filing:  11.04.2013
(51)Int. Cl.: 
G11C 13/00  (2006.01)
G11C 7/12  (2006.01)
(86)International application number:
PCT/US2013/036209
(87)International publication number:
WO 2013/155326 (17.10.2013 Gazette  2013/42)

(54)

APPARATUSES AND METHODS FOR PROVIDING SET AND RESET VOLTAGES AT THE SAME TIME

VORRICHTUNGEN UND VERFAHREN ZUR GLEICHZEITIGEN BEREITSTELLUNG VON EINGESTELLTEN UND RÜCKGESETZTEN SPANNUNGEN

DISPOSITIFS ET PROCÉDÉS PERMETTANT DE FOURNIR SIMULTANÉMENT DES TENSIONS D'INITIALISATION ET DE RÉINITIALISATION


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 12.04.2012 US 201213445577

(43)Date of publication of application:
18.02.2015 Bulletin 2015/08

(73)Proprietor: Micron Technology, Inc.
Boise, ID 83716 (US)

(72)Inventors:
  • TIBURZI, Marco-Domenico
    I-67051 Avezzano (IT)
  • MAROTTA, Giulio-Giuseppe
    I-02043 Contigliano (IT)

(74)Representative: Granleese, Rhian Jane et al
Marks & Clerk LLP 15 Fetter Lane
London EC4A 1BW
London EC4A 1BW (GB)


(56)References cited: : 
US-A1- 2008 259 678
US-A1- 2009 135 637
US-A1- 2010 103 724
US-A1- 2010 321 978
US-A1- 2012 020 141
US-A1- 2009 039 332
US-A1- 2010 080 037
US-A1- 2010 296 330
US-A1- 2012 014 163
US-A1- 2012 020 141
  
  • HOSOI Y ET AL: "High Speed Unipolar Switching Resistance RAM (RRAM) Technology", ELECTRON DEVICES MEETING, 2006. IEDM '06. INTERNATIONAL, IEEE, PI, 1 December 2006 (2006-12-01), pages 1-4, XP031078327, DOI: 10.1109/IEDM.2006.346732 ISBN: 978-1-4244-0438-4
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

Background



[0001] Some semiconductor devices include variable state materials. For example, memory cells such as resistive random access memory (RRAM) cells include a variable state material whose state can be changed from a high resistance state to a low resistance state and back again. Variable state materials are often non-volatile and can be configured in memory cells having a small form factor. However, in some configurations, variable state materials can exhibit longer program times than other storage technologies such as flash memory. Semiconductor device designs that provide improvements in performance, such as speed and reliability, are desired.

[0002] US2009/0135637A, US2012/014163A, US2010/080037 and US2012/020141A each disclose a memory device whose memory cells include a variable state material, and which has a driver to provide set and reset voltages to different cells at the same time.

[0003] US2010/296330A discloses two drivers coupled to a resistive memory array to apply set and reset voltages concurrently to different cells of the array.

[0004] The invention is in the memory device of claim 1 and the method of claim 6.

Brief Description of the Drawings



[0005] 

FIG. 1 shows a block diagram setting a first state of a memory cell component according to an embodiment of the invention.

FIG. 2 shows a block diagram setting a second state of the memory cell component from Figure 1, according to an embodiment of the invention.

FIG. 3 shows a voltage-current diagram of a variable resistive material according to an embodiment of the invention.

FIG. 4 shows a circuit diagram of a memory device according to an embodiment of the invention.

FIG. 5 shows a voltage table according to an embodiment of the invention.

FIG. 6 shows a block diagram of a memory device according to an embodiment of the invention.

FIG. 7 shows an information handling system, including a memory device, according to an embodiment of the invention.


Detailed Description



[0006] In the following detailed description of various embodiments of the invention, reference is made to the accompanying drawings that form a part hereof and in which are shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made.

[0007] Figure 1 shows an example component 100 of a memory cell according to an embodiment of the invention. A variable state material 102 is shown located between a first electrode 104 and a second electrode 106. Although only the variable state material 102 is shown, in selected examples, other structures such as intervening material layers may be included along with the variable state material located between the first and second electrodes 104, 106. In one example, the variable state material 102 is a resistance switching material. Other examples of variable state materials 102 may include magnetic switching materials, or other switching materials having a detectable electronic state.

[0008] In one example, when a voltage is applied in a direction 110 across the variable state material 102, the state of the variable state material 102 is changed from a high resistance state 103 to a low resistance state 105. In an array of memory cells including a component such as component 100, the high resistance state may represent a digital bit of data, such as a logic 1 or a logic 0 value. Selection circuitry, such as row and column selection circuitry, may be used to select a desired memory cell (including a variable state material 102) from an array of cells, to query and/or alter the resistance state, thus providing data recall and storage capability.

[0009] A number of mechanisms can be used to change the physical state (and therefore, the resistance) of the variable state material 102. In one example, the variable state material 102 is changed from a substantially amorphous state to a substantially crystalline state. In another example, upon application of the voltage, one or more conductive filaments are formed within the variable state material 102 that bridge the distance between the first electrode 104 and the second electrode 106. In various mechanisms, the state change is reversible.

[0010] Figure 2 shows the example component 100 from Figure 1, in the low resistance state 105. By application of a second voltage 112 in an opposite direction from that shown in Figure 1, the variable state material 102 is reversed from the low resistance state 105 back to the high resistance state 103. In this way, the physical state (and thus the resistance) of the variable state material 102 can be changed as desired to occupy a selected one of at least two possible states.

[0011] Figure 3 shows an example voltage/current diagram 300 of a bipolar variable state material. The diagram shows voltage on the X-axis 302 and current on the Y-axis 304. In operation, a variable state material exhibits high resistance behavior along a high resistance portion 306 of the illustrated curve 301. If an applied voltage is within a first voltage range 310, or a second voltage range 312 with respect to a reference voltage level 318, the variable state material remains within the high resistance portion 306 of the curve 301. If an applied voltage is greater than or equal to a third voltage 314 (which is in turn greater than the upper limit of the voltage range 310) with respect to the reference voltage level 318, the variable state material exhibits low resistance, as illustrated by point 303 on the curve 301 and moves to a low resistance portion 308 of the curve 301. The variable state material will remain in the low resistance portion 308 of the curve 301 until an applied voltage magnitude is greater than or equal to a fourth voltage 316 (which is in turn greater than the magnitude of the voltage range 312) with respect to the reference voltage level 318. Then the variable state material will again returns to the high resistance portion 306 of the curve 301.

[0012] Although Figure 3 illustrates a bipolar variable state material behavior, some devices described herein may use a unipolar variable state material. In a unipolar variable state material, the state may be changed by application of different magnitudes of applied voltage in the same direction. In one bipolar example, the reference voltage 318 is approximately zero volts, with the third voltage 314 and fourth voltage 316 being substantially equal in magnitude, and opposite in polarity. For example the third voltage 314 may be approximately 1 volt, and the fourth voltage 316 may be approximately -1 volt.

[0013] In a positive only voltage range example, the reference voltage 318 may be approximately 3 volts, with the third voltage 314 and fourth voltage 316 of the same magnitude, as defined by a voltage offset. For example the third voltage 314 may be approximately 4 volts (reference voltage 318 plus a voltage offset of about 1 volt), and the fourth voltage 316 may be approximately 2 volts (reference voltage 318 minus a voltage offset of about 1 volt).

[0014] Variable state materials may be formed into relatively small, non-volatile memory cells. In one example, a one transistor, one resistor (1T1R) configuration is possible, in contrast to transistor-based static random access memory (SRAM) cells that use six transistors.

[0015] Figure 4 shows an example circuit diagram of an apparatus 400 including a variable state material according to an embodiment of the invention. In one example, the apparatus 400 comprises a memory device. As used herein, "apparatus" is used broadly to refer to any of a number of different structures, including, but not limited to, systems, devices, circuits, chip assemblies, etc. In the example of Figure 4, the apparatus 400 includes an array 402 of memory cells 410, and a driver circuit 404. In one example, the driver circuit 404 is configured to provide different voltages to different memory cells 410 in the array 402 at the same time.

[0016] At least some of the cells 410 in the array 402 include a variable state material component 412. In one example, the variable state material component 412 includes a variable state material coupled between a first electrode and a second electrode, similar to or identical to the examples described in Figures 1 and 2. Memory cells 410 in the array 402 may further include a selector device 414. In selected examples, such as cross point architecture, a selector device may not be included. In one example, the selector device 414 includes an n-type metal oxide (NMOS) transistor. In one example, the selector device 414 includes an p-type metal oxide (PMOS) transistor. Other examples of selector devices 414 may include additional circuitry, diodes, and other electronic devices.

[0017] Figure 4 further shows a number of access lines 408 coupled to selector devices 414 in the array 402. In one example, the number of access lines 408 includes a number of word lines. A source 403, and a number of data lines 406a - 406c are shown coupled to the memory cells 410 in the array 402. In one example, the number of data lines 406 includes a number of bit lines. In the example of Figure 4, the driver circuit 404 is configured as a column driver.

[0018] In one example, the driver circuit 404 is configured to provide multiple different voltages to the data lines 406a - 406c of different memory cells at the same time. The driver circuit 404 is shown including a first voltage input node 420, a second voltage input node 422, and a third voltage input node 424. Although three different voltage input nodes are shown, other configurations including two voltage input nodes, or more than three voltage input nodes are within the scope of various embodiments.

[0019] The driver circuit can also include selection circuitry 404 to selectively couple the voltage input nodes 420, 422 and 424 to different memory cells at the same time. The selection circuitry 404 can include a number of selector circuits 405a-405c that can each select any one of the voltage input nodes 420, 422, 424 and thus apply a selected voltage to one or more selected memory cells 410 in the array 402. In the example shown, the selector circuits 405a-405c are individually selectable to apply different voltages to different memory cells 410 in the array 402. In one example, the different voltages are discrete voltages that are substantially constant over the time that they are applied. In one example, the different voltages on the voltage input nodes 420, 422, 424 may be variable over a selected length of time.

[0020] In one example the voltage input nodes 420, 422, 424 are configured as a set voltage node, a reset voltage node, and an inhibit voltage node. Using Figure 3 as an example, the reference voltage 318 comprise an inhibit voltage. Memory cells 410 in the array 402 that receive the inhibit voltage will not be programmed to a high resistance state, or reversed from a high resistance state to a low resistance state.

[0021] A set voltage may include an inhibit voltage plus an offset voltage, such as the third voltage 314. A reset voltage may include an inhibit voltage minus an offset voltage, such as the fourth voltage 316.

[0022] For example, a first selector circuit 405a is shown selectively coupling the second voltage input node 422 to data line 406a. In one example the second voltage input node 422 includes a set voltage. In one example, the set voltage is approximately equal to 4 volts.

[0023] The second selector circuit 405b is shown selectively coupling the third voltage input node 424 to data line 406b. In one example the third voltage input node 424 includes a reset voltage. In one example, the reset voltage is approximately equal to 2 volts.

[0024] The third selector circuit 405c is shown selectively coupling the first voltage input node 420 to data line 406c. In one example the first voltage input node 420 includes an inhibit voltage. In one example, the inhibit voltage is approximately equal to 3 volts.

[0025] In operation, each of the selector circuits 405a-405c are individually selectable, and can provide any desired voltage from the voltage input lines 420, 422, 424 to any desired data line 406a - 406c at the same time. Performance of the apparatus 400 may be enhanced using the driver circuit 404 shown in Figure 4. For example, while selected cells in a given column of the array 402 are being set to a low resistance state, other selected cells in a different given column of the array 402 can be reset at the same time. Additionally, at the same time, other cells in the array 402 may have no operation performed on them as a result of an applied inhibit voltage. Data programming operation times may be reduced by a factor of more than two times when compared to devices that are only capable of driving one voltage to the array at a time.

[0026] Figure 5 illustrates an example voltage table showing the operation of a selected data line 502, an unselected data line 504, a selected access line 506, and an unselected access line 508. In one example, a driver circuit 404 from Figure 4 drives the voltages shown in the table of Figure 5. In an example read operation, the selected data line 502 is driven to a read voltage. In one example, a read voltage is the same as the first voltage range 310 from Figure 3. Further in the example read operation, the selected access line 506 is driven to a logical high voltage, and the unselected access line 508 is driven to approximately ground. In one example, the unselected data line 504 is driven to a standby voltage.

[0027] In an example set operation, the selected data line 502 is driven to an inhibit voltage plus a voltage offset. In one example, a set voltage is the same as the third voltage 314 from Figure 3. Further in the example set operation, the selected access line 506 is driven to a logical high voltage, and the unselected access line 508 is driven to approximately ground. In one example, the unselected data line 504 is driven to an inhibit voltage. In one example the inhibit voltage is the same as the reference voltage 318 from Figure 3.

[0028] In an example reset operation, the selected data line 502 is driven to an inhibit voltage minus a voltage offset. In one example, a reset voltage includes the fourth voltage 316 from Figure 3. Further in the example reset operation, the selected access line 506 is driven to a logical high voltage, and the unselected access line 508 is driven to approximately ground. In one example, the unselected data line 504 is driven to an inhibit voltage. In one example the inhibit voltage includes the reference voltage 318 from Figure 3.

[0029] FIG. 6 illustrates a portion of an apparatus in the form of a memory system 600 incorporating a driver circuit similar to or identical to the driver circuit 404 from Figure 4. The memory system 600 includes an array 602 of memory cells, which may comprise, for example, RRAM or other memory cells incorporating a variable state material that operates as described in various embodiments above. The memory system 600 includes a command decoder 606 that receives memory commands through a command bus 608 and generates corresponding control signals within the memory system 600 to carry out various memory operations. Row and column address signals are applied to the memory system 600 through an address bus 620 and provided to an address latch 610. The address latch then outputs a separate column address and a separate row address.

[0030] The row and column addresses are provided by the address latch 610 to selection circuitry, such as a row address decoder 622 and a column address decoder 628, respectively. The column address decoder 628 selects data lines extending through the array 602 corresponding to respective column addresses. In one example the column address decoder 628 includes a driver circuit similar to the driver circuit 404 of Figure 4. The row address decoder 622 is connected to access line driver 624 that activates respective rows of memory cells in the array 602 corresponding to received row addresses. In one example the rows of memory cells in the array 602 correspond to data lines 408 from Figure 4. The command decoder 606 responds to memory commands applied to the command bus 608 to perform various operations on the memory array 602. In particular, the command decoder 606 is used to generate internal control signals to read data from and write data to the memory array 602.

[0031] An embodiment of an apparatus in the form of an information handling system, such as a computer, is included in Figure 7 to show an embodiment of a high-level device application. Figure 7 is a block diagram of an information handling system 700 incorporating at least one chip or chip assembly 704 that includes a memory device 707 (e.g., a device similar to or identical to the apparatus 400 shown in Figure 4 and/or the apparatus 600 shown in Figure 6) according to an embodiment of the invention. The assembly 704 may also include a processor 706 and other logic 708.

[0032] In one example, the memory device 707 includes a variable state material memory device such as an RRAM. The information handling system 700 shown in Figure 7 is merely one example of a system in which the present invention can be used. Other examples include, but are not limited to, personal data assistants (PDAs), tablet computers, cameras, cellular telephones, MP3 players, aircraft, satellites, military vehicles, etc.

[0033] In this example, information handling system 700 comprises a data processing system that includes a system bus 702 to couple the various components of the system. System bus 702 provides communications links among the various components of the information handling system 700 and may be implemented as a single bus, as a combination of busses, or in any other suitable manner.

[0034] Chip assembly 704 is coupled to the system bus 702. Chip assembly 704 may include any circuit or operably compatible combination of circuits. In one embodiment, chip assembly 704 includes a processor 706 that can be of any type. As used herein, "processor" means any type of computational circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit. Multiple processors such as "multi-core" devices are also within the scope of the invention.

[0035] In one embodiment, a memory device 707, such as a memory device described in embodiments above, is included in the chip assembly 704. Those skilled in the art will recognize that a wide variety of memory device configurations may be used in the chip assembly 704. As discussed above, in selected embodiments, the memory configuration includes RRAM. In selected embodiments the memory cells are arranged in different logical configurations, such as NAND memory or NOR memory.

[0036] In one embodiment, additional logic chips 708 other than processor chips are included in the chip assembly 704. An example of a logic chip 708 other than a processor includes an analog to digital converter. Other circuits on logic chips 708 such as custom circuits, an application-specific integrated circuit (ASIC), etc. are also included in one embodiment of the invention.

[0037] Information handling system 700 may also include an external memory 711, which in turn can include one or more memory elements suitable to the particular application, such as one or more hard drives 712, and/or one or more drives that handle removable media 713 such as flash drives, compact disks (CDs), digital video disks (DVDs), and the like.

[0038] Information handling system 700 may also include a display device 709 such as a monitor, additional peripheral components 710, such as speakers, etc. and a keyboard and/or controller 714, which can include a mouse, a touchscreen interface, or any other device that permits a system user to input information into and receive information from the information handling system 700.

[0039] While a number of embodiments of the invention are described, the above lists are not intended to be exhaustive. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention as claimed. It is to be understood that the above description is intended to be illustrative and not restrictive. Combinations of the above embodiments, and other embodiments, will be apparent to those of skill in the art upon studying the above description.


Claims

1. A memory device (400), comprising:

an array (402) of resistive random access memory cells, each of the resistive random access memory cells (410) including a variable state material to represent data as the variable state;

a column driver (404) coupled to the array of resistive random access memory cells to provide set, reset, and inhibit voltages to different resistive random access memory cells in the array at the same time, wherein a source line is commonly coupled to an inhibit voltage line; and

a set node (422), a reset node (424), and an inhibit node (420) coupled to the column driver (404), wherein the reset node is associated with a reset voltage, the set node is associated with a set voltage and the inhibit node is associated with an inhibit voltage, wherein the column driver includes a plurality of individually selectable selector circuits (405a-405c) to select which of the set node (422), the reset node (424) or the inhibit node (420) to couple to the different memory cells at the same time, the selector circuits comprising, for each of a plurality of address lines, a NOT gate operable to receive a first input which, in one logic state, causes generation of an output which is operable to close a first switch to couple the address line with a first one of the set node (422), the reset node (424) or the inhibit node (420), a first AND gate operable to receive a second input and a third input which, in one logic state, cause the generation of an output which is operable to close a second switch to couple the address line with a second of the set node (422), the reset node (424) or the inhibit node (420), and a second AND gate operable to receive the third input and the inverse of the third input, to cause the generation of an output which is operable to close a third switch to couple the address line with a third of the set node (422), the reset node (424) or the inhibit node (420), the first, second and third inputs being configured so as to drive one of the switches closed to couple the address line with a corresponding one of the set node (422), the reset node (424) or the inhibit node (420), while holding the other switches open.


 
2. The memory device of claim 1, wherein the variable state material includes a resistance switching material.
 
3. The memory device of claim 1, wherein the array further includes selector devices (414) to access the resistive random access memory cells.
 
4. The memory device of claim 3, wherein the selector devices (414) include N channel transistors.
 
5. The memory device of claim 3, wherein the selector devices (414) include P channel transistors.
 
6. A method, comprising:

selecting a plurality of resistive random access memory cells each having a variable state material to represent data as the variable state;

driving reset, set, and inhibit voltages using a column driver circuit to different ones of the resistive random access memory cells in the selected plurality at the same time,

wherein driving an inhibit voltage includes driving an inhibit voltage line from a commonly coupled source line, and wherein driving the reset, set, and inhibit voltages includes coupling one of a set node, a reset node and an inhibit node to selected memory cells using a plurality of individually selectable selector circuits, the selector circuits comprising, for each of a plurality of address lines, a NOT gate operable to receive a first input which, in one logic state, causes generation of an output which is operable to close a first switch to couple the address line with a first one of the reset, set, and inhibit voltages, a first AND gate operable to receive a second input and a third input which, in one logic state, cause the generation of an output which is operable to close a second switch to couple the address line with a second of the reset, set, and inhibit voltages, and a second AND gate operable to receive the third input and the inverse of the third input, to cause the generation of an output which is operable to close a third switch to couple the address line with a third of the reset, set, and inhibit voltages, the first, second and third inputs being configured so as to drive one of the switches closed to couple the address line with a corresponding one of the reset, set, and inhibit voltages, while holding the other switches open.


 
7. The method of claim 6, wherein selecting a plurality of resistive random access memory cells comprises selecting a plurality of resistive random access memory cells using row selection circuitry.
 
8. The method of claim 6, wherein driving reset, set, and inhibit voltages to different ones of the resistive random access memory cells in the selected plurality at the same time includes driving substantially discrete voltages.
 
9. The method of claim 6, wherein the set voltage is substantially equal to the inhibit voltage plus a voltage offset, and wherein the reset voltage is substantially equal to the inhibit voltage minus the voltage offset.
 
10. The method of claim 9, wherein the inhibit voltage is approximately 3 volts, and the voltage offset is approximately one volt.
 
11. The method of claim 6, wherein the reset voltage is less than the inhibit voltage, and the inhibit voltage is less than the set voltage.
 


Ansprüche

1. Speichervorrichtung (400), umfassend:

eine Anordnung (402) von resistiven Direktzugriffspeicherzellen, wobei jede der resistiven Direktzugriffspeicherzellen (410) ein Material variablen Zustands zum Repräsentieren von Daten als den variablen Zustand enthält;

einen Spaltentreiber (404), gekoppelt an die Anordnung von resistiven Direktzugriffspeicherzellen, zum Bereitstellen von Setzen, Rücksetzen und Hemmen von Spannungen zu verschiedenen resistiven Direktzugriffspeicherzellen in der Anordnung zur selben Zeit, wobei eine Quellenleitung an eine Hemmspannungsleitung gemeinsam gekoppelt ist; und

einen Setzknoten (422), einen Rücksetzknoten (424) und einen Hemmknoten (420), gekoppelt an den Spaltentreiber (404), wobei der Rücksetzknoten mit einer Rücksetzspannung assoziiert ist, der Setzknoten mit einer Setzspannung assoziiert ist und der Hemmknoten mit einer Hemmspannung assoziiert ist, wobei der Spaltentreiber eine Vielzahl von einzeln auswählbaren Auswählschaltungen (405a-405c) zum Auswählen, welche des Setzknotens (422), des Rücksetzknotens (424) oder des Hemmknotens (420) an die verschiedenen Speicherzellen zur selben Zeit zu koppeln sind, enthält, die Auswählschaltungen umfassend, für jede einer Vielzahl von Adressleitungen, ein NOT-Gate, funktionsfähig zum Empfangen eines ersten Eingangs, der in einem logischen Zustand die Erzeugung eines Ausgangs bewirkt, der funktionsfähig ist, um einen ersten Schalter zu schließen, um die Adressleitung mit einem ersten einen des Setzknotens (422), des Rücksetzknotens (424) oder des Hemmknotens (420) zu koppeln, ein erstes AND-Gate, funktionsfähig zum Empfangen eines zweiten Eingangs und eines dritten Eingangs, die in einem logischen Zustand die Erzeugung eines Ausgangs bewirken, der funktionsfähig ist, um einen zweiten Schalter zu schließen, um die Adressleitung mit einem zweiten des Setzknotens (422), des Rücksetzknotens (424) oder des Hemmknotens (420) zu koppeln, und ein zweites AND-Gate, funktionsfähig zum Empfangen des dritten Eingangs und der Inversen des dritten Eingangs, um die Erzeugung eines Ausgangs zu bewirken, der funktionsfähig ist, um einen dritten Schalter zu schließen, um die Adressleitung mit einem dritten des Setzknotens (422), des Rücksetzknotens (424) oder des Hemmknotens (420) zu koppeln, wobei der erste, zweite und dritte Eingang konfiguriert sind, einen der geschlossenen Schalter anzusteuern, um die Adressleitung mit einem korrespondierenden einen des Setzknotens (422), des Rücksetzknotens (424) oder des Hemmknotens (420) zu koppeln, während sie die anderen Schalter geöffnet halten.


 
2. Speichervorrichtung nach Anspruch 1, wobei das Material variablen Zustands ein den Widerstand wechselndes Material enthält.
 
3. Speichervorrichtung nach Anspruch 1, wobei die Anordnung ferner Auswählvorrichtungen (414) zum Zugreifen auf die resistiven Direktzugriffspeicherzellen enthält.
 
4. Speichervorrichtung nach Anspruch 3, wobei die Auswählvorrichtungen (414) N-Kanal-Transistoren enthalten.
 
5. Speichervorrichtung nach Anspruch 3, wobei die Auswählvorrichtungen (414) P-Kanal-Transistoren enthalten.
 
6. Verfahren, umfassend:

Auswählen einer Vielzahl von resistiven Direktzugriffspeicherzellen, die jede ein Material variablen Zustands zum Repräsentieren von Daten als den variablen Zustand aufweisen;

Ansteuern von Rücksetz-, Setz- und Hemmspannungen unter Verwendung einer Spaltentreiberschaltung zu verschiedenen resistiven Direktzugriffspeicherzellen in der ausgewählten Vielzahl zur selben Zeit,

wobei Ansteuern einer Hemmspannung enthält, eine Hemmspannungsleitung von einer gemeinsam gekoppelten Quellenleitung anzusteuern, und wobei Ansteuern der Rücksetz-, Setz- und Hemmspannungen enthält, einen eines Setzknotens, eines Rücksetzknotens und eines Hemmknotens an ausgewählte Speicherzellen unter Verwendung einer Vielzahl von einzeln auswählbaren Auswählschaltungen zu koppeln, die Auswählschaltungen umfassend, für jede einer Vielzahl von Adressleitungen, ein NOT-Gate, funktionsfähig zum Empfangen eines ersten Eingangs, der in einem logischen Zustand die Erzeugung eines Ausgangs bewirkt, der funktionsfähig ist, um einen ersten Schalter zu schließen, um die Adressleitung mit einer ersten einen der Rücksetz-, Setz- und Hemmspannungen zu koppeln, ein erstes AND-Gate, funktionsfähig zum Empfangen eines zweiten Eingangs und eines dritten Eingangs, die in einem logischen Zustand die Erzeugung eines Ausgangs bewirken, der funktionsfähig ist, um einen zweiten Schalter zu schließen, um die Adressleitung mit einem zweiten der Rücksetz-, Setz- und Hemmspannungen zu koppeln, und ein zweites AND-Gate, funktionsfähig zum Empfangen des dritten Eingangs und der Inversen des dritten Eingangs, um die Erzeugung eines Ausgangs zu bewirken, der funktionsfähig ist, um einen dritten Schalter zu schließen, um die Adressleitung mit einer dritten der Rücksetz-, Setz- und Hemmspannungen zu koppeln, wobei der erste, zweite und dritte Eingang konfiguriert sind, einen der geschlossenen Schalter anzusteuern, um die Adressleitung mit einer korrespondierenden einen der Rücksetz-, Setz- und Hemmspannungen zu koppeln, während sie die anderen Schalter geöffnet halten.


 
7. Verfahren nach Anspruch 6, wobei Auswählen einer Vielzahl von resistiven Direktzugriffspeicherzellen umfasst, eine Vielzahl von resistiven Direktzugriffspeicherzeiten unter Verwendung von Reihenauswahlschaltungen auszuwählen.
 
8. Verfahren nach Anspruch 6, wobei Ansteuern von Rücksetz-, Setz- und Hemmspannungen zu verschiedenen resistiven Direktzugriffspeicherzellen in der ausgewählten Vielzahl zur selben Zeit enthält, im Wesentlichen diskrete Spannungen anzusteuern.
 
9. Verfahren nach Anspruch 6, wobei die Setzspannung im Wesentlichen gleich der Hemmspannung plus einem Spannungsversatz ist und wobei die Rücksetzspannung im Wesentlichen gleich der Hemmspannung minus dem Spannungsversatz ist.
 
10. Verfahren nach Anspruch 9, wobei die Hemmspannung ungefähr 3 Volt beträgt und der Spannungsversatz ungefähr ein Volt beträgt.
 
11. Verfahren nach Anspruch 6, wobei die Rücksetzspannung kleiner als die Hemmspannung ist und die Hemmspannung kleiner als die Setzspannung ist.
 


Revendications

1. Dispositif de mémoire (400), comprenant :

un réseau (402) de cellules de mémoire vive résistives, chacune des cellules de mémoire vive résistives (410) incluant un matériau d'état variable pour représenter des données en tant qu'état variable ;

un dispositif de pilotage de colonne (404) qui est couplé au réseau de cellules de mémoire vive résistives pour fournir des tensions d'initialisation, de réinitialisation et d'inhibition à différentes cellules de mémoire vive résistives dans le réseau en même temps, dans lequel une ligne de source est couplée de façon commune à une ligne de tension d'inhibition ; et

un nœud d'initialisation (422), un nœud de réinitialisation (424) et un nœud d'inhibition (420) qui sont couplés au dispositif de pilotage de colonne (404), dans lequel le nœud de réinitialisation est associé à une tension de réinitialisation, le nœud d'initialisation est associé à une tension d'initialisation et le nœud d'inhibition est associé à une tension d'inhibition, dans lequel le dispositif de pilotage de colonne inclut une pluralité de circuits de sélecteur pouvant être sélectionnés individuellement (405a - 405c) pour sélectionner le nœud pris parmi le nœud d'initialisation (422), le nœud de réinitialisation (424) et le nœud d'inhibition (420) qu'il convient de coupler aux différentes cellules de mémoire en même temps, les circuits de sélectionneur comprenant, pour chacune d'une pluralité de lignes d'adresse, une porte NON qui peut être activée de manière à ce qu'elle reçoive une première entrée qui, dans un état logique, provoque la génération d'une sortie qui peut être activée pour fermer un premier commutateur afin de coupler la ligne d'adresse à un premier nœud pris parmi le nœud d'initialisation (422), le nœud de réinitialisation (424) et le nœud d'inhibition (420), une première porte ET qui peut être activée de manière à ce qu'elle reçoive une deuxième entrée et une troisième entrée qui, dans un état logique, provoquent la génération d'une sortie qui peut être activée pour fermer un deuxième commutateur afin de coupler la ligne d'adresse à un deuxième nœud pris parmi le nœud d'initialisation (422), le nœud de réinitialisation (424) et le nœud d'inhibition (420), et une seconde porte ET qui peut être activée de manière à ce qu'elle reçoive la troisième entrée et l'inverse de la troisième entrée, afin de provoquer la génération d'une sortie qui peut être activée pour fermer un troisième commutateur afin de coupler la ligne d'adresse à un troisième nœud pris parmi le nœud d'initialisation (422), le nœud de réinitialisation (424) et le nœud d'inhibition (420), les première, deuxième et troisième entrées étant configurées de manière à ce qu'elles pilotent l'un des commutateurs dans l'état fermé afin de coupler la ligne d'adresse à un nœud correspondant pris parmi le nœud d'initialisation (422), le nœud de réinitialisation (424) et le nœud d'inhibition (420) tout en maintenant ouverts les autres commutateurs.


 
2. Dispositif de mémoire selon la revendication 1, dans lequel le matériau d'état variable inclut un matériau de commutation de résistance.
 
3. Dispositif de mémoire selon la revendication 1, dans lequel le réseau inclut en outre des dispositifs de sélecteur (414) pour accéder aux cellules de mémoire vive résistives.
 
4. Dispositif de mémoire selon la revendication 3, dans lequel les dispositifs de sélecteur (414) incluent des transistors à canal N.
 
5. Dispositif de mémoire selon la revendication 3, dans lequel les dispositifs de sélecteur (414) incluent des transistors à canal P.
 
6. Procédé, comprenant :

la sélection d'une pluralité de cellules de mémoire vive résistives dont chacune comporte un matériau d'état variable pour représenter des données en tant qu'état variable ;

le pilotage de tensions de réinitialisation, d'initialisation et d'inhibition en utilisant un circuit de pilotage de colonne sur différentes cellules prises parmi les cellules de mémoire vive résistives dans la pluralité sélectionnée en même temps ;

dans lequel le pilotage d'une tension d'inhibition inclut le pilotage d'une ligne de tension d'inhibition à partir d'une ligne de source couplée de façon commune, et dans lequel le pilotage des tensions de réinitialisation, d'initialisation et d'inhibition inclut le couplage d'un nœud pris parmi un nœud d'initialisation, un nœud de réinitialisation et un nœud d'inhibition à des cellules de mémoire sélectionnées en utilisant une pluralité de circuits de sélecteur pouvant être sélectionnés individuellement, les circuits de sélecteur comprenant, pour chacune d'une pluralité de lignes d'adresse, une porte NON qui peut être activée de manière à ce qu'elle reçoive une première entrée qui, dans un état logique, provoque la génération d'une sortie qui peut être activée pour fermer un premier commutateur afin de coupler la ligne d'adresse à une première tension prise parmi les tensions de réinitialisation, d'initialisation et d'inhibition, une première porte ET qui peut être activée de manière à ce qu'elle reçoive une deuxième entrée et une troisième entrée qui, dans un état logique, provoquent la génération d'une sortie qui peut être activée pour fermer un deuxième commutateur afin de coupler la ligne d'adresse à une deuxième tension prise parmi les tensions de réinitialisation, d'initialisation et d'inhibition, et une seconde porte ET qui peut être activée de manière à ce qu'elle reçoive la troisième entrée et l'inverse de la troisième entrée, afin de provoquer la génération d'une sortie qui peut être activée pour fermer un troisième commutateur afin de coupler la ligne d'adresse à une troisième tension prise parmi les tensions de réinitialisation, d'initialisation et d'inhibition, les première, deuxième et troisième entrées étant configurées de manière à ce qu'elles pilotent l'un des commutateurs dans l'état fermé afin de coupler la ligne d'adresse à une tension correspondante prise parmi les tensions de réinitialisation, d'initialisation et d'inhibition tout en maintenant ouverts les autres commutateurs.


 
7. Procédé selon la revendication 6, dans lequel la sélection d'une pluralité de cellules de mémoire vive résistives comprend la sélection d'une pluralité de cellules de mémoire vive résistives en utilisant un circuit de sélection de rangée.
 
8. Procédé selon la revendication 6, dans lequel le pilotage de tensions de réinitialisation, d'initialisation et d'inhibition sur différentes cellules prises parmi les cellules de mémoire vive résistives dans la pluralité sélectionnée en même temps inclut le pilotage de tensions sensiblement discrètes.
 
9. Procédé selon la revendication 6, dans lequel la tension d'initialisation est sensiblement égale à la tension d'inhibition plus un décalage de tension, et dans lequel la tension de réinitialisation est sensiblement égale à la tension d'inhibition moins le décalage de tension.
 
10. Procédé selon la revendication 9, dans lequel la tension d'inhibition est d'approximativement 3 V, et le décalage de tension est d'approximativement 1 V.
 
11. Procédé selon la revendication 6, dans lequel la tension de réinitialisation est inférieure à la tension d'inhibition, et la tension d'inhibition est inférieure à la tension d'initialisation.
 




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REFERENCES CITED IN THE DESCRIPTION



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Patent documents cited in the description