(19)
(11)EP 2 838 079 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
07.09.2022 Bulletin 2022/36

(21)Application number: 12852476.6

(22)Date of filing:  21.12.2012
(51)International Patent Classification (IPC): 
G09G 3/20(2006.01)
G11C 19/28(2006.01)
G09G 3/32(2016.01)
(52)Cooperative Patent Classification (CPC):
G09G 2300/0408; G09G 2310/0286; G09G 2330/021; G11C 19/28
(86)International application number:
PCT/CN2012/087211
(87)International publication number:
WO 2013/152604 (17.10.2013 Gazette  2013/42)

(54)

SHIFT REGISTER UNIT AND DRIVING METHOD FOR THE SAME, SHIFT REGISTER, AND DISPLAY DEVICE

SCHIEBEREGISTEREINHEIT UND ANSTEUERUNGSVERFAHREN DAFÜR, SCHIEBEREGISTER UND ANZEIGEVORRICHTUNG

UNITÉ DE REGISTRE À DÉCALAGE ET PROCÉDÉ DE COMMANDE DE CETTE UNITÉ, REGISTRE À DÉCALAGE, ET DISPOSITIF D'AFFICHAGE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 13.04.2012 CN 201210109688
30.07.2012 CN 201210269029

(43)Date of publication of application:
18.02.2015 Bulletin 2015/08

(73)Proprietor: BOE Technology Group Co., Ltd.
Beijing 100015 (CN)

(72)Inventor:
  • WU, Zhongyuan
    Beijing 100176 (CN)

(74)Representative: Brötz, Helmut et al
Rieder & Partner mbB Patentanwälte - Rechtsanwalt Yale-Allee 26
42329 Wuppertal
42329 Wuppertal (DE)


(56)References cited: : 
EP-A1- 2 881 934
CN-A- 101 093 647
CN-A- 102 117 659
CN-A- 102 819 998
KR-A- 20090 050 358
US-A1- 2007 296 681
US-A1- 2010 097 368
EP-A2- 0 801 376
CN-A- 101 650 506
CN-A- 102 779 478
CN-U- 202 736 497
US-A1- 2007 248 204
US-A1- 2008 048 712
US-A1- 2011 122 117
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    TECHNICAL FIELD OF THE DISCLOSURE



    [0001] The present disclosure relates to the field of organic light-emitting display, and particularly to a shift register unit and a driving method thereof, a shift register and a display apparatus.

    BACKGROUND



    [0002] In Active Matrix Display, scan lines of respective rows and data lines of respective columns intersect to constitute an active matrix. A progressive scanning method is usually adopted to turn on transistors of respective rows sequentially and write voltage on data lines into pixels. A row scanning and driving circuit integrated on a display back board has the advantages of narrow edge and low cost, and has been used in most of LCD/AMOLED display devices.

    [0003] There are many kinds of processes for manufacturing a back board of display devices at present, for example, a-Si, LTPS, Oxide Thin Film Transistor(TFT), and etc. The a-Si process is relative mature and has low cost, but a-Si TFT has the disadvantages of low mobility and low stability. LTPS TFT has the advantages of rapid speed and great stability and the disadvantages of low uniformity and high cost, and is not suitable to the preparation of a panel with large size. Oxide TFT has the advantages of high mobility, good uniformity and low cost, and is a kind of technology of best suitable to a large size panel in future. However, the I-V transfer characteristics of the Oxide TFT is usually in a depletion mode, that is, the Oxide TFT is still turned on when a gate-source voltage Vgs of the Oxide TFT is zero.

    [0004] A depletion type TFT brings challenge on the integration of a shift register on a display back board. Fig.1A is a structure diagram of a conventional shift register, and all of transistors in Fig.1A are N-type TFTs. As shown in Fig.1A, the conventional shift register includes a first output transistor T1, a second output transistor T2, a first control module 11 for controlling T1 and a second control module 12 for controlling T2. An output terminal of a shift register at each stage is connected to an input terminal of a shift register at a next stage, and shift registers at respective stages are controlled alternately by two clock signals CLK1 and CLK2 having a duty ratio of 50%. All of input signals and control signals have a swing of VGL~VGH, wherein VGL is a low level and VGH is a high level. The first output transistor T1 is connected to the clock signal CLK2 and the output terminal OUT(n) and functions as transferring the high level, and the second output transistor T2 is connected to a low level output terminal for outputting the low level VGL and the output terminal OUT(n) and functions as transferring the low level.

    [0005] As shown in Fig.1B, operations of the shift register can be divided into three phases:

    [0006] A first phase is a pre-charging phase, when an output terminal OUT(n-1) of a shift register at a previous stage generates a high level pulse, a PU node (a node connected to a gate of T1, that is, a pulling-up node) is controlled to be charged to the high level VGH, and meanwhile a PD node (a node connected to a gate of T2, that is, a pulling-down node) is controlled to be discharged to the low level VGL, so that T1 is turned on to transfer the low level of CLK2 to the output terminal OUT(n) and T2 is turned off;

    [0007] A second phase is an evaluating phase, in a next half clock cycle, the PU node becomes a floating state, that is, no signal is input to the PU node since transistors of the first output control module connected thereto are all turned off; CLK2 becomes the high level from the low level, as an output voltage increases, an voltage at the PU node is bootstrapped to a higher level by a capacitor connected between the gate of T1 and the output terminal OUT(n), so that it is ensured that there is no threshold loss in the output voltage at the output terminal OUT(n), and the PD node keeps at the low level to maintain T2 off and in turn it avoids the electric leakage of the high level outputted at the output terminal OUT(n) through T2; and

    [0008] A third phase is a resetting phase, in a third half clock cycle, CLK2 becomes the low level and CLK1 becomes the high level, the PU node is discharged to the low level and the PD node is recharged to the high level, T1 is turned off and T2 is turned on at this time, so that the output voltage at the output terminal OUT(n) becomes the low level via T2.

    [0009] It can be known from Fig.1B, the PU node and the PD node have an opposite relationship, so that it is avoided that T1 and T2 are turned on simultaneously to cause abnormal output.

    [0010] However, if T1 and T2 in Fig.1A arc depletion type transistors, a large distortion occurs in the output voltage. First, in the evaluating phase, the voltage at PU node is at the high level and thus T1 is turned on, on the other hand, T2 cannot be turned off normally but generates a leakage current due to the depletion characteristics of T2 although the gate-source voltage Vgs of T2 is zero since the voltage at the PD node is discharged to the low level VGL, that is, T1 and T2 are turned on simultaneously, and thus the potential of the output voltage outputted at the output terminal depends on the voltage division of T1 and T2 and is usually lower than the normal high voltage too much, which in turn affects normal operations of a shift register at a next stage and may cause malfunction of next stages. Secondly, in the resetting phase, the voltage at the PU node is at the low level and the voltage at the PD node is at the high level, and the output voltage at the output terminal OUT(n) is at the low level; at the same time, T1 is continually turned on as it is the depletion type transistor, and the output voltage at the output terminal OUT(n) would generate a high level pulse and the potential thereof depends on the voltage division of T1 and T2 when CLK2 becomes the high level. A normal waveform of the output voltage at the output terminal OUT(n) is shown by a liquid line in Fig.1C, and a distorted waveform of the output voltage at the output terminal OUT(n) is shown by a dotted line in Fig.1C.

    [0011] Besides the first output transistor T1 and the second output transistor T2, other depletion type TFTs in the internal control circuit would cause abnormal output as well. As shown in Fig.2A, the second control module is a pulling-down transistor control module, and the first control module includes T3 and T4 which are depletion type transistors, wherein T3 is connected to the output terminal OUT(n-1) of the shift register at a previous stage and the PU node (the node connected to the gate of T1) and functions to charge the voltage at the PU node to the high level in the pre-charging phase; T4 has a gate connected to a reset signal Rst and is connected between the PU node and the low level output terminal for outputting the low level VGL, and functions to pull down the voltage at the PU node in the resetting phase. The depletion type transistors T3 and T4 are turned on in the evaluating phase, the voltage at the PU node is pulled down, so that T1 is not turned on completely, which affects the potential of the output voltage at the output terminal OUT(n), as shown by a dotted line in Fig.2B.

    [0012] Therefore, there is a need for improving the circuit structure of the shift register to remove the effect of the depletion type TFT on the output voltage of the shift register. US2010/097368 discloses a display device and a driving method of the same, wherein the display device includes: a display panel having gate lines and data lines; and a gate driver having stages that supply the gate lines with gate signals, each of the stages including a gate output terminal, a pull-down unit, and a holding unit.
    US2007/296681 discloses a gate driving circuit having (n+1) stages connected to each other in series, wherein each stage includes a pull-up part, a carry part to pull up a present carry signal to the first clock; a pull-down part to receive a next gate signal from a next stage; a pull-up driving part to receive a previous carry signal from a previous stage; and a first floating preventing part to provide the present gate signal to a present carry node and to reset the present carry node in response to the first clock.
    EP2881934 discloses a shift register unit, wherein the shift register unit includes: a first output control module (51); a second output control module (52); a staged output module (53), and a pull-up node level maintaining capacitor (C1).
    EP0801376 discloses a display apparatus for applying brightness signals to pixels arranged in a plurality of rows and in a plurality of columns of an array, wherein the display apparatus includes a plurality of column drivers, a source of a toggling, a plurality of stages forming a row select scanner.
    From US 2011/0122117 A1 it is known a display panel including an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal. This document discloses the preamble of claim 1.
    US 2007/0248204 A1 discloses a shift register circuit and an image display apparatus equipped with the same.

    SUMMARY



    [0013] Embodiments of the present disclosure provide a shift register unit and a driving method thereof, a shift register and a display apparatus for removing the effect of a leakage current of a depletion type TFT on the shift register.

    [0014] According to one aspect, there is provided a shift register unit, including:

    an input terminal;

    a first output control module having a control signal output terminal connected to a pulling-up node, configured to pull up a driving signal in an evaluating phase,

    a second output control module having a control signal output terminal connected to a pulling-down node, for pulling down the driving signal in a resetting phase;

    wherein the first output control module is also connected to the input terminal;

    wherein the shift register unit further includes:

    a carry signal output terminal configured to output a carry signal,

    a driving signal output terminal configured to output the driving signal,

    a staged output module connected to the pulling-up node, the pulling-down node, the carry signal output terminal and the driving signal output terminal, wherein the staged output module comprises a carry signal output unit and a driving signal output unit configured to output the carry signal and the driving signal respectively so that the driving signal maintains a high level in the evaluating phase and a second low level in the resetting phase and the carry signal maintains the high level in the evaluating phase and a first low level which is different from the second low level in the resetting phase wherein each of the carry signal output unit and the driving signal output unit is connected to the pulling-up node and the pulling-down node; wherein the shift register unit further includes a pulling-up node level maintaining module configured to, in the evaluating phase, maintain the level at the pulling-up node at another high level via the first output control module so that the driving signal maintains said high level; wherein the first output control module includes a feedback signal receiving terminal; and the pulling-up node level maintaining module includes a first feedback control TFT having a gate connected to the carry signal output terminal, a source connected to the feedback signal receiving terminal, and a drain connected to a first node which is node different from the carry signal output terminal to receive a feedback signal for maintaining the level at the pulling-up node in the evaluating phase,

    wherein the first feedback control TFT is a depletion type TFT;

    a threshold voltage of first feedback control TFT is the depletion threshold voltage;

    the first low level (VGL1) is lower than the second low level (VGL2), and wherein

    1. i) the first node is the driving signal output terminal (OUT(n)) and the absolute value of difference between the first low level and the second low level is larger than the depletion threshold voltage; or
    2. ii) the staged output module (33) further includes a staged output unit (333), the staged output unit (333) is connected to the pulling-up node (PU), the pulling-down node (PD), and the first node (FN), and is configured to output the feedback signal at the first node.



    [0015] In an example, the

    carry signal output unit is configured to make the carry signal output terminal output a first low level under the control of the first output control module in a pre-charging phase and output the first low level under the control of the second output control module in the resetting phase, and making the carry signal output terminal output the high level under the control of the first output control module in the evaluating phase; and

    the driving signal output unit is configured to make the driving signal output terminal output the high level under the control of the second output control module in the evaluating phase, and making the driving signal output terminal output the first low level under the control of the first output control module in the precharging phase and output the second low level under the control of the second output control module in the resetting phase.



    [0016] In an example, the carry signal output unit includes a first carry signal output TFT and a second carry signal output TFT;

    the first carry signal output TFT has a gate connected to the control signal output terminal of the first output control module, a source connected to the carry signal output terminal, and a drain connected to a first clock signal input terminal; and

    the second carry signal output TFT has a gate connected to the control signal output terminal of the second output control module, a source connected to a first low level output terminal, and a drain connected to the carry signal output terminal.



    [0017] In an example, the driving signal output unit includes a first driving TFT, a second driving TFT and a bootstrap capacitor;

    the first driving TFT has a gate connected to the control signal output terminal of the first output control module, a source connected to the driving signal output terminal, and a drain connected to a first clock signal input terminal;

    the second driving TFT has a gate connected to the control signal output terminal of the second output control module, a source connected to a second low level output terminal, and a drain connected to the driving signal output terminal; and

    the bootstrap capacitor is connected in parallel between the gate and the source of the first driving TFT.



    [0018] In an example, the first carry signal output TFT, the second carry signal output TFT, the first driving TFT and the second driving TFT are depletion type TFTs.

    [0019] In an example, a threshold voltage of the first carry signal output TFT, a threshold voltage of the second carry signal output TFT, a threshold voltage of the first driving TFT and a threshold voltage of the second driving TFT are a same depletion threshold voltage;
    the first low level is lower than the second low level, and the absolute value of difference between the first low level and the second low level is larger than the absolute value of the depletion threshold voltage.

    [0020] In an example, the first output control module further includes a first TFT, a second TFT, a third TFT and a fourth TFT, wherein

    a gate and a source of the first TFT are connected to the input terminal, and a drain of the first TFT is connected to a source of the second TFT;

    a gate of the second TFT is connected to the input terminal, and a drain of the second TFT is connected to a drain of the fourth TFT;

    a gate of the third TFT is connected to a reset signal output terminal, a source of the third TFT is connected to the first low level output terminal, and a drain of the third TFT is connected to a source of the fourth TFT;

    a gate of the fourth TFT is connected to the reset signal output terminal;

    wherein the drain of the first TFT is also connected to the pulling-up node level maintaining module; and

    the drain of the second TFT is connected to the control signal output terminal of the first output control module.



    [0021] In an example, the second output control module includes a first output control TFT, a second output control TFT, and a third output control TFT, wherein

    a gate of the first output control TFT is connected to the gate of the first carry signal output TFT, a source of the first output control TFT is connected to a drain of the second output control TFT, and a drain of the first output control TFT is connected to the gate of the second carry signal output TFT;

    a gate of the second output control TFT is connected to the gate of the first carry signal output TFT, and a source of the second output control TFT is connected to the first low level output terminal;

    a gate and a drain of the third output control TFT are connected to a high level output terminal, and a source of the third output control TFT is connected to the gate of the second carry signal output TFT.



    [0022] In an example, the shift register unit according to the embodiments of the present disclosure further includes a cutting-off control signal input terminal and a cutting-off control signal output terminal;

    the pulling-up node level maintaining module further includes a second feedback control TFT;

    a gate of the second feedback control TFT is connected to the carry signal output terminal, a source of the second feedback control TFT is connected to the first node, and a drain of the second feedback control TFT is connected to the cutting-off control signal output terminal; and

    the second output control module is connected to the cutting-off control signal input terminal.



    [0023] In an example, the staged output unit includes a first staged output TFT and a second staged output TFT;

    a gate of the first staged output TFT is connected to the gate of the first carry signal output TFT, a drain of the first staged output TFT is connected to the first clock signal input terminal, and a source of the first staged output TFT is connected to the first node; and

    a gate of the second staged output TFT is connected to the gate of the second carry signal output TFT, a source of the second staged output TFT is connected to the second low level output terminal, and a drain of the second staged output TFT is connected to the source of the first staged output TFT.



    [0024] According to another aspect, there is provided a driving method applied to the above-described shift register unit, the driving method includes:

    in a phase wherein the input terminal inputs a high level, the first clock signal is at the low level, the first output control module controls to pre-charge the bootstrap capacitor, so as to control the carry signal output terminal and the driving signal output terminal to output the first low level; the second output control module controls the control signal output terminal thereof to output the first low level;

    in a next half clock cycle, the first clock signal becomes the high level, the first output control module controls the carry signal output terminal and the driving signal output terminal to output the high level; and the first feedback control TFT maintains the level of the pulling-up node of another high level under control of the carry signal output by the carry signal output terminal which is connected to the gate of the first feedback control TFT; and

    in a third half clock cycle, the first clock signal becomes the low level, the first output control module and the second output control module control the carry signal output terminal to output the first low level and control the driving signal output terminal to output the second low level.



    [0025] According to another aspect, there is provided a shift register including a plurality of the above-described shift register units arranged at a plurality of stages;
    except the shift register unit at a first stage, the input terminal of the shift register unit at each stage is connected to the carry signal output terminal of the shift register unit at a previous stage.

    [0026] Compared to the prior art, the shift register unit, the driving method thereof, and the shift register of the embodiments of the present disclosure remove the effect of the leakage current of the depletion type TFT on the shift register by using staged output and maintaining the pulling-up node level, which increases stability and reliability thereof and decreases power consumption.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0027] 

    FIG.1A is a circuit diagram of a conventional shift register;

    FIG.1B is a timing sequence diagram of respective signals of the conventional shift register in operation;

    FIG.1C is an output waveform at an output terminal OUT(n) of the conventional shift register;

    FIG.2A is a circuit diagram of a particular embodiment of the conventional shift register;

    FIG.2B is a timing sequence diagram of respective signals of the particular embodiment of the conventional shift register in operation;

    Fig.3 is a circuit diagram of a shift register unit according to a first embodiment not covered by the claim;

    Fig.4 is a circuit diagram of a shift register unit according to a second embodiment not covered by the claim;

    Fig.5 is a circuit diagram of a shift register unit according to a third embodiment not covered by the claim;

    Fig.6 is a circuit diagram of a shift register unit according to a fourth embodiment not covered by the claim;

    Fig.7 is a circuit diagram of a shift register unit according to a fifth embodiment of the present disclosure;

    Fig. 8 is a circuit diagram of a shift register unit according to a sixth embodiment of the present disclosure;

    Fig.9 is a timing sequence diagram of respective signals of the shift register unit according to the second, third, fourth, fifth and sixth embodiments of the present disclosure in operation;

    Fig.10 is a circuit diagram of a shift register unit according to a seventh embodiment of the present disclosure;

    Fig.11 is a circuit diagram of a shift register unit according to an eighth embodiment of the present disclosure;

    Fig.12 is a circuit diagram of a shift register unit according to a ninth embodiment of the present disclosure;

    FIG.13 is a timing sequence diagram of respective signals of the shift register unit according the ninth embodiment of the present disclosure in operation;

    Fig.14 is a circuit diagram of a shift register unit according to a tenth embodiment of the present disclosure;

    FIG. 15 is a timing sequence diagram of respective signals of the shift register unit according the tenth embodiment of the present disclosure in operation;

    Fig.16 is a circuit diagram of a shift register unit according to an eleventh embodiment not covered by the claim;

    FIG. 17 is a timing sequence diagram of respective signals of the shift register unit according to the eleventh embodiment not covered by the claims;

    Fig.18 is a circuit diagram of a shift register unit according to a twelfth embodiment not covered by the claim;

    FIG. 19 is a diagram schematically showing the simulation results for the circuit structure according to the present disclosure and the conventional circuit structure with the depletion type TFTs;

    Fig.20 is a circuit diagram of a shift register according to a first embodiment of the present disclosure; and

    Fig.21 is a circuit diagram of a shift register according to a second embodiment of the present disclosure. Figures 3-6 and 16-18 are not part of the invention as claimed by the attached claims but are useful to understand the invention.


    DETAILED DESCRIPTION



    [0028] In one aspect, the technical solutions and the advantages of the present disclosure more clear, detailed descriptions will be given below in particular embodiments of the present disclosure with reference to accompanying drawings.

    [0029] The disclosure provides a shift register unit and a driving method thereof, a shift register and a display apparatus for removing the effect of leakage current of depletion type TFTs on the shift register.

    [0030] As shown in Fig.3, according to a first embodiment not covered by the claim, a shift register unit includes:

    an input terminal IN;

    a carry signal output terminal CA(n);

    a driving signal output terminal OUT(n);

    a first output control module 31 having a control signal output terminal connected to a PU node (a pulling-up node), for pulling up a driving signal in an evaluating phase, the first output control module 31 also being connected to the input terminal IN;

    a second output control module 32 having a control signal output terminal connected to a PD node (a pulling-down node), for pulling down the driving signal in a resetting phase;

    the shift register unit according to the first example further includes:

    a staged output module 33 connected to the PU node, the PD node, the carry signal output terminal CA(n) and the driving signal output terminal OUT(n), respectively, for outputting a carry signal and a driving signal in stages so that the driving signal maintains a high level in the evaluating phase and a low level in the resetting phase; and

    a pulling-up node level maintaining module 34 connected to the first output control module 31 and for, in the evaluating phase, maintaining the level at the PD node at the high level via the first output control module 31, so that the driving signal maintains the high level; and

    the carry signal output terminal CA(n) is connected to the input terminal IN of the shift register unit at a next stage (not shown in Fig.3).



    [0031] The shift register unit according to the first embodiment adopts the staged output module 33 to output the carry signal and the driving signal in stages, so that the driving signal maintains a high level in the evaluating phase and a low level in the resetting phase, as a result, the effect of leakage current of depletion type TFTs on the driving signal of the shift register unit can be removed.

    [0032] The shift register unit according to the first example controls the first output control module 31 through the pulling-up node level maintaining module 31 in the evaluating phase to maintain the level of the PU node at the high level and thus maintain the driving signal at the high level, which avoids the pull-up node(PU node) having electric leakage through the internal TFTs in depletion region in the evaluating phase and removes the effect thereof on the output.

    [0033] As shown in Fig.4, a structure diagram of a shift register unit according to a second embodiment not covered by the claim is shown. The shift register unit according to he second embodiment is based on the shift register unit according to the first embodiment In the second embodiment,

    the staged output module 33 includes a driving signal output unit 331 and a carry signal output unit 332, wherein,

    the carry signal output unit 332 is driven by a first low level output terminal;

    the driving signal output unit 331 is driven by a second low level output terminal;

    the carry signal output unit 332 is used for making the carry signal output terminal CA(n) output a first low level VGL1 under the control of the first output control module 31 in a pre-charging phase and the resetting phase, and making the carry signal output terminal CA(n) output the high level under the control of the second output control module 32 in the evaluating phase; and

    the driving signal output unit 331 is used for making the driving signal output terminal OUT(n) output the high level under the control of the second output control module 32 in the evaluating phase, and making the driving signal output terminal OUT(n) output a second low level VGL2 under the control of the first output control module 31 in the resetting phase.



    [0034] The first low level output terminal outputs the first low level VGL1, and the second low level output terminal outputs the second low level VGL2; and

    [0035] The first low level VGL1 and the second low level VGL2 are different, so that the effect of leakage current of depletion type TFTs on the driving signal of the shift register unit can be avoided.

    [0036] As shown in Fig.5, a circuit diagram of a shift register unit according to a third embodiment not covered by the claim is shown. The shift register unit according to the third embodiment is based on the shift register unit according to the second embodiment. In the third embodiment,

    the carry signal output unit 332 includes a first carry signal output TFT T1 and a second carry signal output TFT T2;

    the driving signal output unit 331 includes a first driving TFT T3, a second driving TFT T4 and a bootstrap capacitor C;

    the first carry signal output TFT T1 has a gate connected to the control signal output terminal of the first output control module 31, a source connected to the carry signal output terminal CA(n), and a drain connected to a first clock signal input terminal; and

    the bootstrap capacitor C is connected in parallel between the gate and the source of the first driving TFT T3;

    the first driving TFT T3 has a gate connected to the control signal output terminal of the first output control module 31, a source connected to the driving signal output terminal OUT(n), and a drain connected to a first clock signal input terminal;

    the second carry signal output TFT T2 has a gate connected to the control signal output terminal of the second output control module 32, a source connected to the first low level output terminal, and a drain connected to the carry signal output terminal CA(n);

    the second driving TFT T4 has a gate connected to the control signal output terminal of the second output control module 32, a source connected to the second low level output terminal, and a drain connected to the driving signal output terminal OUT(n);

    the first output control module 31 is further connected to the first low level output terminal and the input terminal IN;

    the second output control module 32 is further connected to the first low level output terminal.



    [0037] Furthermore, T1, T2, T3 and T4 are n-type TFTs.

    [0038] Furthermore, the first carry signal output TFT T1, the second carry signal output TFT T2, the first driving TFT T3 and the second driving TFT T4 are depletion type TFTs.

    [0039] Furthermore, a threshold voltage of the first carry signal output TFT T1, a threshold voltage of the second carry signal output TFT T2, a threshold voltage of the first driving TFT T3 and a threshold voltage of the second driving TFT T4 are a same depletion threshold voltage Vth;

    wherein the first clock signal CLK1 is inputted from the first clock signal input terminal, the first low level VGL1 is outputted from the first low level output terminal, and the second low level VGL2 is outputted from the second low level output terminal;

    wherein VGL1<VGL2 and |VGL1-VGL2|>|Vth|.



    [0040] The PU node is a node to which the gate of the first carry signal output TFT T1 is connected, and the PD node is a node to which the gate of the second carry signal output TFT T2 is connected. The potential at the PU node and the potential at the PD node are controlled by the first output control module 31 and the second output control module 32, respectively. A timing sequence diagram of the potential at the PU node and a timing sequence diagram of the potential at the PD node are shown in Fig.9. The potential at the PU node is generated according to the timing sequence diagram of the potential at the PU node shown in Fig.9 under the control of the first output control module 31, and the potential at the PD node is generated according to the timing sequence diagram of the potential at the PD node shown in Fig.9 under the control of the second output control module 32.

    [0041] In the third embodiment, the first output control module is connected to a second clock signal input terminal (not shown in Fig.5). In an alternative embodiment not covered by the claims, a second clock signal can be omitted and the first output control module can achieve the same functions without being connected to the second clock signal input terminal. The second clock signal CLK2 is inputted from the second clock signal input terminal, and CLK1 and CLK2 have opposite phases.

    [0042] As shown in Fig.6, a circuit diagram of a shift register unit according to a fourth embodiment not covered by the claim is shown. The shift register unit according to the fourth embodiment is based on the shift register unit according to the third embodiment. In the fourth embodiment, the second output control module 32 includes a first output control TFT T21, a second output control TFT T22, and a third output control TFT T23, wherein,

    a gate of the first output control TFT T21 is connected to the gate of the first carry signal output TFT T1, a source of the first output control TFT T21 is connected to a drain of the second output control TFT T22, and a drain of the first output control TFT T21is connected to the gate of the second carry signal output TFT T2;

    a gate of the second output control TFT T22 is connected to the gate of the first carry signal output TFT T1, and a source of the second output control TFT T2 is connected to the first low level output terminal;

    a gate and a drain of the third output control TFT T23 are connected to a high level output terminal, and a source of the third output control TFT T23 is connected to the gate of the second carry signal output TFT T2, wherein the high level output terminal outputs a high level VGH.



    [0043] As shown in Fig.7, a circuit diagram of a shift register unit according to a fifth embodiment of the present disclosure is shown. The shift register unit according to the fifth embodiment of the present disclosure is based on the shift register unit according to the third embodiment. In the fifth embodiment,

    the first output control module 31 includes a feedback signal receiving terminal CO;

    the pulling-up node level maintaining module 34 includes:

    a first feedback control TFT T41 having a gate connected to the carry signal output terminal CA(n), a source connected to the feedback signal receiving terminal CO of the first output control module 31, and a drain connected to the driving signal output terminal OUT(n);

    wherein the first feedback control TFT T41 is a depletion type TFT;

    a threshold voltage of first feedback control TFT T41 is the depletion threshold voltage Vth; and

    VGL1<VGL2 and |VGL1-VGL2|>|Vth|, so that it is ensured that T41 is turned off in the resetting phase and thus has no effect on the driving signal output terminal.



    [0044] As shown in Fig.8, a circuit diagram of a shift register unit according to a sixth embodiment of the present disclosure is shown. The shift register unit according to the sixth embodiment of the present disclosure includes: a first output control module 31, a second output control module 32, a staged output module 33, a pulling-up node level maintaining module 34, an input terminal IN, a carry signal output terminal CA(n) and a driving signal output terminal OUT(n), wherein,

    the first output control module 31 has a control signal output terminal connected to a PU node (a pulling-up node), for pulling up a driving signal in an evaluating phase;

    the first output control module 31 includes a feedback signal receiving terminal CO;

    and it further includes a first TFT T11, a second TFT T12, a third TFT T13 and a fourth TFT T14, wherein

    a gate of the first TFT T11 is connected to a second clock signal CLK2, a source of the first TFT T11 is connected to the input terminal, and a drain of the first TFT T11 is connected to a source of the second TFT T62;

    a gate of the second TFT T12 is connected to the second clock signal CLK2, and a drain of the second TFT T12 is connected to a drain of the fourth TFT T14;



    [0045] As an alternative embodiment of the embodiment shown in Fig.8, the gates of T1 and T2 may be not connected to the second clock signal CLK2 but connected directly to the input terminal IN with the same function being achieved. The difference lies in that control of the shift register unit according to the present disclosure will be more flexible and accurate when two clock signals CLK1 and CLK2 are used.

    a gate of the third TFT T13 is connected to a reset signal output terminal Rst, a source of the third TFT T13 is connected to the first low level output terminal, and a drain of the third TFT T13 is connected to a source of the fourth TFT T14;

    a gate of the fourth TFT T14 is connected to the reset signal output terminal Rst;

    wherein the drain of the first TFT T11 is also connected to the feedback signal receiving terminal CO of the first output control module 31;

    the drain of the second TFT T12 is also connected to the control signal output terminal of the first output control module 31; and

    the reset signal output terminal Rst is connected to the second output control module 32 (not shown in Fig.8).



    [0046] In Fig.8, a point N is a connection point where the T11 and T12 are connected in series and is also a connection point where T13 and T14 are connected in series; and the feedback signal receiving terminal CO of the first output control module 31 is connected to the point N;

    T11 and T12 are connected in series and function as charging the PU node to a high level;

    T13 and T14 are connected in series and function as discharging the PU node to a low level;

    the second output control module 32 has a control signal output terminal connected to a PD node (a pulling-down node), for pulling down the driving signal in a resetting phase;

    the second output control module 32 is also connected to a first low level output terminal;

    the staged output module 33 includes a first carry signal output TFT T1 and a second carry signal output TFT T2;

    the driving signal output unit 331 includes a first driving TFT T3, a second driving TFT T4 and a bootstrap capacitor C;

    the first carry signal output TFT T1 has a gate connected to the control signal output terminal of the first output control module 31, a source connected to the carry signal output terminal CA(n), and a drain connected to a first clock signal input terminal;

    the bootstrap capacitor C is connected in parallel between the gate and the source of the first driving TFT T3;

    the first driving TFT T3 has a gate connected to the control signal output terminal of the first output control module 31, a source connected to the driving signal output terminal OUT(n), and a drain connected to a first clock signal input terminal;

    the second output control TFT T2 has a gate connected to the control signal output terminal of the second output control module 32, a source connected to the first low level output terminal, and a drain connected to the carry signal output terminal CA(n);

    the second driving TFT T4 has a gate connected to the control signal output terminal of the second output control module 32, a source connected to a second low level output terminal, and a drain connected to the driving signal output terminal OUT(n);

    the pulling-up node level maintaining module 34 includes a first feedback control TFT T41 having a gate connected to the carry signal output terminal CA(n), a source connected to the feedback signal receiving terminal CO of the first output control module 31, and a drain connected to the driving signal output terminal OUT(n).



    [0047] Fig.9 is a timing sequence diagram of signal inputted from CLK1, signal outputted from CA(n), potential at PU node, potential at PD node and signal outputted from OUT(n) of the shift register units according to the second, third, fourth, fifth and sixth embodiments of the present disclosure in operation;
    in Fig. 9, VGH refers to the high level.

    [0048] As shown in Fig.9, the operation of the shift register unit according to the sixth embodiment of the present disclosure is divided into three phases:

    [0049] A first phase is a pre-charging phase S1, when the input terminal IN or the second clock signal CLK2 generates a high level pulse, T11 and T12 are turned on and T13 and T14 are turned off, the potential at the PU node is charged to a high level so that T1 and T3 are turned on, and thus the low level (VGL1) of CLK1 is transferred to OUT(n) via the turned-on T3 to ensure that OUT(n) outputs a low level; and the low level (VGL1) of CLK1 is transferred to CA(n) via the turned-on T1 to ensure that CA(n) outputs a low level. Meanwhile, the potential at the PD node connected to the gate of T2 is controlled to be discharged to VGL1, and the output is not affected by the T2 being turned on in the depletion region, since CA(n) outputs the low level VGL1. At this time, T4 is turned off since VGL1<VGL2.

    [0050] A second phase is an evaluating phase S2, that is, in a next half clock cycle, IN or the second clock signal CLK2 is at the low level, T11 is turned on in the depletion region, CLK1 becomes the high level from the low level, T41 is turned on as the voltages outputted from CA(n) and OUT(n) increase to transfer a high level to the point N; the gate of T12 is at the low level at this time, so for T12, Vgs<0 and thus Vgs<Vth, T12 and T14 arc completely turned off, and thus it is ensured that the PU node is in a floating state (that is, no signal is inputted to the PU node since all the transistors in the first output control module 31 connected thereto are turned off), the voltage at the PU node is bootstrapped to a higher level by the bootstrap capacitor, so that it is ensured that there is no threshold loss in the output voltage at OUT(n); at this time, the potential at the PD node keeps at the low level to maintain T4 being turned off and in turn avoid the high level outputted from OUT(n) having electric leakage through T4; and the stability of the driving output signal from OUT(n) can be ensured although CA(n) is effected to a certain extent by T2 being turned on in the depletion region.

    [0051] A third phase is a resetting phase S3, that is, in a third half clock cycle, CLK1 becomes the low level, T13 and T14 are turned on by the reset signal outputted from the reset signal output terminal Rst (the reset signal may be generated by the second output control module 32 or supplied from outside), the PU node is discharged to a low level VGL1 and the PD node is recharged to a high level, T1 is turned on in the depletion region and T2 is turned on at this time, so the carry signal outputted from CA(n) keeps at the low level; T4 is turned on, and T3 is turned on in the depletion region, so the driving output signal outputted from OUT(n) keeps at the low level VGL2. Therefore, T41 is turned off since VGL1<VGL2 and |VGL1-VGL2|>|Vth|, and it has no effect on the driving output.

    [0052] The output is divided into two stages in the shift register unit according to the above described embodiments of the present disclosure: the carry signal output unit and the driving signal output unit, and the carry signal output unit and the driving signal output unit are driven by the first low level output terminal and the second low level output terminal, respectively, wherein the low levels outputted from the first low level output terminal and the second low level output terminal are different, therefore it is avoided that the output is affected by the leakage current generated by T3 and T4 being turned on in the depletion region. Meanwhile, internal nodes are controlled by the first feedback control TFT T41 in the present disclosure, so that it is avoided that the PU node has a electric leakage through internal TFTs being turned on in the depletion region in the evaluating phase and that the output is affected; and the source control voltage and the gate control voltage of the first feedback control TFT T41 arc controlled by different low levels, so that it is avoided that the output is inversely affected by the variation in potential at the internal nodes. It is not necessary for T1 and T2 to have large size since T1 and T2 are only used to drive the carry signal output terminal.

    [0053] Fig.10 is a circuit diagram of a shift register unit according to a seventh embodiment of the present disclosure, and the shift register unit according to the seventh embodiment of the present disclosure is based on the shift register unit according to the fifth embodiment of the present disclosure.

    [0054] As shown in Fig.10, the shift register unit according to the seventh embodiment of the present disclosure further includes a cutting-off control signal input terminal IOFF_IN and a cutting-off control signal output terminal IOFF(n);

    the pulling-up node level maintaining module 34 further includes a second feedback control TFT T42;

    a gate of the second feedback control TFT T42 is connected to the carry signal output terminal CA(n), a source of the second feedback control TFT T42 is connected to the driving signal output terminal OUT(n), and a drain of the second feedback control TFT T42 is connected to the cutting-off control signal output terminal IOFF(n); and

    the second output control module 32 is connected to the cutting-off control signal input terminal IOFF_IN.



    [0055] The cutting-off control signal output terminal IOFF(n) is connected to the cutting-off control signal input terminal IOFF_IN of the shift register unit at a previous stage (not shown in Fig.10), and the outputted cutting-off control signal is used for controlling the second output control module of the shift register unit at the previous stage to cut off the electric leakage path of the PD node.

    [0056] Fig.11 is a circuit diagram of a shift register unit according to an eighth embodiment of the present disclosure, and the shift register unit according to the eighth embodiment of the present disclosure is based on the shift register unit according to the seventh embodiment of the present disclosure.

    [0057] As shown in Fig.11, in the shift register unit according to the eighth embodiment of the present disclosure, the staged output module 33 further includes a staged output unit 333 connected between the carry signal output unit 332 and the driving signal output unit 331; and

    a first staged output TFT T31 and a second staged output TFT T32;

    wherein a gate of the first staged output TFT T31 is connected to the gate of the first carry signal output TFT T1 , a drain of the first staged output TFT T31 is connected to the first clock signal input terminal, and a source of the first staged output TFT T31 is connected to the source of the second feedback control TFT T42; and

    a gate of the second staged output TFT T32 is connected to the gate of the second carry signal output TFT T2, a source of the second staged output TFT T32 is connected to the second low level output terminal, and a drain of the second staged output TFT T32 is connected to the source of the first staged output TFT T31.



    [0058] In the eighth embodiment, in order to avoid the effects of T41 and T42 on OUT(n), the staged output module 33 is further divided into three stages so as to further ensure no electric leakage in the output.

    [0059] Fig.12 is a circuit diagram of a shift register unit according to a ninth embodiment of the present disclosure, and the shift register unit according to the ninth embodiment of the present disclosure is based on the shift register unit according to the eighth embodiment of the present disclosure.

    [0060] As shown in Fig.12, the first output control module includes a first TFT T11, a second TFT T12, a third TFT T13 and a fourth TFT T14; the second output control module includes a first output control TFT T21, a second output control TFT T22, and a third output control TFT T23;

    a gate of the first TFT T11 is connected to a second clock signal input terminal, a source of the first TFT T11 is connected to a drain of the second TFT T12, and a drain of the first TFT T11 is connected to the input terminal IN;

    a gate of the second TFT T12 is connected to the second clock signal input terminal, and a source of the second TFT T12 is connected to the gate of the first carry signal output TFT T1;

    a gate of the third TFT T13 is connected to the gate of the second carry signal output TFT T2, a source of the third TFT T13 is connected to a drain of the fourth TFT T14, and a drain of the third TFT T13 is connected to a gate of the first output control TFT T21;

    a gate of the fourth TFT T14 is connected to the gate of the second carry signal output TFT T2; and a source of the fourth TFT T14 is connected to the first low level output terminal;

    a gate of the first output control TFT T21 is connected to the gate of the first carry signal output TFT T1, a source of the first output control TFT T21 is connected to the cutting-off control signal input terminal IOFF_IN(n) and a drain of the second output control TFT T22 respectively, and a drain of the first output control TFT T21 is connected to the gate of the second carry signal output TFT T2;

    a gate of the second output control TFT T22 is connected to the gate of the first carry signal output TFT T1, and a source of the second output control TFT T2 is connected to the first low level output terminal;

    a gate and a drain of the third output control TFT T23 arc connected to a high level output terminal, and a source of the third output control TFT T23 is connected to the gate of the second carry signal output TFT T2,

    wherein the second clock signal input terminal inputs the second clock signal CLK2 having an opposite phase to CLK1,

    the high level output terminal outputs a high level VGH.



    [0061] Furthermore, the second output control module, its connection relationship, external signals, etc. shown in Fig.12 are suitable to the shift register units according to the first, second, third, fifth, sixth, seventh, and eighth embodiments of the present disclosure.

    [0062] Fig.13 is a timing sequence diagram of signals inputted from CLK2, CLK1 and IN, potential at PU node, potential at PD node, signal outputted from CO, signal inputted from IOFF_IN(n), signal outputted from CA(n), and signal outputted from OUT(n) of the shift register unit according to the ninth embodiment of the present disclosure in operation, wherein S1, S2 and S3 refer to a pre-charging phase, an evaluating phase and a resetting phase, respectively.

    [0063] Fig.14 is a circuit diagram of a shift register unit according to a tenth embodiment of the present disclosure, and the shift register unit according to the tenth embodiment of the present disclosure is based on the shift register unit according to the ninth embodiment of the present disclosure.

    [0064] As shown in Fig.14, in the shift register unit according to the tenth embodiment of the present disclosure, in order to further avoid the effects of T41 and T42 on OUT(n), the output is divided into three stages so as to further ensure no electric leakage in the output.

    [0065] The shift register unit according to the tenth embodiment of the present disclosure further includes a first staged output TFT T31 and a second staged output TFT T32;

    wherein a gate of the first staged output TFT T31 is connected to the gate of the first carry signal output TFT T1 , a drain of the first staged output TFT T31 is connected to the first clock signal input terminal, and a source of the first staged output TFT T31 is connected to the source of the second feedback control TFT T42; and

    a gate of the second staged output TFT T32 is connected to the gate of the second carry signal output TFT T2, a source of the second staged output TFT T32 is connected to the second low level output terminal, and a drain of the second staged output TFT T32 is connected to the source of the first staged output TFT T31.



    [0066] Fig.15 is a timing sequence diagram of signals inputted from CLK2, CLK1 and IN, potential at PU node, potential at PD node, signal outputted from CO, signal inputted from IOFF_IN(n), signal outputted from CA(n), and signal outputted from OUT(n) of the shift register unit according to the tenth embodiment of the present disclosure in operation, wherein S1, S2 and S3 refer to a pre-charging phase, an evaluating phase and a resetting phase, respectively.

    [0067] Fig.16 is a circuit diagram of a shift register unit according to an eleventh embodiment not covered by the claims, and the shift register unit according to the eleventh example is based on the shift register unit according to the third embodiment. .

    [0068] In the shift register unit according to the eleventh embodiment,

    the first output control module 31 includes a first TFT T11, a second TFT T12, a third TFT T13 and a fourth TFT T14, wherein

    a gate of the first TFT T11 is connected to the input terminal IN, a source of the first TFT T11 is connected to the input terminal IN, and a drain of the first TFT T11 is connected to a source of the second TFT T12;

    a gate of the second TFT T12 is connected to the input terminal IN, and a source of the second TFT T12 is connected to a drain of the fourth TFT T14;

    a gate of the third TFT T13 is connected to a reset signal output terminal Rst(n), a drain of the third TFT T13 is connected to a drain of the second TFT T12, and a source of the third TFT T13 is connected to the drain of the fourth TFT T14;

    a gate of the fourth TFT T14 is connected to the reset signal output terminal Rst(n);

    the pulling-up node level maintaining module 34 includes a potential stabilizing capacitor C1 having a first terminal connected to the first low level output terminal and a second terminal connected to the drain of the first TFT T11 and the source of the third TFT T13.



    [0069] In Fig.16, a point M is a node connected to the second terminal of the potential stabilizing capacitor C1;

    [0070] The carry signal output terminal CA(n) is also connected to the reset signal output terminal RST(n-1) of the shift register unit at a previous stage.

    [0071] As shown in Fig. 17, the operation of the shift register unit according to the eleventh embodiment is divided into three phases:

    [0072] A first phase is a pre-charging phase S1, the first clock signal output terminal and the reset signal output terminal RST(n) output a first low level VGL1, and the input terminal IN inputs a high level VGH, T11 and T12 are turned on so that the bootstrap capacitor C is charged through the PU node and C1 is charged through the point M; Vgs (gate-source voltage) of T14 is zero since the voltage at the source of T14 is VGL1 and the potential at RST(n) is also VGL1, and T14 is turned on to a certain extent (referring to its characteristic graph, it can be seen that T14 is in the linear operation region and has a certain resistance); the potential at the point M increases rapidly as C1 is charged by the input terminal IN, Vgs of T13 is lower than zero since the potential at the source of T13 is the potential at the point M and the potential at the gate of T13 is VGL1, and thus T13 is completely turned off after the potential at the point M increase to a certain value, then the potential at the PU node will reach VGH in a short time; Vgs of T2 is zero since the potential at the PD node is VGL1 and T2 is turned on; Vgs of T4 is lower than zero since VGL2>VGL1 and T4 is turned off. As the potential at the PU node increases, T1 and T3 are turned on, OUT(n) outputs the low level VGL1 and CA(n) outputs the low level VGL1;

    [0073] A second phase is an evaluating phase S2: CLK1 jumps to a high level, the potential at the input terminal IN jumps to the first low level VGL1, RST(n) still outputs the first low level VGL1, Vgs of T11 and Vgs of T14 are zero, and thus T11 and T14 are turned on to a certain extent (that is, T11 and T14 are in the linear operation region and have a resistance); the potentials of the gates of T12 and T13 are VGL1, the potentials of the sources of the T12 and T13 are the potential at the point M, the point M is connected to C1 and the potential at the point M decreases slowly rather than jumping to VGL1 rapidly although C1 is discharged through T11 and T14 slowly, and the potential difference across C1 can be maintained larger than VGL1 in a half pulse width period only if the potential difference across C1 is larger than a certain value, thus the gate-source voltage Vgs of T12 and the gate-source Vgs of T13 are lower than zero and it is ensured that T12 and T13 are turned off, which in turn makes the potential at the PU node unchanged and being at the high level, as a result, T1 and T3 continue to be turned on and the potential at the PD node continues to be maintained at the low level VGL1, and T4 continues to be turned off and T2 keeps to be turned on to a certain extent, at this time, CLK1 is at the high level, the potential at the PU node further increases through C, T1 and T3 are further turned on, so OUT(n) outputs the high level VGH and CA(n) outputs the high level VGH;

    [0074] A third phase is a resetting phase S3: CLK1 jumps the first low level VGL1, RST(n) and the PD node output the high level VGH, T2 and T4 are turned on fully and T13 and T14 are turned on fully, so the potentials of the PU node and the point M are pulled down to VGL1, OUT(n) outputs VGL2 and CA(n) outputs VGL1 since T2 and T4 are turned on.

    [0075] At this point, the operation of the shift register unit ends, after the potential at the PU node is pulled down to VGL1, Vgs of T3 is lower than zero since OUT(n) outputs VGL2 and T3 is turned off, and the output of OUT(n) will not be affected when CLK1 becomes a high level again. CA(n) outputs VGL1 since T2 is turned on, although T1 may be turned on slightly.

    [0076] Fig.18 is a circuit diagram of a shift register unit according to a twelfth embodiment not covered by the claims, and the shift register unit according to the twelfth embodiment is based on the shift register unit according to the eleventh embodiment. .

    [0077] In the twelfth embodiment, the second output control module 32 includes an output control TFT T321 and an output control capacitor C322, wherein

    a gate of the output control TFT T321 is connected to the PU node, a source of the output control TFT T321 is connected to the first low level output terminal, a drain of the output control TFT T321 is connected to a first terminal of the output control capacitor C322;

    the first terminal of the output control capacitor C322 is connected to the drain of the output control TFT T321, and a second terminal of the output control capacitor C322 is connected to the first clock signal output terminal.



    [0078] Fig.19 shows the simulation results of the structure adopted in the present disclosure and the conventional structure for the depletion type TFT. As an example, the threshold voltage of TFT is -2V. In Fig.19, the horizontal axis represents time, and the vertical axis represents output voltage of the shift register, lin represents that the coordinate is a linear coordinate, and u represents that the unit of time is a microsecond. Graphs in the upper portion of Fig.19 show the simulation result of the shift register unit according to the disclosure for the depletion type TFT, and graphs in the lower portion of Fig.19 show the simulation result of the conventional shift register unit for the depletion type TFT. From the comparison between the simulation results of the shift register unit according to the disclosure and of the conventional shift register unit for the depletion type TFT, it can be known that the output of the conventional shift register unit attenuates and distorts rapidly due to the effect of the depletion type TFT, whereas the shift register unit according to the embodiments of the present disclosure operates normally. According to the comparison of the simulation results for the internal node Q, in the conventional shift register unit, the voltage at the point Q is discharged by the depletion type TFT in the evaluating phase, which is the immediate cause for the abnormal output; whereas the voltage at the point Q keeps normal in the shift register unit according to the embodiments of the present disclosure, which means the electric leakage of the depletion type TFT is suppressed effectively.

    [0079] In the present disclosure, there is further provided a driving method applied to the shift register units according to the fifth to tenth embodiments of the present disclosure, the driving method includes:

    a pre-charging step: in a period wherein the input terminal inputs a high level, the first clock signal is at a low level, the first output control module controls to pre-charge the bootstrap capacitor so as to turn the first carry signal output TFT and the first driving TFT on, and controls the carry signal output terminal and the driving signal output terminal to output a first low level so as to turn off the first feedback control TFT; the second output control module controls the control signal output terminal thereof to output the first low level, so as to turn on the second carry signal output TFT and turn off the second driving TFT;

    an evaluating step: in next half clock cycle, the first clock signal becomes a high level, the first output control module controls the carry signal output terminal and the driving signal output terminal to output a high level, so as to turn on the first feedback control TFT and make the gate of the first carry signal output TFT in a floating state; and

    a resetting step: in a third half clock cycle, the first clock signal becomes a low level, the first output control module controls the first carry signal output TFT and the first driving TFT to be turned on, the second output control module controls the second carry signal output TFT and the second driving TFT to be turned on, so as to make the carry signal output terminal output the first low level and the driving signal output terminal output the second low level.



    [0080] In the present disclosure, there is further provided a shift register including a plurality of the above described shift register units arranged at a plurality of stages;

    [0081] Except the shift register unit at a first stage, the input terminal of the shift register unit at each stage is connected to the carry signal output terminal of the shift register unit at a previous stage.

    [0082] As shown in Fig.20, the shift register according to the first embodiment is constituted by the shift register units at N stages and functions as a row scanner of an active matrix, wherein N is usually the number of rows of the active matrix, and N is an integer;

    S1, S2, ..., Sn, ..., Sn represent the shift register unit at a first stage, the shift register unit at a second stage, ..., the shift register unit at an nth stage, ..., and the shift register unit at an Nth stage;

    each of the shift register units is connected to the first clock signal input terminal, the second clock signal input terminal, the first low level output terminal and the second low level output terminal;

    the clock signal inputted from the first clock signal input terminal and the clock signal inputted from the second clock signal input terminal have opposite phases and a duty ratio 50%;

    wherein the input terminal IN of the shift register unit at the first stage is connected to an initial pulse signal STV which is active when being at the high level;

    except the shift register unit at the first stage, the input terminal of the shift register unit at each stage is connected to the carry signal output terminal of the shift register unit at a previous stage; each of the shift register units has two output terminals: the carry signal output terminal CA(n) connected to the input terminal IN of the shift register unit at a next stage, and a driving signal output terminal OUT(n) connected to the row scan line Gn of the Active Matrix, wherein n is an integer and is less than or equal to N;

    the clock control signals of shift register units at two adjacent stages have opposite phases, for example, if the first clock input terminal of the shift register unit at the first stage is connected to the first clock signal CLK1 and the second clock signal input terminal of the shift register unit at the first stage is connected to the second clock signal CLK2, then the first clock signal input terminal of the shift register unit at the second stage adjacent to the first stage is connected to the second clock signal CLK2 and the second clock signal input terminal of the shift register unit at the second stage is connected to the first clock signal CLK1.



    [0083] As shown in Fig.21, a shift register according to the second embodiment is based on the shift register according to the first embodiment, and the shift register according to the second embodiment includes the shift register unit according to the seventh, eighth, ninth or tenth embodiment of the present disclosure.

    [0084] The difference between the shift register according to the second embodiment and the shift register according to the first embodiment lies in that: except the shift register unit at a last stage, the cutting-off control signal input terminal of the shift register unit at each stage is connected to the cutting-off control signal output terminal of the shift register unit at a next stage.

    [0085] In the present disclosure, there is further provided a display apparatus including the above-described shift registers, the display apparatus may include liquid crystal display apparatuses, for example liquid crystal panel, liquid crystal television, mobile phone, liquid crystal display. Besides the liquid crystal display apparatus, the display apparatus may further include Organic Light-Emitting Display or other kinds of display apparatus, for example, electric reader, etc. The shift register can function as the scanning circuit or gate driving circuit of the display apparatus, so as to provide the function of progressive scanning and transfer the scanning signal to the display area.


    Claims

    1. A shift register unit, including:

    an input terminal (IN);

    a first output control module (31) having a control signal output terminal connected to a pulling-up node (PU), configured to pull up a driving signal in an evaluating phase;

    a second output control module (32) having a control signal output terminal connected to a pulling-down node (PD), configured to pull down the driving signal in a resetting phase;

    wherein the first output control module (31) is also connected to the input terminal (IN); wherein the shift register unit further includes:

    a carry signal output terminal (CA(n)) configured to output a carry signal;

    a driving signal output terminal (OUT(n)) configured to output the driving signal;

    a staged output module (33) connected to the pulling-up node (PU), the pulling-down node (PD), the carry signal output terminal (CA(n)) and the driving signal output terminal (OUT(n)), wherein the staged output module (33) comprises a carry signal output unit (332) and a driving signal output unit (331) configured to output the carry signal and the driving signal respectively so that the driving signal maintains a high level in the evaluating phase and a second low level in the resetting phase and the carry signal maintains the high level in the evaluating phase and a first low level which is different from the second low level in the resetting phase, wherein each of the carry signal output unit (332) and the driving signal output unit (331) is connected to the pulling-up node (PU) and the pulling-down node (PD);

    characterized in that the shift register unit further includes

    a pulling-up node level maintaining module (34) configured to, in the evaluating phase, maintain the level at the pulling-up node (PU) at another high level via the first output control module (31) so that the driving signal maintains said high level;

    wherein the first output control module (31) includes a feedback signal receiving terminal (CO); and

    the pulling-up node level maintaining module (34) includes: a first feedback control TFT (T41) having a gate connected to the carry signal output terminal (CA(n)), a source connected to the feedback signal receiving terminal (CO), and a drain connected to a first node (FN) which is a node different from the carry signal output terminal (CA(n)) to receive a feedback signal for maintaining the level at the pulling-up node (PU) in the evaluating phase,

    wherein the first feedback control TFT (T41) is a depletion type TFT;

    a threshold voltage of first feedback control TFT (T41) is the depletion threshold voltage;

    the first low level (VGL1) is lower than the second low level (VGL2), and wherein

    i) the first node is the driving signal output terminal (OUT(n)) and the absolute value of difference between the first low level and the second low level is larger than the depletion threshold voltage; or

    ii) the staged output module (33) further includes a staged output unit (333), the staged output unit (333) is connected to the pulling-up node (PU), the pulling-down node (PD), and the first node (FN), and is configured to output the feedback signal at the first node.


     
    2. The shift register unit according to claim 1, wherein

    the carry signal output unit (332) is configured to make the carry signal output terminal (CA(n)) output a first low level under the control of the first output control module (31) in a pre-charging phase and output the first low level under the control of the second output control module (32) in the resetting phase, and making the carry signal output terminal (CA(n)) output the high level under the control of the first output control module (31) in the evaluating phase; and

    the driving signal output unit is configured to make the driving signal output terminal (OUT(n)) output the high level under the control of the first output control module (31) in the evaluating phase, and making the driving signal output terminal output (OUT(n)) the first low level under the control of the first output control module (31) in the pre-charging phase and output the second low level under the control of the second output control module (32) in the resetting phase.


     
    3. The shift register unit according to claim 2, wherein

    the carry signal output unit (332) includes a first carry signal output Thin Film Transistor TFT (T1) and a second carry signal output TFT (T2);

    the first carry signal output TFT (T1) has a gate connected to the control signal output terminal of the first output control module (31), a source connected to the carry signal output terminal (CA(n)), and a drain connected to a first clock signal input terminal (CLK1); and

    the second carry signal output TFT (T2) has a gate connected to the control signal output terminal of the second output control module (32), a source connected to a first low level output terminal (VGL1), and a drain connected to the carry signal output terminal (CA(n)).


     
    4. The shift register unit according to claim 3, wherein

    the driving signal output unit (331) includes a first driving TFT (T3), a second driving TFT (T4) and a bootstrap capacitor (C);

    the first driving TFT (T3) has a gate connected to the control signal output terminal of the first output control module (31), a source connected to the driving signal output terminal (OUT(n)), and a drain connected to the first clock signal input terminal (CLK1);

    the second driving TFT (T4) has a gate connected to the control signal output terminal of the second output control module (32), a source connected to a second low level output terminal (VGL2), and a drain connected to the driving signal output terminal (OUT(n)); and

    the bootstrap capacitor (C) is connected in parallel between the gate and the source of the first driving TFT (T3).


     
    5. The shift register unit according to claim 4, wherein the first carry signal output TFT (T1), the second carry signal output TFT (T2), the first driving TFT (T3) and the second driving TFT (T4) are depletion type TFTs.
     
    6. The shift register unit according to claim 5, wherein

    a threshold voltage of the first carry signal output TFT (T1), a threshold voltage of the second carry signal output TFT (T2), a threshold voltage of the first driving TFT (T3) and a threshold voltage of the second driving TFT (T4) are a same depletion threshold voltage;

    the first low level is lower than the second low level, and the absolute value of difference between the first low level and the second low level is larger than the absolute value of the depletion threshold voltage.


     
    7. The shift register unit according to any one of claims 4-6, wherein the first output control module (31) further includes a first TFT (T11), a second TFT (T12), a third TFT (T13) and a fourth TFT (T14), wherein

    a gate and a source of the first TFT (T11) are connected to the input terminal (IN), and a drain of the first TFT (T11) is connected to a source of the second TFT (T12);

    a gate of the second TFT (T12) is connected to the input terminal (IN), and a drain of the second TFT (T12) is connected to a drain of the fourth TFT (T14);

    a gate of the third TFT (T13) is connected to a reset signal output terminal (Rst), a source of the third TFT (T13) is connected to the first low level output terminal (VGL1), and a drain of the third TFT (T13) is connected to a source of the fourth TFT (T14);

    a gate of the fourth TFT (T14) is connected to the reset signal output terminal (Rst);

    wherein the drain of the first TFT (T11) is also connected to the pulling-up node level maintaining module (34); and

    the drain of the second TFT (T12) is connected to the control signal output terminal of the first output control module (31).


     
    8. The shift register unit according to any one of claims 4-6 and i), wherein the second output control module (32) includes a first output control TFT (T21), a second output control TFT (T22), and a third output control TFT (T23), wherein

    a gate of the first output control TFT (T21) is connected to the gate of the first carry signal output TFT (T1), a source of the first output control TFT (T21) is connected to a drain of the second output control TFT (T22), and a drain of the first output control TFT (T11) is connected to the gate of the second carry signal output TFT (T2);

    a gate of the second output control TFT (T22) is connected to the gate of the first carry signal output TFT (T1), and a source of the second output control TFT (T22) is connected to the first low level output terminal (VGL1); and

    a gate and a drain of the third output control TFT (T23) are connected to a high level output terminal (VGH), and a source of the third output control TFT (T23) is connected to the gate of the second carry signal output TFT (T2).


     
    9. The shift register unit according to claim 1, wherein the shift register unit includes a cutting-off control signal input terminal (IOFF_IN(n)) and a cutting-off control signal output terminal (IOFF(n));

    the pulling-up node level maintaining module (34) further includes a second feedback control TFT (T42);

    a gate of the second feedback control TFT (T42) is connected to the carry signal output terminal (CA(n)), a source of the second feedback control TFT (T42) is connected to the first node (FN), and a drain of the second feedback control TFT (T42) is connected to the cutting-off control signal output terminal (IOFF(n)); and

    the second output control module (32) is connected to the cutting-off control signal input terminal (IOFF_IN(n)).


     
    10. The shift register unit according to claim 9 and ii), wherein the staged output unit (333) includes a first staged output TFT (T31) and a second staged output TFT (T32);

    a gate of the first staged output TFT (T31) is connected to the gate of the first carry signal output TFT (T1), a drain of the first staged output TFT (T31) is connected to the first clock signal input terminal (CLK1), and a source of the first staged output TFT (T31) is connected to the first node (FN); and

    a gate of the second staged output TFT (T32) is connected to the gate of the second carry signal output TFT (T2), a source of the second staged output TFT (T32) is connected to the second low level output terminal (VGL2), and a drain of the second staged output TFT (T32) is connected to the source of the first staged output TFT (T31).


     
    11. A driving method applied to the shift register unit according to any one of claims 4-10, wherein the driving method includes:

    in a phase wherein the input terminal (IN) inputs the high level, the first clock signal (CLK1) is at the first low level, the first output control module (31) controls to pre-charge the bootstrap capacitor (C), so as to control the carry signal output terminal (CA(n)) and the driving signal output terminal (OUT(n)) to output the first low level; the second output control module (32) controls the output terminal thereof to output the first low level;

    in a next half clock cycle, the first clock signal (CLK1) becomes the high level, the first output control module (31) controls the carry signal output terminal (CA(n)) and the driving signal output terminal (OUT(n)) to output the high level; and

    the first feedback control TFT (T41) maintains the level at the pulling-up node (PU) at another high level under control of the carry signal output by the carry signal output terminal (CA(n)) which is connected to the gate of the first feedback control TFT (T41); and

    in a third half clock cycle, the first clock signal (CLK1) becomes the first low level, the first output control module (31) and the second output control module (32) control the carry signal output terminal (CA(n)) to output the first low level and control the driving signal output terminal (OUT(n)) to output the second low level.


     
    12. A shift register, which includes a plurality of the shift register units (S1,S2,...,SN) according to any one of claims 1-8 arranged at a plurality of stages;
    except the shift register unit at a first stage (S1), the input terminal of the shift register unit at each stage is connected to the carry signal output terminal of the shift register unit at a previous stage.
     


    Ansprüche

    1. Schieberegistereinheit, beinhaltend:

    einen Eingangsanschluss (IN);

    ein erstes Ausgangssteuerungsmodul (31), aufweisend einen Steuerungssignalausgangsanschluss, angeschlossen an einen Pulling-Up-Knoten (PU), konfiguriert, ein Ansteuerungssignal in einer Evaluierungsphase hochzuziehen;

    ein zweites Ausgangssteuerungsmodul (32), aufweisend einen Steuerungssignalausgangsanschluss, angeschlossen an einen Pulling-Down-Knoten (PD), konfiguriert, um das Ansteuerungssignal in einer Rücksetzphase hinunterzuziehen;

    wobei das erste Ausgangssteuerungsmodul (31) auch an den Eingangsanschluss (IN) angeschlossen ist; wobei die Schieberegistereinheit außerdem beinhaltet:

    einen Trägersignalausgangsanschluss (CA(n)), konfiguriert, um ein Trägersignal auszugeben;

    einen Ansteuerungssignalausgangsanschluss (OUT(n)), konfiguriert, das Ansteuerungssignal auszugeben;

    ein gestuftes Ausgangsmodul (33), angeschlossen an den Pulling-Up-Knoten (PU), den Pulling-Down-Knoten (PD), den Trägersignalausgangsanschluss (CA(n)) und den Ansteuerungssignalausgangsanschluss (OUT(n)), wobei das gestufte Ausgangsmodul (33) eine Trägersignalausgangseinheit (332) und eine Ansteuerungssignal-ausgangseinheit (331), konfiguriert, das Trägersignal bzw. das Ansteuerungssignal auszugeben, so dass das Ansteuerungssignal einen hohen Level in der Evaluierungsphase und einen zweiten niedrigen Level in der Rücksetzphase behält und das Trägersignal den hohen Level in der Evaluierungsphase und einen ersten niedrigen Level, der verschieden von dem zweiten niedrigen Level ist, in der Rücksetzphase behält, umfasst, wobei jede von der Trägersignalausgangseinheit (332) und der Ansteuerungssignalausgangseinheit (331) an den Pulling-Up-Knoten (PU) und den Pulling-Down-Knoten (PD) angeschlossen ist;

    dadurch gekennzeichnet, dass die Schieberegistereinheit außerdem beinhaltet

    ein Pulling-Up-Knoten-Level-Erhaltungsmodul (34), konfiguriert, um in der Evaluierungsphase den Level des Pulling-Up-Knotens (PU) bei einem anderen hohen Level mittels des ersten Ausgangssteuerungsmoduls (31) zu erhalten, so dass das Ansteuerungssignal den hohen Level behält;

    wobei das erste Ausgangssteuerungsmodul (31) einen Feedback-Signalempfangsanschluss (CO) beinhaltet; und

    wobei das Pulling-Up-Knoten-Level-Erhaltungsmodul (34) beinhaltet: einen ersten Feedback-Steuerungs-TFT (T41), aufweisend ein Gate, angeschlossen an den Trägersignalausgangsanschluss (CA(n)), eine Source, angeschlossen an den Feedback-Signalempfangsanschluss (CO) und ein Drain, angeschlossen an einen ersten Knoten (FN), welcher ein von dem Trägersignalausgangsanschluss (CA(n)) verschiedener Knoten ist, um ein Feedback-Signal zu empfangen zur Erhaltung des Levels bei dem Pulling-Up-Knoten (PU) in der Evaluierungsphase,

    wobei der erste Feedback-Steuerungs-TFT (T41) ein Verarmungstyp-TFT ist;

    wobei eine Schwellenspannung des ersten Feedback-Steuerungs-TFT (T41) die Verarmungsschwellenspannung ist;

    wobei der erste niedrige Level (VGL1) niedriger ist als der zweite niedrige Level (VGL2), und wobei

    i) der erste Knoten des Ansteuerungssignalausgangsanschlusses (OUT(n)) ist und der absolute Wert der Differenz zwischen dem ersten niedrigen Level und dem zweiten niedrigen Level niedriger als die Verarmungsschwellenspannung ist; oder

    ii) wobei das gestufte Ausgangsmodul (33) außerdem eine gestufte Ausgangseinheit (333) beinhaltet, wobei die gestufte Ausgangseinheit (333) an den Pulling-Up-Knoten (PU), den Pulling-Down-Knoten (PD) und den ersten Knoten (FN) angeschlossen ist und konfiguriert ist, das Feedbacksignal bei dem ersten Knoten auszugeben.


     
    2. Schieberegistereinheit gemäß Anspruch 1, wobei

    die Trägersignalausgangseinheit (332) konfiguriert ist, den Trägersignalausgangsanschluss (CA(n)) zu veranlassen, einen ersten niedrigen Level auszugeben unter der Steuerung des ersten Ausgangssteuerungsmoduls (31) in einer Vorladephase und den ersten niedrigen Level auszugeben unter der Steuerung des zweiten Ausgangssteuerungsmoduls (32) in der Rücksetzphase, und den Trägersignalausgangsanschluss (CA(n)) zu veranlassen, den hohen Level unter der Steuerung des ersten Ausgangssteuerungsmoduls (31) in der Evaluierungsphase auszugeben; und

    wobei die Ansteuerungssignalausgangseinheit konfiguriert ist, den Ansteuerungssignalausgangsanschluss (OUT(n)) zu veranlassen, den hohen Level unter der Steuerung des ersten Ausgangssteuerungsmoduls (31) in der Evaluierungsphase auszugeben, und den Ansteuerungssignalausgangsanschluss (OUT(n)) zu veranlassen, den ersten niedrigen Level unter der Steuerung des ersten Ausgangssteuerungsmoduls (31) in der Vorladephase auszugeben und den zweiten niedrigen Level auszugeben unter der Steuerung des zweiten Ausgangssteuerungsmoduls (32) in der Rücksetzphase.


     
    3. Schieberegistereinheit gemäß Anspruch 2, wobei

    die Trägersignalausgangseinheit (332) einen ersten Trägersignalausgangs-Dünnfilmtransistor TFT (T1) und einen zweiten Trägersignalausgangs-TFT (T2) beinhaltet,

    wobei der erste Trägersignalausgangs-TFT (T1) ein an den Steuerungssignalausgangsanschluss des ersten Ausgangssteuerungsmoduls (31) angeschlossenes Gate, eine an den Trägersignalausgangsanschluss (CA(n)) angeschlossene Source und einen an den ersten Taktsignaleingangsanschluss (CLK1) angeschlossenen Drain aufweist;

    wobei der zweite Trägersignal Ausgangs-TFT (T2) ein an den Steuerungssignalausgangsanschluss des zweiten Ausgangssteuerungsmoduls (32) angeschlossenes Gate, eine an den ersten Niedrig-Level-Ausgangsanschluss (VGL1) angeschlossene Source und einen an den Trägersignalausgangsanschluss (CA(n)) angeschlossenen Drain aufweist.


     
    4. Schieberegistereinheit gemäß Anspruch 3, wobei

    die Ansteuerungssignal-Ausgangseinheit (331) einen ersten Ansteuerungs-TFT (T3), einen Ansteuerungs-TFT (T4) und einen Bootstrap-Kondensator (C) beinhaltet;

    wobei der erste Ansteuerungs-TFT (T3) ein an den Steuerungssignalausgangsanschluss des ersten Ausgangssteuerungsmoduls (31) angeschlossenes Gate, eine an den Ansteuerungssignalausgangsanschluss (OUT(n)) angeschlossene Source und einen an den ersten Taktsignaleingangsanschluss (CLK1) angeschlossenen Drain aufweist;

    wobei der zweite Ansteuerungs-TFT (T4) ein an den Steuerungssignalausgangsanschluss des zweiten Ausgangssteuerungsmoduls (32) angeschlossenes Gate, eine an einen zweiten Niedriglevelausgangsanschluss (VGL2) angeschlossene Source und einen an den Ansteuerungssignalausgangsanschluss (OUT(n)) angeschlossenen Drain aufweist; und

    wobei der Bootstrap-Kondensator (C) zwischen dem Gate und der Source des ersten Ansteuerungs-TFTs (T3) parallel geschaltet ist.


     
    5. Schieberegistereinheit gemäß Anspruch 4, wobei der erste Trägersignalausgangs-TFT (T1), der zweite Trägersignalausgangs-TFT (T2), der erste Ansteuerungs-TFT (T3) und der zweite Ansteuerungs-TFT (T4) Verarmungstyp-TFTs sind.
     
    6. Schieberegistereinheit gemäß Anspruch 5, wobei eine Schwellenspannung des ersten Trägersignalausgangs-TFTs (T1), eine Schwellenspannung des zweiten Trägersignalausgangs-TFTs (T2), eine Schwellenspannung des ersten Ansteuerungs-TFTs (T3) und eine Schwellenspannung des zweiten Ansteuerungs-TFTs (T4) eine gleiche Verarmungs-Schwellenspannung sind;
    wobei der erste niedrige Level niedriger ist als der zweite niedrige Level, und wobei der absolute Wert der Differenz zwischen dem ersten niedrigen Level und dem zweiten niedrigen Level größer ist als der absolute Wert der Verarmungsschwellenspannung.
     
    7. Schieberegistereinheit gemäß einem der Ansprüche 4-6, wobei das erste Ausgangssteuerungsmodul (31) außerdem einen ersten TFT (T11), einen zweiten TFT (T12), einen dritten TFT (T13) und einen vierten TFT (T14) beinhaltet, wobei

    ein Gate und eine Source des ersten TFTs (T11) an den Eingangsanschluss (IN) angeschlossen sind, und wobei ein Drain des ersten TFTs (T11) an eine Source des zweiten TFTs (T12) angeschlossen ist;

    ein Gate des zweiten TFTs (T12) an den Eingangsanschluss (IN) angeschlossen ist, und ein Drain des zweiten TFTs (T12) an einen Drain des vierten TFTs (T14) angeschlossen ist;

    ein Gate des dritten TFTs (T13) an einen Rücksetzsignal-Ausgangsanschluss (Rst) angeschlossen ist, eine Source des dritten TFTs (T13) an den ersten Niedriglevelausgangsanschluss (VGL1) angeschlossen ist,

    und ein Drain des dritten TFTs (T13) an eine Source des vierten TFTs (T14) angeschlossen ist;

    ein Gate des vierten TFTs (T14) an den Rücksetzsignal-Ausgangsanschluss (Rst) angeschlossen ist;

    wobei der Drain des ersten TFTs (T11) auch an das Pulling-Up-Knoten-Level-Erhaltungsmodul (34) angeschlossen ist; und

    der Drain des zweiten TFTs (T12) an den Steuerungssignalausgangsanschluss des ersten Ausgangssteuerungsmoduls (31) angeschlossen ist.


     
    8. Schieberegistereinheit gemäß einem der Ansprüche 4-6 und i), wobei das zweite Ausgangssteuerungsmodul (32) einen ersten Ausgangssteuerungs-TFT (T21), einen zweiten Ausgangssteuerungs-TFT (T22) und einen dritten Ausgangssteuerungs-TFT (T23) beinhaltet, wobei

    ein Gate des ersten Ausgangssteuerungs-TFTs (T21) an das Gate des ersten Trägersignalausgangs-TFTs (T1) angeschlossen ist, eine Source des ersten Ausgangssteuerungs-TFTs (T21) an einen Drain des zweiten Ausgangssteuerungs-TFTs (T22) angeschlossen ist, und ein Drain des ersten Ausgangssteuerungs-TFTs (T11) an das Gate des zweiten Trägersignalausgangs-TFT s (T2) angeschlossen ist;

    wobei ein Gate des zweiten Ausgangssteuerungs-TFTs (T22) an das Gate des ersten Trägersignalausgangs-TFTs (T1) angeschlossen ist, und eine Source des zweiten Ausgangssteuerungs-TFTs (T22) an den ersten Niedriglevelausgangsanschluss (VGL1) angeschlossen ist; und

    wobei ein Gate und ein Drain des dritten Ausgangssteuerungs-TFTs (T23) an einen Hochlevelausgangsanschluss (VGH) angeschlossen sind, und eine Source des dritten Ausgangssteuerungs-TFTs (T23) an das Gate des zweiten Trägersignalausgangs-TFTs (T2) angeschlossen ist.


     
    9. Schieberegistereinheit gemäß Anspruch 1, wobei die Schieberegistereinheit einen Ausschaltsteuerungssignaleingangsanschluss (IOFF_IN(n)) und einen Ausschaltsteuerungssignalausgangsanschluss (IOFF_(n)) enthält;

    wobei das Pulling-Up-Knoten-Level-Erhaltungsmodul (34) außerdem einen zweiten Feedback-Steuerungs-TFT (T42) enthält;

    wobei ein Gate des zweiten Feedback-Steuerungs-TFTs (T42) an den Trägersignalausgangsanschluss (CA(n)) angeschlossen ist, eine Source des zweiten Feedback-Steuerungs-TFTs (T42) an den ersten Knoten (FN) angeschlossen ist, und ein Drain des zweiten Feedback-Steuerungs-TFTs (T42) an den Ausschaltsteuerungssignalausgangsanschluss (IOFF_(n)) angeschlossen ist; und

    wobei das zweite Ausgangssteuerungsmodul (32) an den Ausschaltsteuerungssignaleingangsanschluss (IOFF_IN(n)) angeschlossen ist.


     
    10. Schieberegistereinheit gemäß Anspruch 9 und ii), wobei die gestufte Ausgangseinheit (333) einen ersten gestuften Ausgangs-TFT (T31) und einen zweiten gestuften Ausgangs-TFT (T32) enthält;

    wobei ein Gate des ersten gestuften Ausgangs-TFTs (T31) an das Gate des ersten Trägersignalausgangs-TFTs (T1) angeschlossen ist, ein Drain des ersten gestuften Ausgangs-TFTs (T31) an den ersten Taktsignaleingangsanschluss (CLK1) angeschlossen ist, und eine Source des ersten gestuften Ausgangs-TFTs (T31) an den ersten Knoten (FN) angeschlossen ist; und

    wobei ein Gate des zweiten gestuften Ausgangs-TFTs (T32) an das Gate des zweiten Trägersignalausgangs-TFTs (T2) angeschlossen ist, eine Source des zweiten gestuften Ausgangs-TFTs (T32) an den zweiten Niedriglevelausgangsanschluss (VGL2) angeschlossen ist, und ein Drain des zweiten gestuften Ausgangs-TFTs (T32) an die Source des ersten gestuften Ausgangs-TFTs (T31) angeschlossen ist.


     
    11. Ansteuerungsverfahren, angewendet auf die Schieberegistereinheit gemäß einem der Ansprüche 4-10, wobei das Ansteuerungsverfahren beinhaltet:

    in einer Phase, in welcher der Eingangsanschluss (IN) den hohen Level eingibt, ist das erste Taktsignal (CLK1) bei dem ersten niedrigen Level, das erste Ausgangssteuerungsmodul (31) steuert, um den Bootstrap-Kondensator (C) vorzuladen, um den Trägersignalausgangsanschluss (CA(n)) und den Ansteuerungssignalausgangsanschluss (OUT(n)) zu steuern, den ersten niedrigen Level auszugeben; das zweite Ausgangssteuerungsmodul (32) steuert den Ausgangsanschluss davon, um den ersten niedrigen Level auszugeben;

    in einem nächsten halben Taktzyklus wird das erste Taktsignal (CLK1) das hohe Level, das erste Ausgangssteuerungsmodul (31) steuert den Trägersignalausgangsanschluss (CA(n)) und den Ansteuerungssignalausgangsanschluss (OUT(n)), um den hohen Level auszugeben; und

    der erste Feedback-Steuerungs-TFT (T41) hält den Level bei dem Pulling-Up-Knoten (PU) bei einem anderen hohen Level unter Steuerung des Trägersignalausgangs mittels des Trägersignalausgangsanschlusses (CA(n)), welcher an das Gate des ersten Feedback-Steuerungs-TFTs (T41) angeschlossen ist;

    und in einem dritten halben Taktzyklus wird das erste Taktsignal (CLK1) der erste niedrige Level, das erste Ausgangssteuerungsmodul (31) und das zweite Ausgangssteuerungsmodul (32) steuern den Trägersignalausgangsanschluss (CA(n)), um den ersten niedrigen Level auszugeben, und steuern den Ansteuerungssignalausgangsanschluss (OUT(n)), um den zweiten niedrigen Level auszugeben.


     
    12. Schieberegister, welches eine Mehrzahl von den Schieberegistereinheiten (S1, S2 ..., SN) gemäß einem der Ansprüche 1-8, angeordnet in einer Mehrzahl von Stufen, enthält;
    wobei mit Ausnahme der Schieberegistereinheit bei einer ersten Stufe (S1) der Eingangsanschluss der Schieberegistereinheit bei jeder Stufe an den Trägersignalausgangsanschluss der Schieberegistereinheit bei einer vorangehenden Stufe angeschlossen ist.
     


    Revendications

    1. Unité de registre à décalage, incluant :

    un terminal d'entrée (IN) ;

    un premier module de commande de sortie (31) ayant un terminal de sortie de signal de commande connecté à un nœud ascendant (PU), configuré pour faire monter un signal de pilotage dans une phase d'évaluation ;

    un deuxième module de commande de sortie (32) ayant un terminal de sortie de signal de commande connecté à un nœud descendant (PD), configuré pour faire descendre le signal de pilotage dans une phase de réinitialisation ;

    dans laquelle le premier module de commande de sortie (31) est également connecté au terminal d'entrée (IN) ; dans laquelle l'unité de registre à décalage comprend en outre :

    un terminal de sortie de signal porteur (CA(n)) configuré pour émettre un signal porteur ;

    un terminal de sortie de signal de pilotage (OUT(n)) configuré pour émettre le signal de pilotage ;

    un module de sortie étagé (33) connecté au nœud ascendant (PU), au nœud descendant (PD), au terminal de sortie de signal porteur (CA(n)) et au terminal de sortie de signal de pilotage (OUT(n)), dans laquelle le module de sortie étagé (33) comprend une unité de sortie de signal porteur (332) et une unité de sortie de signal de pilotage (331) configurées pour émettre le signal porteur et le signal de pilotage respectivement de façon à ce que le signal de pilotage maintienne un niveau haut dans la phase d'évaluation et un deuxième niveau bas dans la phase de réinitialisation et que le signal porteur maintienne le niveau haut dans la phase d'évaluation et un premier niveau bas qui est différent du deuxième niveau bas dans la phase de réinitialisation, dans laquelle chacune de l'unité de sortie de signal porteur (332) et de l'unité de sortie de signal de pilotage (331) est connectée au nœud ascendant (PU) et au nœud descendant (PD) ;

    caractérisée en ce que l'unité de registre à décalage comprend en outre

    un module de maintien de niveau de nœud ascendant (34) configuré pour, dans la phase d'évaluation, maintenir le niveau au nœud ascendant (PU) à un autre niveau haut par le biais du premier module de commande de sortie (31) de façon à ce que le signal de pilotage maintienne ledit niveau haut ;

    dans laquelle le premier module de commande de sortie (31) inclut un terminal de réception de signal de retour (CO) ; et

    le module de maintien de niveau de nœud ascendant (34) inclut : un premier TFT de commande de retour (T41) ayant une grille connectée au terminal de sortie de signal porteur (CA(n)), une source connectée au terminal de réception de signal de retour (CO), et un drain connecté à un premier nœud (FN) qui est un nœud différent du terminal de sortie de signal porteur (CA(n)) pour recevoir un signal de retour pour maintenir le niveau au nœud ascendant (PU) dans la phase d'évaluation,

    dans laquelle le premier TFT de commande de retour (T41) est un TFT de type appauvrissement ;

    une tension seuil du premier TFT de commande de retour (T41) est la tension seuil d'appauvrissement ;

    le premier niveau bas (VGL1) est inférieur au deuxième niveau bas (VGL2), et dans laquelle

    i) le premier nœud est le terminal de sortie de signal de pilotage (OUT(n)) et la valeur absolue de différence entre le premier niveau bas et le deuxième niveau bas est plus grande que la tension seuil d'appauvrissement ; ou

    ii) le module de sortie étagé (33) inclut en outre une unité de sortie étagée (333), l'unité de sortie étagée (333) est connectée au nœud ascendant (PU), au nœud descendant (PD) et au premier nœud (FN) et est configurée pour émettre le signal de retour au premier nœud.


     
    2. Unité de registre à décalage selon la revendication 1, dans laquelle l'unité de sortie de signal porteur (332) est configurée pour faire que le terminal de sortie de signal porteur (CA(n)) émette un premier niveau bas sous la commande du premier module de commande de sortie (31) dans une phase de pré-chargement et émette le premier niveau bas sous la commande du deuxième module de commande de sortie (32) dans la phase de réinitialisation, et de faire que le terminal de sortie de signal porteur (CA(n)) émette le niveau haut sous la commande du premier module de commande de sortie (31) dans la phase d'évaluation ; et
    l'unité de sortie de signal de pilotage est configurée pour faire que le terminal de sortie de signal de pilotage (OUT(n)) émette le niveau haut sous la commande du premier module de commande de sortie (31) dans la phase d'évaluation, et pour faire que le terminal de sortie de signal de pilotage (OUT(n)) émette le niveau bas sous la commande du premier module de commande de sortie (31) dans la phase de pré-chargement et émette le deuxième niveau bas sous la commande du deuxième module de commande de sortie (32) dans la phase de réinitialisation.
     
    3. Unité de registre à décalage selon la revendication 2, dans laquelle l'unité de sortie de signal porteur (332) inclut un premier transistor en couches minces TFT de sortie de signal porteur (T1) et un deuxième TFT de sortie de signal porteur (T2) ;

    le premier TFT de sortie de signal porteur (T1) présente une grille connectée au terminal de sortie de signal de commande du premier module de commande de sortie (31), une source connectée au terminal de sortie de signal porteur (CA(n)) et un drain connecté à un premier terminal d'entrée de signal d'horloge (CLK1) ; et

    le deuxième TFT de sortie de signal porteur (T2) présente une grille connectée au terminal de sortie de signal de commande du deuxième module de commande de sortie (32), une source connectée à un premier terminal de sortie de niveau bas (VGL1) et un drain connecté au terminal de sortie de signal porteur (CA(n)).


     
    4. Unité de registre à décalage selon la revendication 3, dans laquelle

    l'unité de sortie de signal de pilotage (331) inclut un premier TFT de pilotage (T3), un deuxième TFT de pilotage (T4) et un condensateur bootstrap (C) ;

    le premier TFT de pilotage (T3) présente une grille connectée au terminal de sortie de signal de commande du premier module de commande de sortie (31), une source connectée au terminal de sortie de signal de pilotage (OUT(n)), et un drain connecté au premier terminal d'entrée de signal d'horloge (CLK1) ;

    le deuxième TFT de pilotage (T4) présente une grille connectée au terminal de sortie de signal de commande du deuxième module de commande de sortie (32), une source connectée à un deuxième terminal de sortie de niveau bas (VGL2), et un drain connecté au terminal de sortie de signal de pilotage (OUT(n)) ;
    et

    le condensateur bootstrap (C) est connecté en parallèle entre la grille et la source du premier TFT de pilotage (F3) .


     
    5. Unité de registre à décalage selon la revendication 4, dans laquelle
    le premier TFT de sortie de signal porteur (T1), le deuxième TFT de sortie de signal porteur (T2), le premier TFT de pilotage (T3) et le deuxième TFT de pilotage (T4) sont des TFT de type appauvrissement.
     
    6. Unité de registre à décalage selon la revendication 5, dans laquelle

    une tension seuil du premier TFT de sortie de signal porteur (T1), une tension seuil du deuxième TFT de sortie de signal porteur (T2), une tension seuil du premier TFT de pilotage (T3) et une tension seuil du deuxième TFT de pilotage (T4) sont une même tension seuil d'appauvrissement ;

    le premier niveau bas est inférieur au deuxième niveau bas, et la valeur absolue de différence entre le premier niveau bas et le deuxième niveau bas est plus grande que la valeur absolue de la tension seuil d'appauvrissement.


     
    7. Unité de registre à décalage selon l'une quelconque des revendications 4-6, dans laquelle le premier module de commande de sortie (31) inclut en outre un premier TFT (T11), un deuxième TFT (T12), un troisième TFT (T13) et un quatrième TFT (T14), dans laquelle

    une grille et une source du premier TFT (T11) sont connectées au terminal d'entrée (IN), et un drain du premier TFT (T11) est connecté à une source du deuxième TFT (T12) ;

    une grille du deuxième TFT (T12) est connectée au terminal d'entrée (IN), et un drain du deuxième TFT (T12) est connecté à un drain du quatrième TFT (T14) ;

    une grille du troisième TFT (T13) est connectée à un terminal de sortie de signal de réinitialisation (Rst), une source du troisième TFT (T13) est connectée au premier terminal de sortie de niveau bas (VGL1) et un drain du troisième TFT (T13) est connecté à une source du quatrième TFT (T14) ;

    une grille du quatrième TFT (T14) est connectée au terminal de sortie de signal de réinitialisation (Rst) ;

    dans laquelle le drain du premier TFT (T11) est également connecté au module de maintien de niveau de nœud ascendant (34) ; et

    le drain du deuxième TFT (T12) est connecté au terminal de sortie de signal de commande du premier module de commande de sortie (31).


     
    8. Unité de registre à décalage selon l'une quelconque des revendications 4-6 et i), dans laquelle le deuxième module de commande de sortie (32) inclut en outre un premier TFT de commande de sortie (T21), un deuxième TFT de commande de sortie (T22) et un troisième TFT de commande de sortie (T23), dans laquelle

    une grille du premier TFT de commande de sortie (T21) est connectée à la grille du premier TFT de sortie de signal porteur (T1), une source du premier TFT de commande de sortie (T21) est connectée à un drain du deuxième TFT de commande de sortie (T22), et un drain du premier TFT de commande de sortie (T11) est connectée à la grille du deuxième TFT de sortie de signal porteur (T2) ;

    une grille du deuxième TFT de commande de sortie (T22) est connectée à la grille du premier TFT de sortie de signal porteur (T1), et une source du deuxième TFT de commande de sortie (T22) est connectée au premier terminal de sortie de niveau bas (VGL1) ; et

    une grille et un drain du troisième TFT de commande de sortie (T23) sont connectées à un terminal de sortie de niveau haut (VGH), et une source du troisième TFT de commande de sortie (T23) est connectée à la grille du deuxième TFT de sortie de signal porteur (T2).


     
    9. Unité de registre à décalage selon la revendication 1, dans laquelle l'unité de registre à décalage inclut un terminal d'entrée de signal de commande de coupure (IOFF_IN(n)) et un terminal de sortie de signal de commande de coupure (IOFF(n)) ;

    le module de maintien de niveau de nœud ascendant (34) inclut en outre un deuxième TFT de commande de retour (T42) ;

    une grille du deuxième TFT de commande de retour (T42) est connectée au terminal de sortie de signal porteur (CA(n)), une source du deuxième TFT de commande de retour (T42) est connectée au premier nœud (FN), et un drain du deuxième TFT de commande de retour (T42) est connecté au terminal de sortie de signal de commande de coupure (IOFF(n)) ; et

    le deuxième module de commande de sortie (32) est connecté au terminal d'entrée de signal de commande de coupure (IOFF_IN(n)).


     
    10. Unité de registre à décalage selon la revendication 9 et ii), dans laquelle l'unité de sortie étagée (333) inclut un premier TFT de sortie étagé (T31) et un deuxième TFT de sortie étagé (T32) ;

    une grille du premier TFT de sortie étagé (T31) est connectée à la grille du premier TFT de sortie de signal porteur (T1), un drain du premier TFT de sortie étagé (T31) est connecté au premier terminal d'entrée de signal d'horloge (CLK1), et une source du premier TFT de sortie étagé (T31) est connectée au premier nœud (FN) ; et

    une grille du deuxième TFT de sortie étagé (T32) est connectée à la grille du deuxième TFT de sortie de signal porteur (T2), une source du deuxième TFT de sortie étagé (T32) est connectée au deuxième terminal de sortie de niveau bas (VGL2), et un drain du deuxième TFT de sortie étagé (T32) est connecté à la source du premier TFT de sortie étagé (T31).


     
    11. Procédé de pilotage appliqué à l'unité de registre à décalage selon l'une quelconque des revendications 4-10, dans lequel le procédé de pilotage inclut :

    dans une phase dans laquelle le terminal d'entrée (IN) entre le niveau haut, le premier terminal d'horloge (CLK1) est au premier niveau bas, le premier module de commande de sortie (31) commande pour pré-charger le condensateur bootstrap (C) de façon à commander le terminal de sortie de signal porteur (CA(n)) et le terminal de sortie de signal de pilotage (OUT(n)) à émettre le premier niveau bas ; le deuxième module de commande de sortie (32) commande le terminal de sortie de celui-ci à émettre le premier niveau bas ;

    dans un demi-cycle d'horloge suivant, le premier signal d'horloge (CLK1) devient le niveau haut, le premier module de commande de sortie (31) commande le terminal de sortie de signal porteur (CA(n)) et le terminal de sortie de signal de pilotage (OUT(n)) à émettre le niveau haut ; et

    le premier TFT de commande de retour (T41) maintient le niveau au nœud ascendant (PU) à un autre niveau haut sous la commande du signal porteur émis par le terminal de sortie de signal porteur (CA(n)) qui est connecté à la grille du premier TFT de commande de retour (T41) ; et

    dans un troisième demi-cycle d'horloge, le premier signal d'horloge (CLK1) devient le premier niveau bas, le premier module de commande de sortie (31) et le deuxième module de commande de sortie (32) commandent le terminal de sortie de signal porteur (CA(n)) à émettre le premier niveau bas et commander le terminal de sortie de signal de pilotage (OUT(n)) à émettre le deuxième niveau bas.


     
    12. Registre à décalage qui inclut une pluralité des unités de registre à décalage (S1, S2, ...SN) selon l'une quelconque des revendications 1 - 8 agencées à une pluralité d'étages ; à l'exception de l'unité de registre à décalage à un premier étage (S1), le terminal d'entrée de l'unité de registre à décalage à chaque étage est connecté au terminal de sortie de signal porteur de l'unité de registre à décalage à un étage précédent.
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description