(19)
(11)EP 2 871 683 A1

(12)EUROPEAN PATENT APPLICATION

(43)Date of publication:
13.05.2015 Bulletin 2015/20

(21)Application number: 14185635.1

(22)Date of filing:  19.09.2014
(51)International Patent Classification (IPC): 
H01L 31/0749(2012.01)
H01L 31/18(2006.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME

(30)Priority: 07.11.2013 EP 13191997

(71)Applicants:
  • IMEC
    3001 Leuven (BE)
  • Katholieke Universiteit Leuven
    3000 Leuven (BE)
  • Universiteit Hasselt
    3500 Hasselt (BE)

(72)Inventors:
  • Buffiere, Marie
    3001 Leuven (BE)
  • Meuris, Marc
    3001 Leuven (BE)
  • Brammertz, Guy
    3001 Leuven (BE)

(74)Representative: Bird Goën & Co 
Wetenschapspark Arenberg Gaston Geenslaan 9
3001 Heverlee
3001 Heverlee (BE)

  


(54)Method for cleaning and passivating chalcogenide layers


(57) A method is disclosed for chemically cleaning and passivating a chalcogenide layer, wherein the method comprises contacting the chalcogenide layer with an ammonium sulfide containing ambient. Further, a method is disclosed for fabricating a photovoltaic cell, wherein the method comprises: providing a chalcogenide semiconductor layer (12) on a substrate (10); contacting the chalcogenide semiconductor layer (12) with an ammonium sulfide ((NH4)2S) containing ambient, thereby removing impurities from and passivating the chalcogenide semiconductor layer; and afterwards providing a buffer layer (13) on the chalcogenide semiconductor layer (12).




Description

Field



[0001] The present disclosure relates to methods for chemically cleaning and passivating chalcogenide layers.

[0002] More in particular, the present disclosure relates to methods for chemically cleaning and passivating chalcogenide semiconductor layers that may be used as active layers in semiconductor devices such as absorber layers in photovoltaic cells.

[0003] The present disclosure further relates to methods for fabricating chalcogenide based photovoltaic cells.

State of the art



[0004] Chalcopyrite ternary thin films, such as copper-indium-gallium-sulfoselenide (CuIn1-XGaX(S,Se)2) films, and kesterite quaternary thin films, such as copper-zinc-tin-sulfoselenide (Cu2ZnSn(S,Se)4) films, generically referred to as CIGS and CZTS, have become the subject of considerable interest and study for semiconductor devices in recent years. These materials are also referred to as I-III-VI2 and I2-II-IV-VI4 materials according to their constituent elemental groups. These materials are of particular interest for use as an absorber layer in photovoltaic devices.

[0005] For photovoltaic applications, a p-type CIGS or CZTS layer may be combined with an thin n-type semiconductor layer such as for example a CdS layer to form a p-n heterojunction CdS/CIGS or CdS/CZTS device. The preparation of the CIGS or CZTS absorber layer requires temperatures around 400°C to 600°C and a vacuum environment. During this preparation, the formation of trace amounts of binary/ternary compositions (secondary phases or impurity phases) consisting of selenides, oxides, carbonates, etc., may occur. These trace amounts of impurity phases may be formed at the nascent absorber surfaces. The presence of such impurities at the CIGS or CZTS surfaces negatively affects photovoltaic conversion efficiencies of photovoltaic cells comprising these materials. Therefore, there is a need to clean the CIGS or CZTS surfaces before the deposition of the CdS buffer layer, to remove these impurities and to avoid their negative influence on the photovoltaic conversion efficiency.

[0006] In addition, photovoltaic cell conversion efficiencies may be improved by the passivation of defects that are inherently present in the compound semiconductor chalcogenide material. Passivation of these defects may lead to longer minority carrier lifetimes and higher photovoltaic cell efficiencies.

[0007] Copper selenide (CuxSe) is a common secondary phase in copper indium gallium selenide (CIGS) and copper zinc tin selenide (CZTS) layers. While a copper-rich layer composition may lead to enhanced grain growth, it results in the formation of a CuxSe phase which can increase the shunt conductance in a photovoltaic cell comprising such absorber layer. Selective etching of the secondary phase after grain growth solves this problem.

[0008] It is known that copper-selenide (CuxSe) impurities and most probably also copper-sulfide (CuxS) impurities may be removed (etched) by means of a potassium cyanide (KCN) solution. However, KCN is a highly toxic compound, and therefore an alternative, safer compound would be more suitable for industrial processing of photovoltaic cells.

[0009] Alternative solutions for removing CuxSe compounds from a CIGS surface have been reported, including chemical, electrochemical and thermal treatments. Chemical treatments may for example comprise treatment in ammonia combined with heating, or bromine/methanol treatment, bromine being a toxic compound. Electrochemical treatments have the disadvantage that the substrate needs to be contacted with electrodes. Thermal treatments may lead to stress and cracks in the layers, e.g. due to differences in thermal expansion coefficient between the CIGS layer and the substrate.

[0010] Methods for the passivation of CIGS layer surfaces have been reported. For example, CIGS films may be treated in an aqueous solution containing InCl3 and CH3CSNH2, resulting in the formation of a passivating CuInS2 layer on the CIGS surface and to an improved photovoltaic cell efficiency. Alternatively, CIGS films may be treated in a Cd or Zn containing solution by immersing the films in the solution and heating. Another alternative method for passivation comprises thermal annealing, e.g. in an H2S containing environment.

Summary



[0011] The present disclosure aims to provide methods for chemically removing, typically undesired, secondary phases (impurity phases) from chalcogenide layers, wherein less toxic chemicals are used as compared to prior art methods.

[0012] The present disclosure aims to provide methods for chemically removing secondary phases (impurity phases) from chalcogenide layers, wherein the surface of the chalcogenide layers is simultaneously passivated.

[0013] The present disclosure aims to provide methods for chemically removing secondary phases (impurity phases) from chalcogenide layers, wherein the chemical removing may be done without heating.

[0014] In embodiments of the present disclosure the chalcogenide layer may comprise a chalcogenide semiconductor material. In embodiments of the present disclosure the chalcogenide layer may for example comprise Cu. The chalcogenide layer may for example comprise a ternary or a quaternary chalcogenide material. For example, the chalcogenide material may be a I2-II-IV-VI4 material such as Copper Zinc Tin Sulfide (CZTS) or Copper Zinc Tin Selenide (CZTSe), or it may be a I-III-VI2 material such as Copper Indium Gallium Sulfide (CIGS) or Copper Indium Gallium Selenide (CIGSe), the present disclosure not being limited thereto.

[0015] The disclosure is related to methods for chemically cleaning and passivating chalcogenide layers. In the context of the present disclosure, "chemically cleaning" means chemically removing secondary phases or impurity phases formed e.g. during the preparation of chalcogenide layers. Such secondary phases or impurity phases may for example contain Cu, the present disclosure not being limited thereto. In the context of the present disclosure, "chemically passivating" means chemically increasing the lifetime of minority carriers in the chalcogenide layer near its surface (or increasing the lifetime of minority carriers in the chalcogenide layer near its surface by purely chemical treatment or processes), or chemically reducing the recombination velocity of minority carriers in the chalcogenide layer at or near its surface (or reducing the recombination velocity of minority carriers in the chalcogenide layer at or near its surface by purely chemical treatment or processes).

[0016] The present disclosure provides a method for chemically cleaning and passivating a chalcogenide layer formed on a substrate, wherein the method comprises contacting the chalcogenide layer with an ammonium sulfide ((NH4)2S) containing ambient, i.e. by bringing in contact the chalcogenide layer and the ammonium sulfide ((NH4)2S) containing ambient, e.g. by exposing the chalcogenide layer to the ammonium sulfide ((NH4)2S) containing ambient.

[0017] Contacting the chalcogenide layer with an ammonium sulfide containing ambient may comprise soaking or dipping or immersing the chalcogenide layer in a liquid solution containing ammonium sulfide. This may for example be done at ambient temperature, using a 1 weight percentage (wt%) to 50 wt% solution, e.g. a 10wt% to 30wt% solution, of ammonium sulfide in water, for about 1 minute to about 60 minutes.

[0018] Alternatively, contacting the chalcogenide layer with an ammonium sulfide containing ambient may comprise bringing the chalcogenide layer in an ambient containing ammonium sulfide vapor. This may for example be done by placing the chalcogenide layer in a closed container (e.g. closed beaker) containing an ammonium sulfide solution, for example for 10 to 60 minutes, e.g. without heating., i.e. at ambient temperature.

[0019] After the step of contacting the chalcogenide layer with an ammonium sulfide containing ambient, a rinsing step may be performed, for example comprising rinsing in deionized water for a few minutes, e.g. 1 to 5 minutes.

[0020] In a method of the present disclosure, the chalcogenide layer may be formed on the substrate by means of any suitable method known by a person skilled in the art, such as for example co-evaporation, Molecular Beam Epitaxy or solution processing, the present disclosure not being limited thereto. The substrate may for example be a soda lime glass substrate coated with a Mo thin film, or any other suitable substrate that withstands the temperatures and atmosphere used during the formation of the chalcogenide layer.

[0021] Methods of the present disclosure may advantageously be used for treating (cleaning, passivating) thin chalcogenide films such as CIGS or CZTS films used as an absorber layer in photovoltaic cells, before the deposition of a buffer layer such as a CdS buffer layer on the absorber layer.

[0022] It is an advantage of a method for chemically cleaning a chalcogenide layer according to the present disclosure that it uses a less toxic and safer chemical compound as compared to methods wherein potassium cyanide (KCN) is used for removing, i.e. etching, Cu-rich and Se-rich phases present on chalcogenide layers or films, such as for example CIGSe or CIGS or CZTSe or CZTS thin films used in thin film photovoltaic cells.

[0023] It is an advantage of a method for chemically cleaning a chalcogenide layer according to the present disclosure that it not only results in removal of secondary phases but that it simultaneously results in passivation of the chalcogenide layer, in particular surface passivation of the chalcogenide layer. The etching or cleaning and the passivation are thus performed in a single process step.

[0024] It is an advantage of a method for chemically cleaning a chalcogenide layer according to the present disclosure that it may be performed at ambient temperature, i.e. it may be performed without heating.

[0025] The present disclosure further provides a method for fabricating photovoltaic cells, wherein the method comprises: providing a chalcogenide semiconductor layer on a substrate; contacting the chalcogenide semiconductor layer with an ammonium sulfide ((NH4)2S) containing ambient (i.e. by bringing in contact the chalcogenide layer and the ammonium sulfide ((NH4)2S) containing ambient, e.g. by exposing the chalcogenide layer to an ammonium sulfide ((NH4)2S) containing ambient), thereby removing impurities from and passivating the chalcogenide semiconductor layer; and afterwards providing a buffer layer on the chalcogenide semiconductor layer.

[0026] Contacting the chalcogenide layer with an ammonium sulfide containing ambient may comprise soaking or dipping or immersing the substrate with the chalcogenide layer in a liquid solution containing ammonium sulfide. This may for example be done at ambient temperature, using a 1 wt% to 50 wt% solution of ammonium sulfide, for about 1 minute to 60 minutes.

[0027] Alternatively, contacting the chalcogenide layer with an ammonium sulfide containing ambient may comprise bringing the substrate with the chalcogenide layer in an ambient containing ammonium sulfide vapor. This may for example be done by placing the chalcogenide layer in a closed container (e.g. closed beaker) containing an ammonium sulfide solution, for example for 10 to 60 minutes, e.g. without heating, i.e. at ambient temperature.

[0028] After the step of contacting the chalcogenide layer with an ammonium sulfide containing ambient, a rinsing step may be performed, for example comprising rinsing in deionized water for a few minutes, e.g. 1 to 5 minutes.

[0029] In a method for fabricating photovoltaic cells according to the present disclosure, the buffer layer may for example be a CdS layer, a zinc oxy-sulfide (Zn(O,S)) layer or an indium sulfide (In2S3) layer, the present disclosure not being limited thereto.

[0030] The method for fabricating photovoltaic cells of the present disclosure may further comprise: providing a rear contact layer on the substrate before providing the chalcogenide semiconductor layer, e.g. directly on top of the rear contact layer; providing a window layer, the window layer being an optically transparent layer e.g. comprising a high band-gap material, such as for example a ZnO layer, on top of the buffer layer; and providing front contacts.

[0031] It is an advantage of a method for fabricating photovoltaic cells according to the present disclosure that it enables the fabrication of cells with improved current-voltage characteristics and with improved cell efficiency.

[0032] Certain objects and advantages of various inventive aspects have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosure. Thus, for example, those skilled in the art will recognize that the disclosure may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein. Further, it is understood that this summary is merely an example and is not intended to limit the scope of the disclosure. The disclosure, both as to organization and method of operation, together with features and advantages thereof, may best be understood by reference to the following detailed description when read in conjunction with the accompanying drawings.

Brief description of the figures



[0033] 

Figure 1 shows the result of lifetime measurements on CIGSe layers after contacting with an ammonium sulfide containing liquid according to a method of the present disclosure, for different contacting times (t= 0, 2, 5 and 15 minutes).

Figure 2 schematically shows a cross section of a CIGSe photovoltaic cell as used in experiments.

Figure 3 shows measured current-voltage characteristics under illumination for CIGSe photovoltaic cells wherein the initially Cu-rich CIGSe layer was treated with KCN, for different treatment times (0, 2, 5 and 15 minutes).

Figure 4 shows measured current-voltage characteristics under illumination for CIGSe photovoltaic cells wherein the initially Cu-rich CIGSe layer was treated with ammonium sulfide in accordance with the present disclosure, for different treatment times (0, 2, 5 and 15 minutes).

Figure 5 shows a graph of measured open-circuit voltages Voc for CIGSe cells fabricated according to a method of the present disclosure, as a function of the duration of the ammonium sulfide treatment, for devices with initially Cu-poor CIGSe layers.

Figure 6 illustrates the evolution of the chemical concentrations of Cu, In, Ga and Se as found by ICP-AES measurements performed on Cu-rich CIGSe samples after different immersion times in KCN or S(NH4)2 solutions.



[0034] Any reference signs in the claims shall not be construed as limiting the scope of the present disclosure.

[0035] In the different drawings, the same reference signs refer to the same or analogous elements.

Detailed description



[0036] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure and how it may be practiced in particular embodiments. However, it will be understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures and techniques have not been described in detail, so as not to obscure the present disclosure.

[0037] The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not necessarily correspond to actual reductions to practice of the disclosure.

[0038] Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. The terms are interchangeable under appropriate circumstances and the embodiments of the disclosure can operate in other sequences than described or illustrated herein.

[0039] Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein are capable of operation in other orientations than described or illustrated herein.

[0040] In the context of the present disclosure, a "Cu-rich" layer or a "Cu-rich" chalcogenide layer is a chalcogenide layer comprising a more than stoichiometric amount of Cu. For example, a Cu-rich CIGS layer is a layer wherein [Cu]/([In] + [Ga]) is larger than 1. For example, a Cu-rich CZTS layer is a CZTS layer wherein [Cu]/([Zn] + [Sn]) is larger than 1. Similarly, in the context of the present disclosure, a "Cu-poor" chalcogenide layer is a chalcogenide layer comprising a less than stoichiometric amount of Cu, such as for example a CIGS layer wherein [Cu]/([In] + [Ga]) is smaller than 1.

[0041] A method of the present disclosure comprises chemically cleaning a chalcogenide layer formed on a substrate by contacting the chalcogenide layer with an ammonium sulfide ((NH4)2S) containing liquid or vapor, thereby removing impurities and/or secondary phases from the chalcogenide layer.

[0042] Experiments were done wherein a CuIn0.7Ga0.3Se2 (CIGSe) layer was deposited by co-evaporation on a glass substrate covered with a Molybdenum (Mo) layer. The thickness of the CIGSe layer was about 2 micrometer. Due to the presence of a CuxSe phase the average Cu ratio ([Cu]/([In]+[Ga]) was about 1.1. The substrate with the Curich CIGSe layer was then dipped in a 20% (NH4)2S solution for 1 minute, 3 minutes and 12 minutes respectively, followed by 3 minutes of rinsing in deionized water. Based on a SEM analysis it was shown that the surface of the Cu-rich CIGSe layer was etched by the (NH4)2S solution. From a comparison with samples etched in KCN, it was concluded that the CuxSe secondary phase had been removed by the (NH4)2S treatment after 12 minutes of etching.

[0043] Figure 6 shows the evolution of the concentrations of Cu, Se, In and Ga species in the KCN or S(NH4)2 solutions for different immersion times (i.e., 30, 60, 120, 740 or 840 s) of Cu-rich CIGSe samples ([Cu]/[In+Ga]=1.2), as measured by Inductively coupled plasma atomic emission spectroscopy (ICP-AES). Both chemical treatments lead to the etching of mainly Cu and Se, while the Ga and In contents in the solutions remain relatively low. Although lower etching rates are observed in case of S(NH4)2 compared to KCN, the obtained results confirm that S(NH4)2 can be used as an alternative selective etchant of CuxSe phases present in CIGSe absorber. The obtained results were further confirmed by top view SEM analysis showing an evolution in the surface morphology of the CIGSe thin film due to the removal of the CuxSe capping layer. Similar results were also observed in case of Cu-rich CZTSe absorber layers treated in both solutions (i.e., KCN and S(NH4)2).

[0044] Minority carrier lifetimes of the CuIn0.7Ga0.3Se2 layers were extracted from Time Resolved Photo-Luminescence (TRPL) measurements, for as-deposited layers (0 minutes etch time) and for layers etched in a 20% (NH4)2S solution for 2 minutes, 5 minutes and 15 minutes respectively, followed by 3 minutes of rinsing in deionized water. The TRPL measurements were done with a near infrared compact fluorescence lifetime measurement system with an excitation wavelength of 532 nm, The illuminated area had a diameter of about 3 mm and the average laser power was 1.38 mW.

[0045] The results of these measurements are shown in Figure 1. It was found that the carrier lifetime increases with increasing treatment duration (increasing etch time). This may confirm the removal of the CuxSe phase, the presence of which is known to decrease the minority carrier lifetime. Similar experiments were done wherein the chalcogenide layers were treated in a KCN solution instead of a (NH4)2S solution. After a 15 minutes treatment of the layers in the (NH4)2S solution, higher minority carrier lifetimes were measured than for layers treated in the KCN solution using an optimal etching time. This may be an indication that the treatment with the (NH4)2S solution also provides a passivation of the chalcogenide layer.

[0046] In further experiments, photovoltaic cells comprising a CIGSe absorber layer and a CdS buffer layer were fabricated. A cross section of the cell structure used in the experiments is schematically shown in Figure 2. On a Soda Lime Glass substrate 10 a Mo back contact layer 11 with a thickness of 400 nm was deposited. A 2 micrometer thick CIGSe absorber layer 12 was then deposited by co-evaporation, optionally followed by etching in a KCN solution according to the prior art or in a (NH4)2S solution in accordance with the present disclosure. Different etching times were used: 0 minutes (no treatment), 2 minutes, 5 minutes and 15 minutes. After rinsing in deionized water, a 50 nm thick CdS buffer layer 13 was provided by chemical bath deposition, followed by RF magnetron sputter deposition of a 60 nm thick intrinsic ZnO window layer 14 and a 350 nm thick ZnO:Al (Al doped ZnO) front contact layer 15. On top of the ZnO:Al front contact layer 15 a Ni:AL grid 16 was provided.

[0047] Figure 3 shows measured current-voltage characteristics under AM1.5G illumination for photovoltaic cells wherein a Cu-rich CIGSe layer ([Cu]/([In] + [Ga]) = 1.1) was treated with KCN, for different treatment times. Figure 4 shows measured current-voltage characteristics under AM1.5G illumination for photovoltaic cells wherein such CIGSe layer was treated with ammonium sulfide in accordance with the present disclosure, for different treatment times.

[0048] The I-V analysis of the Cu-rich samples after different treatment times confirms that the CuxSe phase is removed when using a method of the present disclosure (similar to when using KCN) since the diode behavior of the cells is improved. The I-V curves of the reference samples (i.e. without treatment) show as expected a resistance-like behavior due to shunts induced by the presence of a CuxSe phase. When increasing the etching time, the CuxSe phase is progressively etched and therefore the photovoltaic cell electrical behavior is improved, which is in good agreement with the literature and with SEM pictures. Similar observations can be made for samples treated with KCN and for samples treated with (NH4)2S. However, for the process conditions used (20%wt (NH4)2S solution), the optimal etching time is longer than when using a KCN solution, indicating a lower etching rate in the case of the (NH4)2S treatment.

[0049] Higher cell efficiencies were obtained for photovoltaic cells wherein the absorber layer was treated with a (NH4)2S solution as compared to cells wherein the absorber layer was treated with a KCN solution. This may be related to the passivation of the absorber layer by the (NH4)2S solution.

[0050] A similar experiment was done for photovoltaic cells with an initially Cu-poor CIGSe absorber layer (with [Cu]/([In]+{Ga])=0.9). For these photovoltaic cells a significant improvement of the open circuit voltage (Voc) was obtained when using a treatment according to the present disclosure, as well as an improved homogeneity on a series of photovoltaic cells. The Voc was found to increase with increasing treatment time, until a certain point. This is illustrated in Figure 5, showing a graph of measured open-circuit voltages Voc as a function of the duration of the ammonium sulfide treatment. These results are in agreement with a reduction of the surface recombination velocity of minority carriers as a result of the treatment, and illustrate the passivating effect of a (NH4)2S treatment of the present disclosure.

[0051] X-ray photoelectron spectroscopy (XPS) analyses have been performed on a Cu-poor CIGSe layer without treatment, on a CIGSe layer after 5 min of chemical treatment using ammonia sulfide and 3 min of rinsing in deionized water, and on a CIGSe layer after 5 min of chemical treatment in KCN and 3 min of rinsing in deionized water. Compared to the reference sample without treatment, there is a clear modification of the chemistry of Se after both treatments ((NH4)2S treatment and KCN treatment), which could be either explained by the removal of secondary phases such as CuxSe or elemental Se, or by the etching of Se from the CIGSe phase itself. It was further observed that for the layer treated with ammonia sulfide the sample shows a very limited amount of sulfur (about 1 to 2 atomic percentage (at%)) incorporated on the surface of the absorber. This was not the case for the sample treated in KCN. Further analysis of the ammonia sulfide treated sample indicated that a 1 nm to 2 nm thin Cu(In,Ga)S2 layer was present on the surface of the CIGSe layer. The formation of this sulfur containing layer may explain the passivating effect of the (NH4)2S treatment of the present disclosure.

[0052] The foregoing description details certain embodiments of the disclosure. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the disclosure may be practiced in many ways. It should be noted that the use of particular terminology when describing certain features or aspects of the disclosure should not be taken to imply that the terminology is being re-defined herein to be restricted to including any specific characteristics of the features or aspects of the disclosure with which that terminology is associated.

[0053] While the above detailed description has shown, described, and pointed out novel features of the invention as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the technology without departing from the invention.


Claims

1. A method for chemically cleaning and passivating a chalcogenide layer, wherein the method comprises contacting the chalcogenide layer with an ammonium sulfide containing ambient.
 
2. The method according to claim 1, wherein contacting the chalcogenide layer with the ammonium sulfide containing ambient comprises immersing the chalcogenide layer in a liquid solution containing ammonium sulfide.
 
3. The method according to claim 2, wherein the liquid solution is a solution of 1 wt% to 50 wt% of ammonium sulfide in water.
 
4. The method according to claim 1, wherein contacting the chalcogenide layer with the ammonium sulfide containing ambient comprises bringing the chalcogenide layer in an ambient containing ammonium sulfide vapor.
 
5. The method according to any of the previous claims, wherein the chalcogenide layer is a chalcogenide semiconductor layer.
 
6. The method according to any of the previous claims, wherein the chalcogenide layer is a Cu containing layer.
 
7. A method for fabricating a photovoltaic cell, wherein the method comprises: providing a chalcogenide semiconductor layer (12) on a substrate (10); contacting the chalcogenide semiconductor layer (12) with an ammonium sulfide ((NH4)2S) containing ambient, thereby removing impurities from and passivating the chalcogenide semiconductor layer; and afterwards providing a buffer layer (13) on the chalcogenide semiconductor layer (12).
 
8. The method according to claim 7, wherein contacting the chalcogenide semiconductor layer (12) with the ammonium sulfide containing ambient comprises immersing the chalcogenide semiconductor layer (12) in a liquid solution containing ammonium sulfide.
 
9. The method according to claim 8, wherein the liquid solution is a solution of 1 wt% to 50 wt% of ammonium sulfide in water.
 
10. The method according to claim 7, wherein contacting the chalcogenide semiconductor layer (12) with the ammonium sulfide containing ambient comprises bringing the chalcogenide semiconductor layer (12) in an ambient containing ammonium sulfide vapor.
 
11. The method according to any of claims 7 to 10, wherein the buffer layer (13) is a CdS layer, a zinc oxy-sulfide (Zn(O,S)) layer or an indium sulfide (In2S3) layer.
 
12. The method according to any of claims 7 to 11, further comprising providing a rear contact layer (11) on the substrate (10) before providing the chalcogenide semiconductor layer (12), providing a window layer (14) on top of the buffer layer (13), providing a front contact layer (15) and providing a front contact grid (16).
 




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