(19)
(11)EP 2 894 661 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
07.09.2022 Bulletin 2022/36

(21)Application number: 15150677.1

(22)Date of filing:  09.01.2015
(51)International Patent Classification (IPC): 
H01L 21/18(2006.01)
(52)Cooperative Patent Classification (CPC):
H01L 21/187; H01L 31/0693; H01L 31/1892; H01L 31/043; Y02E 10/544; Y02E 10/547; Y02P 70/50

(54)

Directly bonded, lattice-mismatched semiconductor device

Direkt gebondetes, gitter-fehlangepasstes Halbleiterbauelement

Dispositif de semi-conducteurs directement liés à désaccord de réseau


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 10.01.2014 US 201414152464

(43)Date of publication of application:
15.07.2015 Bulletin 2015/29

(73)Proprietor: The Boeing Company
Chicago, IL 60606-1596 (US)

(72)Inventors:
  • Law, Daniel C.
    Arcadia, CA California 91007 (US)
  • King, Richard R.
    Thousand Oaks, CA California 91360 (US)
  • Krut, Dimitri Daniel
    Encino, CA California 91436 (US)
  • Bhusari, Dhananjay
    Santa Clarita, CA California 91387 (US)

(74)Representative: Howson, Richard Giles Bentham et al
Kilburn & Strode LLP Lacon London 84 Theobalds Road
London WC1X 8NL
London WC1X 8NL (GB)


(56)References cited: : 
US-A1- 2002 052 061
US-A1- 2005 067 377
US-A1- 2012 138 116
US-A1- 2003 213 950
US-A1- 2010 116 327
  
  • M. Levinshtein, S. Rumyantsev, M. Shur: "Handbook series on Semiconductor Parameters", 1 May 1997 (1997-05-01), World Scientific Publishing, Singapore vol. 2
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

FIELD



[0001] The disclosed system and method relate to a semiconductor device and, more particularly, to a directly bonded, lattice-mismatched semiconductor device.

BACKGROUND



[0002] Wafer joining technology may be used to integrate various properties from different materials into one compact process-compatible material system. Wafer joining technology has great potential. For example, joining GaAs or InP-based materials to other semiconductor materials may result in the integration of optical, photovoltaic, and electronic devices and enhance the performance of computers, solar cells, light emitting diodes and other electronic devices.

[0003] Group III-V semiconductor materials are comprised of one or more elements from Group III of the periodic table and one or more elements from Group V of the periodic table. One of the limitations of Group III-V semiconductor devices, such as multi-junction solar cells, is the need to incorporate various lattice-matched device components within a semiconductor device. Specifically, lattice-matching may limit the possible bandgap combinations between device components in the semiconductor device. Thus, in an effort to expand or widen the bandgap combinations between various device components within a semiconductor device, inverted metamorphic (IMM) technologies may be employed to grow device components that are lattice-mismatched to their growth substrate. Specifically, IMM technologies may invert the usual growth order of device components, where the lattice-mismatched device components may be grown last. Moreover, multiple transparent buffer layers may be used to absorb the strain of the lattice-mismatch between various device components. However, incorporating multiple transparent buffer layers may increase the cost of the semiconductor device. Moreover, the resulting semiconductor device grown using IMM technologies may require an additional device handle, which also adds cost to the semiconductor device.

[0004] In another approach to create a semiconductor device, lattice-matched materials of specific bandgap combinations may be directly bonded to one another. A sacrificial lateral etch layer and an epitaxial lift-off process may be employed to recycle the growth substrate in an effort to reduce cost. Some examples of the growth substrate include GaAs-based, InP-based, and GaSb-based materials. However, there still exists a need for a cost-effective semiconductor device having a relatively wide range of bandgap combinations between device components.

[0005] US2002052061A1, in accordance with its abstract, describes a structure and method of fabricating an optically active layer embedded in a Si wafer, such that the outermost epitaxial layer exposed to the CMOS processing equipment is always Si or another CMOS-compatible material such as SiO2. Since the optoelectronic layer is completely surrounded by Si, the wafer is fully compatible with standard Si CMOS manufacturing. For wavelengths of light longer than the bandgap of Si (1.1 µm), Si is completely transparent and therefore optical signals can be transmitted between the embedded optoelectronic layer and an external waveguide using either normal incidence (through the Si substrate or top Si cap layer) or in-plane incidence (edge coupling).

[0006] US2005067377A1, in accordance with its abstract, describes methods of forming a germanium on insulator structure and its associated structures. Those methods comprise forming an epitaxial germanium layer on a sacrificial silicon layer, removing a portion of the epitaxial germanium layer and an oxide layer disposed on a silicon substrate in an oxygen plasma, and bonding the epitaxial germanium layer to the oxide layer to form a germanium on insulator structure.

[0007] US2003213950A1, in accordance with its abstract, describes a substrate including a base substrate, a interfacial bonding layer disposed on the base substrate, and a thin film adaptive crystalline layer disposed on the interfacial bonding layer. The interfacial bonding layer is solid at room temperature, and is in liquid-like form when heated to a temperature above room temperature. The interfacial bonding layer may be heated during epitaxial growth of a target material system grown on the thin film layer to provide the thin film layer with lattice flexibility to adapt to the different lattice constant of the target material system. Alternatively, the thin film layer is originally a strained layer having a strained lattice constant different from that of the target material system but with a relaxed lattice constant very close to that of the target material system, which lattice constant is relaxed to its relaxed value by heating the interfacial bonding layer after the thin film layer is removed from the first semiconductor substrate, so that the thin film layer has am adjusted lattice constant equal to its unstrained, relaxed value and very close to the lattice constant of the target material system.

[0008] US20100116327A1, in accordance with its abstract, describes a method of manufacturing a solar cell by providing a first semiconductor substrate and depositing a first sequence of layers of semiconductor material to form a first solar subcell, including a first bond layer disposed on the top of the first sequence of layers. A second semiconductor substrate is provided, and on the top surface of the second substrate a second sequence of layers of semiconductor material is deposited forming at least a second solar subcell. A second bond layer is disposed o the top of the second sequence of layers. The first solar subcell is mounted on top of the second solar subcell by joining the first bond layer to the second bond layer in an ultra high vacuum chamber, and the first semiconductor substrate is removed.

SUMMARY



[0009] In one aspect of the invention to which this European patent relates, there is provided, a semiconductor device including a first subassembly and a second subassembly. The first subassembly includes a first bonding layer of (Al)(Ga)InP(As)(Sb) and a first substrate constructed of a group III-V material. The second subassembly includes a second substrate constructed of germanium and a second bonding layer of (Al)(Ga)InP(As)(Sb) that is directly bonded to the first bonding layer. The first bonding layer and the second bonding layer are lattice-mismatched with one another. The second bonding layer is lattice-mismatched to the second substrate

[0010] In another aspect of the invention to which this European patent relates, there is provided, a method of making a semiconductor device may include providing a first subassembly comprising a first bonding layer of (Al)(Ga)InP(As)(Sb) and a first substrate constructed of a group III-V material. The method includes providing a second subassembly comprising a second substrate constructed of germanium and a second bonding layer of (Al)(Ga)InP(As)(Sb). The method includes directly bonding the first bonding layer and the second bonding layer together. The first bonding layer and the second bonding layer are lattice-mismatched to one another. The second bonding layer is lattice-mismatched to the second substrate.

[0011] Optionally, a buffer layer is epitaxially grown on the second substrate.

[0012] Optionally, the second substrate includes an active Ge subcell.

[0013] Optionally, the second subassembly includes semiconductor layers lattice-mismatched to the second substrate.

[0014] Optionally, the first bonding layer is lattice-mismatched to the first substrate.

[0015] Optionally, the first subassembly includes first semiconductor layers lattice-matched to the first substrate.

[0016] Optionally, the first subassembly includes a buffer layer epitaxially grown on the first semiconductor layers.

[0017] Optionally, the first subassembly includes second semiconductor layers lattice-mismatched to the first substrate.

[0018] Optionally, the second semiconductor layers are epitaxially grown on the buffer layer.

[0019] Optionally, at least one of the first subassembly and the second subassembly includes one of a photovoltaic device and a solar cell.

[0020] Optionally, the method includes epitaxially growing a buffer layer on the second substrate.

[0021] Optionally, epitaxially growing the second bonding layer upon the buffer layer.

[0022] Optionally, the method comprises creating an active Ge subcell within the second substrate by a diffusion of dopants into a layer of the second substrate.

[0023] Optionally, the method comprises epitaxially growing first semiconductor layers upon the first substrate of the first subassembly, wherein the first semiconductor layers are lattice-matched to the first substrate.

[0024] Optionally, the method comprises epitaxially growing a buffer layer upon the first semiconductor layers.

[0025] Optionally, the method comprises epitaxially growing second semiconductor layers on the buffer layer, wherein the second semiconductor layers are lattice-mismatched to the first substrate, and wherein the first bonding layer is lattice-mismatched to the first substrate. Other objects and advantages of the disclosed method and system will be apparent from the following description, the accompanying drawings and the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS



[0026] 

FIG. 1 is an illustration of an embodiment of a preassembled structure including a first subassembly and a second subassembly;

FIG. 2 is an illustration of the first subassembly and the second subassembly shown in FIG. 1 directly bonded to one another to create a semiconductor device;

FIG. 3 is an exemplary process flow diagram illustrating a method of fabricating the semiconductor device shown in FIG. 2;

FIG. 4 is an illustration of another embodiment of a preassembled structure including a first subassembly and a second subassembly;

FIG. 5 is an illustration of the first subassembly and the second subassembly shown in FIG. 4 directly bonded to one another to create a semiconductor device;

FIG. 6 is an exemplary process flow diagram illustrating a method of fabricating the semiconductor device shown in FIG. 5;

FIG. 7 is an illustration of yet another embodiment of a preassembled structure including a first subassembly and a second subassembly;

FIG. 8 is an illustration of the first subassembly and the second subassembly shown in FIG. 7 directly bonded to one another to create a semiconductor device;

FIG. 9 is an exemplary process flow diagram illustrating a method of fabricating the semiconductor device shown in FIG. 8.


DETAILED DESCRIPTION



[0027] As shown in FIG. 1, a preassembled structure 100 according to an embodiment of the disclosure includes a first subassembly 102 and a second subassembly 104. The first subassembly 102 includes a first wafer 110 and a first bonding layer 120 directly adjacent and upon a first surface 110a of the first wafer 110. The first wafer 110 is a semiconductor selected from group III-V materials. In an embodiment, the first wafer 110 may be selected from the group consisting of GaAs-based, InP-based, GaP based, GaSb-based, Ga(In)N-based materials. The first surface 110a of the first wafer 110 may be a surface of a material layer selected from the group consisting of Gallium Arsenide (GaAs), Indium Phosphide (InP), Gallium Phosphide (GaP), Gallium Antimonide (GaSb), Gallium Indium Arsenide (GaInAs), Gallium Indium Phosphide (GaInP), Gallium Indium Nitride Ga(In)N materials.

[0028] The first bonding layer 120 may be epitaxially grown upon the first surface 110a of the first wafer 110. In one embodiment, the first bonding layer 120 is an (Al)(Ga)InP(As)(Sb) material having a relatively high dopant concentration equal to or greater than about 5 x 1018/cm3. It is to be understood that a relatively high doping concentration may not be necessary for sufficient mechanical bonding, but may be needed for achieving a low electrical resistance across a bonded interface (shown in FIG. 2 as a bonded interface 150). However, if a low electrical resistance across the bonded interface 150 is not required, then a relatively high doping concentration in the first bonding layer 120 may not be necessary. As used herein, and as conventional in the art, the use of parentheses in the (Al)(Ga)InP(As)(Sb) material indicates that the incorporation of aluminum, gallium, arsenic, and antimony is optional. In the embodiment as shown in FIG. 1, the first bonding layer 120 may be lattice-matched to the first wafer 110, and may include a first bonding surface 120a.

[0029] The second subassembly 104 includes a second wafer 130, an optional buffer layer, and a second bonding layer 140. In the embodiment as shown in FIG. 1, the second bonding layer 140 may be directly adjacent and upon a second surface 130a of the second wafer 130. The second wafer 130 is a Ge substrate wafer. The second wafer 130 may be used as a growth substrate as well as for structural support. Specifically, the second wafer 130 may be used as a substrate for epitaxial growth of the second bonding layer 140 as well as the main mechanical support for an assembled semiconductor device 200 (shown in FIG. 2).

[0030] In one embodiment, the second wafer 130 may include an active Ge subcell 134. However, it is to be understood that in some embodiments, the Ge subcell 134 may be omitted. In one exemplary embodiment, the Ge subcell 134 may include an energy bandgap of about 0.67 eV. The Ge subcell 134 may be created by a diffusion of dopants into a surface layer of the second wafer 130. In other words, the Ge subcell 134 may not be epitaxially grown. Thus, the Ge subcell may be part of the second wafer 130.

[0031] The second bonding layer 140 may be epitaxially grown upon the second surface 130a of the second wafer 130. Similar to the first bonding layer 120, in one embodiment the second bonding layer 140 is also an (Al)(Ga)InP(As)(Sb) material having a relatively high dopant concentration equal to or greater than about 5 x 1018/cm3. It is to be understood that a relatively high doping concentration may not be necessary for sufficient mechanical bonding, but may be needed for achieving a low electrical resistance across the bonded interface (shown in FIG. 2 as the bonded interface 150). However, if a low electrical resistance across the bonded interface is not required, then a relatively high doping concentration in the second bonding layer 140 may not be necessary.

[0032] In the exemplary embodiment as shown in FIG. 1, the second bonding layer 140 is lattice-mismatched to the second wafer 130, and is described in detail below and illustrated in FIGS. 4-9. The second bonding layer 140 of the second subassembly 104 is lattice-mismatched to the first bonding layer 120 of the first subassembly 102. In all the embodiments as described and shown in FIGS. 1-9, the first bonding layer 120 and the second bonding layer 140 are lattice-mismatched to one another.

[0033] FIG. 2 is an illustration of the semiconductor device 200 according to an embodiment of the disclosure, where the first bonding layer 120 and the second bonding layer 140 have been directly bonded together to join the first subassembly 102 to the second subassembly 104. In one embodiment, the semiconductor device 200 may be a photovoltaic device, a solar cell, a light sensor, light emitting diode, or a transistor.

[0034] The first subassembly 102 and the second subassembly 104 may be directly bonded to one another by placing the first bonding layer 120 and the second bonding layer 140 in direct contact with one another, where heat and pressure may be applied to bond the first subassembly 102 and the second subassembly 104 together. Referring to FIGS. 1-2, the first bonding surface 120a and a second bonding surface 140a may be placed in contact with one another, and diffuse together to form the bonded interface 150. In one embodiment, the first bonding surface 120a and the second bonding surface 140a may be polished prior to bringing the first bonding layer 120 and the second bonding layer 140 into contact. In one embodiment, the polishing may be performed by Chemical Mechanical Polishing (CMP), with bonding performed using conventional wafer bonding equipment.

[0035] Once the first bonding surface 120a and the second bonding surface 140b have been placed into contact with one another, the first subassembly 102 and the second subassembly 104 may be heated to a bonding temperature of between about 300°C to about 500°C. The semiconductor device 200 may be heated at a pressure of between about 138 kPa (20 psi) and about 345 kPa (50 psi). The semiconductor device 200 may be heated under pressure for about 20 to 300 minutes. Direct semiconductor bonding with (Al)GaInP(As)(Sb) bonding layers has achieved bond strength greater than 4.1 J/m2, electrical resistance as low as 0.3 Ohm-cm2 and optical transparency of greater than 97% across a bonded interface (e.g., the bonded interface 150 as shown in FIG. 2). After direct bonding, the first wafer 110 may be removed.

[0036] FIG. 3 illustrates an exemplary process flow diagram of a method 300 for creating the semiconductor device 200 as shown in FIG. 2. Referring generally to FIGS. 1-3, method 300 may begin at block 302, where the first bonding layer 120 may be epitaxially grown upon the first surface 110a of the first wafer 110 of the first subassembly 102. As discussed above, the first bonding layer 120 may be lattice-matched to the first wafer 110. Method 300 may then proceed to block 304.

[0037] In block 304, the second bonding layer 140 may be epitaxially grown upon the second surface 130a of the second wafer 130 of the second subassembly 104. The second bonding layer 140 of the second subassembly 104 is lattice-mismatched to the first bonding layer 120 of the first subassembly 102. Method 300 may then proceed to block 306.

[0038] In block 306, the first subassembly 102 and the second subassembly 104 are directly bonded to one another at the first bonding surface 120a and the second bonding surface 140a, thus creating the semiconductor device 200 (shown in FIG. 2). Specifically, the first bonding surface 120a and the second bonding surface 140a (FIG. 1) may be placed in contact with one another, and heated to the bonding temperature. The first bonding layer 120 and the second bonding layers 140 diffuse together to form the bonded interface 150 (seen in FIG. 2). Method 300 may then terminate.

[0039] FIG. 4 illustrates an alternative embodiment of preassembled structure 400 according to an embodiment of the disclosure. The preassembled structure 400 includes a first subassembly 402 and a second subassembly 404. The first subassembly 402 may include a first wafer 410, semiconductor layers 412, and a first bonding layer 420. The semiconductor layers 412 may be directly adjacent and upon a first surface 410a of the first wafer 410. In one embodiment, the semiconductor layers 412 may be a photovoltaic device, or a solar cell having one or more subcells. The first bonding layer 420 may be directly adjacent and upon a semiconductor surface 412a of the semiconductor layers 412. Similar to the embodiment as described above and shown in FIGS. 1-3, the first wafer 410 is a semiconductor selected from group III-V materials. In an embodiment, the first wafer 410 may be selected from the group consisting of Gallium Arsenide (GaAs), Indium Phosphide (InP), Gallium Phosphide (GaP), Gallium Antimonide (GaSb), Gallium Indium Arsenide (GaInAs), Gallium Indium Phosphide (GaInP), Gallium Indium Nitride Ga(In)N materials.

[0040] The semiconductor layers 412 may be epitaxially grown upon the first surface 410a of the first wafer 410. The semiconductor layers 412 may be lattice-matched to the first wafer 410. The first bonding layer 420 may be epitaxially grown upon the semiconductor surface 412a of the semiconductor layers 412. Similar to the embodiment as shown in FIGS. 1-3 and described above, the first bonding layer 420 is an (Al)(Ga)InP(As)(Sb) material, and in one embodiment may have a relatively high dopant concentration equal to or greater than about 5 x 1018/cm3. The first bonding layer 420 may also be lattice-matched to the first wafer 410, and may include a first bonding surface 420a.

[0041] The second subassembly 404 may include a second wafer 430, a buffer layer 432, semiconductor layers 436, and a second bonding layer 440. In the embodiment as shown in FIG. 4, the buffer layer 432 may be directly adjacent and upon a second surface 430a of the second wafer 430. The semiconductor layers 436 may be directly adjacent and upon a buffer surface 432a of the buffer layer 432. The second bonding layer 440 may be directly adjacent and upon a semiconductor surface 436a of the semiconductor layers 436.

[0042] Similar to the embodiment as described above and shown in FIGS. 1-3, the second wafer 430 is a Ge substrate, and may be used as a growth substrate as well as for structural support. Specifically, the second wafer 430 may be used as a substrate for epitaxial growth of the buffer layer 432 as well the main mechanical support for an assembled semiconductor device 500 (shown in FIG. 5). The buffer layer 432 may be epitaxially grown upon the second surface 430a of the second wafer 430. In one embodiment, the second wafer 430 may include an active Ge subcell 434. However, it is to be understood that in some embodiments, the Ge subcell 434 may be omitted.

[0043] In the embodiment as shown in FIG. 4, the buffer layer 432 may be epitaxially grown upon the second surface 430a of the second wafer 430. The buffer layer 432 may be a metamorphic transparent graded buffer. In the embodiments as described, the term transparent may be defined as a transmission of equal to or greater than about ninety-seven percent of the light or electromagnetic radiation of a wavelength for activating a cell or subcell disposed underneath. The buffer layer 432 may be used to epitaxially grow material that is lattice-mismatched to the second wafer 430. For example, in the embodiment as shown in FIG. 4 the buffer layer 432 may be used to grow the semiconductor layers 436. The semiconductor layers 436 may be lattice-mismatched to the second wafer 430. The buffer layer 432 may absorb the strain of lattice-mismatch, and generally prevents the vertical propagation of dislocations.

[0044] The second bonding layer 440 may be epitaxially grown upon the semiconductor surface 436a of the semiconductor layers 436. The second bonding layer 440 may include a second bonding surface 440a. Similar to the first bonding layer 420, the second bonding layer 440 is an (Al)(Ga)InP(As)(Sb) material, and may have a relatively high dopant concentration equal to or greater than about 5 x 1018/cm3. In the embodiment as shown in FIG. 4, the semiconductor layers 436 of the second subassembly 404 may be lattice-mismatched to the second wafer 430 and the second bonding layer 440 of the second subassembly 404 is lattice-mismatched to the second wafer 430. The second bonding layer 440 may be lattice-matched to the semiconductor layers 436. Moreover, the first bonding layer 420 of the first subassembly 402 is lattice-mismatched to the second bonding layer 440 of the second subassembly 404.

[0045] FIG. 5 is an illustration of the semiconductor device 500 according to an embodiment of the disclosure, where the first bonding layer 420 and the second bonding layer 440 have been directly bonded together to join the first subassembly 402 to the second subassembly 404. Similar to the embodiment as shown in FIG. 2, the first subassembly 402 and the second subassembly 404 may be directly bonded to one another by placing the first bonding layer 420 and the second bonding layer 440 in direct contact with one another, where heat and pressure may be applied to bond the first subassembly 402 and the second subassembly 404 together. Referring to FIGS. 4-5, the first bonding surface 420a and the second bonding surface 440a may be placed in contact with one another, and diffuse together to form the bonded interface 450.

[0046] FIG. 6 illustrates an exemplary process flow diagram of a method 600 for creating the semiconductor device 500 as shown in FIG. 5. Referring generally to FIGS. 4-6, the method 600 may begin at block 602, where the semiconductor layers 412 and the first bonding layer 420 may be epitaxially grown upon the first wafer 410 of the first subassembly 402. Specifically, the semiconductor layers 412 may be grown upon the first surface 410a of the first wafer 410, and the first bonding layer 420 may be epitaxially grown upon the semiconductor surface 412a of the semiconductor layers 412. Method 600 may then proceed to block 604.

[0047] In block 604, the buffer layer 432 may be epitaxially grown upon the second surface 430a of the second wafer 430 of the second subassembly 404. Method 600 may then proceed to block 606.

[0048] In block 606, the semiconductor layers 436 may be epitaxially grown upon the buffer surface 432a of the buffer layer 432 of the second subassembly 404. As described above, the semiconductor layers 436 may be lattice-mismatched to the second wafer 430. Method 600 may then proceed to block 608.

[0049] In block 608, the second bonding layer 440 may be epitaxially grown upon the semiconductor surface 436a of the semiconductor layers 436 of the second subassembly 404. As discussed above, the second bonding layer 440 is lattice-mismatched to the second wafer 430. The second bonding layer 440 is also lattice-mismatched to the first bonding layer 420 of the first subassembly 402. Method 600 may then proceed to block 610.

[0050] In block 610, the first subassembly 402 and the second subassembly 404 are directly bonded to one another at the first bonding surface 420a and the second bonding surface 440a, thus creating the semiconductor device 500 (shown in FIG. 5). Specifically, the first bonding surface 420a and the second bonding surface 440a (FIG. 4) may be placed in contact with one another, and heated to the bonding temperature. The first bonding layer 420 and the second bonding layer 440 diffuse together to form the bonded interface 450 (seen in FIG. 5). Method 600 may then terminate.

[0051] FIG. 7 illustrates an alternative embodiment of preassembled structure 700 according to an embodiment of the disclosure. The preassembled structure 700 includes a first subassembly 702 and a second subassembly 704. The first subassembly 702 may include a first wafer 710, first semiconductor layers 712, a buffer layer 714, second semiconductor layers 716, and a first bonding layer 720. The first semiconductor layers 712 may be directly adjacent and upon a first surface 710a of the first wafer 710. In one embodiment, the first semiconductor layers 712 may be a photovoltaic device, or a solar cell having one or more subcells. The buffer layer 714 may be epitaxially grown upon a first semiconductor surface 712a of the first semiconductor layers 712. Similar to the buffer layer 432 of the second subassembly 404 shown in FIGS. 4-5, the buffer layer 714 may also be a metamorphic transparent graded buffer. The second semiconductor layers 716 may be directly adjacent and upon a buffer surface 714a of the buffer layer 714. The second semiconductor layers 716 may also be a photovoltaic device, or a solar cell having one or more subcells. The first bonding layer 720 may be directly adjacent and upon a second semiconductor surface 716a of the second semiconductor layers 716.

[0052] Similar to the embodiments as described above and shown in FIGS. 1-6, the first wafer 710 is a semiconductor selected from group III-V materials. In an embodiment, the first wafer 710 may be selected from the group consisting of Gallium Arsenide (GaAs), Indium Phosphide (InP), Gallium Phosphide (GaP), Gallium Antimonide (GaSb), , Gallium Indium Arsenide (GaInAs), Gallium Indium Phosphide (GaInP), Gallium Indium Nitride Ga(In)N materials. The first semiconductor layers 712 may be epitaxially grown upon the first surface 710a of the first wafer 710, and may be lattice-matched to the first wafer 710.

[0053] The buffer layer 714 may be epitaxially grown upon the first semiconductor surface 712a of the first semiconductor layer 712. The buffer layer 714 may be used to epitaxially grow material that is lattice-mismatched to the first wafer 710. For example, in the embodiment as shown in FIG. 7 the buffer layer 714 may be used to grow the second semiconductor layers 716, which may be lattice-mismatched to the first wafer 710.

[0054] The first bonding layer 720 may be epitaxially grown upon the second semiconductor surface 716a of the second semiconductor layers 716. Similar to the embodiment as shown in FIGS. 1-6 and described above, the first bonding layer 720 is (Al)(Ga)InP(As)(Sb) material, and in one embodiment may have a relatively high dopant concentration equal to or greater than about 5 x 1018/cm3. In the embodiment as shown in FIG. 7, the first bonding layer 720 may be lattice-mismatched to the first wafer 710 and lattice-matched to the second semiconductor layers 716, and may include a first bonding surface 720a.

[0055] The second subassembly 704 may include a second wafer 730, a buffer layer 732, semiconductor layers 736, and a second bonding layer 740. In the embodiment as shown in FIG. 7, the buffer layer 732 may be directly adjacent and upon a second surface 730a of the second wafer 730. The semiconductor layers 736 may be directly adjacent and upon a buffer surface 732a of the buffer layer 732. The second bonding layer 740 may be directly adjacent and upon a semiconductor surface 736a of the semiconductor layers 736.

[0056] Similar to the embodiment as described above and shown in FIGS. 1-6, the second wafer 730 is a Ge substrate, and may be used as a growth substrate as well as for structural support. Specifically, the second wafer 730 may be used as a substrate for epitaxial growth of the buffer layer 732, as well as the main mechanical support for an assembled semiconductor device 800 (shown in FIG. 8). The buffer layer 732 may be epitaxially grown upon the second surface 730a of the second wafer 730. In one embodiment, the second wafer 730 may include an active Ge subcell 734. However, it is to be understood that in some embodiments, the Ge subcell 734 may be omitted.

[0057] The buffer layer 732 may be epitaxially grown upon the second surface 730a of the second wafer 730. The buffer layer 732 may be a metamorphic transparent graded buffer. The buffer layer 732 may be used to epitaxially grow material that is lattice-mismatched to the second wafer 730. For example, in the embodiment as shown in FIG. 7, the buffer layer 732 may be used to grow the semiconductor layers 736, which may be lattice-mismatched to the second wafer 730. Specifically, the semiconductor layers 736 may be epitaxially grown upon the buffer surface 732a of the buffer layer 732.

[0058] The second bonding layer 740 may be epitaxially grown upon the semiconductor surface 736a of the semiconductor layers 736. The second bonding layer 740 may include a second bonding surface 740a. Similar to the first bonding layer 720 of the first subassembly 702, the second bonding layer 440 is (Al)(Ga)InP(As)(Sb) material, and may have a relatively high dopant concentration equal to or greater than about 5 x 1018/cm3. In the embodiment as shown in FIG. 7, the semiconductor layers 736 of the second subassembly 704 may be lattice-mismatched to the second wafer 730 and the second bonding layer 740 of the second subassembly 704 is lattice-mismatched to the second wafer 730. The semiconductor layers 736 and the second bonding layer 740 may be lattice-matched to each other. Moreover, the first bonding layer 720 of the first subassembly 702 is lattice-mismatched to the second bonding layer 740 of the second subassembly 704.

[0059] FIG. 8 is an illustration of the semiconductor device 800 according to an embodiment of the disclosure, where the first bonding layer 720 and the second bonding layer 740 have been directly bonded together to join the first subassembly 702 to the second subassembly 704. Similar to the embodiment as shown in FIGS. 2 and 5, the first subassembly 702 and the second subassembly 704 may be directly bonded to one another by placing the first bonding layer 720 and the second bonding layer 740 in direct contact with one another, where heat and pressure may be applied to bond the first subassembly 702 and the second subassembly 704 together. Referring to FIGS. 7-8, the first bonding surface 720a and the second bonding surface 740a may be placed in contact with one another, and diffuse together to form a bonded interface 750.

[0060] FIG. 9 illustrates an exemplary process flow diagram of a method 900 for creating the semiconductor device 800 as shown in FIG. 8. Referring generally to FIGS. 7-9, the method 900 may begin at block 902, where the first semiconductor layers 712 may be epitaxially grown upon the first wafer 710 of the first subassembly 702. As described above, the first semiconductor layers 712 may be lattice-matched to the first wafer 710. Method 900 may then proceed to block 904.

[0061] In block 904, the buffer layer 714 may be epitaxially grown upon the first semiconductor surface 712a of the first semiconductor layers 712 of the first subassembly 702. Method 900 may then proceed to block 906.

[0062] In block 906, the second semiconductor layers 716 may be epitaxially grown upon the buffer surface 714a of the buffer layer 714 of the first subassembly 702. As described above, the second semiconductor layers 716 may be lattice-mismatched to the first wafer 710. Method 900 may then proceed to block 908.

[0063] In block 908, the first bonding layer 720 may be epitaxially grown upon the second semiconductor surface 716a of the second semiconductor layers 716 of the first subassembly 702. As described above, the first bonding layer 720 may be lattice-mismatched to the first wafer 710, but may be lattice-matched to the second semiconductor layers 716. Method 900 may then proceed to block 910.

[0064] In block 910, the buffer layer 732 may be epitaxially grown upon the second surface 730a of the second wafer 730 of the second subassembly 704. Method 900 may then proceed to block 912.

[0065] In block 912, the semiconductor layers 736 may be epitaxially grown upon the buffer surface 732a of the buffer layer 732 of the second subassembly 704. As described above, the semiconductor layers 736 may be lattice-mismatched to the second wafer 730. Method 900 may then proceed to block 914.

[0066] In block 914, the second bonding layer 740 may be epitaxially grown upon the semiconductor surface 736a of the semiconductor layers 736 of the second subassembly 704. As discussed above, the second bonding layer 740 is lattice-mismatched to the second wafer 730, as well as the first bonding layer 720 of the first subassembly 702. The second bonding layer 740 may also be lattice-matched to the semiconductor layers 736. Method 900 may then proceed to block 916.

[0067] In block 916, the first subassembly 702 and the second subassembly 704 are directly bonded to one another at the first bonding surface 720a and the second bonding surface 740a, thus creating the semiconductor device 800 (shown in FIG. 8). Specifically, the first bonding surface 720a and the second bonding surface 740a (FIG. 7) may be placed in contact with one another, and heated to the bonding temperature. The first bonding layer 720 and the second bonding layer 740 diffuse together to form the directly bonded interface 750 (seen in FIG. 8). Method 900 may then terminate.

[0068] Referring generally to FIGS. 1-9, the disclosed semiconductor devices as described above may include a wider range of bandgap combinations between the various device components when compared to some other types of semiconductor devices currently available that only include directly bonded lattice-matched device components. This is because all the disclosed semiconductor devices as described above each include directly bonded lattice-mismatched device components. Lattice-mismatching various device components may widen the possible range of bandgap combinations and may also enhance material quality of the semiconductor device. It should be noted that direct bonding of metamorphic components is typically not practiced in industry at this time.

[0069] Additionally, the disclosed semiconductor devices each include the Ge substrate, and may include the active Ge subcell. The Ge subcell may be used to replace an epitaxially-grown GaInAs subcell including an energy bandgap of about 0.7 eV, which is typically found in a semiconductor device that is grown using inverted metamorphic (IMM) technologies. The Ge subcell may have equal or better performance retention after radiation when compared to the GaInAs subcell found in semiconductor devices grown using IMM technologies. Replacing the GaInAs subcell with the active Ge subcell may substantially reduce the overall cost of the semiconductor device. Moreover, semiconductor devices grown using IMM technologies may also require an additional device handle as well. In contrast, the disclosed Ge substrate may be used as the main mechanical support for the semiconductor device. Thus, no additional device handle may be needed. The disclosed Ge substrate may provide other benefits during semiconductor fabrication as well such as, for example, spalling compatibility, etching chemical selectivity, and simplicity in back-side metal contacts having substrate polarity. The Ge substrate may be relatively thin (e.g., having a thickness of about fifty microns), which may also reduce the overall mass of the disclosed semiconductor devices. Also, the Ge substrate may provide an enhanced power density.

[0070] For example, in one embodiment the disclosed semiconductor device may be a directly bonded five-junction solar cell grown on a Ge substrate including an active Ge subcell. Specifically, the solar cell may be comprised of a first subassembly including lattice-matched device components with relatively high energy bandgaps (e.g., ranging from about 1.3 eV to about 2.0 eV). The first subassembly is directly bonded to a second subassembly. The second subassembly includes the Ge substrate, a single buffer layer, and a device component grown upon the buffer layer and lattice-mismatched to the Ge substrate. The active Ge subcell of the Ge substrate and the device component of the second subassembly may include relatively low energy bandgaps (e.g., 0.67 eV for the Ge subcell and 1.0-1.1 eV for the device component). Some types of solar cells currently available that are grown using IMM technologies may include multiple buffer layers to absorb the strain of lattice-mismatch between various device components. In contrast, the exemplary solar cell as described only includes one buffer layer, which may reduce the overall cost.


Claims

1. A semiconductor device (200), comprising:

a first subassembly (102) comprising a first bonding layer (120) of (Al)(Ga)InP(As)(Sb) and a first substrate (110), wherein the first substrate (110) is constructed of a group III-V material and

a second subassembly (104), comprising:

a second substrate (130) constructed of germanium; and

a second bonding layer (140) of (Al)(Ga)InP(As)(Sb) is directly bonded to the first bonding layer (120), wherein the first bonding layer (120) and the second bonding layer (140) are lattice-mismatched to one another, and wherein:
the second bonding layer (140) is lattice-mismatched to the second substrate (130).


 
2. The semiconductor device of claim 1, wherein a buffer layer (432,732) is epitaxially grown on the second substrate (430,730).
 
3. The semiconductor device of claim 1 or claim 2,
wherein the second substrate (130) includes an active Ge subcell (134).
 
4. The semiconductor device of any preceding claim, wherein the second subassembly (404, 704) includes semiconductor layers (436, 736) lattice-mismatched to the second substrate.
 
5. The semiconductor device of any preceding claim, wherein the first subassembly (402, 702) includes first semiconductor layers (412, 712) lattice-matched to the first substrate (410, 710).
 
6. The semiconductor device of claim 5, wherein the first subassembly (702) includes a buffer layer (714) epitaxially grown on the first semiconductor layers (712).
 
7. The semiconductor device of claim 6, wherein the first subassembly (702) includes second semiconductor layers (716) lattice-mismatched to the first substrate (710).
 
8. The semiconductor device of claim 7, wherein the second semiconductor layers (716) are epitaxially grown on the buffer layer.
 
9. The semiconductor device of any preceding claim, wherein at least one of the first subassembly (102) and the second subassembly (104) includes one of a photovoltaic device and a solar cell.
 
10. A method (300) of making a semiconductor device (200), comprising;

providing a first subassembly (102) comprising a first bonding layer (120) of (Al)(Ga)InP(As)(Sb) and a first substrate (110) wherein the first substrate (110) is constructed of a group III-V material;

providing a second subassembly (104) comprising a second substrate (130) constructed of germanium and a second bonding layer (140) of (Al)(Ga)InP(As)(Sb);

directly bonding the first bonding layer (120) and the second bonding layer (140) together, wherein the first bonding layer (120) and the second bonding layer (140) are lattice-mismatched to one another; and

lattice-mismatching the second bonding layer (140) to the second substrate (130).


 
11. The method of claim 10, comprising epitaxially growing a buffer layer (432,732) on the second substrate (430,730)
 
12. The method of claim 10 or claim 11, comprising creating an active Ge subcell (134) within the second substrate (130) by a diffusion of dopants into a layer of the second substrate (130).
 
13. The method of any one of claims 10 to 12, comprising epitaxially growing first semiconductor layers (712) upon the first substrate (710) of the first subassembly (702), wherein the first semiconductor layers (712) are lattice-matched to the first substrate (710).
 
14. The method of any one of claims 10 to 13, comprising epitaxially growing a buffer layer (714) upon the first semiconductor layers (712).
 
15. The method of claim 11, comprising epitaxially growing second semiconductor layers (716) on the buffer layer (714), wherein the second semiconductor layers (716) are lattice-mismatched to the first substrate (710), and wherein the first bonding layer (720) is lattice-mismatched to the first substrate (710).
 


Ansprüche

1. Halbleitervorrichtung (200), die aufweist:

eine erste Unteranordnung (102), die eine erste Bondingschicht (120) aus (Al)(Ga)InP(As)(Sb) und ein erstes Substrat (110) aufweist, wobei das erste Substrat (110) aus einem Material der Gruppe III-V aufgebaut ist, und

eine zweite Unteranordnung (130), die aufweist:

ein zweites Substrat (130), das aus Germanium aufgebaut ist; und

eine zweite Bondingschicht (140) aus (Al)(Ga)InP(As) (Sb), die direkt an die erste Bondingschicht (120) gebondet ist, wobei die erste Bondingschicht (120) und die zweite Bondingschicht (140) eine Gitterfehlanpassung zueinander haben, und wobei:
die zweite Bondingschicht mit dem zweiten Substrat (130) eine Gitterfehlanpassung hat.


 
2. Halbleitervorrichtung nach Anspruch 1, wobei eine Pufferschicht (432, 732) auf dem zweiten Substrat (430, 730) epitaxial aufwächst.
 
3. Halbleitervorrichtung nach Anspruch 1 oder Anspruch 2, wobei das zweite Substrat (130) eine aktive Ge-Subzelle (134) aufweist.
 
4. Halbleitervorrichtung nach einem der vorhergehenden Ansprüche, wobei die zweite Unteranordnung (404, 704) Halbleiterschichten (436, 736) aufweist, die mit dem zweiten Substrat eine Gitterfehlanpassung haben.
 
5. Halbleitervorrichtung nach einem der vorhergehenden Ansprüche, wobei die erste Unteranordnung (402, 702) erste Halbleiterschichten (412, 712) aufweist, die mit dem ersten Substrat (410, 710) eine Gitterfehlanpassung haben.
 
6. Halbleitervorrichtung nach Anspruch 5, wobei die erste Unteranordnung (702) eine Pufferschicht (714) aufweist, die auf den ersten Halbleiterschichten (712) epitaxial aufwächst.
 
7. Halbleitervorrichtung nach Anspruch 6, wobei die erste Unteranordnung (702) zweite Halbleiterschichten (716) aufweist, die mit dem ersten Substrat (710) eine Gitterfehlanpassung haben.
 
8. Halbleitervorrichtung nach Anspruch 7, wobei die zweiten Halbleiterschichten (716) auf der Pufferschicht epitaxial aufwachsen.
 
9. Halbleitervorrichtung nach einem der vorhergehenden Ansprüche, wobei wenigstens eine der ersten Unteranordnung (102) und der zweiten Unteranordnung (104) eines von einer Photovoltaikvorrichtung und einer Solarzelle aufweist.
 
10. Verfahren (300) zum Herstellen einer Halbleitervorrichtung (200), das aufweist:

Bereitstellen einer ersten Unteranordnung (102), die eine erste Bondingschicht (120) aus (Al)(Ga)InP(As)(Sb) und ein erstes Substrat (110) aufweist, wobei das erste Substrat (110) aus einem Material der Gruppe III-V aufgebaut ist, und

Bereitstellen einer zweiten Unteranordnung (104), die ein zweites Substrat (130) aufweist, das aus Germanium aufgebaut ist und eine zweite Bondingschicht (140) aus (Al) (Ga)InP(As) (Sb) ;

direktes Bonden der ersten Bondingschicht (120) und der zweiten Bondingschicht (140) aneinander, wobei die erste Bondingschicht (120) und die zweite Bondingschicht (140) eine Gitterfehlanpassung zueinander haben; und

Vorsehen einer Gitterfehlanpassung der zweiten Bondingschicht (140) mit dem zweiten Substrat (130).


 
11. Verfahren nach Anspruch 10, das das epitaxiale Aufwachsen einer Pufferschicht (432, 732) auf dem zweiten Substrat (430, 730) aufweist.
 
12. Verfahren nach Anspruch 10 oder Anspruch 11, das das Erzeugen einer aktiven Ge-Subzelle (134) in dem zweiten Substrat (130) durch eine Diffusion von Dotanden in eine Schicht des zweiten Substrats (130) aufweist.
 
13. Verfahren nach einem der Ansprüche 10 bis 12, das das epitaxiale Aufwachsen erster Halbleiterschichten (712) auf dem ersten Substrat (710) der ersten Unteranordnung (702) aufweist, wobei die ersten Halbleiterschichten (712) eine Gitterfehlanpassung mit dem ersten Substrat (710) haben.
 
14. Verfahren nach einem der Ansprüche 10 bis 13, das das epitaxiale Aufwachsen einer Pufferschicht (714) auf den ersten Halbleiterschichten (712) aufweist.
 
15. Verfahren nach Anspruch 11, das das epitaxiale Aufwachsen zweiter Halbleiterschichten (716) auf der Pufferschicht (714) aufweist, wobei die zweiten Halbleiterschichten (716) eine Gitterfehlanpassung mit dem ersten Substrat (710) haben, und wobei die erste Bondingschicht (720) eine Gitterfehlanpassung mit dem ersten Substrat (710) hat.
 


Revendications

1. Dispositif semi-conducteur (200) comprenant :

un premier sous-ensemble (102) comprenant une première couche de liaison (120) de (Al)(Ga)InP(As)(Sb) et un premier substrat (110), premier sous-ensemble dans lequel le premier substrat (110) est constitué d'un matériau du groupe III-V et

un second sous-ensemble (104) comprenant :

un second substrat (130) constitué de germanium ; et

une seconde couche de liaison (140) de (Al)(Ga)InP(As)(Sb) est directement liée à la première couche de liaison (120), dispositif semi-conducteur dans lequel la première couche de liaison (120) et la seconde couche de liaison (140) sont désadaptées au réseau l'une par rapport à l'autre, et dans lequel :
la seconde couche de liaison (140) est désadaptée au réseau par rapport au second substrat (130).


 
2. Dispositif semi-conducteur selon la revendication 1, dans lequel une couche tampon (432, 732) est épitaxiée sur le second substrat (430, 730).
 
3. Dispositif semi-conducteur selon la revendication 1 ou la revendication 2, dans lequel le second substrat (130) comprend une sous-cellule de Ge active (134).
 
4. Dispositif semi-conducteur selon l'une quelconque des revendications précédentes, dans lequel le second sous-ensemble (404, 704) comprend des couches semi-conductrices (436, 736) désadaptées au réseau par rapport au second substrat.
 
5. Dispositif semi-conducteur selon l'une quelconque des revendications précédentes, dans lequel le premier sous-ensemble (402, 702) comprend des premières couches semi-conductrices (412, 712) adaptées au réseau par rapport au premier substrat (410, 710).
 
6. Dispositif semi-conducteur selon la revendication 5, dans lequel le premier sous-ensemble (702) comprend une couche tampon (714) épitaxiée sur les premières couches semi-conductrices (712).
 
7. Dispositif semi-conducteur selon la revendication 6, dans lequel le premier sous-ensemble (702) comprend des deuxièmes couches semi-conductrices (716) désadaptées au réseau par rapport au premier substrat (710) .
 
8. Dispositif semi-conducteur selon la revendication 7, dans lequel les deuxièmes couches semi-conductrices (716) sont épitaxiées sur la couche tampon.
 
9. Dispositif semi-conducteur selon l'une quelconque des revendications précédentes, dans lequel au moins un du premier sous-ensemble (102) et du second sous-ensemble (104) comprend l'un (l'une) d'un dispositif photovoltaïque et d'une cellule solaire.
 
10. Procédé (300) de fabrication d'un dispositif semi-conducteur (200), ledit procédé comprenant :

le fait de fournir un premier sous-ensemble (102) comprenant une première couche de liaison (120) de (Al)(Ga)InP(As)(Sb) et un premier substrat (110), premier sous-ensemble dans lequel le premier substrat (110) est constitué d'un matériau du groupe III-V ;

le fait de fournir un second sous-ensemble (104) comprenant un second substrat (130) constitué de germanium, et une seconde couche de liaison (140) de (Al)(Ga)InP(As)(Sb) ;

le fait de lier ensemble, directement, la première couche de liaison (120) et la seconde couche de liaison (140), procédé dans lequel la première couche de liaison (120) et la seconde couche de liaison (140) sont désadaptées au réseau l'une par rapport à l'autre ; et

le fait de désadapter au réseau la seconde couche de liaison (140) par rapport au second substrat (130).


 
11. Procédé selon la revendication 10, comprenant la croissance épitaxiale d'une couche tampon (432, 732) sur le second substrat (430, 730).
 
12. Procédé selon la revendication 10 ou la revendication 11, comprenant la création d'une sous-cellule de Ge active (134) dans le second substrat (130), par une diffusion de dopants dans une couche du second substrat (130).
 
13. Procédé selon l'une quelconque des revendications 10 à 12, comprenant la croissance épitaxiale de premières couches semi-conductrices (712) sur le premier substrat (710) du premier sous-ensemble (702), procédé dans lequel les premières couches semi-conductrices (712) sont adaptées au réseau par rapport au premier substrat (710).
 
14. Procédé selon l'une quelconque des revendications 10 à 13, comprenant la croissance épitaxiale d'une couche tampon (714) sur les premières couches semi-conductrices (712).
 
15. Procédé selon la revendication 11, comprenant la croissance épitaxiale de deuxièmes couches semi-conductrices (716) sur la couche tampon (714), procédé dans lequel les deuxièmes couches semi-conductrices (716) sont désadaptées au réseau par rapport au premier substrat (710), et procédé dans lequel la première couche de liaison (720) est désadaptée au réseau par rapport au premier substrat (710) .
 




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Cited references

REFERENCES CITED IN THE DESCRIPTION



This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description