(19)
(11)EP 2 905 904 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
05.12.2018 Bulletin 2018/49

(21)Application number: 13843816.3

(22)Date of filing:  02.10.2013
(51)International Patent Classification (IPC): 
H03M 13/11(2006.01)
H03M 13/03(2006.01)
(86)International application number:
PCT/JP2013/005886
(87)International publication number:
WO 2014/054283 (10.04.2014 Gazette  2014/15)

(54)

CODING METHOD, DECODING METHOD, CODER, AND DECODER

CODIERUNGSVERFAHREN, DECODIERUNGSVERFAHREN, CODIERER UND DECODIERER

PROCÉDÉ DE CODAGE, PROCÉDÉ DE DÉCODAGE, CODEUR ET DÉCODEUR


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 05.10.2012 JP 2012223569
05.10.2012 JP 2012223570
05.10.2012 JP 2012223571
05.10.2012 JP 2012223572
05.10.2012 JP 2012223573

(43)Date of publication of application:
12.08.2015 Bulletin 2015/33

(73)Proprietor: Sun Patent Trust
New York, NY 10017 (US)

(72)Inventor:
  • MURAKAMI, Yutaka
    Osaka-shi, Osaka 540-6207 (JP)

(74)Representative: Grünecker Patent- und Rechtsanwälte PartG mbB 
Leopoldstraße 4
80802 München
80802 München (DE)


(56)References cited: : 
WO-A1-2011/058760
JP-B2- 4 928 613
JP-A- 2009 246 926
US-A1- 2011 283 162
  
  • CHEN Z ET AL: "CONSTRUCTION OF LOW-DENSITY PARITY-CHECK CONVOLUTIONAL CODES THROUGH PROGRESSIVE EDGE-GROWTH", IEEE COMMUNICATIONS LETTERS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 9, no. 12, 1 December 2005 (2005-12-01), pages 1058-1060, XP001237858, ISSN: 1089-7798, DOI: 10.1109/LCOMM.2005.1576587
  • YIXIANG WANG ET AL: "Quasi-cyclic low-density parity-check convolutional code", PROC., IEEE 7TH INTERNATIONAL CONFERENCE ON WIRELESS AND MOBILE COMPUTING, NETWORKING AND COMMUNICATIONS, WIMOB 2011, 10 October 2011 (2011-10-10), pages 351-356, XP032000196, DOI: 10.1109/WIMOB.2011.6085376 ISBN: 978-1-4577-2013-0
  • PUSANE A E ET AL: "Deriving Good LDPC Convolutional Codes from LDPC Block Codes", IEEE TRANSACTIONS ON INFORMATION THEORY, IEEE PRESS, USA, vol. 57, no. 2, 1 February 2011 (2011-02-01), pages 835-857, XP011348929, ISSN: 0018-9448, DOI: 10.1109/TIT.2010.2095211
  • MARCOS B S TAVARES ET AL: "Tail-Biting LDPC Convolutional Codes", INFORMATION THEORY, 2007. ISIT 2007. IEEE INTERNATIONAL SYMPOSIUM ON, IEEE, PISCATAWAY, NJ, USA, 24 June 2007 (2007-06-24), pages 2341-2345, XP031441061, ISBN: 978-1-4244-1397-3
  • YUTAKA MURAKAMI ET AL.: 'A Design Scheme for LDPC Convolutional Codes Based on Parity Check Polynomials with a Time Period of 2' IEICE TECHNICAL REPORT vol. 109, no. 440, 24 February 2010, pages 309 - 314, XP008168466
  • TAKAAKI KISHIGAMI ET AL.: 'Rate Compatible LDPC-Convolutional Codes for the Change Request to 802.16m SDD' IEEE C802.16M-09/0412 27 February 2009, XP017797498
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

[Technical Field]



[0001] The present invention relates to an encoding method, a decoding method, an encoder, and a decoder using low-density parity check convolutional codes (LDPC-CCs) having coding rates no smaller than 1/2 and not satisfying (n-1)/n (where n is an integer no smaller than two), and LDPC-CCs using improved tail-biting schemes (LDPC block codes using LDPC-CC).

[Background Art]



[0002] In recent years, attention has been attracted to a low-density parity-check (LDPC) code as an error correction code that provides high error correction capability with a feasible circuit scale. Because of its high error correction capability and ease of implementation, an LDPC code has been adopted in an error correction coding scheme for IEEE802.11n high-speed wireless LAN systems, digital broadcasting systems, and so forth.

[0003] An LDPC code is an error correction code defined by low-density parity check matrix H. Furthermore, the LDPC code is a block code having the same block length as the number of columns N of check matrix H (see Non-Patent Literature 1, Non-Patent Literature 2, Non-Patent Literature 3). For example, random LDPC code, QC-LDPC code (QC: Quasi-Cyclic) are proposed.

[0004] Studies are being carried out on LDPC-CC (Low-Density Parity Check Convolutional Codes) capable of performing encoding or decoding on an information sequence of an arbitrary length for LDPC code (hereinafter, LDPC-BC: Low-Density Parity Check Block Code) of a block code (e.g. see Non-Patent Literature 4 and Non-Patent Literature 5).

[0005] LDPC-CC is a convolutional code defined by a low-density parity check matrix. For example, parity check matrix HT[0, n] of LDPC-CC having a coding rate of R=1/2 (=b/c) is shown in FIG. 1. Here, element h1(m)(t) of HT[0, n] takes zero or one. All elements other than h1(m)(t) are zeroes. M represents the LDPC-CC memory length, and n represents the length of an LDPC-CC codeword. As shown in FIG. 1, a characteristic of an LDPC-CC check matrix is that it is a parallelogram-shaped matrix in which ones are placed only in diagonal terms of the matrix and neighboring elements, and the bottom-left and top-right elements of the matrix are zero.

[0006] An LDPC-CC encoder defined by parity check matrix HT[0, n] where h1(0)(t)=1 and h2(0)(t)=1 is represented by FIG. 2. As shown in FIG. 2, an LDPC-CC encoder is formed with 2×(M+1) shift registers having a bit length of c and a mod 2 adder (exclusive OR operator). Thus, a feature of the LDPC-CC encoder is that it can be realized with a very simple circuit compared to a circuit that performs multiplication of a generator matrix or an LDPC-BC encoder that performs calculation based on a backward (forward) substitution method. Also, since the encoder in FIG. 2 is a convolutional code encoder, it is not necessary to divide an information sequence into fixed-length blocks when encoding, and an information sequence of any length can be encoded.

[0007] Patent Literatures 1 and 2 describe an LDPC-CC generating method based on a parity check polynomial. In particular, Patent Literature 1 describes a method of generating an LDPC-CC using parity check polynomials having a time-varying period of two, a time-varying period of three, a time-varying period of four, and a time-varying period of a multiple of three. In particular, Patent Literature 2 describes a relationship between time-varying periods and parity check polynomials.

[Citation List]


[Patent Literature]



[0008] 

[Patent Literature 1]
Japanese Patent Application Publication No. 2009-246926

[Patent Literature 2]
International Application WO 2011/058760


[Non-Patent Literature]



[0009] 

[Non-Patent Literature 1]
R. G. Gallager, "Low-density parity check codes," IRE Trans. Inform. Theory, IT-8, pp. 21-28, 1962.

[Non-Patent Literature 2]
D. J. C. Mackay, "Good error-correcting codes based on very sparse matrices," IEEE Trans. Inform. Theory, vol. 45, no. 2, pp. 399-431, March 1999.

[Non-Patent Literature 3]
M. P. C. Fossorier, "Quasi-cyclic low-density parity-check codes from circulant permutation matrices," IEEE Trans. Inform. Theory, vol. 50, no. 8, pp. 1788-1793, Nov. 2001.

[Non-Patent Literature 4]
A. J. Feltstrom, and K. S. Zigangirov, "Time-varying periodic convolutional codes with low-density parity-check matrix," IEEE Trans. Inform. Theory, vol. 45, no. 6, pp. 2181-2191, Sep. 1999.

[Non-Patent Literature 5]
R. M. Tanner, D. Sridhara, A. Sridharan, T. E. Fuja, and D. J. Costello Jr., "LDPC block and convolutional codes based on circulant matrices," IEEE Trans. Inform. Theory, vol. 50, no. 12, pp. 2966-2984, Dec. 2004.

[Non-Patent Literature 6]
M. P. C. Fossorier, M. Mihaljevic, and H. Imai, "Reduced complexity iterative decoding of low-density parity check codes based on belief propagation," IEEE Trans. Commun., vol. 47, no. 5, pp. 673-680, May 1999.

[Non-Patent Literature 7]
J. Chen, A. Dholakia, E. Eleftheriou, M. P. C. Fossorier, and X.-Yu Hu, "Reduced-complexity decoding of LDPC codes," IEEE Trans. Commun., vol. 53, no. 8, pp. 1288-1299, Aug. 2005.

[Non-Patent Literature 8]
J. Zhang, and M. P. C. Fossorier, "Shuffled iterative decoding," IEEE Trans. Commun., vol. 53, no. 2, pp. 209-213, Feb. 2005.

[Non-Patent Literature 9]
G. Miller, and D. Burshtein, "Bounds on the maximum likelihood decoding error probability of low-density parity check codes," IEEE Trans. Inf. Theory, vol. 47, no. 7, pp. 2696-2710, Nov. 2001.

[Non-Patent Literature 10]
R. G. Gallager, "A simple derivation of the coding theorem and some applications," IEEE Trans. Inf. Theory, vol. IT-11, no. 1, pp. 3-18, Jan. 1965.

[Non-Patent Literature 11]
A. J. Viterbi, "Error bounds for convolutional codes and an asymptotically optimum decoding algorithm," IEEE Trans. Inf. Theory, vol. IT-13, no. 2, pp. 260-269, April 1967.

[Non-Patent Literature 12]
A. J. Viterbi, and J. K. Omura, "Principles of digital communication and coding," McGraw-Hill, New York, 1979.

[Non-Patent Literature 13]
Y. Murakami, S. Okamura, S. Okasaka, T. Kishigami, and M. Orihashi, "LDPC convolutional codes based on parity check polynomials with time period of 3," IEICE Trans. Fundamentals, vol. E-92, no. 10, pp. 2479-2483, Oct. 2009.

[Non-Patent Literature 14]
M. B. S. Tavares, K. S. Zigangirov, and G. P. Fettweis, "Tail-biting LDPC convolutional codes," Proc. of IEEE ISIT 2007, pp. 2341-2345, June 2007.

[Non-Patent Literature 15]
H. H. Ma, and J. K. Wolf, "On tail biting convolutional codes," IEEE Trans. Commun., vol. com-34, no. 2, pp.104-111, Feb. 1986.

[Non-Patent Literature 16]
C. Weiss, C. Bettstetter, and S. Riedel, "Code construction and decoding of parallel concatenated tail-biting codes," IEEE Trans. Inform. Theory, vol. 47, no. 1, pp. 366-386, Jan. 2001.

[Non-Patent Literature 17]
J.Zhang, and M.P.C Fossorier, "A modified weighted bit-flipping decoding of low density parity-check codes," IEEE Communications Letters, vol. 8, no. 3, pp. 165-167, 2004.

[Non-Patent Literature 18]
IEEE Standard for Local and Metropolitan Area Networks, IEEEP802.16e/D12, Oct. 2005.


[Summary of Invention]


[Technical Problem]



[0010] Although Patent Literatures 1 and 2 describe a code generation method for an LDPC-CC of coding rate (n-1)/n (where n is an integer no smaller than two) based on a parity check polynomial, Patent Literatures 1 and 2 lack disclosure of a method of generating an LDPC-CC of a coding rate no smaller than 1/2 and not satisfying (n-1)/n (where n is an integer no smaller than two), and an LDPC-CC based on a parity check polynomial that uses an improved tail-biting scheme (LDPC block codes using LDPC-CC)

[0011] It is therefore an object of the present invention to provide an encoding method, a decoding method, an encoder, and a decoder for an LDPC-CC of a coding rate no smaller than 1/2 and not satisfying (n-1)/n (where n is an integer no smaller than two), and an LDPC-CC based on a parity check polynomial that uses an improved tail-biting scheme (LDPC block codes using LDPC-CC)

[Solution to Problem]



[0012] One aspect of the present invention is an encoding method as specified in claim 1.

[0013] One aspect of the present invention is a decoding method as specified in claim 2.

[Advantageous Effects of Invention]



[0014] The present invention can achieve high error correction capability, and can thereby secure high data quality.

[Brief Description of Drawings]



[0015] 

FIG. 1 shows an LDPC-CC check matrix.

FIG. 2 shows a configuration of an LDPC-CC encoder.

FIG. 3 shows a parity check matrix of a (7, 5) convolutional code.

FIG. 4 shows an example of the configuration of LDPC-CC check matrix having a coding rate of (n-1)/n and a time-varying period of six.

FIG. 5 shows an example of an LDPC-CC tree having a time-varying period of six.

FIG. 6 shows an example of an LDPC-CC tree having a time-varying period of six.

FIG. 7 shows an example of the configuration of LDPC-CC check matrix having a coding rate of (n-1)/n and a time-varying period of seven.

FIG. 8 shows an example of an LDPC-CC tree having a time-varying period of seven.

FIG. 9 shows a circuit example of encoder having a coding rate of 1/2.

FIG. 10 shows a circuit example of encoder having a coding rate of 1/2.

FIG. 11 shows a circuit example of encoder having a coding rate of 1/2.

FIG. 12 shows an example of the configuration of an LDPC-CC encoding section.

FIG. 13 shows a zero-termination method.

FIG. 14 shows an example of check matrix when zero-termination is performed.

FIG. 15 shows a relationship between check nodes corresponding to parity check polynomials #α and #β, and a variable node.

FIG. 16 shows a sub-matrix generated by extracting only parts relating to X1(D) of parity check matrix H.

FIG. 17 shows an example of LDPC-CC tree having a time-varying period of seven.

FIG. 18 shows an example of LDPC-CC tree having a time-varying period of h as a time-varying period of six.

FIG. 19 shows an example of LDPC-CC check matrix.

FIG. 20 shows an example of the configuration of check matrix when tail-biting is performed.

FIG. 21 shows an example of the configuration of check matrix when tail-biting is performed.

FIG. 22 is an overall diagram of a communication system.

FIG. 23 shows an example of the configuration of check matrix when improved tail-biting is performed.

FIG. 24 shows an example of the configuration of check matrix when improved tail-biting is performed.

FIG. 25 is an overall diagram of a communication system.

FIG. 26 shows an example of the configuration of check matrix when improved tail-biting is performed.

FIG. 27 shows an example of the configuration of check matrix when improved tail-biting is performed.

FIG. 28 shows an example of the configuration of check matrix when improved tail-biting is performed.

FIG. 29 shows an example of the configuration of partial matrix of check matrix when improved tail-biting is performed.

FIG. 30 shows an example of the configuration of partial matrix of check matrix when improved tail-biting is performed.

FIG. 31 shows an example of the configuration of check matrix when improved tail-biting is performed.

FIG. 32 shows an example of the configuration of a transmitting device when interleaving is performed on a transmission sequence.

FIG. 33 shows an example of the configuration of check matrix equivalent to check matrix when improved tail-biting is performed.

FIG. 34 shows an example of the configuration of a receiving device when interleaving is performed on a transmission sequence.

FIG. 35 shows an example of the configuration of check matrix corresponding to transmission sequence of jth block of LDPC code of coding rate n-m/n.

FIG. 36 shows an example of the configuration of check matrix obtained by performing row permutation on check matrix corresponding to transmission sequence of jth block of LDPC code of coding rate n-m/n.

FIG. 37 shows an example of the configuration of check matrix for LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 38 shows an example of the configuration of check matrix for LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 39 shows an example of the configuration of check matrix for LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 40 shows an example of the configuration of an encoder for LDPC-CC of coding rate 2/4 that is based on a parity check polynomial.

FIG. 41 is a diagram for explaining a zero-termination method.

FIG. 42 is a diagram for explaining a zero-termination method.

FIG. 43 shows an example of the configuration of check matrix for LDPC-CC of coding rate 2/4 when tail-biting is performed.

FIG. 44 shows an example of the configuration of check matrix for LDPC-CC of coding rate 2/4 when improved tail-biting is performed.

FIG. 45 shows an example of the configuration of check matrix for LDPC-CC of coding rate 2/4 when improved tail-biting is performed.

FIG. 46 is an overall diagram of a communication system.

FIG. 47 shows an example of time-domain frame configuration of a transmission signal transmitted by a transmitting device.

FIG. 48 shows an example of the configuration of sections generating a modulation signal in a transmitting device in a base station (broadcast station, access point, etc.,) when switching between transmission schemes is possible.

FIG. 49 is a diagram for explaining an example differing from that in FIG. 48.

FIG. 50 is a diagram for explaining an example differing from that in FIG. 48.

FIG. 51 shows an example of a configuration differing from FIG. 50.

FIG. 52 shows an example of time and frequency domain frame configurations when a single stream is transmitted.

FIG. 53 shows an example of time and frequency domain frame configurations when two stream are transmitted.

FIG. 54 is a system configuration diagram including a device executing transmission method and reception method.

FIG. 55 illustrates a sample configuration of a reception device executing a reception method.

FIG. 56 illustrates a sample configuration for multiplexed data.

FIG. 57 is a schematic diagram illustrating an example of the manner in which the multiplexed data are multiplexed.

FIG. 58 illustrates an example of storage in a video stream.

FIG. 59 illustrates the format of TS packets ultimately written into the multiplexed data.

FIG. 60 describes the details of PMT data structure.

FIG. 61 illustrates the configuration of file information for the multiplexed data.

FIG. 62 illustrates the configuration of stream attribute information.

FIG. 63 illustrates the configuration of a sample audiovisual output device.

FIG. 64 illustrates a sample broadcasting system using a method of switching between precoding matrices according to a rule.

FIG. 65 illustrates an optical disc device.

FIG. 66 shows an example of the configuration of check matrix for LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 67 shows an example of the configuration of check matrix for LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 68 shows an example of the configuration of check matrix for LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 69 shows an example of the configuration of an encoder for LDPC-CC of coding rate 3/5 that is based on a parity check polynomial.

FIG. 70 is a diagram for explaining a zero-termination method.

FIG. 71 is a diagram for explaining a zero-termination method.

FIG. 72 shows an example of the configuration of check matrix for LDPC-CC of coding rate 3/5 when tail-biting is performed.

FIG. 73 shows an example of the configuration of check matrix for LDPC-CC of coding rate 3/5 when improved tail-biting is performed.

FIG. 74 shows an example of the configuration of check matrix for LDPC-CC of coding rate 3/5 when improved tail-biting is performed.

FIG. 75 shows an example of the configuration of check matrix for LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 76 shows an example of the configuration of check matrix for LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 77 shows an example of the configuration of check matrix for LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 78 shows an example of the configuration of an encoder for LDPC-CC of coding rate 5/7 that is based on a parity check polynomial.

FIG. 79 is a diagram for explaining a zero-termination method.

FIG. 80 is a diagram for explaining a zero-termination method.

FIG. 81 shows an example of the configuration of check matrix for LDPC-CC of coding rate 5/7 when tail-biting is performed.

FIG. 82 shows an example of the configuration of check matrix for LDPC-CC of coding rate 5/7 when improved tail-biting is performed.

FIG. 83 shows an example of the configuration of check matrix for LDPC-CC of coding rate 5/7 when improved tail-biting is performed.

FIG. 84 shows an example of the configuration of check matrix for LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 85 shows an example of the configuration of check matrix for LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 86 shows an example of the configuration of check matrix for LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 87 shows an example of the configuration of an encoder for LDPC-CC of coding rate 7/9 that is based on a parity check polynomial.

FIG. 88 is a diagram for explaining a zero-termination method.

FIG. 89 is a diagram for explaining a zero-termination method.

FIG. 90 shows an example of the configuration of check matrix for LDPC-CC of coding rate 7/9 when tail-biting is performed.

FIG. 91 shows an example of the configuration of check matrix for LDPC-CC of coding rate 7/9 when improved tail-biting is performed.

FIG. 92 shows an example of the configuration of check matrix for LDPC-CC of coding rate 7/9 when improved tail-biting is performed.

FIG. 93 shows an example of the configuration of check matrix for LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 94 shows an example of the configuration of check matrix for LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 95 shows an example of the configuration of check matrix for LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 96 shows an example of the configuration of an encoder for LDPC-CC of coding rate 13/15 that is based on a parity check polynomial.

FIG. 97 is a diagram for explaining a zero-termination method.

FIG. 98 is a diagram for explaining a zero-termination method.

FIG. 99 shows an example of the configuration of check matrix for LDPC-CC of coding rate 13/15 when tail-biting is performed.

FIG. 100 shows an example of the configuration of check matrix for LDPC-CC of coding rate 13/15 when improved tail-biting is performed.

FIG. 101 shows an example of the configuration of check matrix for LDPC-CC of coding rate 13/15 when improved tail-biting is performed.


[Description of Embodiments]



[0016] Embodiments of the present invention are described below, with reference to the accompanying drawings.

[0017] Before describing specific configurations and operations of the embodiments, an LDPC-CC based on parity check polynomials described in Patent Literatures 1 and 2 is described first.

[0018] For example, a convolutional code of a coding rate of 1/2 and generator polynomial G=[1G1(D)/G0(D)] will be considered as an example. Here, G1 represents a feed-forward polynomial and G0 represents a feedback polynomial. If a polynomial representation of an information sequence (data) is X(D), and a polynomial representation of a parity sequence is P(D), a parity check polynomial is represented as shown in expression 1 below.
[Math. 1]

where D is a delay operator.

[0019] FIG. 3 shows information relating to a (7, 5) convolutional code. A (7, 5) convolutional code generator polynomial is represented as G=[1(D2+1)/(D2+D+1)]. Therefore, a parity check polynomial is as shown in expression 2 below.
[Math. 2]



[0020] Here, data at point in time i are represented by Xi, and parity bit by Pi, and transmission sequence Wi is represented as Wi=(Xi, Pi). Then, transmission vector w is represented as w=(X1, P1, X2, P2, ..., Xi, Pi ...)T. Thus, from expression 2, parity check matrix H can be represented as shown in FIG. 3. At this time, the relational expression in expression 3 below holds true.
[Math. 3]



[0021] Therefore, with parity check matrix H, the decoding side can perform decoding using belief propagation (BP) decoding, min-sum decoding similar to BP decoding, offset BP decoding, normalized BP decoding, shuffled BP decoding, scheduled layered BP decoding, or suchlike belief propagation, as shown in Non-Patent Literature 4, Non-Patent Literature 6, Non-Patent Literature 7, and Non-Patent Literature 8.

[LDPC-CC of Coding Rate (n-1)/n (where n is an integer no smaller than two) based on Parity Check Polynomial]



[0022] The following describes a code configuration method of an LDPC-CC based on a parity check polynomial having a time-varying period greater than three and having excellent error correction capability.

[Time-varying Period of Six]



[0023] First, an LDPC-CC having a time-varying period of six is described as an example.

[0024] Consider expression 4-0 through 4-5 as parity check polynomials (that satisfy 0) of an LDPC-CC having a coding rate of (n-1)/n (n is an integer no smaller than two) and a time-varying period of six.
[Math. 4]



[0025] Here, X1(D), X2(D), ..., Xn-1(D) are polynomial representations of data (information) X1, X2, ... Xn-1, P(D) is a polynomial representation of parity, and D is a delay operator. In expression 4-0 through 4-5, when, for example, the coding rate is 1/2, only the terms of X1(D) and P(D) are present and the terms of X2(D), ..., Xn-1(D) are not present. Similarly, when the coding rate is 2/3, only the terms of X1(D), X2(D) and P(D) are present and the terms of X3(D), ..., Xn-1(D) are not present. The other coding rates may also be considered in a similar manner.

[0026]  Here, expression 4-0 through 4-5 are assumed to have such parity check polynomials that three terms are present in each of X1(D), X2(D), ..., Xn-1(D) and P(D).

[0027] Furthermore, in expression 4-0 through 4-5, it is assumed that the following holds true for X1(D), X2(D), ..., Xn-1(D) and P(D).

[0028] In expression 4-q, it is assumed that a#q,p,1, a#q,p,2 and a#q,p,3 are natural numbers and a#q,p,1≠a#q,p,2, a#q,p,1≠a#q,p,3 and a#q,p,2≠a#q,p,3 hold true. Furthermore, it is assumed that b#q,1, b#q,2 and b#q,3 are natural numbers and b#q,1≠b#q,2, b#q,1≠b#q,3 and b#q,1≠b#q,3 hold true (q=0, 1, 2, 3, 4, 5; p=1, 2, ..., n-1).

[0029] The parity check polynomial of expression 4-q is called check equation #q and the sub-matrix based on the parity check polynomial of expression 4-q is called qth sub-matrix Hq. Next, consider an LDPC-CC of a time-varying period of six generated from zeroth sub-matrix H0, first sub-matrix H1, second sub-matrix H2, third sub-matrix H3, fourth sub-matrix H4 and fifth sub-matrix H5.

[0030] In an LDPC-CC having a time-varying period of six and a coding rate of (n-1)/n (where n is an integer no smaller than two), the parity bit and information bits at point in time i are represented by Pi and Xi,1, Xi,2, ..., Xi,n-1, respectively. If i%6g=k (where k=0, 1, 2, 3, 4, 5) is assumed at this time, a parity check polynomial of expression 4-(k) holds true. For example, if i=8, i%6g=2 (k=2), expression 5 holds true.
[Math. 5]



[0031] It is assumed that a#q,1,3=0 and b#q,3=0 (q=0, 1, 2, 3, 4, 5) so as to simplify the relationship between the parity bits and information bits in expression 4-0 through 4-5 and sequentially find the parity bits when tail-biting is not performed. Therefore, the parity check polynomials (that satisfy 0) of expression 4-0 through 4-5 are represented as shown in expression 6-0 through expression 6-5.
[Math. 6]





[0032] Furthermore, it is assumed that zeroth sub-matrix H0, first sub-matrix H1, second sub-matrix H2, third sub-matrix H3, fourth sub-matrix H4 and fifth sub-matrix H5 are represented as shown in expression 7-0 through expression 7-5.
[Math. 7]





[0033] In expression 7-0 through expression 7-5, n continuous ones correspond to the terms of X1(D), X2(D), ..., Xn-1(D) and P(D) in each of expression 6-0 through expression 6-5.

[0034] Here, parity check matrix H can be represented as shown in FIG. 4. As shown in FIG. 4, a configuration is employed in which a sub-matrix is shifted n columns to the right between an ith row and (i+1)th row in parity check matrix H (see FIG. 4). Assuming transmission vector u as u=(X1,0, X2,0, ..., Xn-1,0, P0, X1,1, X2,1, ..., Xn-1,1, P1, ..., X1,k, X2,k, ..., Xn-1,k, Pk, ...)T, Hu=0 holds true. (Here, the zero in Hu=0 indicates that vector Hu is a (column) vector all elements of which are zeroes.)

[0035] Here, examples of conditions for the parity check polynomials in expression 6-0 through expression 6-5 are described under which high error correction capability can be achieved.

[0036] Condition #1-1 and Condition #1-2 below are important for the terms relating to X1(D), X2(D), ..., Xn-1(D). In the following conditions, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6.





By designating Condition #1-1 and Condition #1-2 as constraint conditions, the LDPC-CC that satisfies the constraint conditions becomes a regular LDPC code, and can thereby achieve high error correction capability.

[0037] Next, other important constraint conditions are described.

<Conditions #2-1>



[0038] In Condition #1-1, vp=1, vp=2, vp=3, vp=4, ..., vp=k, ..., vp=n-2, vp=n-1, and w are set to one, four, and five. That is, vp=k (k=1, 2, ..., n-1) and w are set to one and natural numbers other than divisors of a time-varying period of six.

<Condition #2-2>



[0039] In Condition #1-2, yp-1, yp=2, yp=3, yp=4, ..., yp=k, ..., yp=n-2, yp=n-1 and z are set to one, four, and five. That is, yp=k (k=1, 2, ..., n-1) and z are set to one and natural numbers other than divisors of a time-varying period of six

[0040]  By adding the constraint conditions of Condition #2-1 and Condition #2-2 or the constraint conditions of Condition #2-1 or Condition #2-2, it is possible to use time-varying periods effectively. This point is described in detail with reference to the accompanying drawings.

[0041] For simplicity of explanation, a case is considered where X1(D) in parity check polynomials 6-0 to 6-5 of an LDPC-CC having a time-varying period of six and a coding rate of (n-1)/n based on parity check polynomials has two terms. At this time, the parity check polynomials are represented as shown in expression 8-0 through expression 8-5.
[Math. 8]



[0042] Here, a case is considered where vp=k (k=1, 2, ..., n-1) and w are set to three. Three is a divisor of a time-varying period of six.

[0043] FIG. 5 shows a tree of check nodes and variable nodes when only information X1 is focused upon when it is assumed that vp=1 and w are set to three and (a#0,1,1%6=a#1,1,1%6=a#2,1,1%6=a#3,1,1%6=a#4,1,1%6=a#5,1,1%6=3).

[0044] The parity check polynomial of expression 8-q is termed check equation #q. In FIG. 5, a tree is drawn from check equation #0. In FIG. 5, the symbols ○ (single circle) and ⊚ (double circle) represent variable nodes, and the symbol □ (square) represents a check node. The symbol o (single circle) represents a variable node relating to X1(D) and the symbol ⊚ (double circle) represents a variable node relating to Da#q,1,1X1(D). Furthermore, the symbol □ (square) described as #Y (Y=0, 1, 2, 3, 4, 5) means a check node corresponding to a parity check polynomial of expression 8-Y.

[0045] In FIG. 5, values that do not satisfy Condition #2-1, that is, vp=1, vp=2, vp=3, vp=4, ..., vp=k, ···, vp=n-2, vp=n-1 (k=1, 2, ..., n-1) and w are set to a divisor other than one among divisors of time-varying period of six (w=3).

[0046] In this case, as shown in FIG. 5, #Y only have limited values such as zero or three at check nodes. That is, even if the time-varying period is increased, belief is propagated only from a specific parity check polynomial, which means that the effect of having increased the time-varying period is not achieved.

[0047] In other words, the condition for #Y to have only limited values is to set vp=1, vp=2, vp=3, vp=4, ···, vp-k, ···, vp=n-2, vp=n-1 (k=1, 2, ..., n-1) and w to a divisor other than one among divisors of a time-varying period of six.

[0048] By contrast, FIG. 6 shows a tree when vp=k (k=1, 2, ..., n-1) and w are set to one in the parity check polynomial. When vp=k (k=1, 2, ..., n-1) and w are set to one, the condition of Condition #2-1 is satisfied.

[0049] As shown in FIG. 6, when the condition of Condition #2-1 is satisfied, #Y takes all values from zero to five at check nodes. That is, when the condition of Condition #2-1 is satisfied, belief is propagated by all parity check polynomials corresponding to the values of #Y. As a result, even when the time-varying period is increased, belief is propagated from a wide range and the effect of having increased the time-varying period can be achieved. That is, it is clear that Condition #2-1 is an important condition to achieve the effect of having increased the time-varying period. Similarly, Condition #2-2 becomes an important condition to achieve the effect of having increased the time-varying period.

[Time-varying Period of Seven]



[0050] When the above is taken into consideration, the time-varying period being a prime number is an important condition to achieve the effect of having increased the time-varying period.

[0051] Consider expression 9-0 through 9-6 as parity check polynomials (that satisfy 0) of an LDPC-CC having a coding rate of (n-1)/n (n is an integer no smaller than two) and a time-varying period of seven.
[Math. 9]



[0052] In expression 9-q, it is assumed that a#q,p,1 and a#q,p,2 are natural numbers no smaller than one, and a#q,p,1≠a#q,p,2 holds true. Furthermore, it is assumed that b#q,1 and b#q,2 are natural numbers no smaller than one, and b#q,1≠b#q,2 holds true (q=0, 1, 2, 3, 4, 5, 6; p=1, 2, ..., n-1).

[0053] In an LDPC-CC having a time-varying period of seven and a coding rate of (n-1)/n (where n is an integer no smaller than two), the parity bit and information bits at point in time i are represented by Pi and Xi,1, Xi,2, ..., Xi,n-1respectively. If i%7=k (where k=0, 1, 2, 3, 4, 5, 6) is assumed at this time, the parity check polynomial of expression 9-(k) holds true.

[0054] For example, if i=8, i%7=1 (k=1), expression 10 holds true.
[Math. 10]



[0055] Furthermore, when the sub-matrix (vector) of expression 9-g is assumed to be Hg, the parity check matrix can be created using the method described in [LDPC-CC based on parity check polynomial]. Here, the 0th sub-matrix, first sub-matrix, second sub-matrix, third sub-matrix, fourth sub-matrix, fifth sub-matrix and sixth sub-matrix are represented as shown in expression 11-0 through expression 11-6.
[Math. 11]



[0056] In expression 11-0 through expression 11-6, n continuous ones correspond to the terms of X1(D), X2(D), ..., Xn-1(D), and P(D) in each of expression 9-0 through expression 9-6.

[0057]  Here, parity check matrix H can be represented as shown in FIG. 7. As shown in FIG. 7, a configuration is employed in which a sub-matrix is shifted n columns to the right between an ith row and (i+1)th row in parity check matrix H (see FIG. 7). When transmission vector u is assumed to be u=(X1,0, X2,0, ..., Xn-1,0, P0, X1,1, X2,1, ..., Xn-1,1, P1, ..., X1,k, X2,k, ..., Xn-1,k, Pk, ...)T, Hu=0 holds true. (Here, the zero in Hu=0 indicates that vector Hu is a column vector all elements of which are zeroes.)

[0058] Here, the condition for the parity check polynomials in expression 9-0 through expression 9-6 to achieve high error correction capability is as follows as in the case of the time-varying period of six. In the following conditions, % means a modulo, and for example, α%7 represents a remainder after dividing α by seven.





By designating Condition #1-1' and Condition #1-2' constraint conditions, the LDPC-CC that satisfies the constraint conditions becomes a regular LDPC code, and can thereby achieve high error correction capability.

[0059] In the case of a time-varying period of six, achieving high error correction capability further requires Condition #2-1 and Condition #2-2, or Condition #2-1, or Condition #2-2. By contrast, when the time-varying period is a prime number as in the case of a time-varying period of seven, the condition corresponding to Condition #2-1 and Condition #2-2, or Condition #2-1, or Condition #2-2 required in the case of the time-varying period of six, is unnecessary.

[0060] That is to say,
in Condition #1-1', values of vp=1, vp=2, vp=3, vp=4, ..., vp=k, ..., vp=n-2, vp=n-1 (k=1, 2, ..., n-1) and w may be one of values 0, 1, 2, 3, 4, 5 and 6.

[0061] Also,
in Condition #1-2', values of yp=1, yp=2, yp=3, yp=4,..., yp=k, ..., yp=n-2, yp=n-1 (k= 1, 2, ..., n-1) and z may be one of values 0, 1, 2, 3, 4, 5, and 6.

[0062] The reason is described below.

[0063] For simplicity of explanation, a case is considered where X1(D) in parity check polynomials 9-0 to 9-6 of an LDPC-CC having a time-varying period of seven and a coding rate of (n-1)/n based on parity check polynomials has two terms. In this case, the parity check polynomials are represented as shown in expression 12-0 through expression 12-6.
[Math. 12]





[0064] Here, a case is considered where vp=k (k=1, 2, ..., n-1) and w are set to two.

[0065] FIG. 8 shows a tree of check nodes and variable nodes when only information X1 is focused upon when vp=1 and w are set to two and a#0,1,1%7=a#1,1,1%7=a#2,1,1%7=a#3,1,1%7=a#4,1,1%7=a#5,1,1%7=a#6,1,1%7=2.

[0066] The parity check polynomial of expression 12-q is termed check equation #q. In FIG. 8, a tree is drawn from check equation #0. In FIG. 8, the symbols ○ (single circle) and ⊚ (double circle) represent variable nodes, and the symbol □ (square) represents a check node. The symbol o (single circle) represents a variable node relating to X1(D) and the symbol ⊚ (double circle) represents a variable node relating to Da#q,1,1X1(D). Furthermore, the symbol □ (square) described as #Y (Y=0, 1, 2, 3, 4, 5, 6) means a check node corresponding to a parity check polynomial of expression 12-Y.

[0067] In the case of a time-varying period of six, for example, as shown in FIG. 5, there may be cases where #Y only has a limited value and check nodes are only connected to limited parity check polynomials. By contrast, when the time-varying period is seven (a prime number) such as a time-varying period of seven, as shown in FIG. 8, #Y have all values from zero to six and check nodes are connected to all parity check polynomials. Thus, belief is propagated by all parity check polynomials corresponding to the values of #Y. As a result, even when the time-varying period is increased, belief is propagated from a wide range and it is possible to achieve the effect of having increased the time-varying period. Although FIG. 8 shows the tree when a#q,1,1%7 (q=0, 1, 2, 3, 4, 5, 6) is set to two, check nodes can be connected to all the applicable parity check polynomials if a#q,1,1%7 is set to any value other than zero.

[0068]  Thus, it is clear that if the time-varying period is set to a prime number in this way, constraint conditions relating to parameter settings for achieving high error correction capability are drastically relaxed compared to a case where the time-varying period is not a prime number. When the constraint conditions are relaxed, adding another constraint condition enables higher error correction capability to be achieved. Such a code configuration method is described below.

[Time-Varying Period of q (q is a prime number greater than three): expression 13]



[0069] First, a case will be considered where a gth (g=0, 1, ..., q-1) parity check polynomial of a coding rate of (n-1)/n and a time-varying period of q (q is a prime number greater than three) is represented as shown in expression 13.
[Math. 13]



[0070] In expression 13, it is also assumed that a#g,p,1 and a#g,p,2 are natural numbers no smaller than one and that a#g,p,1≠a#g,p,2 holds true. Furthermore, it is also assumed that b#g,1 and b#g,2 are natural numbers no smaller than one and that b#g,1≠b#g,2 holds true (g=0, 1, 2, ..., q-2, q-1; p=1, 2, ..., n-1).

[0071] In the same way as the above description, Condition #3-1 and Condition #3-2 described below are one of important requirements for an LDPC-CC to achieve high error correction capability. In the following conditions, % means a modulo, and for example, α%q represents a remainder after dividing α by q.







[0072] In addition, when Condition #4-1 or Condition #4-2 holds true for a set of (vp=1, yp=1), (vp=2, yp=2), (vp=3, yp=3), ... (vp=k, yp=k), ..., (vp=n-2, yp=n-2), (vp=n-1, yp=n-1), and (w, z), high error correction capability can be achieved. Here, k=1, 2, ..., n-1.

<Condition #4-1>



[0073] Consider (vp=i, yp=i) and (vp=j, yp=j), where it is assumed that i=1, 2, ..., n-1, j=1, 2, ..., n-1, and i≠j. At this time, i and j (i≠j) are present where (vp=i, yp=i)≠(vp=j, yp=j) and (vp=i, yp=i)#(yp=j, vp=j) hold true.

<Condition #4-2>



[0074] Consider (vp=i, yp=i) and (w, z), where it is assumed that i=1, 2, ..., n-1. At this time, i is present where (vp=i, yp=i)≠(w, z) and (vp=i, yp=i)≠(z, w) hold true.

[0075] By making more severe the constraint conditions of Condition #4-1 and Condition #4-2, it is more likely to be able to generate an LDPC-CC of a time-varying period of q (q is a prime number no smaller than three) with higher error correction capability. The condition is that Condition #5-1 and Condition #5-2, or Condition #5-1, or Condition #5-2 should hold true.

<Condition #5-1>



[0076] Consider (vp=i, yp=i) and (vp=j, yp=j), where i=1, 2, ..., n-1, j=1, 2, ..., n-1, and i≠j. At this time, (vp=i, yp=i)≠(vp=j, yp=j) and (vp=i, yp=i)≠(yp=j, vp=j) hold true for all i and j (i≠j).

<Condition #5-2>



[0077] Consider (vp=i, yp=i) and (w, z), where i=1, 2, ..., n-1. Here, (vp=i, yp=i)≠(w, z) and (vp=i, yp=i)≠(z, w) hold true for all i.

[0078] Furthermore, when vp=i≠yp=i (i=1, 2, ..., n-1) and w≠z hold true, it is possible to suppress the occurrence of short loops in a Tanner graph.

[0079] In addition, when 2n<q, if (vp=i, yp=i) and (z, w) have different values, it is more likely to be able to generate an LDPC-CC of a time-varying period of q (q is a prime number greater than three) with higher error correction capability.

[0080] Furthermore, when 2n≥q, if (vp=i, yp=i) and (z, w) are set so that all values of 0, 1, 2, ..., q-1 are present, it is more likely to be able to generate an LDPC-CC having a time-varying period of q (q is a prime number greater than three) with higher error correction capability.

[0081] In the above description, expression 13 having three terms in X1(D), X2(D), ..., Xn-1(D) and P(D) has been handled as the gth parity check polynomial of an LDPC-CC having a time-varying period of q (q is a prime number greater than three). In expression 13, it is also likely to be able to achieve high error correction capability when the number of terms of any of X1(D), X2(D), ..., Xn-1(D) and P(D) is one or two. For example, the following method is available as the method of setting the number of terms of X1(D) to one or two. In the case of a time-varying period of q, there are q parity check polynomials that satisfy zero and the number of terms of X1(D) is set to one or two for all the q parity check polynomials that satisfy zero. Alternatively, instead of setting the number of terms of X1(D) to one or two for all the q parity check polynomials that satisfy zero, the number of terms of X1(D) may be set to one or two for any number (equal to or less than q-1) of parity check polynomials that satisfy zero. The same applies to X2(D), ..., Xn-1(D) and P(D). In this case, satisfying the above-described condition constitutes an important condition in achieving high error correction capability. However, the condition relating to the deleted terms is unnecessary.

[0082] Furthermore, high error correction capability may also be likely to be achieved even when the number of terms of any of X1(D), X2(D), ..., Xn-1(D) and P(D) is four or more. For example, the following method is available as the method of setting the number of terms of X1(D) to four or more. In the case of a time-varying period of q, there are q parity check polynomials that satisfy zero and the number of terms of X1(D) is set to four or more for all the q parity check polynomials that satisfy zero. Alternatively, instead of setting the number of terms of X1(D) to four or more for all the q parity check polynomials that satisfy zero, the number of terms of X1(D) may be set to four or more for any number (equal to or less than q-1) of parity check polynomials that satisfy zero. The same applies to X2(D), ..., Xn-1(D) and P(D). Here, the above-described condition is excluded for the added terms.

[Time-Varying Period of h (h is a non-prime integer greater than three): expression 14]



[0083] Next, a code configuration method when time-varying period h is a non-prime integer greater than three will be considered.

[0084] First, a case will be considered where the gth (g=0, 1, ..., h-1) parity check polynomial of a coding rate of (n-1)/n and a time-varying period of h (h is a non-prime integer greater than three) is represented as shown in expression 14.
[Math. 14]



[0085] In expression 14, it is assumed that a#g,p,1 and a#g,p,2 are natural numbers no smaller than one and a#g,p,1≠a#g,p,2 holds true. Furthermore, it is assumed that b#g,1 and b#g,2 are natural numbers no smaller than one and b#g,1≠b#g,2 holds true (g=0, 1, 2, ..., h-2, h-1; p=1, 2, ..., n-1).

[0086] In the same way as the above description, Condition #6-1 and Condition #6-2 described below are one of important requirements for an LDPC-CC to achieve high error correction capability. In the following conditions, % means a modulo, and for example, α%h represents a remainder after dividing α by h.







[0087] In addition, as described above, high error correction capability can be achieved by adding Condition #7-1 or Condition #7-2.

<Condition #7-1>



[0088] In Condition #6-1, vp=1, vp=2, vp=3, vp=4, ..., vp=k, ..., vp=n-2, vp=n-1 (k=1, 2, ..., n-1) and w are set to one and are natural numbers other than divisors of a time-varying period of h.

<Condition #7-2>



[0089] In Condition #6-2, yp=1, yp=2, yp=3, yp=4, ..., yp=k, ..., yp=n-2, yp=n-1 (k=1, 2, ..., n-1) and z are set to one and are natural numbers other than divisors of a time-varying period of h.

[0090] Then, consider a set of (vp=1, yp=1), (vp=2, yp=2), (vp=3, yp=3), ... (vp=k, yp=k), ..., (vp=n-2, yp=n-2), (vp=n-1, yp=n-1) and (w, z). Here, it is assumed that k=1, 2, ..., n-1. If Condition #8-1 or Condition #8-2 holds true, higher error correction capability can be achieved.

<Condition #8-1>



[0091] Consider (vp=i, yp=i) and (vp=j, yp=j), where it is assumed that i=1, 2, ..., n-1, j=1, 2, ..., n-1 and i≠j. At this time, there are i and j (i≠j) for which (vp=i, yp=i)≠(vp=j, yp=j) and (vp=i, yp=i)≠(yp=j, vp=j) hold true.

<Condition #8-2>



[0092] Consider (vp=i, yp=i) and (w, z), where it is assumed that i=1, 2, ..., n-1. At this time, there is i for which (vp=i, yp=i)≠(w, z) and (vp=i, yp=i)≠(z, w) hold true.

[0093] Furthermore, by making more severe the constraint conditions of Condition #8-1 and condition #8-2, it is more likely to be able to generate an LDPC-CC of a time-varying period of h (h is a non-prime integer no smaller than three) with higher error correction capability. The condition is that Condition #9-1 and Condition #9-2, Condition #9-1, or Condition #9-2 should hold true.

<Condition #9-1>



[0094] Consider (vp=i, yp=i) and (vp=j, yp=j), where it is assumed that i=1, 2, ..., n-1, j=1, 2, ..., n-1 and i≠j. At this time, (vp=i, yp=i)≠(vp=j, yp=j) and (vp=i, yp=i)≠(yp=j, vp=j) hold true for all i and j (i≠j).

<Condition #9-2>



[0095] Consider (vp=i, yp=i) and (w, z), where it is assumed that i=1, 2, ..., n-1. At this time, (vp=i, yp=i)≠(w, z) and (vp=i, yp=i)≠(z, w) hold true for all i.

[0096] Furthermore, when vp=i≠yp=i (i=1, 2, ..., n-1) and w≠z hold true, it is possible to suppress the occurrence of short loops in a Tanner graph.

[0097] In the above description, expression 14 having three terms in X1(D), X2(D), ···, Xn-1(D) and P(D) has been handled as the gth parity check polynomial of an LDPC-CC having a time-varying period of h (h is a non-prime integer greater than three). In expression 14, it is also likely to be able to achieve high error correction capability when the number of terms of any of X1(D), X2(D), ..., Xn-1(D) and P(D) is one or two. For example, the following method is available as the method of setting the number of terms of X1(D) to one or two. In the case of a time-varying period of h, there are h parity check polynomials that satisfy zero and the number of terms of X1(D) is set to one or two for all the h parity check polynomials that satisfy zero. Alternatively, instead of setting the number of terms of X1(D) to one or two for all the h parity check polynomials that satisfy zero, the number of terms of X1(D) may be set to one or two for any number (equal to or less than h-1) of parity check polynomials that satisfy zero. The same applies to X2(D), ..., Xn-1(D) and P(D). In this case, satisfying the above-described condition constitutes an important condition in achieving high error correction capability. However, the condition relating to the deleted terms is unnecessary.

[0098] Moreover, even when the number of terms of any of X1(D), X2(D), ..., Xn-1(D) and P(D) is four or more, it is also likely to be able to achieve high error correction capability. For example, the following method is available as the method of setting the number of terms of X1(D) to four or more. In the case of a time-varying period of h, there are h parity check polynomials that satisfy zero, and the number of terms of X1(D) is set to four or more for all the h parity check polynomials that satisfy zero. Alternatively, instead of setting the number of terms of X1(D) to four or more for all the h parity check polynomials that satisfy zero, the number of terms of X1(D) may be set to four or more for any number (equal to or less than h-1) of parity check polynomials that satisfy zero. The same applies to X2(D), ..., Xn-1(D) and P(D). At this time, the above-described condition is excluded for the added terms.

[0099] The following describes an LDPC-CC encoding method and the configuration of an encoder based on the parity check polynomials described above.

[0100] First, consider an LDPC-CC having a coding rate of 1/2 and a time-varying period of three as an example. Parity check polynomials of a time-varying period of three are provided below.
[Math. 15]



[0101] At this time, P(D) is obtained as shown below.
[Math. 16]



[0102] Then, expression 16-0 through expression 16-2 are represented as follows:
[Math. 17]

where the symbol ⊕ represents the exclusive OR operator.

[0103] Here, FIG. 9 shows the circuit corresponding to expression 17-0, FIG. 10 shows the circuit corresponding to expression 17-1 and FIG. 11 shows the circuit corresponding to expression 17-2. (Here, it is assumed that tail-biting is not performed.)

[0104] At point in time i=3k, the parity bit at point in time i is obtained through the circuit shown in FIG. 9 corresponding to expression 16-0, that is, expression 17-0. At point in time i=3k+1, the parity bit at point in time i is obtained through the circuit shown in FIG. 10 corresponding to expression 16-1, that is, expression 17-1. At point in time i=3k+2, the parity bit at point in time i is obtained through the circuit shown in FIG. 11 corresponding to expression 16-2, that is, expression 17-2. Therefore, the encoder can adopt the configuration of FIG. 12. In FIG. 12, a weight control section 130 outputs signals for controlling weight as time elapses. Further, 112-0 through 112-M and 122-0 through 122-M in FIG. 12 change weight as time elapses, based on these signals for controlling weight.

[0105] Encoding can be performed also when the time-varying period is other than three and the coding rate is (n-1)/n in the same way as that described above. For example, the gth (g=0, 1, ..., q-1) parity check polynomial of an LDPC-CC having a time-varying period of q and a coding rate of (n-1)/n is represented as shown in expression 13, and therefore P(D) is represented as follows, where q is not limited to a prime number.
[Math. 18]



[0106] When expressed in the same way as expression 17-0 through expression 17-2, expression 18 is represented as follows:
[Math. 19]

where the symbol represents the exclusive OR operator.

[0107] Here, Xr[i] (r=1, 2, ..., n-1) represents an information bit at point in time i and P[i] represents a parity bit at point in time i.

[0108] Therefore, when i%q=k at point in time i, the parity bit at point in time i in expression 18 and expression 19 can be achieved using a formula resulting from substituting k for g in expression 18 and expression 19.

[0109] Since an LDPC-CC is a kind of convolutional code, securing belief in decoding of information bits requires termination or tail-biting, or performing tail-biting. Here, a case is considered where termination is performed (hereinafter, information-zero-termination, or simply zero-termination).

[0110] FIG. 13 is a diagram illustrating information-zero-termination for an LDPC-CC having a coding rate of (n-1)/n. It is assumed that information bits X1, X2, ..., Xn-1 and parity bit P at point in time i (i=0, 1, 2, 3, ..., s) are represented by X1,i, X2,i, ..., Xn-1,i, and parity bit Pi, respectively. As shown in FIG. 13, Xn-1, s is assumed to be the final bit of the information to transmit.

[0111] If the encoder performs encoding only until point in time s and the transmitting apparatus on the encoding side performs transmission only up to Ps to the receiving apparatus on the decoding side, receiving quality of information bits of the decoder considerably deteriorates. To solve this problem, encoding is performed assuming information bits from final information bit Xn-1,s onward (hereinafter virtual information bits) to be zeroes, and a parity bit (1303) is generated.

[0112] To be more specific, as shown in FIG. 13, the encoder performs encoding assuming X1,k, X2,k, ..., Xn-1,k (k=t1, t2, ..., tm) to be zeroes and obtains Pt1, Pt2, ..., Ptm. After transmitting X1,s, X2,s, ..., Xn-1,s, and Ps at point in time s, the transmitting apparatus on the encoding side transmits Pt1, Pt2, ..., Ptm. The decoder performs decoding taking advantage of knowing that virtual information bits are zeroes from point in time s onward.

[0113] In termination such as information-zero-termination, for example, LDPC-CC encoder 100 in FIG. 12 performs encoding assuming the initial state of the register is zero. As another interpretation, when encoding is performed from point in time i=0, if, for example, z is less than zero in expression 19, encoding is performed assuming X1[z], X2[z], ..., Xn-1[z], and P[z] to be zeroes.

[0114] Assuming a sub-matrix (vector) in expression 13 to be Hg, a gth sub-matrix can be represented as shown below.
[Math. 20]



[0115] Here, n continuous ones correspond to the terms of X1(D), X2(D), ..., Xn-1(D) and P(D) in expression 13.

[0116] Therefore, when termination is used, the LDPC-CC check matrix having a coding rate of (n-1)/n and a time-varying period of q represented by expression 13 is represented as shown in FIG. 14.

[0117] As shown in FIG. 14, a configuration is employed in which a sub-matrix is shifted n columns to the right between an ith row and (i+1)th row in parity check matrix H (see FIG. 14). However, an element to the left of the first column (H'1 in the example of FIG. 14) is not reflected in the parity check matrix (see FIG. 14). When transmission vector u is assumed to be u=(X1,0, X2,0, ..., Xn-1,0, P0, X1,1, X2,1, ..., Xn-1,1, P1, ..., X1,k, X2,k, ..., Xn-1,k, Pk, ...)T, Hu=0 holds true. (Here, the zero in Hu=0 indicates that vector Hu is a column vector all elements of which are zeroes.)

[0118] As described above, the encoder receives information bits Xr[i] (r=1, 2, ..., n-1) at point in time i as input, generates parity bit P[i] at point in time i using expression 19, outputs parity bit [i], and can thereby perform encoding of the LDPC-CC described in embodiment 1.

[0119] The following describes a conventional time-varying LDPC-CC having a coding rate of R=(n-1)/n (where n is an integer no smaller than two). Information bits of X1, X2, ... and Xn-1 and parity bit P at point in time j are represented by X1,j, X2,j, ..., Xn-1,j, and Pj, respectively. Vector uj at point in time j is represented by uj=(X1,j, X2,j, ..., Xn-1,j, Pj). Furthermore, the encoded sequence is represented by u=(u0, u1, ..., uj, ...)T. Assuming D to be a delay operator, the polynomial of information bits X1, X2, ..., Xn-1 is represented by X1(D), X2(D), ..., Xn-1(D) and the polynomial of parity bit P is represented by P(D). At this time, consider a parity check polynomial that satisfies zero represented as shown in expression 21.
[Math. 21]



[0120] In expression 21, it is assumed that ap,q (p=1, 2, ..., n-1; q=1, 2, ..., rp) and bs (s=1, 2, ..., ε) are natural numbers. Furthermore, ap, y≠ap,z is satisfied for (y, z) of y, z=1, 2, ..., rp, y≠z. Furthermore, by≠bz is satisfied for (y, z) of y, z=1, 2, ..., ε, y≠z. Here, ∀ is the universal quantifier.

[0121] To create an LDPC-CC having a coding rate of R=(n-1)/n and a time-varying period of m, a parity check polynomial based on expression 21 is provided. At this time, an ith (i=0, 1, ..., m-1) parity check polynomial is represented as shown in expression 22.
[Math. 22]



[0122] In expression 22, maximum orders of D of AXδ,i(D) (δ=1, 2, ..., n-1) and Bi (D) are represented by ΓXδ,i and ΓP,i, respectively. A maximum value of ΓXδ,i and ΓP,i is assumed to be Γi. A maximum value of Γi (i=0, 1, ..., m-1) is assumed to be Γ. When encoded sequence u is taken into consideration, using Γ, vector hi corresponding to an ith parity check matrix is represented as shown in expression 23.
[Math. 23]



[0123] In expression 23, hi,v (v=0, 1, ..., Γ) is a vector of 1 ×n and represented as shown in expression 24.
[Math. 24]



[0124] This is because the parity check polynomial of expression 22 has αi,v,XwDvXw(D) and βi,vDvP(D) (w=1, 2, ..., n-1, and αi,v,Xw, βi,v∈[0, 1]). At this time, the parity check polynomial that satisfies zero of expression 22 has D0X1(D), D0X2(D), ..., D0Xn-1(D) and D0P(D), and therefore satisfies expression 25.
[Math. 25]



[0125] In expression 25, Λ(k)=Λ(k+m) is satisfied for k, where Λ(k) corresponds to hi on a kth row of the parity check matrix.

[0126] Using expression 23, expression 24 and expression 25, an LDPC-CC parity check matrix based on the parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m is represented as shown in expression 26.
[Math. 26]


[Overview of LDPC-CC based on Parity Check Polynomial]



[0127] The following describes important items relating to an LDPC-CC based on a parity check polynomial having a time-varying period greater than three.

[0128] An LDPC-CC is a code defined by a low-density parity check matrix as in the case of an LDPC-BC, can be defined by a time-varying parity check matrix of an infinite length, but can actually be considered with a periodically time-varying parity check matrix.

[0129]  Assuming that a parity check matrix is H and a syndrome former is HT, HT of an LDPC-CC having a coding rate of R=d/c (d<c) can be represented as shown in expression 27.
[Math. 27]



[0130] In expression 27, HTi(t) (i=0, 1, ..., ms) is a c×(c-d) periodic sub-matrix and if the period is assumed to be Ts, HTi(t)=HTi(t+Ts) holds true for i and t. Furthermore, Ms is a memory size.

[0131] The LDPC-CC defined by expression 27 is a time-varying convolutional code and this code is called a time-varying LDPC-CC. As for decoding, BP decoding is performed using parity check matrix H. When encoded sequence vector u is assumed, the following relational expression holds true.
[Math. 28]



[0132] An information sequence is obtained by performing BP decoding using the relational expression in expression 28.

<LDPC-CC based on Parity Check Polynomial>



[0133] Consider a systematic convolutional code of a coding rate of R=1/2 of generator matrix G=[1G1(D)/G0(D)]. At this time, G1 represents a feed forward polynomial and G0 represents a feedback polynomial.

[0134] Assuming a polynomial representation of an information sequence is X(D) and a polynomial representation of a parity sequence is P(D), a parity check polynomial that satisfies zero can be represented as shown below.
[Math. 29]



[0135] Here, the parity check polynomial is provided as expression 30 that satisfies expression 29.
[Math. 30]





[0136] In expression 30, ap and bq are integers no smaller than one (p=1, 2, ..., r; q=1, 2, ..., s), terms of D0 are present inX(D) and P(D). The code defined by a parity check matrix based on the parity check polynomial that satisfies zero of expression 30 becomes a time-invariant LDPC-CC.

[0137] An m (m is an integer no smaller than two) number of different parity check polynomials based on expression 30 are provided. The parity check polynomial that satisfies zero is represented as shown below.
[Math. 31]



[0138] At this time, i=0, 1, ..., m-1.

[0139] The data and parity at point in time j are represented by Xj and Pj as uj=(Xj, Pj). It is then assumed that the parity check polynomial that satisfies zero of expression 32 holds true.
[Math. 32]



[0140] Parity Pj at point in time j can then be determined from expression 32. The code defined by the parity check matrix generated based on the parity check polynomial that satisfies zero of expression 32 becomes an LDPC-CC having a time-varying period of m (TV-m-LDPC-CC: Time-Varying LDPC-CC with a time period of m).

[0141] At this time, there are terms of D0 in P(D) of the time-invariant LDPC-CC defined in expression 30 and TV-m-LDPC-CC defined in expression 32, where bj is an integer no smaller than zero. Therefore, there is a characteristic that parity can be easily found sequentially by means of a register and exclusive OR (when tail-biting is not performed).

[0142] The decoding section creates parity check matrix H from expression 30 using the time-invariant LDPC-CC and creates parity check matrix H from expression 32 using the TV-m-LDPC-CC. The decoding section performs BP decoding on encoded sequence u=(u0, u1, ..., uj, ...)T using expression 28 and obtains an information sequence.

[0143] Next, consider a time-invariant LDPC-CC and TV-m-LDPC-CC of a coding rate of (n-1)/n (where n is an integer no smaller than two). It is assumed that information sequence X1, X2, ..., Xn-1 and parity P at point in time j are represented by X2,j, ..., Xn-1,j, and Pj respectively, and uj=(X1,j, X2,j, ..., Xn-1,j, Pj). When it is assumed that a polynomial representation of information sequence X1, X2, ..., Xn-1 is X1(D), X2(D), ..., Xn-1(D), the parity check polynomial that satisfies zero is represented as shown below.
[Math. 33]



[0144] In expression 33, ap,i is an integer no smaller than one (p=1, 2, ..., n-1; i=1, 2, ... rp), and satisfies ap,y≠ap,z ((y, z)|y, z=1, 2, ..., rp, y≠z) and b≠bz ((y, z)|y, z=1, 2, ..., ε, y≠z).

[0145] m (m is an integer no smaller than two) different parity check polynomials based on expression 33 are provided. A parity check polynomial that satisfies zero is represented as shown below.
[Math. 34]

where i=0, 1, ..., m-1.

[0146] It is then assumed that expression 35 holds true for X1,j, X2,j, ..., Xn-1,j, and Pj of information X1, X2, ..., Xn-1 and parity P at point in time j.
[Math. 35]



[0147] At this time, the codes based on expression 33 and expression 35 become time-invariant LDPC-CC and TV-m-LDPC-CC having a coding rate of (n-1)/n.

[0148] The following describes a regular TV-m-LDPC-CC.

[0149] A #qth parity check polynomial of a TV-m-LDPC-CC of a coding rate of (n-1)/n that satisfies zero is provided as shown below (q=0, 1, ..., m-1).
[Math. 36]





[0150] In expression 36, a#q,p,i is an integer no smaller than zero (p=1, 2, ..., n-1 ; i=1, 2, ..., rp) and satisfies a#q,p,y≠a#q,p,z ((y,z)|y, z=1, 2, ..., rp, y≠z) and b#q,y≠b#q,z ((y,z)|y, z=1, 2, ..., ε, y≠z).

[0151] The following features are then provided.

Feature 1:



[0152] There is a relationship as shown below between the term of Da#α,p,iXp(D) of parity check polynomial #α, the term of Da#β,p,jXp(D) of parity check polynomial #β (α, β=0, 1, ..., m-1; p=1, 2, ..., n-1; i, j=1, 2, ..., rp) and between the term of Db#α,iP(D) of parity check polynomial #α and the term of Db#β,jP(D) of parity check polynomial #β (α, β=0, 1, ..., m-1 (β≥α); i, j=1, 2, ..., rp).

<1> When β=α:



[0153] When {a#α,p,i mod m=a#β,p,j mod m} ∩ {i≠j} holds true, variable node $1 is present which forms edges of both a check node corresponding to parity check polynomial #α and a check node corresponding to parity check polynomial #β as shown in FIG. 15.

[0154] When {b#α,i mod m=b#β,j mod m} ∩ {i≠j} holds true, variable node $1 is present which forms edges of both a check node corresponding to parity check polynomial #α and a check node corresponding to parity check polynomial #β as shown in FIG. 15.

When β≠α:



[0155] It is assumed that β-α=L.

1) When a#α,p,i mod m<a#β,p,j mod m



[0156] When (a#β,p,j mod m)-(a#α,p,i mod m)=L, variable node $1 is present which forms edges of both a check node corresponding to parity check polynomial #α and a check node corresponding to parity check polynomial #β as shown in FIG. 15.

2) When a#α,p,i mod m>a#β,p,j mod m



[0157] When (a#β,p,j mod m)-(a#α,p,i mod m)=L+m, variable node $1 is present which forms edges of both a check node corresponding to parity check polynomial #α and a check node corresponding to parity check polynomial #β as shown in FIG. 15.

3) When b#α,i mod m<b#β,j mod m



[0158] When (b#β,j mod m)-(b#α,i mod m)=L, variable node $1 is present which forms edges of both a check node corresponding to parity check polynomial #α and a check node corresponding to parity check polynomial #β as shown in FIG. 15.

4) When b#α,i mod m>b#β,j mod m



[0159] When (b#β,j mod m)-(b#α,i mod m)=L+m, variable node $1 is present which forms edges of both a check node corresponding to parity check polynomial #α and a check node corresponding to parity check polynomial #β as shown in FIG. 15.

[0160] Theorem 1 holds true for cycle length six (CL6: cycle length of six) of a TV-m-LDPC-CC.

[0161] Theorem 1: The following two conditions are provided for a parity check polynomial that satisfies zero of the TV-m-LDPC-CC:

[0162] There are p and q that satisfy C#1.1: a#q,p,i mod m=a#q,p,j mod m=a#q,p,k mod m, where i≠j, i≠k and j≠k.

[0163] There is q that satisfies C#1.2: b#q,i mod m=b#q,j mod m=b#q,k mod m, where i≠j, i≠k and j≠k.

[0164] There is at least one CL6 when C#1.1 or C#1.2 is satisfied.

Proof:



[0165] If it is possible to prove that at least one CL6 is present when a#0,1,i mod m=a#0,1,j mod m=a#0,1,k mod m when p=1 and q=0, it is possible to prove that at least one CL6 is present also for X2(D), ..., Xn-1(D), P(D) by substituting X2(D), ..., Xn-1(D), P(D) for X1(D), if C#1.1 and C#1.2 hold true when q=0.

[0166] Furthermore, when q=0 if the above description can be proved, it is possible to prove that at least one CL6 is present also when q=1, ..., m-1 if C#1.1 and C#1.2 hold true, in the same way of thinking.

[0167] Therefore, when p=1, q=0, if a#0,1,i mod m=a#0,1,j mod m=a#0,1,k mod m holds true, it is possible to prove that at least one CL6 is present.

[0168] In X1(D) when q=0 is assumed for a parity check polynomial that satisfies zero of the TV-m-LDPC-CC in expression 36, if two or fewer terms are present, C#1.1 is never satisfied.

[0169]  In X1(D) when q=0 is assumed for a parity check polynomial that satisfies zero of the TV-m-LDPC-CC in expression 36, if three terms are present and a#q,p,i mod m=a#q,p,j mod m=a#q,p,k mod m is satisfied, the parity check polynomial that satisfies zero of q=0 can be represented as shown in expression 37.
[Math. 37]



[0170] Here, even when a#0,1,1>a#0,1,2>a#0,1,3 is assumed, generality is not lost, and γ and δ become natural numbers. At this time, in expression 37, when q=0, the term relating to X1(D), that is, (Da#0,1,3+mγ+mδ+D a#0,1,3+mδ+Da#0,1,3) X1(D) is focused upon. At this time, a sub-matrix generated by extracting only a portion relating to X1(D) in parity check matrix H is represented as shown in FIG. 16. In FIG. 16, h1,x1, h2,x1, ..., hm-1,x1 are vectors generated by extracting only portions relating to X1(D) when q=1, 2, ..., m-1 in the parity check polynomial that satisfies zero of expression 37, respectively.

[0171] At this time, the relationship as shown in FIG. 16 holds true because <1> of feature 1 holds true. Therefore, CL6 formed with a one shown by the symbol Δ as shown in FIG. 16 is always generated only in a sub-matrix generated by extracting only a portion relating to X1(D) of the parity check matrix in expression 37 regardless of γ and δ values.

[0172] When four or more X1(D)-related terms are present, three terms are selected from among four or more terms and if a#0,1,i mod m=a#0,1,j mod m=a#0,1,k mod m holds true in the selected three terms, CL6 is formed as shown in Fig. 16.

[0173] As shown above, when q=0, if a#0,1,i mod m=a#0,1,j mod m=a#0,1,k mod m holds true about X1(D), CL6 is present.

[0174] Furthermore, by also substituting X1(D) for X2(D), ..., Xn-1(D), P(D), at least one CL6 occurs when C#1.1 or C#1.2 holds true.

[0175]  Furthermore, in the same way of thinking, also for when q=1, ..., m-1, at least one CL6 is present when C#1.1 or C#1.2 is satisfied.

[0176] Therefore, in the parity check polynomial that satisfies zero of expression 37, when C#1.1 or C#1.2 holds true, at least one CL6 is generated.

[0177] The #qth parity check polynomial that satisfies zero of a TV-m-LDPC-CC having a coding rate of (n-1)/n, which will be described hereinafter, is provided below based on expression 30 (q=0, ..., m-1):
[Math. 38]



[0178] Here, in expression 38, it is assumed that there are three terms in X1(D), X2(D), ..., Xn-1(D) and P(D), respectively.

[0179] According to theorem 1, to suppress the occurrence of CL6, it is necessary to satisfy {a#q,p,1 mod m≠a#q,p,2 mod m}∩{a#q,p,1 mod m≠a#q,p,3 mod m}∩{a#q,p,2 mod m≠a#q,p,3 mod m} in Xq(D) of expression 38. Similarly, it is necessary to satisfy {b#q,1 mod m≠b#q,2 mod m} ∩ {b#q,1 mod m≠b#q,3 mod m}∩{b#q,2 mod m≠b#q,3 mod m} in P(D) of expression 38. ∩ represents an intersection.

[0180] Then, according to feature 1, the following condition is considered as an example of the condition to be a regular LDPC code.

[0181] C#2: for q, (a#q,p,1 mod m, a#q,p,2 mod m, a#q,p,3 mod m)=(Np,1, Np,2, Np,3)∩(b#q,1 mod m, b#q,2 mod m, b#q,3 mod m)=(M1, M2, M3) holds true. However, {a#q,p,1 mod m≠a#q,p,2 mod m}∩{a#q,p,1 mod m≠a#q,p,3 mod m}∩{a#q,p,2 mod m≠a#q,p,3 mod m} and {b#q,1 mod m≠b#q,2 mod m}∩{b#q,1 mod m≠b#q,3 mod m} ∩ {b#q,2 mod m≠b#q,3 mod m} is satisfied. Here, the symbol of q is a universal quantifier and q means all q.

[0182] The following discussion will treat a regular TV-m-LDPC-CC that satisfies the condition of C#2.

[Code Design of Regular TV-m-LDPC-CC]



[0183] Non-Patent Literature 9 shows a decoding error rate when a uniformly random regular LDPC code is subjected to maximum likelihood decoding in a binary-input output-symmetric channel and shows that Gallager's belief function (see Non-Patent Literature 10) can be achieved by a uniformly random regular LDPC code. However, when BP decoding is performed, it is unclear whether or not Gallager's belief function can be achieved by a uniformly random regular LDPC code.

[0184] As it happens, an LDPC-CC belongs to a convolutional code. Non-Patent Literature 11 and Non-Patent Literature 12 describe the belief function of the convolutional code and describe that the belief depends on a constraint length. Since the LDPC-CC is a convolutional code, it has a structure specific to a convolutional code in a parity check matrix, but when the time-varying period is increased, positions at which ones of the parity check matrix exist approximate to uniform randomness. However, since the LDPC-CC is a convolutional code, the parity check matrix has a structure specific to a convolutional code and the positions at which ones exist depend on the constraint length.

[0185] From these results, inference of inference #1 on a code design is provided in a regular TV-m-LDPC-CC that satisfies the condition of C#2.

Inference #1:



[0186] When BP decoding is used, if time-varying period m of a TV-m-LDPC-CC increases in a regular TV-m-LDPC-CC that satisfies the condition of C#2, uniform randomness is approximated for positions at which ones exist in the parity check matrix and a code of high error correction capability is obtained.

[0187] The method of realizing inference #1 will be discussed below.

[Feature of Regular TV-m-LDPC-CC]



[0188] A feature will be described that holds true when drawing a tree about expression 38 which is a #qth parity check polynomial that satisfies zero of a regular TV-m-LDPC-CC that satisfies the condition of C#2 having a coding rate of (n-1)/n, which will be treated in the present discussion.

Feature 2:



[0189] In a regular TV-m-LDPC-CC that satisfies the condition of C#2, when time-varying period m is a prime number, consider a case where C#3.1 holds true with attention focused on one of X1(D), ..., Xn-1(D).

[0190]  C#3.1: In parity check polynomial (38) that satisfies zero of a regular TV-m-LDPC-CC that satisfies the condition of C#2, a#q,p,i mod m≠a#q,p,j mod m holds true in Xp(D) for q (q=0, ..., m-1), where i≠j.

[0191] In parity check polynomial (38) that satisfies zero of a regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to Da#q,p,iXp(D) and Da#q,p,jXp(D) that satisfy C#3.1.

[0192] At this time, according to feature 1, there are check nodes corresponding to all #0 to #m-1 parity check polynomials for q in a tree whose starting point is a check node corresponding to a #qth parity check polynomial that satisfies zero of expression 38.

[0193] Similarly, when time-varying period m is a prime number in a regular TV-m-LDPC-CC that satisfies the condition of C#2, consider a case where C#3.2 holds true with attention focused on the term of P(D).

[0194] C#3.2: In parity check polynomial (38) that satisfies zero of a regular TV-m-LDPC-CC that satisfies the condition of C#2, b#q,i mod m≠b#q,j mod m holds true in P(D) for q, where i≠j.

[0195] In parity check polynomial (38) that satisfies zero of a regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to Db#q,iP(D) and Db#q,jP(D) that satisfy C#3.2.

[0196] At this time, according to feature 1, there are check nodes corresponding to all #0 to #m-1 parity check polynomials for q in a tree whose starting point is a check node corresponding to a #qth parity check polynomial that satisfies zero of expression 38.

[0197] Example: In parity check polynomial (38) that satisfies zero of a regular TV-m-LDPC-CC that satisfies the condition of C#2, it is assumed that time-varying period m=7 (prime number) and (b#q,1, b#q,2)=(2, 0) holds true for q. Therefore, C#3.2 is satisfied.

[0198] When a tree is drawn exclusively for variable nodes corresponding to Db#q,1P(D) and Db#q,2P(D), a tree whose starting point is a check node corresponding to a #0th parity check polynomial that satisfies zero of expression 38 is represented as shown in FIG. 17. As is clear from FIG. 17, time-varying period m=7 satisfies feature 2.

Feature 3:



[0199] In a regular TV-m-LDPC-CC that satisfies the condition of C#2, when time-varying period m is not a prime number, consider a case where C#4.1 holds true with attention focused on one of X1(D),...,Xn-1(D).

[0200] C#4.1: In parity check polynomial (38) that satisfies zero of a regular TV-m-LDPC-CC that satisfies the condition of C#2, when a#q,p,i mod m≥a#q,p,j mod m in Xp(D) for q, |a#q,p,i mod m-a#q,p,j mod m| is a divisor other than one of m, where i≠j.

[0201] In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to Da#q,p,iXp(D) and Da#q,p,jXp(D) that satisfy C#4.1. At this time, according to feature 1, in the tree whose starting point corresponds to the #q-th parity check polynomial that satisfies zero of expression 38, there is no check node corresponding to all #0 to #m-1parity check polynomials for q.

[0202] Similarly, in the regular TV-m-LDPC-CC that satisfies the condition of C#2, consider a case where C#4.2 holds true when time-varying period m is not a prime number with attention focused on the term of P(D).

[0203] C#4.2: In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, when b#q,i mod m>b#q,j mod m in P(D) for q, |b#q,i mod m-b#q,j mod m| is a divisor other than one of m, where i≠j.

[0204] In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to Db#q,iP(D) and Db#q,jP(D) that satisfy C#4.2. At this time, according to feature 1, in the tree whose starting point is a check node corresponds to the #qth parity check polynomial that satisfies zero of expression 38, there are not all check nodes corresponding to #0 to #m-1 parity check polynomials for q.

[0205] Example: In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, it is assumed that time-varying period m=6 (not a prime number) and (b#q,1, b#q,2)=(3, 0) holds true for q. Therefore, C#4.2 is satisfied.

[0206] When a tree is drawn exclusively for variable nodes Db#q,1P(D) and Db#q,2P(D), a tree whose starting point is a check node corresponding to #0th parity check polynomial that satisfies zero of expression 38 is represented as shown in FIG. 18. As is clear from FIG. 18, time-varying period m=6 satisfies feature 3.

[0207] Next, in the regular TV-m-LDPC-CC that satisfies the condition of C#2, a feature will be described which particularly relates to when time-varying period m is an even number.

Feature 4:



[0208] In the regular TV-m-LDPC-CC that satisfies the condition of C#2, when time-varying period m is an even number, consider a case where C#5.1 holds true with attention focused on one of X1(D), ..., Xn-1(D).

[0209] C#5.1: In parity check polynomial (82) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, when a#q,p,i mod m≥a#q,p,j mod m in Xp(D) for q, |a#q,p,i mod m-a#q,p,j mod m| is an even number, where i≠j.

[0210] In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to Da#q,p,iXp(D) and Da#q,p,jXp(D) that satisfy C#5.1. At this time, according to feature 1, when q is an odd number, there are only check nodes corresponding to odd-numbered parity check polynomials in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38. On the other hand, when q is an even number, there are only check nodes corresponding to even-numbered parity check polynomials in a tree whose starting point is a check node corresponding to the #q-th parity check polynomial that satisfies zero of expression 38.

[0211] Similarly, in the regular TV-m-LDPC-CC that satisfies the condition of C#2, when time-varying period m is an even number, consider a case where C#5.2 holds true with attention focused on the term of P(D).

[0212] C#5.2: In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, when b#q,i mod m≥b#q,j mod m in P(D) for q, |b#q,i mod m-b#q,j mod m| is an even number, where i≠j.

[0213] In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to Db#q,iP(D) and Db#q,jP(D) that satisfy C#5.2. At this time, according to feature 1, when q is an odd number, only check nodes corresponding to odd-numbered parity check polynomials are present in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38. On the other hand, when q is an even number, only check nodes corresponding to even-numbered parity check polynomials are present in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38.

[Design Method of Regular TV-m-LDPC-CC]



[0214] A design policy will be considered for providing high error correction capability in the regular TV-m-LDPC-CC that satisfies the condition of C#2. Here, a case of C#6.1, C#6.2, or the like will be considered.

[0215] C#6.1: In parity check polynomial (82) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to Da#q,p,iXp(D) and Da#q,p,jXp(D) (where i≠j). At this time, all check nodes corresponding to #0 to #m-1 parity check polynomials for q are not present in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38.

[0216] C#6.2: In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to Db#q,iP(D) and Db#q,jP(D) (where i≠j). At this time, all check nodes corresponding to #0 to #m-1 parity check polynomials for q are not present in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38.

[0217] In such cases as C#6.1 and C#6.2, since all check nodes corresponding to #0 to #m-1 parity check polynomials for q are not present, the effect in inference #1 when the time-varying period is increased is not obtained. Therefore, with the above description taken into consideration, the following design policy is given to provide high error correction capability.

[0218] [Design policy]: In the regular TV-m-LDPC-CC that satisfies the condition of C#2, a condition of C#7.1 is provided with attention focused on one of X1(D), ..., Xn-1(D).

[0219] C#7.1: A case will be considered where a tree is drawn exclusively for variable nodes corresponding to Da#q,p,iXp(D) and Da#q,p,jXp(D) in parity check polynomial (38) that satisfies zero of a regular TV-m-LDPC-CC that satisfies the condition of C#2 (where i≠j). At this time, check nodes corresponding to all #0 to #m-1 parity check polynomials are present in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38 for q.

[0220]  Similarly, in the regular TV-m-LDPC-CC that satisfies the condition of C#2, the condition of C#7.2 is provided with attention focused on the term of P(D).

[0221] C#7.2: In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to Db#q,iP(D) and Db#q,jP(D) (where i≠j). At this time, check nodes corresponding to all #0 to #m-1 parity check polynomials are present in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38 for q.

[0222] In the present design policy, it is assumed that C#7.1 holds true for (i,j) and also holds true for p, and C#7.2 holds true for (i,j).

[0223] Inference #1 is then satisfied.

[0224] Next, a theorem relating to the design policy will be described.

[0225] Theorem 2: Satisfying the design policy requires a#q,p,i mod m≠a#q,p,j mod m and b#q,i mod m≠b#q,j mod m to be satisfied, where i≠j.

[0226] Proof: When a tree is drawn exclusively for variable nodes corresponding to Da#q,p,iXp(D) and Da#q,p,jXp(D) in expression 38 of the parity check polynomial that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, if theorem 2 is satisfied, check nodes corresponding to all #0 to #m-1 parity check polynomials are present in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38. This holds true for all p.

[0227] Similarly, when a tree is drawn exclusively for variable nodes corresponding to Db#q,iP(D) and Db#q,jP(D) in expression 38 of the parity check polynomial that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, if theorem 2 is satisfied, check nodes corresponding to all #0 to #m-1 parity check polynomials are present in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38.

[0228] Therefore, theorem 2 is proven.

□ (end of proof)



[0229] Theorem 3: In the regular TV-m-LDPC-CC that satisfies the condition of C#2, when time-varying period m is an even number, there is no code that satisfies the design policy.

[0230]  Proof: In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, when p=1, if it is possible to prove that the design policy is not satisfied, this means that theorem 3 has been proven. Therefore, the proof is continued assuming p=1.

[0231] In the regular TV-m-LDPC-CC that satisfies the condition of C#2, (Np,1, Np,2, Np,3)=(o, o, o)∪(o, o, e)∪(o, e, e)∪(e, e, e) can represent all cases. Here, o represents an odd number and e represents an even number. Therefore, (Np,1, Np,2, Np,3)=(o, o, o)∪(o, o, e)∪(o, e, e)∪(e, e, e) shows that C#7.1 is not satisfied. U represents a union.

[0232] When (Np,1, Np,2, Np,3)=(o, o, o), C#5.1 is satisfied so that i, j=1, 2, 3 (i≠j) is satisfied in C#5.1 no matter what the value of the set of (i, j) may be.

[0233] When (Np,1, Np,2, Np,3)=(o, o, e), C#5.1 is satisfied when (i, j)=(1, 2) in C#5.1.

[0234] When (Np,1, Np,2, Np,3)=(o, e, e), C#5.1 is satisfied when (i, j)=(2, 3) in C#5.1.

[0235] When (Np,1, Np,2, Np,3)=(e, e, e), C#5.1 is satisfied so that i, j=1, 2, 3 (i≠j) is satisfied in C#5.1 no matter what the value of the set of (i, j) may be.

[0236] Therefore, when (Np,1, Np,2, Np,3)=(o, o, o)∪(o, o, e)∪(o, e, e)∪(e, e, e), there are always sets of (i, j) that satisfy C#5.1. Thus, theorem 3 has been proven according to feature 4.

□ (end of proof)



[0237] Therefore, to satisfy the design policy, time-varying period m must be an odd number. Furthermore, to satisfy the design policy, the following conditions are effective according to feature 2 and feature 3.

•Time-varying period m is a prime number.

•Time-varying period m is an odd number and the number of divisors of m is small.



[0238] Especially, when the condition that time-varying period m is an odd number and the number of divisors of m is small is taken into consideration, the following cases can be considered as examples of conditions under which codes of high error correction capability are likely to be achieved: (Note that the following cases are mere examples, and codes of high error correction capability may be achieved under other conditions.)
  1. (1) The time-varying period m is assumed to be α×β,
    where α and β are odd numbers other than one and are prime numbers.
  2. (2) The time-varying period m is assumed to be αn,
    where α is an odd number other than one and is a prime number, and n is an integer no smaller than two.
  3. (3) The time-varying period m is assumed to be α×β×γ,
    where α, β, and γ are odd numbers other than one and are prime numbers.


[0239] However, when z mod m (z is an integer no smaller than zero) is computed, there are m values that can be taken, and therefore the number of values taken when z mod m is computed increases as m increases. Therefore, when m is increased, it is easier to satisfy the above-described design policy. However, when time-varying period m is assumed to be an even number, this does not mean that a code having high error correction capability cannot be obtained.

[0240] The following describes tail-biting in an LDPC-CC. An LDPC-CC based on parity check polynomials described in Non-Patent Literature 13 is described first, as an example.

[0241] A time-varying LDPC-CC having a coding rate of R=(n-1)/n based on parity check polynomials is described below. At time j, the information bits X1, X2, ..., Xn-1 and the parity bit P are respectively represented as X1,j, X2,j, ..., Xn-1,j and Pj. Thus, vector uj at time j is expressed as uj=(X1,j, X2,j, ..., Xn-1,j, Pj). Also, the encoded sequence is expressed as u=(u0, u1, ...,uj, ...)T. Given a delay operator D, the polynomial of the information bits X1, X2, ..., Xn-1 is expressed as X1(D), X2(D), ..., Xn-1(D), and the polynomial of the parity bit P is expressed as P(D). Thus, a parity check polynomial satisfying zero is expressed by expression 39.
[Math. 39]



[0242] In expression 39, ap,q(p=1, 2, ..., n-1; q=1, 2, ..., rp) and bs(s=1, 2, ...,ε) are natural numbers. Also, for (y, z) where y, z=1, 2, ..., r, y≠z, ap,y≠ap,z holds. Also, for (y,z) where y, z=1, 2, ..., ε, y≠z, by≠bz holds.

[0243]  In order to create an LDPC-CC having a time-varying period of m and a coding rate of R=(n-1)/n, a parity check polynomial that satisfies zero based on expression 39 is prepared. A parity check polynomial that satisfies zero for the ith (i=0, 1, ..., m-1) is expressed as follows in expression 40.
[Math. 40]



[0244] In expression 40, the maximum degrees of D in AXδ,i(D) (δ=1, 2, ...,n-1) and Bi(D) are, respectively, ΓXδ,i and ΓP,i. The maximum values of ΓXδ,i and ΓP,i are Γi. The maximum value of Γi(i=0, 1, ..., m-1) is Γ. Taking the encoded sequence u into consideration and using Γ, vector hi corresponding to the ith parity check polynomial is expressed as follows in expression 41.
[Math. 41]



[0245] In expression 41, hi,v(v=0, 1, ..., Γ) is a 1×n vector expressed as [αi,v,X1, (αi,v,X2, ..., αi,v,Xn-1i,v]. This is because, for the parity check polynomial of expression 41, αi,v,XwDvXw(D) and βi,vDvP(D) (w=1, 2, ..., n-1, and αi,v,Xwi,v∈[0,1]). In such cases, the parity check polynomial that satisfies zero for expression 41 has terms D0X1(D), D0X2(D), ..., D0Xn-1(D) and D0P(D), thus satisfying expression 42.
[Math. 42]



[0246] Using expression 42, the check matrix of the LDPC-CC based on the parity check polynomial having a time-varying period of m and a coding rate of R=(n-1)/n is expressed as follows in expression 43.
[Math. 43]





[0247] In expression 43, A(k)=A(k+m) is satisfied for k. Here, A(k) corresponds to hi at the kth row of the parity check matrix.

[0248] Although expression 39 is handled, above, as a parity check polynomial serving as a base, no limitation to the format of expression 39 is intended. For example, instead of expression 39, a parity check polynomial satisfying zero for expression 44 may be used.
[Math. 44]



[0249] In expression 44, ap,q (p=1, 2, ..., n-1; q=1, 2, ..., rp) and bs (s=1, 2, ..., ε) are natural numbers. Also, for (y, z) where y, z=1, 2, ..., rp, y≠z, ap,y≠ap,z holds. Also, for (y,z) where y, z=1, 2, ..., ε, y≠z, by≠bz holds.

[0250] The following describes a tail-biting scheme for the present embodiment, using time-varying LDPC-CC based on the above-described parity check polynomial.

[Tail-Biting Scheme]



[0251] For the LDPC-CC based on the above-discussed parity check polynomials, the gth (g=0, 1, ..., q-1) that satisfies zero for a time-varying period of q is expressed below as a parity check polynomial (see expression 40) of expression 45.
[Math. 45]



[0252] Let a#g,p,1 and a#g,p,2 be natural numbers, and let a#g,p,1≠a#g,p,2 hold true. Furthermore, let b#g,1 and b#g,2 be natural numbers, and let b#g,1≠b#g,2 hold true (g=0, 1, 2, ..., q-1; p=1, 2, ..., n-1). For simplicity, the quantity of terms X1(D), X2(D), ... Xn-1(D) and P(D) is three.

[0253] Assuming a sub-matrix (vector) in a parity check matrix to be Hg, a gth sub-matrix can be represented as expression 46, shown below.
[Math. 46]



[0254] In expression 46, the n consecutive ones correspond to the terms X1(D), X2(D), Xn-1(D) and P(D) in each form of expression 45.

[0255] Here, parity check matrix H can be represented as shown in FIG. 19. As shown in FIG. 19, a configuration is employed in which a sub-matrix is shifted n columns to the right between an ith row and (i+1)th row in parity check matrix H (see FIG. 19). In addition, a sub-matrix is shifted n columns to the right between an (i+1)th row and ith row in parity check matrix H. Thus, the data at time k for information X1, X2, .. Xn-1 and parity P are respectively given as X1,k, X2,k, ..., Xn-1,k,, and Pk. When transmission vector u is given as u=(X1,0, X2,0, ..., Xn-1,0, P0, X1,1, X2,1, ..., Xn-1,1, P1, ..., X1,k, X2,k, ..., Xn-1,k, Pk, ...)T, Hu=0 holds true. (Here, the zero in Hu=0 indicates that vector Hu is a (column) vector all elements of which are zeroes.)

[0256] In Non-Patent Literature 14, a check matrix is described for when tail-biting is employed. The parity check matrix is given as follows.
[Math. 47]



[0257] In expression 47, H is the check matrix and HT is the syndrome former. Also, HTi(t) (i=0, 1, ..., Ms) is a c×(c-b) sub-matrix, and Ms is the memory size.

[0258]  FIG. 19 and expression 47 show that, for the LDPC-CC having a coding rate of (n-1)/n and a time-varying period of q that is based on the parity check polynomial, the parity check matrix H required for decoding that obtains greater error-correction capability strongly prefers the following conditions.

<Condition #1>



[0259] The number of rows in the parity check matrix is a multiple of q.
  • Accordingly, the number of columns in the parity check matrix is a multiple of n×q. Here, the (for example) log-likelihood ratio needed upon decoding is the log-likelihood ratio of the bit portion that is a multiple of n×q.


[0260] Here, the parity check polynomial that satisfies zero for the LDPC-CC having a coding rate of (n-1)/n and a time-varying period of q required by Condition #1 is not limited to that of expression 45, but may also be the time-varying LDPC-CC based on expression 39 or 44.

[0261] Incidentally, for the parity check polynomial, when there is only one parity term P(D), expression 47 is expressible as expression 48.
[Math. 48]



[0262] Such a time-varying period LDPC-CC is a type of feed-forward convolutional code. Thus, a coding scheme given by Non-Patent Literature 15 or Non-Patent Literature 16 can be applied as the coding scheme used when tail-biting is used. The procedure is as shown below.

<Procedure 1>



[0263] For example, the time-varying LDPC-CC defined by expression 48 has a term P(D) expressed as follows.
[Math. 49]



[0264] Then, expression 49 is represented as follows.
[Math. 50]

where ⊕ represents the exclusive OR operator.

[0265] Accordingly, at time i, when (i-1)%q=k (% represents the modulo operator), parity is calculated in expression 49 and expression 50 at time i when g=k. The registers are initialized to values of zero. That is, using expression 49, when (i-1)%q=k at time i (i=1, 2, ...), then in expression 49, the parity at time i is calculated for g=k. In expression 49, for terms X1[z], X2[z], ..., Xn-1[z] and P[z], any term for which z is less than one is taken as a zero and expression 49 is used for coding. Calculations proceed up to the final parity bit. The state of each register of the encoder at this time is stored.

<Procedure 2>



[0266] Coding is performed a second time from time i=1 from the state of the registers stored during Procedure 1 (that is, for terms Xi[z], X2[z], ..., Xn-1[z], and P[z] of expression 49, the values obtained using Procedure 1 are used where z is less than one) and parity is calculated.

[0267] The parity bit and information bits obtained at this time constitute an encoded sequence when tail-biting is performed.

[0268] However, upon comparison of feed-forward LDPC-CCs and feedback LDPC-CCs under conditions of having the same coding rate and substantially similar constraint lengths, the feedback LDPC-CCs have a stronger tendency to exhibit strong error-correction capability but present difficulties in calculating the encoded sequence (i.e., calculating the parity). The following presents a new tail-biting scheme as a solution to this problem, enabling simple encoded sequence (parity) calculation.

[0269] First, a parity check matrix for performing tail-biting with an LDPC-CC based on a parity check polynomial is described.

[0270] For example, for the LDPC-CC based on the parity check polynomial having a time-varying period of q and a coding rate of (n-1)/n as defined by expression 45, the information terms X1, X2, ..., Xn-1 and the parity term P are represented at time i as X1,i, X2,i, ..., Xn-1,i, and Pi. Then, in order to satisfy Condition #1, tail-biting is performed such that i=1, 2, 3, ..., q, ..., q×N-q+1, q×N-q+2, q×N-q+3, ..., q×N.

[0271]  Here, N is a natural number, the transmission sequence u is u=(X1,1, X2,1, ..., Xn-1,1, P0, X1,2, X2,2, ..., Xn-1,2, P2, ..., X1,k, X2,k, ..., Xn-1,k, Pk, ..., X1,q×N, X2,q×N, ..., Xn-1,q×N, Pq×N)T, and Hu=0 all hold true. (Here, the zero in Hu=0 indicates that vector Hu is a (column) vector all elements of which are zeroes.)

[0272] The configuration of the parity check matrix is described using Figs. 20 and 21.

[0273] Assuming a sub-matrix (vector) in expression 45 to be Hg, a gth sub-matrix can be represented as expression 51, shown below.
[Math. 51]



[0274] In expression 51, the n consecutive ones correspond to the terms X1(D), X2(D), Xn-1(D), and P(D) in each form of expression 45.

[0275] Among the parity check matrix corresponding to the transmission sequence u defined above, the parity check matrix in the vicinity of time q×N are represented by FIG. 20. As shown in FIG. 20, a configuration is employed in which a sub-matrix is shifted n columns to the right between an ith row and (i+1)th row in parity check matrix H (see FIG. 20).

[0276] Also, in FIG. 20, the q×Nth (i.e., the last) row of the parity check matrix has reference sign 2001, and corresponds to the (q-1)th parity check polynomial that satisfies zero in order to satisfy Condition #1. The q×N-1th row of the parity check matrix has reference sign 2002, and corresponds to the (q-2)th parity check polynomial that satisfies zero in order to satisfy Condition #1. Reference sign 2003 represents a column group corresponding to time q×N. Column group 2003 is arranged in the order X1,q×N, X2,q×N, ... Xn-1,q×N, Pq×N. Reference sign 2004 represents a column group corresponding to time q×N-1. Column group 2004 is arranged in the order X1,q×N-1, X2,q×N-1, ... Xn-1,q×N-1, Pq×N-1.

[0277] Next, by reordering the transmission sequence, the parity check matrix corresponding to u=(..., X1,q×N-1, X2,q×N-1, ..., Xn-1,q×N-1, Pq×N-1, X1,q×N, X2,q×N, ..., Xn-1,q×N, Pq×N, X1,0, X2,1, ..., Xn-1,1, P1, X1,2, X2,2, ..., Xn-1,2, P2, ...)T in the vicinity of times q×N-1, q×N, 1, 2 is the parity check matrix shown in FIG. 21. Here, the parity check matrix portion shown in FIG. 21 is a characteristic portion when tail-biting is performed. The configuration thereof is identical to the configuration shown in expression 47. As shown in FIG. 21, a configuration is employed in which a sub-matrix is shifted n columns to the right between an ith row and (i+1)th row in parity check matrix H (see FIG. 21).

[0278]  Also, in FIG. 21, when expressed as a parity check matrix like that of FIG. 20, reference sign 2105 corresponds to the (q×N×n)th column and, when similarly expressed as a parity check matrix like that of FIG. 20, reference sign 2106 corresponds to the first column.

[0279] Reference sign 2107 represents a column group corresponding to time q×N-1. Column group 2107 is arranged in the order X1,q×N-1, X2,q×N-1, ..., Xn-1,q×N-1, Pq×N-1. Reference sign 2108 represents a column group corresponding to time q×N. Column group 2108 is arranged in the order X1,q×N, X2,q×N, ... Xn-1,q×N, PqxN. Reference sign 2109 represents a column group corresponding to time 1. Column group 2109 is arranged in the order X1,1, X2,1, ..., Xn-1,1, P1. Reference sign 2110 represents a column group corresponding to time 2. Column group 2110 is arranged in the order X1,2, X2,2, ..., Xn-1,2, P2.

[0280] When expressed as a parity check matrix like that of FIG. 20, reference sign 2111 corresponds to the (q×N)th row, and when similarly expressed as a parity check matrix like that of FIG. 20, reference sign 2112 corresponds to the first row.

[0281] In FIG. 21, the characteristic portion of the parity check matrix on which tail-biting is performed is the portion left of reference sign 2113 and below reference sign 2114 (See also expression 47).

[0282] When expressed as a parity check matrix like that of FIG. 20, and when Condition #1 is satisfied, the rows begin with a row corresponding to a parity check polynomial that satisfies a zeroth zero, and the rows end with a parity check polynomial that satisfies a (q-1)th zero. This point is critical for obtaining better error-correction capability. In practice, the time-varying LDPC-CC is designed such that the code thereof produces a small number of cycles of length each being of a short length on a Tanner graph. As the description of FIG. 21 makes clear, in order to ensure a small number of cycles of length each being of a short length on a Tanner graph when tail-biting is performed, maintaining conditions like those of FIG. 21, i.e., maintaining Condition #1, is critical.

[0283] However, in a communication system, when tail-biting is performed, circumstances occasionally arise in which some shenanigans are required in order to satisfy Condition #1 for the block length (or information length) requested by the system. This point is explained by way of example.

[0284] FIG. 22 is an overall diagram of the communication system. The communication system is configured to include a transmitting device 2200 and a receiving device 2210.

[0285] The transmitting device 2200 is in turn configured to include an encoder 2201 and a modulation section 2202. The encoder 2201 receives information as input, performs encoding, and generates and outputs a transmission sequence. Then, the modulation section 2202 receives the transmission sequence as input, performs predetermined processing such as mapping, quadrature modulation, frequency conversion, and amplification, and outputs a transmission signal. The transmission signal arrives at the receiving device 2210 via a communication medium (radio, power line, light or the like).

[0286] The receiving device 2210 is configured to include a receiving section 2211, a log-likelihood ratio generation section 2212, and a decoder 2213. The receiving section 2211 receives a received signal as input, performs processing such as amplification, frequency conversion, quadrature demodulation, channel estimation, and demapping, and outputs a baseband signal and a channel estimation signal. The log-likelihood ratio generation section 2212 receives the baseband signal and the channel estimation signal as input, generates a log-likelihood ratio in bit units, and outputs a log-likelihood ratio signal. The decoder 2213 receives the log-likelihood ratio signal as input, performs iterative decoding using, specifically, BP (Belief Propagation) decoding (see Non-Patent Literature 4, Non-Patent Literature 6, Non-Patent Literature 7, and Non-Patent Literature 8), and outputs an estimated transmission sequence or (and) an estimated information sequence.

[0287] For example, consider an LDPC-CC having a coding rate of 1/2 and a time-varying period of 12 as an example. Assuming that tail-biting is performed at this time, the set information length (coding length) is designated 16384. The information bits are designated X1,1, X1,2, X1,3, ..., X1,16384. If parity bits are determined without any shenanigans, P1, P2, P3, ..., P16384 are determined. However, despite a parity check matrix being created for transmission sequence u=(X1,1, P1, X1,2, P2, ..., X1,16384, P16384), Condition #1 is not satisfied. Therefore, X1,16385, X1,16386, X1,16387, and X1,16388 may be added to the transmission sequence so as to determine P16385, P16386, P16387, and P16388. Here, the encoder (transmitting device) is set such that, for example, X1,16385=0, X1,16386=0, X1,16387=0, and X1,16388=0, then performs decoding to obtain P16385, P16386, P16387, and P16388. However, for the encoder (transmitting device) and the decoder (receiving device), when mutually agreed-upon settings are in place such that X1,16385=0, X1,16386=0, X1,16387=0, and X1,16388=0, there is no need to transmit X1,16385, X1,16386, X1,16387, and X1,16388.

[0288] Accordingly, the encoder takes the information sequence X=(X1,1, X1,2, X1,3, ..., X1,16384, X1,16385, X1,16386, X1,16387, X1,16388)=(X1,1, X1,2, X1,3, ..., X1,16384, 0, 0, 0, 0) as input, and obtains the sequence (X1,1, P1, X1,2, P2, ..., X1,16384, P16384, X1,16385, P16385, X1,16386, P16386, X1,16387, P16387, X1,16388, P16388)=(X1,1, P1, X1,2, P2, ..., X1,16384, P16384, 0, P16385, 0, P16386, 0, P16387, 0, P16388) therefrom. Then, the encoder (transmitting device) and the decoder (receiving device) delete the known zeroes, such that the transmitting device transmits the transmission sequence as (X1,1, P1, X1,2, P2, ..., X1,16384, P16384, P16385, P16386, P16387, P16388).

[0289] The receiving device 2210 obtains, for example, the log-likelihood ratios for each transmission sequence of LLR(X1,1), LLR(P1), LLR(X1,2), LLR(P2), ..., LLR(X1,16384), LLR(P16384), LLR(P16385), LLR(P16386), LLR(P16387), LLR(P16388).

[0290] Then, the log-likelihood ratios LLR(X1,16385)=LLR(0), LLR(X1,16386)=LLR(0), LLR(X1,16387)=LLR(0), LLR(X1,16388)=LLR(0) of the zero-value termsX1,16385, X1,16386, X1,16387, and X1,16388 not transmitted by the transmitting device 2200 are generated, obtaining LLR(X1,1), LLR(P1), LLR(X1,2), LLR(P2), ..., LLR(X1,16384), LLR(P16384), LLR(X1,16385)=LLR(0), LLR(P16385), LLR(X1,16386)=LLR(0), LLR(P16386), LLR(X1,16387)=LLR(0), LLR(P16387), LLR(X1,16388)=LLR(0), and LLR(P16388). As such, the estimated transmission sequence and the estimated information sequence are obtainable by using the 16388×32776 parity check matrix of the LDPC-CC having a time-varying period of 12 and a coding rate of 1/2 and performing decoding using belief propagation, such as BP decoding described in Non-Patent Literature 4, Non-Patent Literature 6, Non-Patent Literature 7, and Non-Patent Literature 8, min-sum decoding that approximates BP decoding, offset BP decoding, Normalized BP decoding, or shuffled BP decoding.

[0291] As the example makes clear, for an LDPC-CC having a time-varying period of q and a coding rate of (n-1)/n and for which tail-biting is performed, when the receiving device performs decoding, the decoding proceeds with a parity check matrix that satisfies Condition #1. Accordingly, the decoder holds a parity check matrix in which (rows)×(columns)=(q×M)×(q×n×M) (where M is a natural number).

[0292] The corresponding encoder uses a number of information bits needed for coding that corresponds to q×(n-1)×M. Accordingly, q×M bits of parity are computed. In contrast, when the number of information bits input to the encoder is less than q×(n-1)×M, the encoder inserts known bits (for example, zeroes (or ones)) into inter-device transmissions (between the encoder and the decoder) such that the total number of information bits is q×(n-1)×M. Thus, q×M bits of parity are computed. Here, the transmitting device transmits the parity bits computed from the information bits with the inserted known bits deleted. (However, although the known bits are normally transmitted with q×(n-1)×M bits of information and q×M bits of parity, the presence of known bits may lead to a decrease in transmission speeds).

[0293] The following describes a periodic time-varying LDPC-CC that is based on a parity check polynomial and that uses improved tail-biting of coding rate (n-1)/n (where n is an integer no smaller than two) described in Patent Literature 2.

[Periodic Time-varying LDPC-CC based on Parity Check Polynomial and Using Improved Tail-biting of Coding Rate (n-1)/n (where n is an integer no smaller than two)]



[0294] First, explanation is provided of a problem present in a conventional LDPC convolutional code using a tail-biting scheme.

[0295] Here, explanation is provided of a time-varying LDPC-CC having a coding rate of R=(n-1)/n based on a parity check polynomial. Information bits X1, X2, ..., Xn-1 and parity bit P at time j are respectively expressed as X1,j, X2,j, ..., Xn-1,j and Pj. Further, a vector uj at time j is expressed as uj=(X1,j, X2,j, ..., Xn-1,j, Pj). Also, an encoded sequence is expressed as u=(u0, u1, ..., uj, ...)T. Given a delay operator D, a polynomial expression of the information bits X1, X2, ..., Xn-1 is X1(D), X2(D), ..., Xn-1(D), and a polynomial expression of the parity bit P is P(D). Here, a parity check polynomial that satisfies zero, according to expression 52, is considered.
[Math. 52]



[0296] In expression 52, ap,q (p=1, 2, ..., n-1; q=1, 2, ..., rp) and bs (s=1, 2, ..., ε) are natural numbers. Also, for (y, z) where y, z=1, 2, ..., rp and y#z, ap,y≠ap,z holds true. Also, for (y, z) where y, z=1, 2, ..., ε and y#z, by≠bz holds true. In order to create an LDPC-CC having a time-varying period of m, m parity check polynomials that satisfy zero are prepared. Here, the m parity check polynomials that satisfy zero are referred to as a parity check polynomial #0, a parity check polynomial #1, a parity check polynomial #2, ..., a parity check polynomial #(m-2), and a parity check polynomial #(m-1). Based on parity check polynomials that satisfy zero, according to expression 52, the number of terms of Xp(D) (p=1, 2, ..., n-1) is equal in the parity check polynomial #0, the parity check polynomial #1, the parity check polynomial #2, ..., the parity check polynomial #(m-2), and the parity check polynomial #(m-1), and the number of terms of P(D) is equal in the parity check polynomial #0, the parity check polynomial #1, the parity check polynomial #2, ..., the parity check polynomial #(m-2), and the parity check polynomial #(m-1). However, expression 52 merely provides one example of a parity check polynomial that satisfies zero, and the number of terms of Xp(D) (p=1, 2, ..., n-1) need not be equal in the parity check polynomial #0, the parity check polynomial #1, the parity check polynomial #2, ..., the parity check polynomial #(m-2), and the parity check polynomial #(m-1), and the number of terms of P(D) need not be equal in the parity check polynomial #0, the parity check polynomial #1, the parity check polynomial #2, ..., the parity check polynomial #(m-2), and the parity check polynomial #(m-1).

[0297] In order to create an LDPC-CC having a coding rate of R=(n-1)/n and a time-varying period of m, parity check polynomials that satisfy zero are prepared. An ith parity check polynomial (i=0, 1, ..., m-1) that satisfies zero, according to expression 52, is expressed as shown in expression 53.
[Math. 53]





[0298] In expression 53, the maximum degrees of D in AXδ,i(D) (δ=1, 2, ..., n-1) and Bi(D) are respectively expressed as ΓXδ,i and ΓP,i. Further, the maximum values of ΓXδ,i and ΓP,i are Γi. Also, the maximum value of Γi (i=0, 1, ..., m-1) is Γ. When taking the encoded sequence u into consideration and when using Γ, a vector hi corresponding to the ith parity check polynomial is expressed as shown in expression 54.
[Math. 54]



[0299] In expression 54, hi,v (v=0, 1, ..., Γ) is a vector having one row and n columns and is expressed as [αi,v,X1, αi,v,X2, ..., αi,v,Xn-1, βi,v]. This is because a parity check polynomial, according to expression 53, has αi,v,XwDvXw(D) and βi,vDvP(D) (w=1, 2, ..., n-1, and αi,v,Xwi,v∈[0,1]). In such a case, a parity check polynomial that satisfies zero, according to expression 53, has terms D0X1(D), D0X2(D), ..., D0Xn-1(D) and D0P(D), thus satisfying expression 55.
[Math. 55]



[0300] When using expression 55, a parity check matrix for an LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m is expressed as shown in expression 56.
[Math. 56]



[0301] In expression 56, A(k)=A(k + m) is satisfied for k. Here, A(k) corresponds to hi of a kth row of the parity check matrix.

[0302] Although explanation is provided above while referring to expression 52 as a parity check polynomial serving as a basis, no limitation to the format of expression 52 is intended. For example, instead of a parity check polynomial according to expression 52, a parity check polynomial that satisfies zero, according to expression 57, may be used.
[Math. 57]



[0303] In expression 57, ap,q (p=1, 2, ..., n-1; q=1, 2, ..., rp) and bs(s=1, 2, ..., ε) are natural numbers. Also, for (y, z) where y, z=1, 2, ..., rp and y≠z, ap,y≠ap,z holds true. Also, for (y, z) where y, z=1, 2, ..., ε and y≠z, by≠bz holds true.

[0304] Here, an ith parity check polynomial (i=0, 1, ..., m-1) that satisfies zero for an LDPC-CC having a coding rate of R=(n-1)/n and a time-varying period of m is expressed as shown below.
[Math. 58]



[0305] Here, bs,i (s=1, 2, ...,) is a natural number, and for (y, z) where y, z=1, 2, ..., ε and y≠z, by,i≠bz,i holds true. Also, ε is a natural number. Accordingly, there are two or more terms of P(D) in an ith parity check polynomial (i=0, 1, ..., m-1) that satisfies zero, which serves as a parity check polynomial that satisfies zero for an LDPC-CC having a coding rate of R=(n-1)/n and a time-varying period of m.

[0306] In the following, a case is considered where tail-biting is performed when there are two or more terms of P(D) in an ith parity check polynomial (i=0, 1, ..., m-1) that satisfies zero, which serves as a parity check polynomial that satisfies zero for an LDPC-CC having a coding rate of R=(n-1)/n and a time-varying period of m. In such a case, an encoder obtains a parity P from information bits X1, X2, ..., Xn-1 by performing encoding.

[0307] Here, when assuming a transmission vector u to be u=(X1,1, X2,1, ..., Xn-1,1, P1, X1,2, X2,2, ..., Xn-1,2, P2, ..., X1,k, X2,k, ..., Xn-1,k, Pk, ...)T and assuming a parity check matrix for an LDPC-CC having a coding rate of R=(n-1)/n and a time-varying period of m using the tail-biting scheme to be H, Hu=0 holds true. (here, the zero in Hu=0 indicates that all elements of the vector are zeros.) Accordingly, parities P1, P2, ..., Pk, ..., can be obtained by solving simultaneous equations for Hu=0. However, one problem is that a great amount of computation (i.e., a great circuit scale) is required for obtaining the parities since there are two or more terms of P(D).

[0308] Taking this into consideration, there is a tail-biting scheme using a feed-forward LDPC-CC having a time-varying period of m in order to reduce the amount of computation (i.e., circuit scale) required for obtaining parities. However, as is commonly known, the use of a feed-forward LDPC-CC is problematic in that a feed-forward LDPC-CC has relatively low error correction capability (when comparing a feed-forward LDPC-CC and a feedback LDPC-CC having substantially similar constraint lengths, it is more likely that the feedback LDPC-CC has higher error correction capability than the feed-forward LDPC-CC).

[0309] In view of the two problems presented above, Patent Literature 2 describes an LDPC-CC using an improved tail-biting scheme that achieves high error correction capability and a reduced amount of computation performed by an encoder (i.e., a reduced circuit scale of an encoder).

[0310] Explanation is provided in the following of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme that is described in Patent Literature 2. Note that in the following, n is assumed to be a natural number no smaller than two.

[0311] As a basis (i.e., a basic structure) of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme that is described in Patent Literature 2, an LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m is used.

[0312] An ith parity check polynomial (i=0, 1, ..., m-1) that satisfies zero for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC described in Patent Literature 2, is expressed as shown in expression 59.
[Math. 59]



[0313] Here, k=1, 2, ..., n-2, n-1 (k is an integer no smaller than one and less than or equal to n-1), i=1, 2, ..., m-1 (i is an integer no smaller than zero and less than or equal to m-1), and AXk,i(D)≠0 holds true for all conforming k and i. Also, b1,i is a natural number.

[0314] Accordingly, there are two terms P(D) in the ith parity check polynomial (i=0, 1, ..., m-1) that satisfies zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC described in Patent Literature 2. This is one important requirement for enabling finding parities sequentially and reducing computation amount (i.e., reducing circuit scale).

[0315] Note that the following function is defined for a polynomial part of a parity check polynomial that satisfies zero, according to expression 59.
[Math. 60]



[0316] Here, the two methods presented below realize a time-varying period of m.

Method 1:



[0317] [Math. 61]



[0318] In the above expression, v is an integer no smaller than zero and less than or equal to m-1, w is an integer no smaller than zero and less than or equal to m-1, v≠w, and Fv(D)≠Fw(D) holds true for all conforming v and w.

Method 2:



[0319] [Math. 62]



[0320] In the above expression, v is an integer no smaller than zero and less than or equal to m-1, w is an integer no smaller than zero and less than or equal to m-1, v≠w, and values of v and w that satisfy expression 62 exist. In addition, expression 63 also holds true.
[Math. 63]



[0321] In the above expression, v is an integer no smaller than zero and less than or equal to m-1, w is an integer no smaller than zero and less than or equal to m-1, v≠w, values of v and w that satisfy expression 63 exist. However, a time-varying period is m is realized.

[0322] Next, a relationship is described between a time-varying period m of a parity check polynomial that satisfies zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis (i.e., the basic structure) of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme that is described in Patent Literature 2, and a block size of the proposed LDPC-CC having a coding rate of R=(n-1)/n using the tail-biting scheme.

[0323] Concerning this point, the following conditions are important when performing tail-biting on the LDPC-CC based on a parity check polynomial (a parity check polynomial that satisfies zero as defined in expression 59) having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis (i.e., the basic structure) of the LDPC-CC described in Patent Literature 2, in order to achieve higher error correction capability.

<Condition #A1>



[0324] •The number of rows in a parity check matrix is a multiple of m.

•Thus, the number of columns in the parity check matrix is a multiple of n×m. According to this condition, (for example) a log-likelihood ratio that is necessary when performing decoding is a log-likelihood ratio of the number of columns in the parity check matrix.



[0325] However, a parity check polynomial that satisfies zero for the LDPC-CC having a time-varying period of m and a coding rate of (n-1)/n, which serves as the basic structure of the proposed LCPC-CC, and requires Condition #A1 is not limited to expression 59.

[0326] Further, the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 also satisfies Condition #A1. (Note that detailed explanation of the difference between the proposed LDPC-CC having a coding rate of R=(n-1)/n using the tail-biting scheme and the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis (i.e., the basic structure) of the LDPC-CC described in Patent Literature 2, is provided in the following.) Thus, when assuming that a parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 is Hpro, the number of columns of Hpro can be expressed as n×m×z (where z is a natural number). Accordingly, a transmission sequence (encoded sequence (codeword)) composed of an sth block of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be expressed as vs=(Xs,1,1, Xs,2,1, ..., Xs,n-1,1, Ppro,s,1, Xs,1,2, Xs,2,2, ..., Xs,n-1,2, Ppro,s,2, ..., Xs,1,k, Xs,2,k, ..., Xs,n-1,k, Ppro,s,k, Xs,1,m×z, Xs,2,m×z, ..., Xs,n-1,m×z, Ppro,s,m×z)T (where k=1, 2, ..., m×z-1), and Hprovs=0 holds true (here, the zero in Hprovs=0 indicates that all elements of the vector are zeros). Here, Xs,j,k represents an information bit Xj (j is an integer no smaller than one and less than or equal to n-1), and Ppro,s,k represents a bit of parity P. Further, the number of rows of Hpro, which is the parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, is m×z.

[0327] Next, explanation is provided of requirements that enable finding parities sequentially in the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2.

[0328] When drawing a tree as in each of FIGs. 5, 6, 8, 17, and 18, which is composed of only terms corresponding to parities of parity check polynomials that satisfy zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis (i.e., the basic structure) of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, it is required that check nodes corresponding to all parity check polynomials from the zeroth to the (m-1)th parity check polynomials, according to expression 59, appear in such a tree, as in each of FIGs. 6, 8, and 17. As such, the following conditions are considered as being effective.

<Condition #A2-1>



[0329] •In a parity check polynomial that satisfies zero, according to expression 59, i is an integer greater than equal to zero and less than or equal to m-1, j is an integer greater than equal to zero and less than or equal to m-1, i≠j, and b1,i%m=b1,j%m=β (where β is a fixed value that is a natural number) holds true for all conforming i and j.

<Condition #A2-2>



[0330] •When expressing a set of divisors of m other than one as R, β is not to belong to R.

[0331] In the present embodiment (in fact, commonly applying to the entirety of the present disclosure), % means a modulo, and for example, α%q represents a remainder after dividing α by q (where α is an integer no smaller than zero, and q is a natural number).

[0332] Note that, in addition to the above-described condition that, when expressing a set of divisors of m other than one as R, β is not to belong to R, it is desirable that the new condition below be satisfied.

<Condition #A2-3>



[0333] 
  • β belongs to a set of integers no smaller than one and less than or equal to m-1, and β also satisfies the following condition.


[0334] When expressing a set of values w obtained by extracting all values w satisfying β/w=g (where g is a natural number) as S, an intersection R∩s produces an empty set. The set R has been defined in Condition #A2-2.

[0335] Condition #A2-3 is also expressible as Condition #A2-3'.

<Condition #A2-3'>



[0336] 
  • β belongs to a set of integers no smaller than one and less than or equal to m-1, and β also satisfies the following condition.


[0337] When expressing a set of divisors of β as S, an intersection R∩S produces an empty set.

[0338] Condition #A2-3 and Condition #A2-3' are also expressible as Condition #A2-3".

<Condition #A2-3">



[0339] 
  • β belongs to a set of integers no smaller than one and less than or equal to m-1, and β also satisfies the following condition.


[0340] The greatest common divisor of β and m is one.

[0341] A supplementary explanation of the above is provided. According to Condition #A2-1, β is an integer no smaller than one and less than or equal to m-1. Also, when β satisfies both Condition #A2-2 and Condition #A2-3, β is not a divisor of m other than one, and β is not a value expressible as an integral multiple of a divisor of m other than one.

[0342] In the following, explanation is provided while referring to an example. Assume a time-varying period of m=6. Then, according to Condition #A2-1, β={1, 2, 3, 4, 5} since β is a natural number.

[0343] Further, according to Condition #A2-2, when expressing a set of divisors of m other than one as R, β is not to belong to R. As such, R={2, 3, 6} (since, among the divisors of six, one is excluded from the set R). As such, when β satisfies both Condition #A2-1 and Condition #A2-2, β={1, 4, 5}.

[0344] Next, Condition #A2-3 is considered (similar as when considering Condition #A2-3' or Condition #A2-3"). First, since β belongs to a set of integers no smaller than one and less than or equal to m-1, β={1, 2, 3, 4, 5}.

[0345] Further, when expressing a set of values w obtained by extracting all values w that satisfy β/w=g (where g is a natural number) as S, the intersection R∩S produces an empty set. Here, as explained above, the set R={2, 3, 6}.

[0346] When β=1, the set S={1}. As such, the intersection R∩S produces an empty set, and Condition #A2-3 is satisfied.

[0347] When β=2, the set S={1, 2}. As such, R∩S={2}, and Condition #A2-3 is not satisfied.

[0348] When β=3, the set S={1, 3}. As such, R∩S={3}, and Condition #A2-3 is not satisfied.

[0349] When β=4, the set S={1, 2, 4}. As such, R∩S={2}, and Condition #A2-3 is not satisfied.

[0350] When β=5, the set S={1, 5}. As such, the intersection R∩S produces an empty set, and Condition #A2-3 is satisfied.

[0351] As such, β satisfies both Condition #A2-1 and Condition #A2-3 when β={1, 5}.

[0352] In the following, explanation is provided while referring to another example. Assume a time-varying period of m=7. Then, since β is a natural number according to Condition #A2-1, β={1, 2, 3, 4, 5, 6}.

[0353] Further, according to Condition #A2-2, when expressing a set of divisors of m other than one as R, β is not to belong to R. Here, R={7} (since, among the divisors of seven, one is excluded from the set R). As such, when β satisfies both Condition #A2-1 and Condition #A2-2, β={1, 2, 3, 4, 5, 6}.

[0354] Next, Condition #A2-3 is considered. First, since β is an integer no smaller than one and less than or equal to m-1, β={1, 2, 3, 4, 5, 6}.

[0355] Next, when expressing a set of values w obtained by extracting all values w that satisfy β/w=g (where g is a natural number) as S, the intersection R∩S produces an empty set. Here, as explained above, the set R={7}.

[0356] When β=1, the set S={1}. As such, the intersection R∩S produces an empty set, and Condition #A2-3 is satisfied.

[0357] When β=2, the set S={1, 2}. As such, the intersection R∩S produces an empty set, and Condition #A2-3 is satisfied.

[0358] When β=3, the set S={1, 3}. As such, the intersection R∩S produces an empty set, and Condition #A2-3 is satisfied.

[0359] When β=4, the set S={1, 2, 4}. As such, the intersection R∩S produces an empty set, and Condition #A2-3 is satisfied.

[0360] When β=5, the set S={1, 5}. As such, the intersection R∩S produces an empty set, and Condition #A2-3 is satisfied.

[0361] When β=6, the set S={1, 2, 3, 6}. As such, the intersection R∩S produces an empty set, and Condition #A2-3 is satisfied.

[0362] As such, β satisfies both Condition #A2-1 and Condition #A2-3 when β={1, 2, 3, 4, 5, 6}.

[0363] In addition, as described in Non-Patent Literature 2, the possibility of high error correction capability being achieved is high if there is randomness in the positions at which ones are present in a parity check matrix. So as to make this possible, it is desirable that the following conditions be satisfied.

<Condition #A2-4>



[0364] 
  • In a parity check polynomial that satisfies zero, according to expression 59, i is an integer greater than equal to zero and no greater than m-1, j is an integer greater than equal to zero and no greater than m-1, i#j, b1,i%m=b1,j%m=β (where β is a fixed value that is a natural number) holds true for all conforming i and j.


[0365] Also, v is an integer no smaller than zero and less than or equal to m-1, w is an integer no smaller than zero and less than or equal to m-1, v≠w, and values of v and w that satisfy b1,v≠b1,w exist.

[0366] However, note that even when Condition #A2-4 is not satisfied, high error correction capability may be achieved. In addition, the following conditions can be considered so as to increase the randomness as described above.

<Condition #A2-5>



[0367] 
  • In a parity check polynomial that satisfies zero, according to expression 59, i is an integer greater than equal to zero and no greater than m-1, j is an integer greater than equal to zero and no greater than m-1, i≠j, and b1,i%m=b1,j%m=β (where β is a fixed value that is a natural number) holds true for all conforming i and j.


[0368] Also, v is an integer no smaller than zero and less than or equal to m-1, w is an integer no smaller than zero and less than or equal to m-1, v≠w, and b1,v≠b1,w holds true for all conforming v and w.

[0369] However, note that even when Condition #A2-5 is not satisfied, high error correction capability may be achieved.

[0370] Further, when taking into consideration that the proposed code is a convolutional code, the possibility is high of higher error correction capability being achieved for relatively long constraint lengths. Considering this point, it is desirable that the following condition be satisfied.

<Condition #A2-6>



[0371] 
  • The condition is not satisfied that, in a parity check polynomial that satisfies zero, according to expression 59, i is an integer greater than equal to zero and no greater than m-1, and b1,i=1 holds true for all conforming i.


[0372] However, note that even when Condition #A2-6 is not satisfied, high error correction capability may be achieved.

[0373] In the following, explanation is provided of the description above that, as the basis (i.e., the basic structure) of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, a parity check polynomial that satisfies zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m is used.

[0374] Description regarding tail-biting schemes has been provided above.

[0375] First, a parity check matrix is considered for a periodic time-varying LDPC-CC formed by using only a parity check polynomial that satisfies zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m.

[0376] FIG. 23 illustrates a configuration of a parity check matrix H for the periodic time-varying LDPC-CC using tail-biting formed by performing tail-biting by using only a parity check polynomial that satisfies zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m. Since Condition #A1 is satisfied in FIG. 23, the number of rows of the parity check matrix H is m×z and the number of columns of the parity check matrix H is n×m×z.

[0377] The first row of the parity check matrix H in FIG. 23 can be obtained by converting a zeroth parity check polynomial among the zeroth to (m-1)th parity check polynomials that satisfy zero, according to expression 59 (i.e., can be obtained by generating a vector having one row and n×m×z columns from the zeroth parity check polynomial). As such, the first row of the parity check matrix H in FIG. 23 is indicated as a "row corresponding to zeroth parity check polynomial".

[0378] The second row of the parity check matrix H in FIG. 23 can be obtained by converting the first parity check polynomial among the zeroth to (m-1)th parity check polynomials that satisfy zero, according to expression 59 (i.e., can be obtained by generating a vector having one row and n×m×z columns from the first parity check polynomial). As such, the second row of the parity check matrix H in FIG. 23 is indicated as a "row corresponding to first parity check polynomial".

[0379] The (m-1)th row of the parity check matrix H in FIG. 23 can be obtained by converting the (m-2)th parity check polynomial among the zeroth to (m-1)th parity check polynomials that satisfy zero, according to expression 59 (i.e., can be obtained by generating a vector having one row and n×m×z columns from the (m-2)th parity check polynomial). As such, the (m-1)th row of the parity check matrix H in FIG. 23 is indicated as a "row corresponding to (m-2)th parity check polynomial".

[0380] The mth row of the parity check matrix H in FIG. 23 can be obtained by converting the (m-1)th parity check polynomial among the zeroth to (m-1)th parity check polynomials that satisfy zero, according to expression 59 (i.e., can be obtained by generating a vector having one row and n×m×z columns from the (m-1)th parity check polynomial). As such, the mth row of the parity check matrix H in FIG. 23 is indicated as a "row corresponding to (m-1)th parity check polynomial".

[0381] The (m×z-1)th row of the parity check matrix H in FIG. 23 can be obtained by converting the (m-2)th parity check polynomial among the zeroth to (m-1)th parity check polynomials that satisfy zero, according to expression 59 (i.e., can be obtained by generating a vector having one row and n×m×z columns from the (m-2)th parity check polynomial).

[0382] The (m×z)th row of the parity check matrix H in FIG. 23 can be obtained by converting the (m-1)th parity check polynomial among the zeroth to (m-1)th parity check polynomials that satisfy zero, according to expression 59 (i.e., can be obtained by generating a vector having one row and n×m×z columns from the (m-1)th parity check polynomial).

[0383] As such, a kth row (where k is an integer no smaller than one and less than or equal to (m×z)) of the parity check matrix H in FIG. 23 can be obtained by converting the (k-1)%mth parity check polynomial among the zeroth to (m-1)th parity check polynomials that satisfy zero, according to expression 59 (i.e., can be obtained by generating a vector having one row and n×m×z columns from the (k-1)%mth parity check polynomial).

[0384] To prepare for the explanation to be provided in the following, a mathematical expression is provided of the parity check matrix H in FIG. 23 for the periodic time-varying LDPC-CC using tail-biting formed by performing tail-biting by using only a parity check polynomial that satisfies zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m. When assuming a vector having one row and n×m×z columns of the kth row of the parity check matrix H to be a vector hk, the parity check matrix H in FIG. 23 is expressed as shown in expression A13.
[Math. 64-1]



[0385] In the following, explanation is provided of a parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent-Literature 2.

[0386] FIG. 24 illustrates one example configuration of a parity check matrix Hpro for the DPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent-Literature 2. Note that the parity check matrix Hpro for LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent-Literature 2 satisfies Condition #A1.

[0387] When assuming a vector having one row and n×m×z columns in a kth row of the parity check matrix Hpro for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 to be a vector gk, the parity check matrix Hpro in FIG. 24 is expressed as shown in expression 64-2.
[Math. 64-2]



[0388] Note that, the transmission sequence (encoded sequence (codeword)) composed of an sth block of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be expressed as vs=(Xs,1,1, Xs,2,1, ..., Xs,n-1,1, Ppro,s,1, Xs,1,2, Xs,2,2, ..., Xs,n-1,2, Ppro,s,2, ..., Xs,1,k, Xs,2,k, ..., Xs,n-1,k, Ppro,s,k, Xs,1,m×z, Xs,2,m×z, ..., Xs,n-1,m×z, Ppro,s,m×z)T (where k=1, 2, ..., m×z-1, m×z), and Hprovs=0 holds true (here, the zero in Hprovs=0 indicates that all elements of the vector are zeros). Here, Xs,j,k represents an information bit Xj (j is an integer no smaller than one and less than or equal to n-1) and Ppro,s,k represents a bit of parity P.

[0389] In FIG. 24, which illustrates one example of the configuration of the parity check matrix Hpro for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, the rows of the parity check matrix Hpro other than the first row, or that is, the configuration of the second row to the (m×z)th row of the parity check matrix Hpro in FIG. 24 is identical to the configuration of the second row to the (mxz)th row of the parity check matrix H in FIG. 23 (refer to FIGS. 23 and 24). As such, a first row 2401 in FIG. 24 is indicated as a "row corresponding to zero'th parity check polynomial" (further explanation concerning this point is provided in the following). Accordingly, the following relational expression holds true from expression 64-1 and expression 64-2.
[Math. 65]

(i is an integer greater than equal to two and less than or equal to mxz, and expression 65 holds true for all conforming i)

[0390] Further, the following expression holds true when i equals one.
[Math. 66]



[0391] Accordingly, the parity check matrix Hpro for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be expressed as shown in expression 67.
[Math. 67]



[0392] Note that, in expression 67, expression 66 holds true.

[0393] Next, explanation is provided of a configuration method of g1 in expression 67 for enabling finding parities sequentially and achieving high error correction capability.

[0394] One example of a configuration method of g1 in expression 67 for enabling finding parities sequentially and achieving high error correction capability can be created by using a parity check polynomial that satisfies zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis (i.e., the basic structure) of the LDPC-CC described in Patent Literature 2.

[0395] Since g1 is the first row of the parity check matrix Hpro for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, (row number-1)%m=(1-1)%m=0. As such, g1 is created from a parity check polynomial that satisfies zero that is obtained by transforming the zeroth parity check polynomial that satisfies zero among the parity check polynomials that satisfy zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis (i.e., the basic structure) of the LDPC-CC described in Patent Literature 2.
[Math. 68]



[0396] One example of a parity check polynomial that satisfies zero for generating a vector g1 of the first row of the parity check matrix Hpro for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 is expressed as shown in expression 69, by using expression 59.
[Math.69]



[0397] Accordingly, a vector having one row and n×m×z columns that is created by performing tail-biting on expression 69 is the vector g1.

[0398] Note that in the following, a parity check polynomial that satisfies zero, according to expression 69, is referred to as a parity check polynomial Y that satisfies zero.

[0399] Accordingly, the first row of the parity check matrix Hpro for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be obtained by transforming the parity check polynomial Y that satisfies zero, according to expression 69 (that is, a vector g1=c1 having one row and n×m×z columns can be obtained).

[0400] The transmission sequence (encoded sequence (codeword)) composed of an sth block of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 is vs=(Xs,1,1, Xs,2,1, ..., Xs,n-1,1, Ppro,s,1, Xs,1,2, Xs,2,2, ..., Xs,n-1,2, Ppro,s,2, ..., Xs,1,k, Xs,2,k, ..., Xs,n-1,k, Ppro,s,k, Xs,1,m×z,Xs,2,m×z, ..., Xs,n-1,m×z, Ppro,s,m×z)T, and m×z parity check polynomials that satisfy zero are necessary for obtaining this transmission sequence vs. Here, a parity check polynomial that satisfies zero appearing eth, when the m×z parity check polynomials that satisfy zero are arranged in sequential order, is referred to as an eth parity check polynomial that satisfies zero (where e is an integer no smaller than zero and less than or equal to mxz-1). As such, the m×z parity check polynomials that satisfy zero are arranged in the following order.

zeroth: zeroth parity check polynomial that satisfies zero

first: first parity check polynomial that satisfies zero

second: second parity check polynomial that satisfies zero

eth: eth parity check polynomial that satisfies zero

(m×z-2)th: (m×z-2)th parity check polynomial that satisfies zero

(m×z-1)th: (m×z-1)th parity check polynomial that satisfies zero



[0401] As such, the transmission sequence (encoded sequence (codeword)) vs of an sth block of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be obtained. (Note that, as can be seen from the above, when expressing the parity check matrix Hpro for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 as shown in expression 64-2, a vector composed of the (e+1)th row of the parity check matrix Hpro corresponds to the eth parity check polynomial that satisfies zero.)

[0402] Then, in the proposed LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2,
the zeroth parity check polynomial that satisfies zero is the parity check polynomial Y that satisfies zero, according to expression 69,
the first parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 59,
the second parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 59,

the (m-2)th parity check polynomial that satisfies zero is the (m-2)th parity check polynomial that satisfies zero, according to expression 59,
the (m-1)th parity check polynomial that satisfies zero is the (m-1)th parity check polynomial that satisfies zero, according to expression 59,
the mth parity check polynomial that satisfies zero is the zeroth parity check polynomial that satisfies zero, according to expression 59,
the (m+1)th parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 59,
the (m+2)th parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 59,

the (2m-2)th parity check polynomial that satisfies zero is the (m-2)th parity check polynomial that satisfies zero, according to expression 59,
the (2m-1)th parity check polynomial that satisfies zero is the (m-1)th parity check polynomial that satisfies zero, according to expression 59,
the 2mth parity check polynomial that satisfies zero is the zeroth parity check polynomial that satisfies zero, according to expression 59,
the (2m+1)th parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 59,
the (2m+2)th parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 59,

the (mxz-2)th parity check polynomial that satisfies zero is the (m-2)th parity check polynomial that satisfies zero, according to expression 59, and
the (m×z-1)th parity check polynomial that satisfies zero is the (m-1)th parity check polynomial that satisfies zero, according to expression 59.

[0403] That is, the zeroth parity check polynomial that satisfies zero is the parity check polynomial Y that satisfies zero, according to expression 69, and the eth parity check polynomial that satisfies zero (where e is an integer no smaller than one and less than or equal to mxz-1) is the e%mth parity check polynomial that satisfies zero, according to expression 59.

[0404] Further, when the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 satisfies Conditions #A1, #A2-1, and #A2-2 as described in the present embodiment, multiple parities can be found sequentially, and therefore, an advantageous effect of a reduction in the amount of computation (a reduction in circuit scale) can be achieved.

[0405] Note that, when Conditions #A1, #A2-1, #A2-2, and #A2-3 are satisfied, an advantageous effect is achieved such that a great number of parities can be found sequentially. (Alternatively, the same advantageous effect can be achieved when Conditions #A1, #A2-1, #A2-2, and #A2-3' are satisfied or when Conditions #A1, #A2-1, #A2-2, and #A2-3" are satisfied.)

[0406] In the following, explanation is provided of what is meant by enabling finding parities sequentially.

[0407] In the example described above, since Hprovs=0 holds true for the transmission sequence (encoded sequence (codeword)) vs composed of an sth block of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, which is expressed as vs=(Xs,1,1, Xs,2,1, ..., Xs,n-1,1, Ppro,s,1, Xs,1,2, Xs,2,2, ..., Xs,n-1,2, Ppro,s,2, ..., Xs,1,k, Xs,2,k, ..., Xs,n-1,k, Ppro,sk, Xs,1,m×z, Xs,2,m×z, ..., Xs,n-1,m×z, Ppro,s,m×z)T (where k=1, 2, ..., m×z-1, ,m×z), g1vs=0 holds true from expression 67. Since g1 is obtained by transforming the parity check polynomial Y that satisfies zero, according to expression 69, Ppro,s,1 can be calculated from g1vs=0 (Ppro,s,1 can be determined since there is only one term of P(D) in a parity check polynomial that satisfies zero, according to expression 69).

[0408] Since Xs,j,k is a known bit (i.e., a bit before encoding) for all j that is an integer no smaller than one and less than n-1 and all k that is an integer no smaller than one and less than or equal to mxz, and since Ppro,s,1 is already obtained, ga[2]vs=0 holds true for ga[2] (refer to expression 64-2) that is a vector in the a[2]th row (a[2]≠1) of Hpro and vs, and therefore, Ppro,s,a[2] can be calculated.

[0409] Further, since Xs,j,k is a known bit (i.e., a bit before encoding) for all j that is an integer no smaller than one and less than n-1 and all k that is an integer no smaller than one and less than or equal to mxz, and since Ppro,s,a[2] is already obtained, ga[3]vs=0 holds true for ga[3] (refer to expression 64-2) that is a vector in the a[3]th row (a[3]≠1 and a[3]≠a[2]) of Hpro and vs, and therefore, Ppro,s,a[3] can be calculated.

[0410] Similarly, since Xs,j,k is a known bit (i.e., a bit before encoding) for all j that is an integer no smaller than one and less than n-1 and all k that is an integer no smaller than one and less than or equal to mxz, and since Ppro,s,a[3] is already obtained, ga[4]vs=0 holds true for ga[4] (refer to expression 64-2) that is a vector in the a[4]th row (a[4]≠1, a[4]≠a[2], and a[4]≠a[3]) of Hpro and vs, and therefore, Ppro,s,a[4] can be calculated.

[0411] By repeating the operations as described above, multiple parities Ppro,s,k can be calculated. In the explanation provided above, the repetitive execution of such operations is referred to as finding parities sequentially, which has an advantageous effect such that circuit scale of an encoder (amount of computation performed by an encoder) can be reduced due to the multiple parities Ppro,s,k being obtainable without calculation of complex simultaneous equations. Note that, when Ppro,s,k can be calculated for all k that is an integer no smaller than one and less than or equal to m×z by repetitively performing similar operations as those described above, an advantageous effect is achieved such that circuit scale (amount of computation) can be reduced to be extremely small.

[0412] Note that in the description provided above, high error correction capability may be achieved when at least one of Conditions #A2-4, #A2-5, and #A2-6 is satisfied, but high error correction capability may also be achieved when none of Conditions #A2-4, #A2-5, and #A2-6 is satisfied.

[0413] As description has been provided above, the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, at the same time as achieving high error correction capability, enables finding multiple parities sequentially, and therefore, achieves an advantageous effect of reducing circuit scale of an encoder.

[0414] Note that, in a parity check polynomial that satisfies zero for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis (i.e., the basic structure) of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, high error correction capability may be achieved by setting the number of terms of either one of or all of information X1(D), X2(D), ..., Xn-2(D), and Xn-1(D) to two or more or three or more. Further, in such a case, to achieve the effect of having an increased time-varying period when a Tanner graph is drawn, the time-varying period m is beneficially an odd number, and further, the conditions as provided in the following are effective, for example.
  1. (1) The time-varying period m is a prime number.
  2. (2) The time-varying period m is an odd number, and the number of divisors of m is small.
  3. (3) The time-varying period m is assumed to be α×β,
    where α and β are odd numbers other than one and are prime numbers.
  4. (4) The time-varying period m is assumed to be αn,
    where α is an odd number other than one and is a prime number, and n is an integer no smaller than two.
  5. (5) The time-varying period m is assumed to be α×β×γ,
    where α, β, and γ are odd numbers other than one and are prime numbers.
  6. (6) The time-varying period m is assumed to be α×β×γ×δ,
    where, α, β, γ, and δ are odd numbers other than one and are prime numbers.
  7. (7) The time-varying period m is assumed to be Au×Bv,
    where, A and B are odd numbers other than one and are prime numbers, A≠B, and u and v are integers no smaller than one.
  8. (8) The time-varying period m is assumed to be Au×Bv×Cw,
    where, A, B, and C are odd numbers other than one and are prime numbers, A≠B, A≠C, and B≠C, and u, v, and w are integers no smaller than one.
  9. (9) The time-varying period m is assumed to be Au×Bv×Cw×Dx,
    where, A, B, C, and D are odd numbers other than one and are prime numbers, A≠B, A≠C, A≠D, B≠C, B≠D, and C≠D, and u, v, w, and x are integers no smaller than one.
    However, it is not necessarily true that a code having high error-correction capability cannot be obtained when the time-varying period m is an even number, and for example, the conditions as shown below may be satisfied when the time-varying period m is an even number.
  10. (10) The time-varying period m is assumed to be 2g×K,
    where, K is a prime number, and g is an integer no smaller than one.
  11. (11) The time-varying period m is assumed to be 2g×L,
    where, L is an odd number and the number of divisors of L is small, and g is an integer no smaller than one.
  12. (12) The time-varying period m is assumed to be 2g×α×β,
    where, α and β are odd numbers other than one and are prime numbers, and g is an integer no smaller than one.
  13. (13) The time-varying period m is assumed to be 2g×αn,
    where, α is an odd number other than one and is a prime number, n is an integer no smaller than two, and g is an integer no smaller than one.
  14. (14) The time-varying period m is assumed to be 2g×α×β×γ,
    where, α, β, and γ are odd numbers other than one and are prime numbers, and g is an integer no smaller than one.
  15. (15) The time-varying period m is assumed to be 2g×α×β×γ×δ,
    where, α, β, γ, and δ are odd numbers other than one and are prime numbers, and g is an integer no smaller than one.
  16. (16) The time-varying period m is assumed to be 2g×Au×Bv,
    where, A and B are odd numbers other than one and are prime numbers, A≠B, u and v are integers no smaller than one, and g is an integer no smaller than one.
  17. (17) The time-varying period m is assumed to be 2g×Au×Bv×Cw,
    where, A, B, and C are odd numbers other than one and are prime numbers, A≠B, A≠C, and B≠C, u, v, and w are integers no smaller than one, and g is an integer no smaller than one.
  18. (18) The time-varying period m is assumed to be 2g×Au×Bv×Cw×Dx,
    where, A, B, C, and D are odd numbers other than one and are prime numbers, A≠B, A≠C, A≠D, B≠C, B≠D, and C≠D, u, v, w, and x are integers no smaller than one, and g is an integer no smaller than one.


[0415] As a matter of course, high error-correction capability may also be achieved when the time-varying period m is an odd number that does not satisfy the above conditions (1) through (9). Similarly, high error-correction capability may also be achieved when the time-varying period m is an even number that does not satisfy the above conditions (10) through (18).

[0416] In addition, when the time-varying period m is small, error floor may occur at a high bit error rate particularly for a small coding rate. When the occurrence of error floor is problematic in implementation in a communication system, a broadcasting system, a storage, a memory etc., it is desirable that the time-varying period m be set so as to be greater than three. However, when within a tolerable range of a system, the time-varying period m may be set so as to be less than or equal to three.

[0417] Next, explanation is provided of configurations and operations of an encoder and a decoder supporting the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2.

[0418] In the following, one example case is considered where the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 is used in a communication system. When the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 is applied to a communication system, an encoder and a decoder for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 are characterized for being configured and operating based on the parity check matrix Hpro for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 and the relation Hprovs=0.

[0419] Here, explanation is provided while referring to the overall diagram of the communication system in FIG. 25.

[0420] An encoder 2511 of a transmitting device 2501 takes an information sequence of an sth block (Xs,1,1, Xs,2,1, ..., Xs,n-1,1, Xs,1,2, Xs,2,2, ..., Xs,n-1,2, ..., Xs,1,k, Xs,2,k, ..., Xs,n-1,k, ..., Xs,1,m×z, Xs,2,m×z, ..., Xs,n-1,m×z) as input, performs encoding based on the parity check matrix Hpro for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 and the relation Hprovs=0, and generates and outputs the transmission sequence (encoded sequence (codeword)) vs of the sth block of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, which is expressed as vs=(Xs,1,1, Xs,2,1, ..., Xs,n-1,1, Ppro,s,1, Xs,1,2, Xs,2,2, ..., Xs,n-1,2, Ppro,s,2, ..., Xs,1,k, Xs,2,k, ..., Xs,n-1,k, Ppro,s,k, Xs,1,m×z, Xs,2,m×z, ..., Xs,n-1,m×z, Ppro,s,m×z)T. Here, note that, as explanation has been provided above, the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 is characterized for enabling finding parities sequentially.

[0421] A decoder 2523 of a receiving device 2520 in FIG. 25 takes as input a log-likelihood ratio of each bit of, for instance, the transmission sequence (encoded sequence (codeword)) vs c of the sth block, which is expressed as vs=(Xs,1,1, Xs,2,1, ..., Xs,n-1,1, Ppro,s,1, Xs,1,2, Xs,2,2, ..., Xs,n-1,2, Ppro,s,2, ..., Xs,1,k, Xs,2,k, ..., Xs,n-1,k, Ppro,s,k, Xs,1,m×z, Xs,2,m×z, ..., Xs,n-1,m×z, Ppro,s,m×z)T, output from a log-likelihood ratio generation section 2522, performs decoding according to the parity check matrix Hpro for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, and thereby obtains and outputs an estimation transmission sequence (an estimation encoded sequence) (a reception sequence). Here, the decoding performed by the decoder 2523 may be Belief Propagation (BP) decoding as described in, for instance, Non-Patent Literatures 4, 6, 7, and 8, including simple BP decoding such as min-sum decoding, offset BP decoding, and Normalized BP decoding, and Shuffled BP decoding and Layered BP decoding in which scheduling is performed with respect to the row operations (Horizontal operations) and the column operations (Vertical operations), or may be decoding for an LDPC code such as bit-flipping decoding described in Non-Patent Literature 17, etc.

[0422] Note that, although explanation has been provided on operations of an encoder and a decoder by taking a communication system as one example in the above, an encoder and a decoder may be used in the field of storages, memories, etc.

[Periodic Time-varying LDPC-CC based on Parity Check Polynomial and Using Improved Tail-biting of Coding Rate (n-1)/n (where n is an integer no smaller than two)]



[0423] The following provides a specific example of a configuration of a parity check matrix for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2.

[0424] When assuming that a parity check matrix for the proposed LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2 is Hpro, the number of columns of Hpro can be expressed as n×m×z (where z is a natural number) (here, note that m is the time-varying period of the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n, which serves as the basis of the proposed LDPC-CC).

[0425] Accordingly, a transmission sequence (encoded sequence (codeword)) composed of an n×m×z number of bits of an sth block of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be expressed as vs=(Xs,1,1, Xs,2,1, ..., Xs,n-1,1, Ppro,s,1, Xs,1,2, Xs,2,2, ..., Xs,n-1,2, Ppro,s,2, ..., Xs,1,m×z-1, Xs,2,m×z-1, ..., Xs,n-1,m×z-1, Ppro,s,m×z-1, Xs,1,m×z, Xs,2,m×z, ..., Xs,n-1,m×z, Ppro,s,m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,m×z-1, λpro,s,m×z)T, and Hprovs=0 holds true (here, the zero in Hprovs=0 indicates that all elements of the vector are zeros). Here, Xs,j,k represents an information bit Xj (j is an integer no smaller than one and less than or equal to n-1), Ppro,s,k represents the parity bit of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, and λpro,s,k=(Xs,1,k, Xs,2,k, ..., Xs,n-1,k, Ppro,s,k) (accordingly, λpro,s,k=(Xs,1,k, Ppro,s,k) when n=2, λpro,s,k=(Xs,1,k, Xs,2,k, Ppro,s,k) when n=3, λpro,s,k=(Xs,1,k, Xs,2,k, Xs,3,k, Ppro,s,k) when n=4, λpro,s,k=(Xs,1,k, Xs,2,k, Xs,3,k, Xs,4,k, Ppro,s,k) when n=5, and λpro,s,k=(Xs,1,k, Xs,2,k, Xs,3,k, Xs,4,k, Xs,5,k Ppro,s,k) when n=6). Here, k=1, 2, ..., m×z-1, m×z, or that is, k is an integer no smaller than one and less than or equal to m×z. Further, the number of rows of Hpro, which is the parity check matrix for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, is m×z.

[0426] In addition, as explained above, an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m-1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, can be expressed as shown in expression 59.

[0427] Here, an ith parity check polynomial that satisfies zero, according to expression 59, is expressed as shown in expression 70.
[Math. 70]



[0428] In expression 70, ap,i,q (p=1, 2, ..., n-1 (p is an integer no smaller than one and less than or equal to n-1); q=1, 2, ..., rp (q is an integer no smaller than one and less than or equal to rp)) is a natural number. Also, when y, z=1, 2, ..., rp (y and z are integers no smaller than one and less than or equal to rp) and y≠z, and ap,i,y≠ap,i,z holds true for conforming (y, z) (for all conforming y and z).

[0429] Further, in order to achieve high error correction capability, each of r1, r2, ..., rn-2, rn-1 is set to three or greater (k is an integer no smaller than one and less than or equal to n-1, and rk is three or greater for all conforming k). In other words, k is an integer no smaller than one and less than or equal to n-1 in expression 70, and the number of terms of Xk(D) is four or greater for all conforming k. Also, b1,i is a natural number.

[0430] As such, expression 69, which is a parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix Hpro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2, is expressed as shown in expression 71 (is expressed by using the zeroth parity check polynomial that satisfies zero, according to expression 70).
[Math. 71]



[0431] Note that the zeroth parity check polynomial (that satisfies zero), according to expression 70, that is used for generating expression 71 is expressed as shown in expression 72.
[Math. 72]



[0432] As described above, the transmission sequence (encoded sequence (codeword)) composed of an n×m×z number of bits of an sth block of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 is vs=(Xs,1,1, Xs,2,1, ..., Xs,n-1,1, Ppro,s,1, Xs,1,2, Xs,2,2, ..., Xs,n-1,2, Ppro,s,2, ..., Xs,1,m×z-1, Xs,2,m×z-1, ..., Xs,n-1,m×z-1, Ppro,s,m×z-1, Xs,1,m×z, Xs,2,m×z, ..., Xs,n-1,m×z, Ppro,s,m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,m×z-1, λpro,s,m×z)T, and m×z parity check polynomials that satisfy zero are necessary for obtaining this transmission sequence vs. Here, a parity check polynomial that satisfies zero appearing eth, when the m×z parity check polynomials that satisfy zero are arranged in sequential order, is referred to as an eth parity check polynomial that satisfies zero (where e is an integer no smaller than zero and less than or equal to m×z-1). As such, the m×z parity check polynomials that satisfy zero are arranged in the following order.

zeroth: zeroth parity check polynomial that satisfies zero

first: first parity check polynomial that satisfies zero

second: second parity check polynomial that satisfies zero

eth: eth parity check polynomial that satisfies zero

(m×z-2)th: (m×z-2)th parity check polynomial that satisfies zero

(m×z-1)th: (m×z-1)th parity check polynomial that satisfies zero



[0433] As such, the transmission sequence (encoded sequence (codeword)) vs of an sth block of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be obtained. (Note that a vector composed of the (e+1)th row of the parity check matrix Hpro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 corresponds to the eth parity check polynomial that satisfies zero.)

[0434] From the explanation provided above, in the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2,
the zeroth parity check polynomial that satisfies zero is a parity check polynomial that satisfies zero, according to expression 71,
the first parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 70,
the second parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 70,

the (m-2)th parity check polynomial that satisfies zero is the (m-2)th parity check polynomial that satisfies zero, according to expression 70,
the (m-1)th parity check polynomial that satisfies zero is the (m-1)th parity check polynomial that satisfies zero, according to expression 70,
the mth parity check polynomial that satisfies zero is the zeroth parity check polynomial that satisfies zero, according to expression 70,
the (m+1)th parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 70,
the (m+2)th parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 70,

the (2m-2)th parity check polynomial that satisfies zero is the (m-2)th parity check polynomial that satisfies zero, according to expression 70,
the (2m-1)th parity check polynomial that satisfies zero is the (m-1)th parity check polynomial that satisfies zero, according to expression 70,
the 2mth parity check polynomial that satisfies zero is the zeroth parity check polynomial that satisfies zero, according to expression 70,
the (2m+1)th parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 70,
the (2m+2)th parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 70,

the (m×z-2)th parity check polynomial that satisfies zero is the (m-2)th parity check polynomial that satisfies zero, according to expression 70, and
the (m×z-1)th parity check polynomial that satisfies zero is the (m-1)th parity check polynomial that satisfies zero, according to expression 70.

[0435] That is, the zeroth parity check polynomial that satisfies zero is the parity check polynomial that satisfies zero, according to expression 71, and the eth parity check polynomial that satisfies zero (where e is an integer no smaller than one and less than or equal to m×z-1) is the e%mth parity check polynomial that satisfies zero, according to expression 70.

[0436] In the present embodiment (in fact, commonly applying to the entirety of the present disclosure), % means a modulo, and for example, α%q represents a remainder after dividing α by q (where α is an integer no smaller than zero, and q is a natural number).

[0437] Next, detailed explanation is provided of a configuration of a parity check matrix in the case described above.

[0438] As described above, a transmission sequence (encoded sequence (codeword)) composed of an n×m×z number of bits of an sth block of the LDPC-CC (an LDPC block code using LDPC-CC), which is definable by expression 70 and expression 71, having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be expressed as vs=(Xs,1,1, Xs,2,1, ..., Xs,n-1,1, Ppro,s,1, Xs,1,2, Xs,2,2, ..., Xs,n-1,2, Ppro,s,2, ..., Xs,1,m×z-1, Xs,2,m×z-1, ..., Xs,n-1,m×z-1, Ppro,s,m×z-1, Xs,1,m×z, Xs,2,m×z, ..., Xs,n-1,m×z, Ppro,s,m×z)T=(kpro,s,1, λpro,s,2, ..., λpro,s,m×z-1, λpro,s,m×z)T, and Hprovs=0 holds true (here, the zero in Hprovs=0 indicates that all elements of the vector are zeros). Here, Xs,j,k represents an information bit Xj (j is an integer no smaller than one and less than or equal to n-1), Ppro,s,k represents the parity bit of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, and λpro,s,k=(Xs,1,k, Xs,2,k, ..., Xs,n-1,k, Ppro,s,k) (accordingly, λpro,s,k=(Xs,1,k, Ppro,s,k) when n=2, λpro,s,k=(Xs,1,k, Xs,2,k, Ppro,s,k) when n=3, λpro,s,k=(Xs,1,k, Xs,2,k, Xs,3,k, Ppro,s,k) when n=4, λpro,s,k=(Xs,1,k, Xs,2,k, Xs,3,k, Xs,4,k, Ppro,s,k) when n=5, and λpro,s,k=(Xs,1,k, Xs,2,k, Xs,3,k, Xs,4,k, Xs,5,k, Ppro,s,k) when n=6). Here, k=1, 2, ..., m×z-1, m×z, or that is, k is an integer no smaller than one and less than or equal to m×z. Further, the number of rows of Hpro, which is the parity check matrix for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, is m×z.

[0439] In the following, explanation is provided of a configuration, when tail-biting is performed according to the improved tail-biting scheme, of the parity check matrix Hpro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 while referring to FIGs. 26 and 27.

[0440] When assuming a sub-matrix (vector) corresponding to the parity check polynomial shown in expression 70, which is the ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m-1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, to be H;, an ith sub-matrix Hi is expressed as shown in expression 73.
[Math. 73]



[0441] In expression 73, the n consecutive ones correspond to the terms D0X1(D)=1×X1(D), D0X2(D)=1×X2(D), ..., D0Xn-1(D)=1×Xn-1(D) (that is, D0Xk(D)=1×Xk(D), where k is an integer no smaller than one and less than or equal to n-1), and D0P(D)=1×P(D) in each form of expression 70.

[0442] A parity check matrix Hpro in the vicinity of time m×z, among the parity check matrix Hpro corresponding to the above-defined transmission sequence vs for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 when tail-biting is performed according to the improved tail-biting scheme, is shown in FIG. 26. As shown in FIG. 26, a configuration is employed in which a sub-matrix is shifted n columns to the right between an ith row and an (i+1)th row in the parity check matrix Hpro (see FIG. 26).

[0443] Also, in FIG. 26, a reference sign 2601 indicates the (m×z)th (i.e., the last) row of the parity check matrix Hpro, and corresponds to the (m-1)th parity check polynomial that satisfies zero, according to expression 70, as described above. Similarly, a reference sign 2602 indicates the (m×z-1)th row of the parity check matrix Hpro, and corresponds to the (m-2)th parity check polynomial that satisfies zero, according to expression 70, as described above. Further, a reference sign 2603 indicates a column group corresponding to time point m×z, and the column group of the reference sign 2603 is arranged in the order of: Xs,1,m×z; Xs,2,m×z; Xs,n-1,m×z; ..., and Ppro,s,m×z. A reference sign 2604 indicates a column group corresponding to time point mxz-1, and the column group of the reference sign 2604 is arranged in the order of: Xs,1,m×z-1; Xs,2,m×z-1; ..., Xs,n-1,m×z-1; and Ppro,s,m×z-1.

[0444] Next, a parity check matrix Hpro in the vicinity of times m×z-1, m×z, 1, 2, among the parity check matrix Hpro corresponding to a reordered transmission sequence, specifically vs=(..., Xs,1,m×z-1, Xs,2,m×z-1, ..., Xs,n-1,m×z-1, Ppro,s,m×z-1, Xs,1,m×z, Xs,2,m×z, ..., Xs,n-1,m×z, Ppro,s,m×z, ..., Xs,1,1, Xs,2,1, ..., Xs,n-1,1, Ppro,s,1, Xs,1,2, Xs,2,2, ..., Xs,n-1,2, Ppro,s,2, ...,)T is shown in FIG. 27. In this case, the portion of the parity check matrix Hpro shown in FIG. 27 is the characteristic portion of the parity check matrix Hpro when tail-biting is performed according to the improved tail-biting scheme. As shown in FIG. 27, a configuration is employed in which a sub-matrix is shifted n columns to the right between an ith row and an (i+1)th row in the parity check matrix Hpro when the transmission sequence is reordered (refer to FIG. 27).

[0445] Also, in FIG. 27, when the parity check matrix is expressed as shown in FIG. 26, a reference sign 2705 indicates a column corresponding to a (m×z×n)th column and a reference sign 2706 indicates a column corresponding to the first column.

[0446] A reference sign 2707 indicates a column group corresponding to time point mxz-1, and the column group of the reference sign 2707 is arranged in the order of: Xs,1,m×z-1; Xs,2,m×z-1; ..., Xs,n-1,m×z-1; and Ppro,s,m×z-1. Further, a reference sign 2708 indicates a column group corresponding to time point mxz, and the column group of the reference sign 2708 is arranged in the order of: Xs,1,m×z; Xs,2,m×z; ..., Xs,n-1,m×z; and Ppro,s,m×z. A reference sign 2709 indicates a column group corresponding to time point one, and the column group of the reference sign 2709 is arranged in the order of: Xs,1,1; Xs,2,1; ..., Xs,n-1,1; and Ppro,s,1. A reference sign 2710 indicates a column group corresponding to time point two, and the column group of the reference sign 2710 is arranged in the order of: Xs,1,2; Xs,2,2; ..., Xs,n-1,2; and Ppro,s,2.

[0447] When the parity check matrix is expressed as shown in FIG. 26, a reference sign 2711 indicates a row corresponding to a (m×z)th row and a reference sign 2712 indicates a row corresponding to the first row. Further, the characteristic portions of the parity check matrix H when tail-biting is performed according to the improved tail-biting scheme are the portion left of the reference sign 2713 and below the reference sign 2714 in FIG. 27 and the portion corresponding to the first row indicated by the reference sign 2712 in FIG. 27 when the parity check matrix is expressed as shown in FIG. 26.

[0448] When assuming a sub-matrix (vector) corresponding to expression 71, which is the parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix Hpro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2, to be Ω0, Ω0 can be expressed as shown in expression 74.
[Math. 74]



[0449] In expression 74, the n consecutive ones correspond to the terms D0X1(D)=1×X1(D), D0X2(D)=1×X2(D), ..., D0Xn-1(D)=1×Xn-1(D) (that is, D0Xk(D)=1×Xk(D), where k is an integer no smaller than one and less than or equal to n-1), and D0P(D)=1×P(D) in each form of expression 71.

[0450] Then, the row corresponding to the first row indicated by the reference sign 2712 in FIG. 27 when the parity check matrix is expressed as shown in FIG. 26 can be expressed by using expression 74 (refer to reference sign 2712 in FIG. 27). Further, the rows other than the row corresponding to the reference sign 2712 in FIG. 27 (i.e., the row corresponding to the first row when the parity check matrix is expressed as shown in FIG. 26) are rows each corresponding to one of the parity check polynomials that satisfy zero according to expression 70, which is the ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m-1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 (as explanation has been provided above).

[0451] To provide a supplementary explanation of the above, although not shown in FIG. 26, in the parity check matrix Hpro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 as expressed in FIG. 26, a vector obtained by extracting the first row of the parity check matrix Hpro is a vector corresponding to expression 71, which is a parity check polynomial that satisfies zero.

[0452] Further, a vector composed of the (e+1)th row (where e is an integer no smaller than one and less than or equal to m×z-1) of the parity check matrix Hpro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 as expressed in FIG. 26, corresponds to an e%mth parity check polynomial that satisfies zero, according to expression 70, which is the ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m-1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2.

[0453] In the description provided above, for ease of explanation, explanation has been provided of the parity check matrix for the LDPC-CC in the present embodiment, which is definable by expression 70 and expression 71, having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2. However, a parity check matrix for the LDPC-CC, which is definable by expression 59 and expression 68, having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated in a similar manner as described above.

[0454] Next, explanation is provided of a parity check polynomial matrix that is equivalent to the above-described parity check matrix for the LDPC-CC, which is definable by expression 70 and expression 71, having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2.

[0455] In the above, explanation has been provided of the configuration of the parity check matrix Hpro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 where the transmission sequence (encoded sequence (codeword)) of an sth block is vs=(Xs,1,1, Xs,2,1, ..., Xs,n-1,1, Ppro,s,1, Xs,1,2, Xs,2,2, ..., Xs,n-1,2, Ppro,s,2, ..., Xs,1,m×z-1, Xs,2,m×z-1, ..., Xs,n-1,m×z-1, Ppro,s,m×z-1, Xs,1,m×z, Xs,2,m×z, ..., Xs,n-1,m×z, Ppro,s,m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,m×z-1, λpro,s,m×z)T, and Hprovs=0 holds true (here, the zero in Hprovs=0 indicates that all elements of the vector are zeros). In the following, explanation is provided of a configuration of a parity check matrix Hpro_m for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 where Hpro_mus=0 holds true (here, the zero in Hpro_mus=0 indicates that all elements of the vector are zeros) when a transmission sequence (encoded sequence (codeword)) of an sth block is expressed as us=(Xs,1,1, Xs,1,2, ..., Xs,1,m×z, Xs,2,1, Xs,2,2, ..., Xs,2,m×z, ..., Xs,n-2,1, Xs,n-2,2, ..., Xs,n-2,m×z, Xs,n-1,1, Xs,n-2,2, ..., Xs,n-1,m×z, Ppro,s,1, Ppro,s,2, ..., Ppro,s,m×z)T=(ΛX1,s, ΛX2,s, ΛX3,s, ..., ΛXn-2,s, ΛXn-1,s, Λpro,s)T.

[0456] Here, note that ΛXk,s is expressible as ΛXk,s=(Xs,k,1, Xs,k,2, Xs,k,3, ..., Xs,k,m×z-2, Xs,k,m×z-1, Xs,k,m×z) (where k is an integer no smaller than one and less than or equal to n-1) and Λpro,s is expressible as Λpro,s=(Ppro,s,1, Ppro,s,2, Ppro,s,3, ..., Ppro,s,m×z-2, Ppro,s,m×z-1, Ppro,s,m×z). Accordingly, for example, us=(ΛX1,s, Λpro,s)T when n=2, us=(ΛX1,s, ΛX2,s, Λpro,s)T when n=3, us=(ΛX1,s, ΛX2,s, ΛX3,s, ΛPro,s)T when n=4, us=(ΛX1,s, ΛX2,s, ΛX3,s, ΛX4,s, Λpro,s)T when n=5, Us=(ΛX1,s, ΛX2,s, ΛX3,s, ΛX4,s, ΛX5,s, Λpro,s)T when n=6, us=(ΛX1,s, ΛX2,s, ΛX3,s, ΛX4,s, ΛX5,s, ΛX6,s, Λpro,s)T when n=7, and us=(ΛX1,s, ΛX2,s, ΛX3,s, ΛX4,s, ΛX5,s, ΛX6,s, ΛX7,s, Λpro,s)T when n=8.

[0457] Here, since an m×z number of information bits X1 are included in one block, an m×z number of information bits X2 are included in one block, ..., an m×z number of information bits Xn-2 are included in one block, an m×z number of information bits Xn-1 are included in one block (as such, an m×z number of information bits Xk are included in one block (where k is an integer no smaller than one and less than or equal to n-1)), and an m×z number of parity bits Ppro are included in one block, the parity check matrix Hpro_m for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be expressed as Hpro_m=[Hx,1, Hx,2, ..., Hx,n-2, Hx,n-1, Hp] as shown in FIG. 28.

[0458] Further, since the transmission sequence (encoded sequence (codeword)) of an sth block is expressed as us=(Xs,1,1, Xs,1,2, ..., Xs,1,m×z, Xs,2,1, Xs,2,2, ..., Xs,2,m×z, ..., Xs,n-2,1, Xs,n-2,2, ..., Xs,n-2,m×z, Xs,n-1,1, Xs,n-1,2, ..., Xs,n-1,m×z, Ppro,s,1, Ppro,s,2, ..., Ppro,s,m×z)T=(ΛX1,s, ΛX2,s, ΛX3,s, ..., ΛXn-2,s, ΛXn-1,s, Λpro,s)T, Hx,1 is a partial matrix pertaining to information X1, Hx,2 is a partial matrix pertaining to information X2, ..., Hx,n-2 is a partial matrix pertaining to information Xn-2, Hx,n-1 is a partial matrix pertaining to information Xn-1 (as such, Hx,k is a partial matrix pertaining to information Xk (where k is an integer no smaller than one and less than or equal to n-1)), and Hp is a partial matrix pertaining to a parity Ppro. In addition, as shown in FIG. 28, the parity check matrix Hpro_m is a matrix having m×z rows and n×m×z columns, the partial matrix Hx,1 pertaining to information X1 is a matrix having m×z rows and m×z columns, the partial matrix Hx,2 pertaining to information X2 is a matrix having m×z rows and m×z columns, ..., the partial matrix Hx,n-2 pertaining to information Xn-2 is a matrix having m×z rows and m×z columns, the partial matrix Hx,n-1 pertaining to information Xn-1 is a matrix having m×z rows and m×z columns (as such, the partial matrix Hx,k pertaining to information Xk is a matrix having m×z rows and m×z columns (where k is an integer no smaller than one and less than or equal to n-1)), and the partial matrix Hp pertaining to the parity Ppro is a matrix having m×z rows and m×z columns.

[0459] The transmission sequence (encoded sequence (codeword)) composed of an n×m×z number of bits of an sth block of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 is us=(Xs,1,1, Xs,1,2, ..., Xs,1,m×z, Xs,2,1, Xs,2,2, ..., Xs,2,m×z, ..., Xs,n-2,1, Xs,n-2,2, ..., Xs,n-2,m×z, Xs,n-1,1, Xs,n-1,2, ..., Xs,n-1,m×z, Ppro,s,1, Ppro,s,2, ..., Ppro,s,m×z)T=(ΛX1,s, ΛX2,s, ΛX3,s, ..., ΛXn-2,s, ΛXn-1,s, Λpro,s)T, and m×z parity check polynomials that satisfy zero are necessary for obtaining this transmission sequence us. Here, a parity check polynomial that satisfies zero appearing eth, when the m×z parity check polynomials that satisfy zero are arranged in sequential order, is referred to as an eth parity check polynomial that satisfies zero (where e is an integer no smaller than zero and less than or equal to m×z-1). As such, the m×z parity check polynomials that satisfy zero are arranged in the following order.

zeroth: zeroth parity check polynomial that satisfies zero

first: first parity check polynomial that satisfies zero

second: second parity check polynomial that satisfies zero

eth: eth parity check polynomial that satisfies zero

(m×z-2)th: (m×z-2)th parity check polynomial that satisfies zero

(m×z-1)th: (m×z-1)th parity check polynomial that satisfies zero



[0460] As such, the transmission sequence (encoded sequence (codeword)) us of an sth block of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be obtained. (Note that a vector composed of the (e+1)th row of the parity check matrix Hpro_m for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 corresponds to the eth parity check polynomial that satisfies zero.)

[0461] Accordingly, in the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2,
the zeroth parity check polynomial that satisfies zero is a parity check polynomial that satisfies zero, according to expression 71,
the first parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 70,
the second parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 70,

the (m-2)th parity check polynomial that satisfies zero is the (m-2)th parity check polynomial that satisfies zero, according to expression 70,
the (m-1)th parity check polynomial that satisfies zero is the (m-1)th parity check polynomial that satisfies zero, according to expression 70,
the mth parity check polynomial that satisfies zero is the zeroth parity check polynomial that satisfies zero, according to expression 70,
the (m+1)th parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 70,
the (m+2)th parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 70,

the (2m-2)th parity check polynomial that satisfies zero is the (m-2)th parity check polynomial that satisfies zero, according to expression 70,
the (2m-1)th parity check polynomial that satisfies zero is the (m-1)th parity check polynomial that satisfies zero, according to expression 70,
the 2mth parity check polynomial that satisfies zero is the zeroth parity check polynomial that satisfies zero, according to expression 70,
the (2m+1)th parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 70,
the (2m+2)th parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 70,

the (m×z-2)th parity check polynomial that satisfies zero is the (m-2)th parity check polynomial that satisfies zero, according to expression 70, and
the (m×z-1)th parity check polynomial that satisfies zero is the (m-1)th parity check polynomial that satisfies zero, according to expression 70.

[0462] That is, the zeroth parity check polynomial that satisfies zero is the parity check polynomial that satisfies zero, according to expression 71, and the eth parity check polynomial that satisfies zero (where e is an integer no smaller than one and less than or equal to m×z-1) is the e%mth parity check polynomial that satisfies zero, according to expression 70.

[0463] In the present embodiment (in fact, commonly applying to the entirety of the present disclosure), % means a modulo, and for example, α%q represents a remainder after dividing α by q (where α is an integer no smaller than zero, and q is a natural number).

[0464] FIG. 29 shows a configuration of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2.

[0465] According to the explanation provided above, a vector composing the first row of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the zeroth parity check polynomial that satisfies zero, or that is, the parity check polynomial that satisfies zero, according to expression 71.

[0466] Similarly, a vector composing the second row of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the first parity check polynomial that satisfies zero, or that is, the first parity check polynomial that satisfies zero, according to expression 70.

[0467] A vector composing the third row of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the second parity check polynomial that satisfies zero, or that is, the second parity check polynomial that satisfies zero, according to expression 70.

[0468] ⋮
A vector composing the (m-1)th row of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (m-2)th parity check polynomial that satisfies zero, or that is, the (m-2)th parity check polynomial that satisfies zero, according to expression 70.

[0469] A vector composing the mth row of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (m-1)th parity check polynomial that satisfies zero, or that is, the (m-1)th parity check polynomial that satisfies zero, according to expression 70.

[0470] A vector composing the (m+1)th row of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the mth parity check polynomial that satisfies zero, or that is, the zeroth parity check polynomial that satisfies zero, according to expression 70.

[0471] A vector composing the (m+2)th row of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (m+1)th parity check polynomial that satisfies zero, or that is, the first parity check polynomial that satisfies zero, according to expression 70.

[0472] A vector composing the (m+3)th row of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (m+2)th parity check polynomial that satisfies zero, or that is, the second parity check polynomial that satisfies zero, according to expression 70.

[0473] ⋮
A vector composing the (2m-1)th row of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (2m-2)th parity check polynomial that satisfies zero, or that is, the (m-2)th parity check polynomial that satisfies zero, according to expression 70.

[0474] A vector composing the 2mth row of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (2m-1)th parity check polynomial that satisfies zero, or that is, the (m-1)th parity check polynomial that satisfies zero, according to expression 70.

[0475] A vector composing the (2m+1)th row of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the 2mth parity check polynomial that satisfies zero, or that is, the zeroth parity check polynomial that satisfies zero, according to expression 70.

[0476] A vector composing the (2m+2)th row of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (2m+1)th parity check polynomial that satisfies zero, or that is, the first parity check polynomial that satisfies zero, according to expression 70.

[0477] A vector composing the (2m+3)th row of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (2m+2)th parity check polynomial that satisfies zero, or that is, the second parity check polynomial that satisfies zero, according to expression 70.

[0478] ⋮
A vector composing the (m×z-1)th row of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (m×z-2)th parity check polynomial that satisfies zero, or that is, the (m-2)th parity check polynomial that satisfies zero, according to expression 70.

[0479] A vector composing the (m×z)th row of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (m×z-1)th parity check polynomial that satisfies zero, or that is, the (m-1)th parity check polynomial that satisfies zero, according to expression 70.

[0480] As such, a vector composing the first row of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the zeroth parity check polynomial that satisfies zero, or that is, the parity check polynomial that satisfies zero, according to expression 71, and a vector composing the (e+1)th row (where e is an integer no smaller than one and less than or equal to m×z-1) of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the eth parity check polynomial that satisfies zero, or that is, the e%mth parity check polynomial that satisfies zero, according to expression 70.

[0481] Here, note that m is the time-varying period of the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n, which serves as the basis of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2.

[0482] FIG. 29 shows the configuration of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2. In the following, an element at row i, column j of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 is expressed as Hp,comp[i][j] (where i and j are integers no smaller than one and less than or equal to m×z (i, j=1, 2, 3, ..., m×z-1, m×z)). The following logically follows.

[0483] In the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, when a parity check polynomial that satisfies zero satisfies expression 70 and expression 71, a parity check polynomial pertaining to the first row of the partial matrix Hp pertaining to the parity Ppro is expressed as shown in expression 71.

[0484] As such, when the first row of the partial matrix Hp pertaining to the parity Ppro has elements satisfying one, expression 75 holds true.
[Math. 75]



[0485] Further, elements of Hp,comp[1][j] in the first row of the partial matrix Hp pertaining to the parity Ppro other than those given by expression 75 are zeroes. That is, when j is an integer no smaller than one and less than or equal to m×z and satisfies j≠1, Hp,comp[1][j]=0 holds true for all conforming j. Note that expression 75 expresses elements corresponding to D0P(D) (=P(D)) in expression 71 (refer to FIG. 29).

[0486] In the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, when a parity check polynomial that satisfies zero satisfies expression 70 and expression 71, and further, when assuming that (s-1)%m=k (where % is the modulo operator (modulo)) holds true for an sth row (where s in an integer no smaller than two and less than or equal to m×z) of the partial matrix Hp pertaining to the parity Ppro, a parity check polynomial pertaining to the sth row of the partial matrix Hp pertaining to the parity Ppro is expressed as shown in expression 76, according to expression 70.
[Math. 76]



[0487] As such, when the sth row of the partial matrix Hp pertaining to the parity Ppro has elements satisfying one, expression 77 holds true.
[Math. 77]



[0488] Expressions. 78-1 and 78-2 also hold true.
[Math. 78]



[0489] Further, elements of Hp,comp[s][j] in the sth row of the partial matrix Hp pertaining to the parity Ppro other than those given by expression 77, expression 78-1, and expression 78-2 are zeroes. That is, when s-b1,k≥1, j≠s, and j≠s-b1,k, Hp,comp[s][j]=0 holds true for all conforming j (where j is an integer no smaller than one and less than or equal to mxz). On the other hand, when s-b1,k<1, j≠s, and j≠s-b1,k+(m × z), Hp,comp[s][j]=0 holds true for all conforming j (where j is an integer no smaller than one and less than or equal to m×z).

[0490] Note that expression 77 expresses elements corresponding to D0P(D) (=P(D)) in expression 76 (corresponding to the ones in the diagonal component of the matrix shown in FIG. 29), the sorting in expression 78-1 and expression 78-2 applies since the partial matrix Hp pertaining to the parity Ppro has the first to (m×z)th rows, and in addition, also has the first to (m×z)th columns.

[0491] In addition, the relation between the rows of the partial matrix Hp pertaining to the parity Ppro in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 and the parity check polynomials shown in expression 70 and expression 71 is as shown in FIG. 29, and is therefore similar to the relation shown in FIG. 24, explanation of which being provided above.

[0492] Next, explanation is provided of values of elements composing a partial matrix Hx,q pertaining to information Xq in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 (here, q is an integer no smaller than one and less than or equal to n-1).

[0493]  FIG. 30 shows a configuration of the partial matrix Hx,q pertaining to information Xq in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2.

[0494] In the following, an element at row i, column j of the partial matrix Hx,1 pertaining to information X1 in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 is expressed as Hx,1,comp[i][j] (where i and j are integers no smaller than one and less than or equal to m×z (i, j=1, 2, 3, ..., m×z-1, m×z)). The following logically follows.

[0495] In the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, when a parity check polynomial that satisfies zero satisfies expression 70 and expression 71, a parity check polynomial pertaining to the first row of the partial matrix X1 pertaining to information X1 is expressed as shown in expression 71.

[0496] As such, when the first row of the partial matrix Hx,1 pertaining to information X1 has elements satisfying one, expression 79 holds true.
[Math. 79]



[0497] Expression 80 also holds true since 1-a1,0,y<1 (where a1,0,y is a natural number).
[Math. 80]



[0498] Expression 80 is satisfied when y is an integer no smaller than one and less than or equal to r1 (y=1, 2, ..., r1-1, r1). Further, elements of Hx,1,comp[1][j] in the first row of the partial matrix Hx,1 pertaining to information X1 other than those given by expression 79 and expression 80 are zeroes. That is, Hx,1,comp[1][j]=0 holds true for all j (j is an integer no smaller than one and less than or equal to m×z) satisfying the conditions of {j≠1} and {j≠1-a1,0,y+m×z for all y, where y is an integer no smaller than one and less than or equal to r1}.

[0499] Here, note that expression 79 expresses elements corresponding to D0X1(D) (=X1(D)) in expression 71 (corresponding to the ones in the diagonal component of the matrix shown in FIG. 30), and expression 80 is satisfied since the partial matrix Hx,1 pertaining to information X1 has the first to (m×z)th rows, and in addition, also has the first to (m×z)th columns.

[0500] In the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, when a parity check polynomial that satisfies zero satisfies expression 70 and expression 71, and further, when assuming that (s-1)%m=k (where % is the modulo operator (modulo)) holds true for an sth row (where s in an integer no smaller than two and less than or equal to m×z) of the partial matrix Hx,1 pertaining to information X1, a parity check polynomial pertaining to the sth row of the partial matrix Hx,1 pertaining to information X1 is expressed as shown in expression 76, according to expression 70.

[0501] As such, when the first row of the partial matrix Hx,1 pertaining to information X1 has elements satisfying one, expression 81 holds true.
[Math. 81]



[0502] Expressions. 82-1 and 82-2 also hold true.
[Math. 82]

(where y is an integer no smaller than one and less than or equal to r1 (y=1, 2, ..., r1-1, r1))

[0503] Further, elements of Hx,1,comp[s][j] in a sth row of the partial matrix Hx,1 pertaining to information X1 other than those given by expression 81, expression 82-1, and expression 82-2 are zeroes. That is, Hx,1,comp[s][j]=0 holds true for all j (j is an integer no smaller than one and less than or equal to m×z) satisfying the conditions of {j≠s} and {j≠s-a1,k,y when s-a1,k,y≥1, and j≠s-a1,k,y+m×z when s-a1,k,y<1, for all y, where y is an integer no smaller than one and less than or equal to r1}.

[0504] Here, note that expression 81 expresses elements corresponding to D0X1(D)(=X1(D)) in expression 76 (corresponding to the ones in the diagonal component of the matrix shown in FIG. 30), and the sorting in expression 82-1 and expression 82-2 applies since the partial matrix Hx,1 pertaining to information X1 has the first to (m×z)th rows, and in addition, also has the first to (m×z)th columns.

[0505] In addition, the relation between the rows of the partial matrix Hx,1 pertaining to information X1 in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 and the parity check polynomials shown in expression 70 and expression 71 is as shown in FIG. 30 (where q=1), and is therefore similar to the relation shown in FIG. 24, explanation of which being provided above.

[0506] In the above, explanation has been provided of the configuration of the partial matrix Hx,1 pertaining to information X1 in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2. In the following, explanation is provided of a configuration of a partial matrix Hx,q pertaining to information Xq (where q is an integer no smaller than one and less than or equal to n-1) in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 (Note that the configuration of the partial matrix Hx,q can be explained in a similar manner as the configuration of the partial matrix Hx,1 explained above).

[0507] FIG. 30 shows a configuration of the partial matrix Hx,q pertaining to information Xq in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2.

[0508] In the following, an element at row i, column j of the partial matrix Hx,q pertaining to information Xq in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 is expressed as Hx,q,comp[i][j] (where i and j are integers no smaller than one and less than or equal to m×z (i, j=1, 2, 3, ..., m×z-1, m×z)). The following logically follows.

[0509] In the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, when a parity check polynomial that satisfies zero satisfies expression 70 and expression 71, a parity check polynomial pertaining to the first row of the partial matrix Hx,q pertaining to information Xq is expressed as shown in expression 71.

[0510] As such, when the first row of the partial matrix Hx,q pertaining to information Xq has elements satisfying one, expression 83 holds true.
[Math. 83]



[0511] Expression 84 also holds true since 1-aq,0,y<1 (where aq,0,y is a natural number).
[Math. 84]



[0512] Expression 84 is satisfied when y is an integer no smaller than one and less than or equal to rq (where y=1, 2, ..., rq-1, rq).

[0513] Further, elements of Hx,q,comp[1][j] in the first row of the partial matrix Hx,q pertaining to information Xq other than those given by expression 83 and expression 83 are zeroes. That is, Hx,q,comp[1][j]=0 holds true for all j (j is an integer no smaller than one and less than or equal to m×z) satisfying the conditions of {j≠1} and {j≠1-aq,0,y+m×z for all y, where y is an integer no smaller than one and less than or equal to rq}.

[0514] Here, note that expression 83 expresses elements corresponding to D0Xq(D) (=Xq(D)) in expression 71 (corresponding to the ones in the diagonal component of the matrix shown in FIG. 30), and expression 84 is satisfied since the partial matrix Hx,q pertaining to information Xq has the first to (m×z)th rows, and in addition, also has the first to (m×z)th columns.

[0515] In the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, when a parity check polynomial that satisfies zero satisfies expression 70 and expression 71, and further, when assuming that (s-1)%m=k (where % is the modulo operator (modulo)) holds true for an sth row (where s in an integer no smaller than two and less than or equal to m×z) of the partial matrix Hx,q pertaining to information Xq, a parity check polynomial pertaining to the sth row of the partial matrix Hx,q pertaining to information Xq is expressed as shown in expression 76, according to expression 70.

[0516] As such, when the sth row of the partial matrix Hx,q pertaining to information Xq has elements satisfying one, expression 85 holds true.
[Math. 85]



[0517] Expressions. 86-1 and 86-2 also hold true.
[Math. 86]

(where y is an integer no smaller than one and less than or equal to rq (y=1, 2, ..., rq-1, rq))

[0518] Further, elements of Hx,q,comp[s][j] in the sth row of the partial matrix Hx,q pertaining to information Xq other than those given by expression 85, expression 86-1, and expression 86-2 are zeroes. That is, Hx,q,comp[s][j]=0 holds true for all j (j is an integer no smaller than one and less than or equal to m×z) satisfying the conditions of {j≠s} and {j≠s-aq,k,y when s-aq,k,y≥1, and j≠s-aq,k,y+m×z when s-aq,k,y<1, for all y, where y is an integer no smaller than one and less than or equal to rq}.

[0519] Here, note that expression 85 expresses elements corresponding to D0Xq(D) (=Xq(D)) in expression 76 (corresponding to the ones in the diagonal component of the matrix shown in FIG. 30), and the sorting in expression 86-1 and expression 85-2 applies since the partial matrix Hx,q pertaining to information Xq has the first to (mxz)th rows, and in addition, also has the first to (mxz)th columns.

[0520] In addition, the relation between the rows of the partial matrix Hx,q pertaining to information Xq in the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 and the parity check polynomials shown in expression 70 and expression 71 is as shown in FIG. 30, and is therefore similar to the relation shown in FIG. 24, explanation of which being provided above.

[0521] In the above, explanation has been provided of the configuration of the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2. In the following, explanation is provided of a generation method of a parity check matrix that is equivalent to the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2.

[0522] FIG. 31 illustrates the configuration of a parity check matrix H for an LDPC (block) code having a coding rate of (N-M)/N (where N>M>0). For example, the parity check matrix of FIG. 31 has M rows and N columns. In the following, explanation is provided under the assumption that the parity check matrix H of FIG. 31 represents the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 (as such, Hpro_m=H (of FIG. 31), and in the following, H refers to the parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2).

[0523] In FIG. 31, the transmission sequence (codeword) for a jth block is vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) (for systematic codes, Yj,k (where k is an integer no smaller than one and less than or equal to N) is the information X or the parity P (parity Ppro)).

[0524] Here, Hvj=0 is satisfied (where the zero in Hvj=0 indicates that all elements of the vector are zeroes, or that is, a kth row has a value of zero for all k (where k is an integer no smaller than one and less than or equal to M)).

[0525] Here, the element of the kth row (where k is an integer no smaller than one and less than or equal to M) of the transmission sequence vj for the jth block (in FIG. 31, the element in a kth column of a transpose matrix vjT of the transmission sequence vj) is Yj,k, and a vector extracted from a kth column of the parity check matrix H for the LDPC (block) code having a coding rate of (N-M)/N (where N>M>0) (i.e., the parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2) is expressed as ck, as shown in FIG. 31. Here, the parity check matrix H for the LDPC (block) code (i.e., the parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2) is expressed as shown in expression 87.



[0526] FIG. 32 indicates a configuration when interleaving is applied to the transmission sequence (codeword) vjT for the jth block expressed as vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N). In FIG. 32, an encoding section 3202 takes information 3201 as input, performs encoding thereon, and outputs encoded data 3203. For example, when encoding the LDPC (block) code having a coding rate (N-M)/N (where N>M>0) (i.e., the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2) as shown in FIG. 32, the encoding section 3202 takes the information for the jth block as input, performs encoding thereon based on the parity check matrix H for the LDPC (block) code having a coding rate of (N-M)/N (where N>M>0) (i.e., the parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2) as shown in FIG. 31, and outputs the transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) for the jth block.

[0527] Then, an accumulation and reordering section (interleaving section) 3204 takes the encoded data 3203 as input, accumulates the encoded data 3203, performs reordering thereon, and outputs interleaved data 3205. Accordingly, the accumulation and reordering section (interleaving section) 3204 takes the transmission sequence vj=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N)T for the jth block as input, and outputs a transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T as shown in FIG. 32, which is a result of reordering being performed on the elements of the transmission sequence vj (here, note that v'j is one example of a transmission sequence output by the accumulation and reordering section (interleaving section) 3204). Here, as discussed above, the transmission sequence v'j is obtained by reordering the elements of the transmission sequence vj for the jth block. Accordingly, v'j is a vector having one row and n columns, and the N elements of v'j are such that one each of the terms Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N is present.

[0528] Here, an encoding section 3207 as shown in FIG. 32 having the functions of the encoding section 3202 and the accumulation and reordering section (interleaving section) 3204 is considered. Accordingly, the encoding section 3207 takes the information 3201 as input, performs encoding thereon, and outputs the encoded data 3203. For example, the encoding section 3207 takes the information of the jth block as input, and as shown in FIG. 32, outputs the transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T. In the following, explanation is provided of a parity check matrix H' for the LDPC (block) code having a coding rate of (N-M)/N (where N>M>0) corresponding to the encoding section 3207 (i.e., a parity check matrix H' that is equivalent to the parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2) while referring to FIG. 33.

[0529]  FIG. 33 a configuration of the parity check matrix H' when the transmission sequence (codeword) is v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T. Here, the element in the first row of the transmission sequence v'j for the jth block (the element in the first column of the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) is Yj,32. Accordingly, a vector extracted from the first row of the parity check matrix H', when using the above-described vector ck (k=1, 2, 3, ..., N-2, N-1, N), is c32. Similarly, the element in the second row of the transmission sequence v'j for the jth block (the element in the second column of the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) is Yj,99. Accordingly, a vector extracted from the second row of the parity check matrix H' is c99. Further, as shown in FIG. 33, a vector extracted from the third row of the parity check matrix H' is c23, a vector extracted from the (N-2)th row of the parity check matrix H' is c234, a vector extracted from the (N-1)th row of the parity check matrix H' is c3, and a vector extracted from the Nth row of the parity check matrix H' is c43.

[0530] That is, when the element in the ith row of the transmission sequence v'j for the jth block (the element in the ith column of the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) is expressed as Yj,g (g=1, 2, 3, ..., N-2, N-1, N), then the vector extracted from the ith column of the parity check matrix H' is cg, when using the above-described vector ck.

[0531] Thus, the parity check matrix H' for the transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T is expressed as shown in expression 88.
[Math. 88]



[0532] When the element in the ith row of the transmission sequence v'j for the jth block (the element in the ith column of the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) is represented as Yj,g (g=1, 2, 3, ..., N-2, N-1, N), then the vector extracted from the ith column of the parity check matrix H' is cg, when using the above-described vector ck. When the above is followed to create a parity check matrix, then a parity check matrix for the transmission sequence v'j of the jth block is obtainable with no limitation to the above-given example.

[0533] Accordingly, when interleaving is applied to the transmission sequence (codeword) of the parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, a parity check matrix of the interleaved transmission sequence (codeword) is obtained by performing reordering of columns (i.e., a column permutation) as described above on the parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2.

[0534] As such, it naturally follows that the transmission sequence (codeword) (vj) obtained by returning the interleaved transmission sequence (codeword) (v'j) to the original order is the transmission sequence (codeword) of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2. Accordingly, by returning the interleaved transmission sequence (codeword) (v'j) and the parity check matrix H' corresponding to the interleaved transmission sequence (codeword) (v'j) to their respective orders, the transmission sequence vj and the parity check matrix corresponding to the transmission sequence vj can be obtained, respectively. Further, the parity check matrix obtained by performing the reordering as described above is the parity check matrix H of FIG. 31, or in other words, the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2.

[0535] FIG. 34 illustrates an example of a decoding-related configuration of a receiving device, when encoding of FIG. 32 has been performed. The transmission sequence obtained when the encoding of FIG. 32 is performed undergoes processing, in accordance with a modulation scheme, such as mapping, frequency conversion and modulated signal amplification, whereby a modulated signal is obtained. A transmitting device transmits the modulated signal. The receiving device then receives the modulated signal transmitted by the transmitting device to obtain a received signal. A log-likelihood ratio calculation section 3400 in FIG. 34 takes the received signal as input, calculates a log-likelihood ratio for each bit of the codeword, and outputs a log-likelihood ratio signal 3401.

[0536] For example, assume that the transmitting device transmits a transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T for the jth block. Then, the log-likelihood ratio calculation section 3400 calculates, from the received signal, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, and outputs the log-likelihood ratios.

[0537] An accumulation and reordering section (deinterleaving section) 3402 takes the log-likelihood ratio signal 3401 as input, performs accumulation and reordering thereon, and outputs a deinterleaved log-likelihood ratio signal 3403.

[0538] For example, the accumulation and reordering section (deinterleaving section) 3402 takes, as input, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, performs reordering, and outputs the log-likelihood ratios in the order of: the log-likelihood ratio for Yj,1, the log-likelihood ratio for Yj,2, the log-likelihood ratio for Yj,3, ..., the log-likelihood ratio for Yj,N-2, the log-likelihood ratio for Yj,N-1, and the log-likelihood ratio for Yj,N in the stated order.

[0539] A decoder 3404 takes the deinterleaved log-likelihood ratio signal 3403 as input, performs belief propagation decoding, such as the BP decoding given in Non-Patent Literature 6 to 8, sum-product decoding, min-sum decoding, offset BP decoding, Normalized BP decoding, Shuffled BP decoding, and Layered BP decoding in which scheduling is performed, based on the parity check matrix H for the LDPC (block) code having a coding rate of (N-M)/N (where N>M>0) as shown in FIG. 31 (that is, based on the parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2), and thereby obtains an estimation sequence 3405 (note that the decoder 3404 may perform decoding according to decoding methods other than belief propagation decoding).

[0540] For example, the decoder 3404 takes, as input, the log-likelihood ratio for Yj,1, the log-likelihood ratio for Yj,2, the log-likelihood ratio for Yj,3, ..., the log-likelihood ratio for Yj,N-2, the log-likelihood ratio for Yj,N-1, and the log-likelihood ratio for Yj,N in the stated order, performs belief propagation decoding based on the parity check matrix H for the LDPC (block) code having a coding rate of (N-M)/N (where N>M>0) as shown in FIG. 31 (that is, based on the parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2), and obtains the estimation sequence (note that the decoder 3404 may perform decoding according to decoding methods other than belief propagation decoding).

[0541] In the following, a decoding-related configuration that differs from the above is described. The decoding-related configuration described in the following differs from the decoding-related configuration described above in that the accumulation and reordering section (deinterleaving section) 3402 is not included. The operations of the log-likelihood ratio calculation section 3400 are identical to those described above, and thus, explanation thereof is omitted in the following.

[0542] For example, assume that the transmitting device transmits a transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T for the jth block. Then, the log-likelihood ratio calculation section 3400 calculates, from the received signal, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, and outputs the log-likelihood ratios (corresponding to 3406 in FIG. 34).

[0543] A decoder 3407 takes a log-likelihood ratio signal 3406 as input, performs belief propagation decoding, such as the BP decoding given in Non-Patent Literature 6 to 8, sum-product decoding, min-sum decoding, offset BP decoding, Normalized BP decoding, Shuffled BP decoding, and Layered BP decoding in which scheduling is performed, based on the parity check matrix H' for the LDPC (block) code having a coding rate of (N-M)/N (where N>M>0) as shown in FIG. 33 (that is, based on the parity check matrix H' that is equivalent to the parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2), and thereby obtains an estimation sequence 3409 (note that the decoder 3407 may perform decoding according to decoding methods other than belief propagation decoding).

[0544]  For example, the decoder 3407 takes, as input, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43 in the stated order, performs belief propagation decoding based on the parity check matrix H' for the LDPC (block) code having a coding rate of (N-M)/N (where N>M>0) as shown in FIG. 33 (that is, based on the parity check matrix H' that is equivalent to the parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2), and obtains the estimation sequence (note that the decoder 3407 may perform decoding according to decoding methods other than belief propagation decoding).

[0545] As explained above, even when the transmitted data is reordered due to the transmitting device interleaving the transmission sequence vj=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N)T for the jth block, the receiving device is able to obtain the estimation sequence by using a parity check matrix corresponding to the reordered transmitted data.

[0546] Accordingly, when interleaving is applied to the transmission sequence (codeword) of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, the receiving device uses, as a parity check matrix for the interleaved transmission sequence (codeword), a matrix obtained by performing reordering of columns (i.e., column permutation) as described above on the parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2. As such, the receiving device is able to perform belief propagation decoding and thereby obtain an estimation sequence without performing interleaving on the log-likelihood ratio for each acquired bit.

[0547] In the above, explanation is provided of the relation between interleaving applied to a transmission sequence and a parity check matrix. In the following, explanation is provided of reordering of rows (row permutation) performed on a parity check matrix.

[0548] FIG. 35 illustrates a configuration of a parity check matrix H corresponding to the transmission sequence (codeword) VjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) for the jth block of the LDPC (block) code having a coding rate of (N-M)/N. For example, the parity check matrix H of FIG. 35 is a matrix having M rows and N columns. In the following, explanation is provided under the assumption that the parity check matrix H of FIG. 35 represents the parity check matrix Hpro_m for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 (as such, Hpro_m=H (of FIG. 35), and in the following, H refers to the parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2) (for systematic codes, Yj,k (where k is an integer no smaller than one and less than or equal to N) is the information X or the parity P (the parity Ppro), and is composed of (N-M) information bits and M parity bits). Here, Hvj=0 is satisfied (where the zero in Hvj=0 indicates that all elements of the vector are zeroes, or that is, a kth row has a value of zero for all k (where k is an integer no smaller than one and less than or equal to M)).

[0549] Further, a vector extracted from the kth row (where k is an integer no smaller than one and less than or equal to M) of the parity check matrix H of FIG. 35 is expressed as a vector zk. Here, the parity check matrix H for the LDPC (block) code (i.e., the parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2) is expressed as shown in expression 89.
[Math. 89]



[0550] Next, a parity check matrix obtained by performing reordering of rows (row permutation) on the parity check matrix H of FIG. 35 is considered.

[0551] FIG. 36 shows an example of a parity check matrix H' obtained by performing reordering of rows (row permutation) on the parity check matrix H of FIG. 35. The parity check matrix H', similar as the parity check matrix shown in FIG. 35, is a parity check matrix corresponding to the transmission sequence (codeword) VjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) for the jth block of the LDPC (block) code having a coding rate of (N-M)/N (i.e., the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2) (or that is, a parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2).

[0552] The parity check matrix H' of FIG. 36 is composed of vectors zk extracted from the kth row (where k is an integer no smaller than one and less than or equal to M) of the parity check matrix H of FIG. 35. For example, in the parity check matrix H', the first row is composed of vector z130, the second row is composed of vector z24, the third row is composed of vector z45, .., the (M-2)th row is composed of vector z33, the (M-1)th row is composed of vector z9, and the Mth row is composed of vector z3. Note that M row-vectors extracted from the kth row (where k is an integer no smaller than one and less than or equal to M) of the parity check matrix H' are such that one each of the terms z1, z2, z3, ..., zM-2, zM-1, zM is present.

[0553] The parity check matrix H' for the LDPC (block) code (i.e., the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2) is expressed as shown in expression 90.
[Math. 90]



[0554] Here, H'vj=0 is satisfied (where the zero in H'vj=0 indicates that all elements of the vector are zeroes, or that is, a kth row has a value of zero for all k (where k is an integer no smaller than one and less than or equal to M)).

[0555] That is, for the transmission sequence vjT for the jth block, a vector extracted from the ith row of the parity check matrix H' of FIG. 36 is expressed as ck (where k is an integer no smaller than one and less than or equal to M), and the M row-vectors extracted from the kth row (where k is an integer no smaller than one and less than or equal to M) of the parity check matrix H' of FIG. 36 are such that one each of the terms z1, z2, z3, ..., zM-2, zM-1, zM is present.

[0556] As described above, for the transmission sequence vjT for the jth block, a vector extracted from the ith row of the parity check matrix H' of FIG. 36 is expressed as ck (where k is an integer no smaller than one and less than or equal to M), and the M row-vectors extracted from the kth row (where k is an integer no smaller than one and less than or equal to M) of the parity check matrix H' of FIG. 36 are such that one each of the terms z1, z2, z3, ..., zM-2, zM-1, zM is present. Note that, when the above is followed to create a parity check matrix, then a parity check matrix for the transmission sequence vj of the jth block is obtainable with no limitation to the above-given example.

[0557] Accordingly, even when the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 is being used, it does not necessarily follow that a transmitting device and a receiving device are using the parity check matrix explained above or the parity check matrix explained with reference to FIGs. 26 through 30. As such, a transmitting device and a receiving device may use, in place of the parity check matrix explained above, a matrix obtained by performing reordering of columns (column permutation) as described above or a matrix obtained by performing reordering of rows (row permutation) as described above as a parity check matrix. Similarly, a transmitting device and a receiving device may use, in place of the parity check matrix explained with reference to FIGs. 26 through 30, a matrix obtained by performing reordering of columns (column permutation) as described above or a matrix obtained by performing reordering of rows (row permutation) as described above as a parity check matrix.

[0558] In addition, a matrix obtained by performing both reordering of columns (column permutation) as described above and reordering of rows (row permutation) as described above on the parity check matrix explained above for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 may be used as a parity check matrix.

[0559] In such a case, a parity check matrix H1 is obtained by performing reordering of columns (column permutation) on the parity check matrix explained above for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 (for example, through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H2 is obtained by performing reordering of rows (row permutation) on the parity check matrix H1 (for example, through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). A transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H2 so obtained.

[0560] Alternatively, a parity check matrix H1,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix explained above for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 (for example, through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H2,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix H1,1 (for example, through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36).

[0561] Further, a parity check matrix H1,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H2,1. Finally, a parity check matrix H2,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H1,2.

[0562] As described above, a parity check matrix H2,s may be obtained by repetitively performing reordering of columns (column permutation) and reordering of rows (row permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H1,k is obtained by performing a kth (where k is an integer no smaller than two and less than or equal to s) reordering of columns (column permutation) on a parity check matrix H2,k-1. Then, a parity check matrix H2,k is obtained by performing a kth reordering of rows (row permutation) on the parity check matrix H1,k. Note that in the first iteration in such a case, a parity check matrix H1,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix explained above for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2. Then, a parity check matrix H2,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H1,1.

[0563] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H2,s.

[0564] In another method, a parity check matrix H3 is obtained by performing reordering of rows (row permutation) on the parity check matrix explained above for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 (for example, through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H4 is obtained by performing reordering of columns (column permutation) on the parity check matrix H3 (for example, through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H4 so obtained.

[0565] Alternatively, a parity check matrix H3,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix explained above for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 (for example, through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H4,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix H3,1 (for example, through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33).

[0566] Further, a parity check matrix H3,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H4,1. Finally, a parity check matrix H4,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H3,2.

[0567] As described above, a parity check matrix H4,s may be obtained by repetitively performing reordering of rows (row permutation) and reordering of columns (column permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H3,k is obtained by performing a kth (where k is an integer no smaller than two and less than or equal to s) reordering of rows (row permutation) on a parity check matrix H4,k-1. Then, a parity check matrix H4,k is obtained by performing a kth reordering of columns (column permutation) on the parity check matrix H3,k. Note that in the first iteration in such a case, a parity check matrix H3,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix explained above for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2. Then, a parity check matrix H4,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H3,1.

[0568] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H4,s.

[0569] Here, note that by performing reordering of rows (row permutation) and reordering of columns (column permutation), the parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 or the parity check matrix explained with reference to FIGs. 26 through 30 for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be obtained from each of the parity check matrix H2, the parity check matrix H2,s, the parity check matrix H4, and the parity check matrix H4,s.

[0570]  In addition, a matrix obtained by performing both reordering of columns (column permutation) as described above and reordering of rows (row permutation) as described above on the parity check matrix explained with reference to FIGs. 26 through 30 for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 may be used as a parity check matrix.

[0571] In such a case, a parity check matrix H5 is obtained by performing reordering of columns (column permutation) on the parity check matrix explained with reference to FIGs. 26 through 30 for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 (for example, through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H6 is obtained by performing reordering of rows (row permutation) on the parity check matrix H5 (for example, through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). A transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H6 so obtained.

[0572] Alternatively, a parity check matrix H5,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix explained with reference to FIGs. 26 through 30 for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 (for example, through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H6,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix H5,1 (for example, through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36).

[0573] Further, a parity check matrix H5,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H6,1. Finally, a parity check matrix H6,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H5,2.

[0574] As described above, a parity check matrix H6,s may be obtained by repetitively performing reordering of columns (column permutation) and reordering of rows (row permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H5,k is obtained by performing a kth (where k is an integer no smaller than two and less than or equal to s) reordering of columns (column permutation) on a parity check matrix H6,k-1. Then, a parity check matrix H6,k is obtained by performing a kth reordering of rows (row permutation) on the parity check matrix H5,k. Note that in the first iteration in such a case, a parity check matrix H5,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix explained with reference to FIGs. 26 through 30 for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2. Then, a parity check matrix H6,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H5,1.

[0575] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H6,s.

[0576] In another method, a parity check matrix H7 is obtained by performing reordering of rows (row permutation) on the parity check matrix explained with reference to FIGs. 26 through 30 for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 (for example, through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H8 is obtained by performing reordering of columns (column permutation) on the parity check matrix H7 (for example, through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H8 so obtained.

[0577] Alternatively, a parity check matrix H7,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix explained with reference to FIGs. 26 through 30 for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 (for example, through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H8,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix H7,1 (for example, through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33).

[0578] Then, a parity check matrix H7,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H8,1. Finally, a parity check matrix H8,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H7,2.

[0579] As described above, a parity check matrix H8,s may be obtained by repetitively performing reordering of rows (row permutation) and reordering of columns (column permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H7,k is obtained by performing a kth (where k is an integer no smaller than two and less than or equal to s) reordering of rows (row permutation) on a parity check matrix H8,k-1. Then, a parity check matrix H8,k is obtained by performing a kth reordering of columns (column permutation) on the parity check matrix H7,k. Note that in the first iteration in such a case, a parity check matrix H7,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix explained with reference to FIGs. 26 through 30 for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2. Then, a parity check matrix H8,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H7,1.

[0580] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H8,s.

[0581] Here, note that by performing reordering of rows (row permutation) and reordering of columns (column permutation), the parity check matrix for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 or the parity check matrix explained with reference to FIGs. 26 through 30 for the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2 can be obtained from each of the parity check matrix H6, the parity check matrix H6,s, the parity check matrix H8, and the parity check matrix H8,s.

[0582] Expression 70 and expression 71 have been used as the parity check polynomials for forming the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme. However, parity check polynomials usable for forming the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme are not limited to those shown in expression 70 and expression 71. For instance, instead of the parity check polynomial shown in expression 70, a parity check polynomial as shown in expression 91 may used as an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m-1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme.
[Math. 91]



[0583] Here, ap,i,q (p=1, 2, ..., n-1 (p is an integer no smaller than one and less than or equal to n-1); q=1, 2, ..., rp (q is an integer no smaller than one and less than or equal to rp)) is assumed to be a natural number. Also, when y, z=1, 2, ..., rp (y and z are integers no smaller than one and less than or equal to rp) and y≠z, ap,i,y≠ap,i,z holds true for conforming (y,z) (for all conforming y and z).

[0584] Further, in order to achieve high error correction capability, each of r1, r2, ..., rn-2, and rn-1 is set to four or greater (k is an integer no smaller than one and less than or equal to n-1, and rk is four or greater for all conforming k). In other words, k is an integer no smaller than one and less than or equal to n-1 in expression 91, and the number of terms of Xk(D) is four or greater for all conforming k. Also, b1,i is a natural number.

[0585] As such, expression 69, which is a parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix Hpro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2, is expressed as shown in expression 92 (is expressed by using the zeroth parity check polynomial that satisfies zero, according to expression 91).
[Math. 92]



[0586] Further, as another method, in an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m-1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme, the number of terms of Xk(D) (where k is an integer no smaller than one and less than or equal to n-1) may be set for each parity check polynomial. According to this method, for instance, instead of the parity check polynomial shown in expression 70, a parity check polynomial as shown in expression 93 may used as an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m-1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme.
[Math. 93]





[0587] Here, ap,i,q (p=1, 2, ..., n-1 (p is an integer no smaller than one and less than or equal to n-1); q=1, 2, ..., rp,i (q is an integer no smaller than one and less than or equal to rp,i) is assumed to be a natural number. Also, when y, z=1, 2, ..., rp,i (y and z are integers no smaller than one and less than or equal to rp,i) and y≠z, ap,i,y≠ap,i,z holds true for conforming (y,z) (for all conforming y and z). Also, b1,i is a natural number. Note that expression 93 is characterized in that rp,i can be set for each i.

[0588] Further, in order to achieve high error correction capability, it is desirable that p is an integer no smaller than one and less than or equal to n-1, i is an integer no smaller than zero and less than or equal to m-1, and rp,i be set to one or greater for all conforming p and i.

[0589] As such, expression 69, which is a parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix Hpro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2, is expressed as shown in expression 94 (is expressed by using the zeroth parity check polynomial that satisfies zero, according to expression 93).
[Math. 94]



[0590] Further, as another method, in an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m-1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme, the number of terms of Xk(D) (where k is an integer no smaller than one and less than or equal to n-1) may be set for each parity check polynomial. According to this method, for instance, instead of the parity check polynomial shown in expression 70, a parity check polynomial as shown in expression 95 may used as an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m-1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme.
[Math. 95]



[0591] Here, ap,i,q (p=1, 2, ..., n-1 (p is an integer no smaller than one and less than or equal to n-1); q=1, 2, ..., rp,i (q is an integer no smaller than one and less than or equal to rp,i) is assumed to be an integer no smaller than zero. Also, when y, z=1, 2, ..., rp,i (y and z are integers no smaller than one and less than or equal to rp,i) and y≠z, ap,i,y≠ap,i,z holds true for conforming (y,z) (for all conforming y and z). Also, b1,i is a natural number. Note that expression 95 is characterized in that rp,i can be set for each i.

[0592] Further, in order to achieve high error correction capability, it is desirable that p is an integer no smaller than one and less than or equal to n-1, i is an integer no smaller than zero and less than or equal to m-1, and rp,i be set to two or greater for all conforming p and i.

[0593] As such, expression 69, which is a parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix Hpro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2, is expressed as shown in expression 96 (is expressed by using the zeroth parity check polynomial that satisfies zero, according to expression 95).
[Math. 96]





[0594] In the above, expression 70 and expression 71 have been used as the parity check polynomials for forming the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme. In the following, explanation is provided of examples of conditions to be applied to the parity check polynomials in expression 70 and expression 71 for achieving high error correction capability.

[0595] As explanation is provided above, in order to achieve high error correction capability, each of r1, r2, ..., rn-2, and rn-1 is set to three or greater (k is an integer no smaller than one and less than or equal to n-1, and rk is three or greater for all conforming k), or that is, in expression 70, k is an integer no smaller than one and less than or equal to n-1, and the number of terms of Xk(D) is set to four or greater for all conforming k. In the following, explanation is provided of examples of conditions for achieving high error correction capability when each of r1, r2, ..., rn-2, and rn-1 is set to three or greater.

[0596] Here, note that since the parity check polynomial of expression 71 is created by using the zeroth parity check polynomial of expression 70, in expression 71, k is an integer no smaller than one and less than or equal to n-1, and the number of terms of Xk(D) is four or greater for all conforming k.

[0597] Further, as explained above, the parity check polynomial that satisfies zero, according to expression 70, becomes an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m-1) that satisfies zero for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, and the parity check polynomial that satisfies zero, according to expression 71, becomes a parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix Hpro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2.

[0598] Here, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information X1 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme. Note that a column weight of a column α in a parity check matrix is defined as the number of ones existing among vector elements in a vector extracted from the column α.

(where, in the above, g is an integer no smaller than zero and less than or equal to m-1)

[0599] Similarly, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information X2 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme.

(where, in the above, g is an integer no smaller than zero and less than or equal to m-1)

[0600] Generalizing the above, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information Xk in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme (where k is an integer no smaller than one and less than or equal to n-1).

(where, in the above, g is an integer no smaller than zero and less than or equal to m-1)

[0601] Similarly, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information Xn-1 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme.

(where, in the above, g is an integer no smaller than zero and less than or equal to m-1)

[0602] In the above, % means a modulo, and for example, α%m represents a remainder after dividing α by m. Conditions #B-1-1 through #B-1-(n-1) are also expressible as follows. In the following, j is one or two.



[0603] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, and a1,g,j%m=v1,j (where v1,j is a fixed value) holds true for all conforming g.)



[0604] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, and a2,g,j%m=V2,j (where v2,j is a fixed value) holds true for all conforming g.)

[0605] The following is a generalization of the above.



[0606] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, and ak,g,j%m=Vk,j (where vk,j is a fixed value) holds true for all conforming g.)

[0607] (In the above, k is an integer no smaller than one and less than or equal to n-1.)



[0608] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, and an-1,g,j%m=vn-1,j (where vn-1,j is a fixed value) holds true for all conforming g.)

[0609] Further, high error correction capability is achievable when the following conditions are also satisfied.







[0610] The following is a generalization of the above.

(In the above, k is an integer no smaller than one and less than or equal to n-1.)




[0611] Further, since partial matrices pertaining to information X1 through Xn-1 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme should be irregular, the following conditions are taken into consideration.



[0612] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, h is an integer no smaller than zero and less than or equal to m-1, g≠h, and a1,g,v%m=a1,h,v%m holds true for all conforming g and h.) ... Condition #Xa-1

[0613] In the above, v is an integer no smaller than three and less than or equal to r1, and Condition #Xa-1 does not hold true for all v.



[0614] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, h is an integer no smaller than zero and less than or equal to m-1, g≠h, and a2,g,v%m=a2,h,v%m holds true for all conforming g and h.) ... Condition #Xa-2

[0615] In the above, v is an integer no smaller than three and less than or equal to r2, and Condition #Xa-2 does not hold true for all v.

[0616] The following is a generalization of the above.



[0617] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, h is an integer no smaller than zero and less than or equal to m-1, g≠h, and ak,g,v%m=ak,h,v%m holds true for all conforming g and h.) ... Condition #Xa-k

[0618] In the above, v is an integer no smaller than three and less than or equal to rk, and Condition #Xa-k does not hold true for all v.

[0619] (In the above, k is an integer no smaller than one and less than or equal to n-1.)



[0620] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, h is an integer no smaller than zero and less than or equal to m-1, g≠h, and an-1,g,v%m=an-1,h,v%m holds true for all conforming g and h.) ... Condition #Xa-(n-1)

[0621] In the above, v is an integer no smaller than three and less than or equal to rn-1, and Condition #Xa-(n-1) does not hold true for all v.

[0622] Conditions #B-3-1 through #B-3-(n-1) are also expressible as follows.



[0623] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, h is an integer no smaller than zero and less than or equal to m-1, g≠h, and values of g and h that satisfy a1,g,v%m≠a1,h,v%m exist.) ... Condition #Ya-1

[0624] In the above, v is an integer no smaller than three and less than or equal to r1, and Condition #Ya-1 holds true for all conforming v.



[0625] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, h is an integer no smaller than zero and less than or equal to m-1, g≠h, and values of g and h that satisfy a2,g,v%m≠a2,h,v%m exist.) ... Condition #Ya-2

[0626] In the above, v is an integer no smaller than three and less than or equal to r2, and Condition #Ya-2 holds true for all conforming v.

[0627] The following is a generalization of the above.



[0628] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, h is an integer no smaller than zero and less than or equal to m-1, g≠h, and values of g and h that satisfy ak,g,v%m≠ak,h,v%m exist.) ... Condition #Ya-k

[0629] In the above, v is an integer no smaller than three and less than or equal to rk, and Condition #Ya-k holds true for all conforming v.

[0630] (In the above, k is an integer no smaller than one and less than or equal to n-1.)



[0631] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, h is an integer no smaller than zero and less than or equal to m-1, g≠h, and values of g and h that satisfy an-1,g,v%m≠an-1,h,v%m exist.) ... Condition #Ya-(n-1)

[0632] In the above, v is an integer no smaller than three and less than or equal to rn-1, and Condition #Ya-(n-1) holds true for all conforming v.

[0633] By ensuring that the conditions above are satisfied, a minimum column weight of each of a partial matrix pertaining to information X1, a partial matrix pertaining to information X2, ..., a partial matrix pertaining to information Xn-1 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme is set to three. As such, the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme, when satisfying the above conditions, produces an irregular LDPC code, and high error correction capability is achieved.

[0634] Based on the conditions above, an LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme, and achieving high error correction capability, can be generated. Note that, in order to easily obtain an LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme, and achieving high error correction capability, it is desirable that r1=r2=...=rn-2=rn-1=r (where r is three or greater) be satisfied.

[0635] In addition, it may be desirable that, when drawing a tree, check nodes corresponding to the parity check polynomials of expression 70 and expression 71, which are parity check polynomials for forming the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme, appear in a great number as possible in the tree.

[0636] In order to ensure that check nodes corresponding to the parity check polynomials of expression 70 and expression 71 appear in a great number as possible in the above-described tree, it is desirable that vk,1 and vk,2 (where k is an integer no smaller than one and less than or equal to n-1) as described above satisfy the following conditions.

<Condition #B-4-1>



[0637] 
  • When expressing a set of divisors of m other than one as R, vk,1 is not to belong to R.

<Condition #B-4-2>



[0638] 
  • When expressing a set of divisors of m other than one as R, vk,2 is not to belong to R.


[0639] In addition to the above-described conditions, the following conditions may further be satisfied.

<Condition #B-5-1>



[0640] 
  • vk,1 belongs to a set of integers no smaller than one and less than or equal to m-1, and vk,1 also satisfies the following condition. When expressing a set of values w obtained by extracting all values w satisfying vk,1/w=g (where g is a natural number) as S, an intersection R∩S produces an empty set. The set R has been defined in Condition #B-4-1.

<Condition #B-5-2>



[0641] 
  • vk,2 belongs to a set of integers no smaller than one and less than or equal to m-1, and vk,2 also satisfies the following condition. When expressing a set of values w obtained by extracting all values w satisfying vk,2/w=g (where g is a natural number) as S, an intersection R∩S produces an empty set. The set R has been defined in Condition #B-4-2.


[0642] Condition #B-5-1 and Condition #B-5-2 are also expressible as Condition #B-5-1' and Condition #B-5-2', respectively.

<Condition #B-5-1'>



[0643] 
  • vk,1 belongs to a set of integers no smaller than one and less than or equal to m-1, and vk,1 also satisfies the following condition. When expressing a set of divisors of vk,1 as S, an intersection R∩S produces an empty set.

<Condition #B-5-2'>



[0644] 
  • vk,2 belongs to a set of integers no smaller than one and less than or equal to m-1, and vk,2 also satisfies the following condition. When expressing a set of divisors of vk,2 as S, an intersection R∩S produces an empty set.


[0645] Condition #B-5-1 and Condition #B-5-1' are also expressible as Condition #B-5-1", and Condition #B-5-2 and Condition #B-5-2' are also expressible as Condition #B-5-2".

<Condition #B-5-1">



[0646] 
  • vk,1 belongs to a set of integers no smaller than one and less than or equal to m-1, and vk,1 also satisfies the following condition. The greatest common divisor of vk,1 and m is one.

<Condition #B-5-2">



[0647] 
  • vk,2 belongs to a set of integers no smaller than one and less than or equal to m-1, and vk,2 also satisfies the following condition. The greatest common divisor of vk,2 and m is one.


[0648] In the above, expression 91 and expression 92 have been used as the parity check polynomials for forming the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme. In the following, explanation is provided of examples of conditions to be applied to the parity check polynomials in expression 91 and expression 92 for achieving high error correction capability.

[0649] As explained above, in order to achieve high error correction capability, each of r1, r2, ..., rn-2, and rn-1 is set to four or greater (k is an integer no smaller than one and less than or equal to n-1, and rk is three or greater for all conforming k). In other words, k is an integer no smaller than one and less than or equal to n-1 in expression 70, and the number of terms of Xk(D) is four or greater for all conforming k.

[0650] In the following, explanation is provided of examples of conditions for achieving high error correction capability when each of r1, r2, ..., rn-2, and rn-1 is set to four or greater.

[0651] Here, note that since the parity check polynomial of expression 92 is created by using the zeroth parity check polynomial of expression 91, in expression 92, k is an integer no smaller than one and less than or equal to n-1, and the number of terms of Xk(D) is four or greater for all conforming k.

[0652] Further, as explained above, the parity check polynomial that satisfies zero, according to expression 91, becomes an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m-1) that satisfies zero for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, and the parity check polynomial that satisfies zero, according to expression 92, becomes a parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix Hpro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2.

[0653] Here, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in the partial matrix pertaining to information X1 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme. Note that a column weight of a column α in a parity check matrix is defined as the number of ones existing among vector elements in a vector extracted from the column α.

(where, in the above, g is an integer no smaller than zero and less than or equal to m-1)

[0654] Similarly, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in the partial matrix pertaining to information X2 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme.

(where, in the above, g is an integer no smaller than zero and less than or equal to m-1)

[0655] Generalizing the above, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information Xk in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme (where k is an integer no smaller than one and less than or equal to n-1).



(where, in the above, g is an integer no smaller than zero and less than or equal to m-1)

[0656] Similarly, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information Xn-1 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme.

(where, in the above, g is an integer no smaller than zero and less than or equal to m-1)

[0657] In the above, % means a modulo, and for example, α%m represents a remainder after dividing α by m. Conditions #B-6-1 through #B-6-(n-1) are also expressible as follows. In the following, j is one, two, or three.



[0658] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, and a1,g,j%m=v1,j (where v1,j is a fixed value) holds true for all conforming g.)



[0659] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, and a2,g,j%m=v2,j (where v2,j is a fixed value) holds true for all conforming g.) ⋮

[0660] The following is a generalization of the above.



[0661] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, and ak,g,j%m=Vk,j (where vk,j is a fixed value) holds true for all conforming g.)

[0662] (In the above, k is an integer no smaller than one and less than or equal to n-1.)



[0663] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, and an-1,g,j%m=vn-1,j (where vn-1,j is a fixed value) holds true for all conforming g.)

[0664] Further, high error-correction capability is achievable when the following conditions are also satisfied.





[0665] The following is a generalization of the above.

(where, in the above, k is an integer no smaller than one and less than or equal to n-1)



[0666] Further, since the partial matrices pertaining to information X1 through Xn-1 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme should be irregular, the following conditions are taken into consideration.



[0667] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, h is an integer no smaller than zero and less than or equal to m-1, g≠h, and a1,g,v%m=a1,h,v%m holds true for all conforming g and h.) ... Condition #Xa-1

[0668] In the above, v is an integer no smaller than four and less than or equal to r1, and Condition #Xa-1 does not hold true for all v.



[0669] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, h is an integer no smaller than zero and less than or equal to m-1, g≠h, and a2,g,v%m=a2,h,v%m holds true for all conforming g and h.) ... Condition #Xa-2

[0670] In the above, v is an integer no smaller than four and less than or equal to r2, and Condition #Xa-2 does not hold true for all v.

[0671] The following is a generalization of the above.



[0672] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, h is an integer no smaller than zero and less than or equal to m-1, g≠h, and ak,g,v%m=ak,h,v%m holds true for all conforming g and h.) ... Condition #Xa-k

[0673] In the above, v is an integer no smaller than four and less than or equal to rk, and Condition #Xa-k does not hold true for all v.

[0674] (In the above, k is an integer no smaller than one and less than or equal to n-1.)



[0675] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, h is an integer no smaller than zero and less than or equal to m-1, g≠h, and an-1,g,v%m=an-1,h,v%m holds true for all conforming g and h.) ... Condition #Xa-(n-1)

[0676] In the above, v is an integer no smaller than four and less than or equal to rn-1, and Condition #Xa-(n-1) does not hold true for all v.

[0677] Conditions #B-8-1 through #B-8-(n-1) are also expressible as follows.



[0678] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, h is an integer no smaller than zero and less than or equal to m-1, g≠h, and values of g and h that satisfy a1,g,v%m≠a1,h,v%m exist.) ... Condition #Ya-1

[0679] In the above, v is an integer no smaller than four and less than or equal to r1, and Condition #Ya-1 holds true for all conforming v.



[0680] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, h is an integer no smaller than zero and less than or equal to m-1, g≠h, and values of g and h that satisfy a2,g,v%m≠a2,h,v%m exist.) ... Condition #Ya-2

[0681] In the above, v is an integer no smaller than four and less than or equal to r2, and Condition #Ya-2 holds true for all conforming v.

[0682] ⋮
The following is a generalization of the above.



[0683] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, h is an integer no smaller than zero and less than or equal to m-1, g≠h, and values of g and h that satisfy ak,g,v%m≠ak,h,v%m exist.) ... Condition #Ya-k

[0684] In the above, v is an integer no smaller than four and less than or equal to rk, and Condition #Ya-k holds true for all conforming v.

[0685] (In the above, k is an integer no smaller than one and less than or equal to n-1)




[0686] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, h is an integer no smaller than zero and less than or equal to m-1, g≠h, and values of g and h that satisfy an-1,g,v%m≠an-1,h,v%m exist.) ... Condition #Ya-(n-1)

[0687] In the above, v is an integer no smaller than four and less than or equal to rn-1, and Condition #Ya-(n-1) holds true for all conforming v.

[0688] By ensuring that the conditions above are satisfied, a minimum column weight of each of a partial matrix pertaining to information X1, a partial matrix pertaining to information X2, ..., a partial matrix pertaining to information Xn-1 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme is set to three. As such, the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme, when satisfying the above conditions, produces an irregular LDPC code, and high error correction capability is achieved.

[0689] Based on the conditions above, an LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme, and achieving high error correction capability, can be generated. Note that, in order to easily obtain an LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme, and achieving high error correction capability, it is desirable that r1=r2=...=rn-2=rn-1=r (where r is four or greater) be satisfied.

[0690] In the above, expression 93 and expression 94 have been used as the parity check polynomials for forming the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme. In the following, explanation is provided of examples of conditions to be applied to the parity check polynomials in expression 93 and expression 94 for achieving high error correction capability.

[0691] In order to achieve high error correction capability, when i is an integer no smaller than zero and less than or equal to m-1, each of r1,i, r2,i, ..., rn-2,i, rn-1,i is set to two or greater for all conforming i. In the following, explanation is provided of conditions for achieving high error correction capability in the above-described case.

[0692] As described above, the parity check polynomial that satisfies zero, according to expression 93, becomes an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m-1) that satisfies zero for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, and the parity check polynomial that satisfies zero, according to expression 94, becomes a parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix Hpro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2.

[0693] Here, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in the partial matrix pertaining to information X1 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme. Note that a column weight of a column α in a parity check matrix is defined as the number of ones existing among vector elements in a vector extracted from the column α.

(where, in the above, g is an integer no smaller than zero and less than or equal to m-1)

[0694] Similarly, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in the partial matrix pertaining to information X2 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme.

(where, in the above, g is an integer no smaller than zero and less than or equal to m-1)

[0695] Generalizing the above, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information Xk in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme (where k is an integer no smaller than one and less than or equal to n-1).

(where, in the above, g is an integer no smaller than zero and less than or equal to m-1)

[0696] Similarly, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information Xn-1 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme.

(where, in the above, g is an integer no smaller than zero and less than or equal to m-1)

[0697] In the above, % means a modulo, and for example, α%m represents a remainder after dividing α by m. Conditions #B-9-1 through #B-9-(n-1) are also expressible as follows. In the following, j is one or two.



[0698] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, and a1,g,j%m=v1,j (where v1,j is a fixed value) holds true for all conforming g.)



[0699] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, and a2,g,j%m=v2,j (where v2,j is a fixed value) holds true for all conforming g.) ⋮

[0700] The following is a generalization of the above.



[0701] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, and ak,g,j%m=vk,j (where vk,j is a fixed value) holds true for all conforming g.)

[0702] (In the above, k is an integer no smaller than one and less than or equal to n-1.) ⋮



[0703] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, and an-1,g,j%m=vn-1,j (where vn-1,j is a fixed value) holds true for all conforming g.)

[0704] Further, high error-correction capability is achievable when the following conditions are also satisfied.





[0705] The following is a generalization of the above.

(where, in the above, k is an integer no smaller than one and less than or equal to n-1)




[0706] By ensuring that the conditions above are satisfied, a minimum column weight of each of a partial matrix pertaining to information X1, a partial matrix pertaining to information X2, ..., a partial matrix pertaining to information Xn-1 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme is set to three. As such, the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme, when satisfying the above conditions, produces an irregular LDPC code, and high error correction capability is achieved.

[0707] In addition, it may be desirable that, when drawing a tree, check nodes corresponding to the parity check polynomials of expression 93 and expression 94, which are parity check polynomials for forming the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme, appear in a great number as possible in the tree.

[0708] In order to ensure that check nodes corresponding to the parity check polynomials of expression 93 and expression 94 appear in a great number as possible in the above-described tree, it is desirable that vk,1 and vk,2 (where k is an integer no smaller than one and less than or equal to n-1) as described above satisfy the following conditions.

<Condition #B-11-1>



[0709] 
  • When expressing a set of divisors of m other than one as R, vk,1 is not to belong to R.

<Condition #B-11-2>



[0710] 
  • When expressing a set of divisors of m other than one as R, vk,2 is not to belong to R.


[0711] In addition to the above-described conditions, the following conditions may further be satisfied.

<Condition #B-12-1>



[0712] 
  • vk,1 belongs to a set of integers no smaller than one and less than or equal to m-1, and vk,1 also satisfies the following condition. When expressing a set of values w obtained by extracting all values w satisfying vk,1/w=g (where g is a natural number) as S, an intersection R∩S produces an empty set. The set R has been defined in Condition #B-11-1.

<Condition #B-12-2>



[0713] 
  • vk,2 belongs to a set of integers no smaller than one and less than or equal to m-1, and vk,2 also satisfies the following condition. When expressing a set of values w obtained by extracting all values w satisfying vk,2/w=g (where g is a natural number) as S, an intersection R∩S produces an empty set. The set R has been defined in Condition #B-11-2.


[0714] Condition #B-12-1 and Condition #B-12-2 are also expressible as Condition #B-12-1' and Condition #B-12-2', respectively.

<Condition #B-12-1'>



[0715] 
  • vk,1 belongs to a set of integers no smaller than one and less than or equal to m-1, and vk,1 also satisfies the following condition. When expressing a set of divisors of vk,1 as S, an intersection R∩S produces an empty set.

<Condition #B-12-2'>



[0716] 
  • vk,2 belongs to a set of integers no smaller than one and less than or equal to m-1, and vk,2 also satisfies the following condition. When expressing a set of divisors of vk,2 as S, an intersection R∩S produces an empty set.


[0717] Condition #B-12-1 and Condition #B-12-1' are also expressible as Condition #B-12-1", and Condition #B-12-2 and Condition #B-12-2' are also expressible as Condition #B-12-2".

<Condition #B-12-1">



[0718] 
  • vk,1 belongs to a set of integers no smaller than one and less than or equal to m-1, and vk,1 also satisfies the following condition. The greatest common divisor of vk,1 and m is one.

<Condition #B-12-2">



[0719] 
  • vk,2 belongs to a set of integers no smaller than one and less than or equal to m-1, and vk,2 also satisfies the following condition. The greatest common divisor of vk,2 and m is one.


[0720] In the above, expression 95 and expression 96 have been used as the parity check polynomials for forming the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme. In the following, explanation is provided of examples of conditions to be applied to the parity check polynomials in expression 95 and expression 96 for achieving high error correction capability.

[0721] In order to achieve high error correction capability, when i is an integer no smaller than zero and less than or equal to m-1, each of r1,i, r2,i, ..., rn-2,i, rn-1,i is set to three or greater for all conforming i. In the following, explanation is provided of conditions for achieving high error correction capability in the above-described case.

[0722] As described above, the parity check polynomial that satisfies zero, according to expression 95, becomes an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m-1) that satisfies zero for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, and the parity check polynomial that satisfies zero, according to expression 96, becomes a parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix Hpro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2.

[0723] Here, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in the partial matrix pertaining to information X1 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme. Note that a column weight of a column α in a parity check matrix is defined as the number of ones existing among vector elements in a vector extracted from the column α.

(where, in the above, g is an integer no smaller than zero and less than or equal to m-1)

[0724] Similarly, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in the partial matrix pertaining to information X2 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme.

(where, in the above, g is an integer no smaller than zero and less than or equal to m-1)

[0725] Generalizing the above, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information Xk in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme (where k is an integer no smaller than one and less than or equal to n-1).

(where, in the above, g is an integer no smaller than zero and less than or equal to m-1)

[0726] Similarly, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information Xn-1 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme.

(where, in the above, g is an integer no smaller than zero and less than or equal to m-1)

[0727] In the above, % means a modulo, and for example, α%m represents a remainder after dividing α by m. Conditions #B-13-1 through #B-13-(n-1) are also expressible as follows. In the following, j is one, two, or three.



[0728] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, and a1,g,j%m=v1,j (where v1,j is a fixed value) holds true for all conforming g.)



[0729] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, and a2,g,j%m=v2,j (where v2,j is a fixed value) holds true for all conforming g.) ⋮

[0730] The following is a generalization of the above.



[0731] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, and ak,g,j%m=vk,j (where vk,j is a fixed value) holds true for all conforming g.)

[0732] (In the above, k is an integer no smaller than one and less than or equal to n-1.) ⋮



[0733] (The above indicates that g is an integer no smaller than zero and less than or equal to m-1, and an-1,g,j%m=vn-1,j (where vn-1,j is a fixed value) holds true for all conforming g.)

[0734] Further, high error-correction capability is achievable when the following conditions are also satisfied.





[0735] The following is a generalization of the above.

(where, in the above, k is an integer no smaller than one and less than or equal to n-1)



[0736] By ensuring that the conditions above are satisfied, a minimum column weight of each of a partial matrix pertaining to information X1, a partial matrix pertaining to information X2, ..., a partial matrix pertaining to information Xn-1 in the parity check matrix Hpro_m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme is set to three. As such, the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme, when satisfying the above conditions, produces an irregular LDPC code, and high error correction capability is achieved.

[0737] Description is provided on specific examples of the configuration of a parity check matrix for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2. An LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme, when generated as described above, may achieve high error correction capability. Due to this, an advantageous effect is realized such that a receiving device having a decoder, which may be included in a broadcasting system, a communication system, etc., is capable of achieving high data reception quality. Note that the configuration methods of codes described in the present embodiment are mere examples, and an LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme generated according to a method different from those explained above may also achieve high error correction capability.

[0738] In the above, description is provided of an example of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2. In the example described above, explanation is provided of using a parity check polynomial that satisfies zero for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n-1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n-1)/n using the improved tail-biting scheme described in Patent Literature 2, and further, of applying a specific parity check polynomial satisfying zero to the first row of a parity check matrix. Note that Patent Literature 2 also describes applying a specific parity check polynomial satisfying zero to a jth row of a parity check matrix (where j is a natural number).

[0739] While describing an LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of (n-1)/n (n being an integer no smaller than two) using an improved tail-biting scheme, Patent Literature 2 does not disclose an LDPC-CC (an LDPC block code using LDPC-CC) that uses an improved tail-biting scheme and does not satisfy coding rate (n-1)/n (n being an integer no smaller than two).

[0740] The present invention is related to an LDPC-CC (an LDPC block code using LDPC-CC) that uses an improved tail-biting scheme and does not satisfy coding rate (n-1)/n (n being an integer no smaller than two).

(Embodiment 1)



[0741] The present embodiment describes a method of configuring an LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, as one example of an LDPC-CC not satisfying coding rate (n-1)/n.

[0742] Although coding rate 2/4 equals coding rate 1/2, the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial pertaining to the present embodiment differs, in terms of generation method, from a conventional LDPC-CC of coding rate (n-1)/n or a conventional LDPC-CC of coding rate (n-1)/n that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[0743] Bits of information bits X1, X2 and parity bits P1, P2, at time point j, are expressed X1,j, X2,j and P1,j, P2,j, respectively.

[0744] A vector uj, at time point j, is expressed uj = (X1,j, X2,j, P1,j, P2,j).

[0745] Given a delay operator D, polynomial expressions of the information bits X1, X2 are X1(D), X2(D), and polynomial expressions of the parity bits P1, P2 are P1(D), P2(D).

[0746] Further, consideration is given to an LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial.

[0747] The following mathematical expressions are provided as parity check polynomials satisfying zero for an LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial.

[0748] First, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1×P2(D).
[Math. 97]









[0749] In expression (97-1-1), (97-1-2), (97-2-1), (97-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[0750] In expression (97-1-1), (97-1-2), (97-2-1), (97-2-2), α#(2i),p,q (where p is an integer no smaller than one and no greater than two, q is an integer no smaller than one and no greater than r#(2i),p (where r#(2i),p is a natural number)) and β#(2i),0 is a natural number, β#(2i),1 is a natural number, β#(2i),2 is an integer no smaller than zero, and β#(2i),3 is a natural number.

[0751] Further, y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for (y,z) where y≠z. ∀ is a universal quantifier, (y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for all y and all z satisfying y≠z.)

[0752] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (97-1-1) or expression (97-1-2) is referred to as "#(2i); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (97-2-1) or expression (97-2-2) is referred to as "#(2i); second expression" for realizing a time-varying period 2m.

[0753] Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (97-1-1) or expression (97-1-2) is prepared.

[0754] That is, for i=0, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=0 is prepared.

[0755] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=m-1 is prepared.



[0756] Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (97-2-1) or expression (97-2-2) is prepared.

[0757] That is, for i=0, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=0 is prepared.

[0758] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=m-1 is prepared.



[0759] Similarly, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1×P2(D).
[Math. 98]









[0760] In expression (98-1-1), (98-1-2), (98-2-1), (98-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0,1, ..., m-2, m-1).

[0761] In expression (98-1-1), (98-1-2), (98-2-1), (98-2-2), α#(2i+1),p,q (where p is an integer no smaller than one and no greater than two, q is an integer no smaller than one and no greater than r#(2i+1),p (where r#(2i+1),p is a natural number)) and β#(2i+1),0 is a natural number, β#(2i+1),1 is a natural number, β#(2i+1),2 is an integer no smaller than zero, and β#(2i+1),3 is a natural number.

[0762] Further, y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for (y,z) where y≠z. ∀ is a universal quantifier, (y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for all y and all z satisfying y≠z.)

[0763] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (98-1-1) or expression (98-1-2) is referred to as "#(2i+1); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (98-2-1) or expression (98-2-2) is referred to as "#(2i+1); second expression" for realizing a time-varying period 2m.

[0764] Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (98-1-1) or expression (98-1-2) is prepared.

[0765] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=0 is prepared.

[0766] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=m-1 is prepared.



[0767] Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (98-2-1) or expression (98-2-2) is prepared.

[0768] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=0 is prepared.

[0769] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=m-1 is prepared.



[0770] As such, an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0771] Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (97-1-1) or expression (97-1-2), parity check polynomials satisfying zero provided by expression (97-2-1) or expression (97-2-2), parity check polynomials satisfying zero provided by expression (98-1-1) or expression (98-1-2), and parity check polynomials satisfying zero provided by expression (98-2-1) or expression (98-2-2).

[0772] For example, the time varying period 2×m can be formed by preparing a 4×m number of different parity check polynomials satisfying zero.

[0773] Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

[0774] The following describes the relationship between time point j and expression (97-1-1), (97-1-2), (97-2-1), (97-2-2), (98-1-1), (98-1-2), (98-2-1), and (98-2-2) (where j is an integer no smaller than zero).

[0775] The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m-1).

[0776] Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i = k in #(2i); first expression and #(2i); second expression, hold true.

[0777] Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m-1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

[0778] The following describes a method of configuring a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0779] As already described above, a vector uj at time point j is expressed as uj=(X1,j, X2,j, P1,j, P2,j) (where j is an integer no smaller than zero). In the following, a case where u is a transmission vector is considered. Note that in the following, j is an integer no smaller than one, and thus j differs between the description having been provided above and the description provided in the following. (j is set as such to facilitate understanding of the correspondence between the column numbers and the row numbers of the parity check matrix.)

[0780] Accordingly, u=(u1, u2, u3, ..., uy-1, uy, Uy+1, ...)T=(X1,1, X2,1, P1,1, P2,1, X1,2, X2,2, P1,2, P2,2, X1,3, X2,3, P1,3, P2,3, ..., X1,y-1, X2,y-1, P1,y-1, P2,y-1, X1,y, X2,y, P1,y, P2,y, X1,y+1, X2,y+1, P1,y+1, P2,y+1, ...)T. Further, when using H to denote a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, Hu=0 holds true (here, Hu=0 indicates that all elements of the vector Hu are zeroes).

[0781] FIG. 37 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the topmost row of the parity check matrix is considered as the first row. Further, row number is incremented by one each time moving to a lower row. Accordingly, the topmost row is considered as the first row, the row immediately below the first row is considered as the second row, and the subsequent rows are considered as the third row, the fourth row, and so on.

[0782] As illustrated in FIG. 37:

"a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";
"a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×(2m-1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression";

"a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression";

"a vector for the 2×(2m+1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the 2×(2m+2)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×i-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); first expression"; and

"a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); second expression", and so on (where i is an integer no smaller than one).



[0783] FIG. 38 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the leftmost column of the parity check matrix is considered as the first column. Further, column number is incremented by one each time moving to a rightward column. Accordingly, the leftmost column is considered as the first column, the column immediately to the right of the first column is considered as the second column, and the subsequent columns are considered as the third column, the fourth column, and so on.

[0784] As illustrated in FIG. 38:

"a vector for the first column of the parity check matrix H is related to X1 at time point 1";

"a vector for the second column of the parity check matrix H is related to X2 at time point 1";

"a vector for the third column of the parity check matrix H is related to P1 at time point 1";

"a vector for the fourth column of the parity check matrix H is related to P2 at time point 1";

"a vector for the 4×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 4×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 4×(j-1)+3th column of the parity check matrix H is related to P1 at time point j"; and

"a vector for the 4×(j-1)+4th column of the parity check matrix H is related to P2 at time point j", and so on (where j is an integer no smaller than one).



[0785] FIG. 39 indicates a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0786] The following focuses on 1×X1(D), 1×X2(D), 1×P1(D), 1×P2(D) in the parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0787] The parity check polynomials at time point j=1 are parity check polynomials when i=0 in expression (97-1-1), (97-1-2), (97-2-1), (97-2-2).

[0788] A vector for the first row in FIG. 39 can be generated from a parity check polynomial when i=0 in expression (97-1-1) or expression (97-1-2) (refer to FIG. 37).

[0789] In expression (97-1-1) and (97-1-2):
  • a term for 1×X1(D) exists;
  • a term for 1×X2(D) does not exist; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[0790] Further, the relationship between column numbers and X1, X2, P1, P2 is as indicated in FIG. 38. Based on the relationship indicated in FIG. 38 and the fact that a term for 1×X1(D) exists, a column related to X1 in the vector for the first row in FIG. 39 is "1". Further, based on the relationship indicated in FIG. 38 and the fact that a term for 1×X2(D) does not exist, a column related to X2 in the vector for the first row in FIG. 39 is "0". In addition, based on the relationship indicated in FIG. 38 and the fact that a term for 1×P1(D) exists but a term for 1×P2(D) does not exist, a column related to P1 in the vector for the first row in FIG. 39 is "1", and a column related to P2 in the vector for the first row in FIG. 39 is "0".

[0791] As such, the vector for the first row in Fig, 39 is "1010", as indicated by 3900-1 in FIG. 39.

[0792] A vector for the second row in FIG. 39 can be generated from a parity check polynomial when i=0 in expression (97-2-1) or expression (97-2-2) (refer to FIG. 37).

[0793] In expression (97-2-1) and (97-2-2):
  • a term for 1×X1(D) does not exist;
  • a term for 1×X2(D) exists; and
  • a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists.


[0794] Further, the relationship between column numbers and X1, X2, P1, P2 is as indicated in FIG. 38. Based on the relationship indicated in FIG. 38 and the fact that a term for 1×X1(D) does not exist, a column related to X1 in the vector for the second row in FIG. 39 is "0". Further, based on the relationship indicated in FIG. 38 and the fact that a term for 1×X2(D) exists, a column related to X2 in the vector for the second row in FIG. 39 is "1". In addition, based on the relationship indicated in FIG. 38 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the second row in FIG. 39 is "Y", and a column related to P2 in the vector for the second row in FIG. 39 is "1", where Y is either "0" or "1".

[0795] As such, the vector for the second row in Fig, 39 is "01Y1", as indicated by 3900-2 in FIG. 39.

[0796] The parity check polynomials at time point j=2 are parity check polynomials when i=0 in expression (98-1-1), (98-1-2), (98-2-1), (98-2-2).

[0797] A vector for the third row in FIG. 39 can be generated from a parity check polynomial when i=0 in expression (98-1-1) or expression (98-1-2) (refer to FIG. 37).

[0798] In expression (98-1-1) and (98-1-2):
  • a term for 1×X1(D) does not exist;
  • a term for 1×X2(D) exists; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[0799] Further, the relationship between column numbers and X1, X2, P1, P2 is as indicated in FIG. 38. Based on the relationship indicated in FIG. 38 and the fact that a term for 1×X1(D) does not exist, a column related to X1 in the vector for the third row in FIG. 39 is "0". Further, based on the relationship indicated in FIG. 38 and the fact that a term for 1×X2(D) exists, a column related to X2 in the vector for the third row in FIG. 39 is "1". In addition, based on the relationship indicated in FIG. 38 and the fact that a term for 1×P1(D) exists but a term for 1×P2(D) does not exist, a column related to P1 in the vector for the third row in FIG. 39 is "1", and a column related to P2 in the vector for the third row in FIG. 39 is "0".

[0800] As such, the vector for the third row in Fig, 39 is "0110", as indicated by 3901-1 in FIG. 39.

[0801] A vector for the fourth row in FIG. 39 can be generated from a parity check polynomial when i=0 in expression (98-2-1) or expression (98-2-2) (refer to FIG. 37).

[0802] In expression (98-2-1) and (98-2-2):
  • a term for 1×X1(D) exists;
  • a term for 1×X2(D) does not exist; and
  • a term for 1 ×P1(D) may or may not exist but a term for 1×P2(D) exists.


[0803] Further, the relationship between column numbers and X1, X2, P1, P2 is as indicated in FIG. 38. Based on the relationship indicated in FIG. 38 and the fact that a term for 1×X1(D) exists, a column related to X1 in the vector for the fourth row in FIG. 39 is "1". Further, based on the relationship indicated in FIG. 38 and the fact that a term for 1×X2(D) does not exist, a column related to X2 in the vector for the fourth row in FIG. 39 is "0". In addition, based on the relationship indicated in FIG. 38 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the fourth row in FIG. 39 is "Y", and a column related to P2 in the vector for the fourth row in FIG. 39 is "1".

[0804] As such, the vector for the fourth row in Fig, 39 is "10Y1", as indicated by 3901-2 in FIG. 39.

[0805] Because it can be considered that the above similarly applies to cases where time point j=3, 4, 5, the parity check matrix H has the configuration indicated in FIG. 39.

[0806] That is, due to the parity check polynomials of expression (97-1-1), (97-1-2), (97-2-1), (97-2-2) being used at time point j=2k+1 (where k is an integer no smaller than zero), "1010" exists in the 2×(2k+1)-1th row of the parity check matrix H, and "01Y1" exists in the 2×(2k+1)th row of the parity check matrix H, as illustrated in FIG. 39.

[0807] Further, due to the parity check polynomials of expression (98-1-1), (98-1-2), (98-2-1), (98-2-2) being used at time point j=2k+2 (where k is an integer no smaller than zero), "0110" exists in the 2×(2k+2)-1th row of the parity check matrix H, and "10Y1" exists in the 2×(2k+2)th row of the parity check matrix H, as illustrated in FIG. 39.

[0808] Accordingly, as illustrated in FIG. 39, when denoting a column number of a leftmost column corresponding to "1" in "1010" in a row where "1010" exists (e.g., 3900-1 in FIG. 39) as "a", "0110" (e.g., 3901-1 in FIG. 39) exists in a row that is two rows below the row where "1010" exists, starting from column "a+4".

[0809] Similarly, as illustrated in FIG. 39, when denoting a column number of a leftmost column corresponding to "1" in "01Y1" in a row where "01Y1" exists (e.g., 3900-2 in FIG. 39) as "b", "10Y1" (e.g., 3901-2 in FIG. 39) exists in a row that is two rows below the row where "01Y1" exists, starting from column "b+4".

[0810] Similarly, as illustrated in FIG. 39, when denoting a column number of a leftmost column corresponding to "1" in "0110" in a row where "0110" exists (e.g., 3901-1 in FIG. 39) as "c", "1010" (e.g., 3902-1 in FIG. 39) exists in a row that is two rows below the row where "0110" exists, starting from column "c+4".

[0811] Similarly, as illustrated in FIG. 39, when denoting a column number of a leftmost column corresponding to "1" in "10Y1" in a row where "10Y1" exists (e.g., 3901-2 in FIG. 39) as "d", "01Y1" (e.g., 3902-2 in FIG. 39) exists in a row that is two rows below the row where "10Y1" exists, starting from column "d+4".

[0812] The following describes a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial when tail-biting is not performed, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0813] In the following, Hcom[u][v] (where u and v are integers no smaller than one) denotes an element at row "u" column "v" of a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0814] Based on description above provided with reference to FIG. 37:

"a vector for the 2×g-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); first expression"; and

"a vector for the (2×g)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); second expression" (where g is an integer no smaller than one).



[0815] Based on description above provided with reference to FIG. 38:

"a vector for the 4×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 4×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 4×(j-1)+3th column of the parity check matrix H is related to P1 at time point j"; and

"a vector for the 4×(j-1)+4th column of the parity check matrix H is related to P2 at time point j" (where j is an integer no smaller than one).



[0816] Based on the above, the following describes component Hcom[2×g-1][v] in row 2×g-1 (where g is an integer no smaller than one) and component Hcom[2×g][v] in row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0817] As already described above, a parity check polynomial satisfying zero of #((g-1)%2m); first expression can be used to generate a vector for row 2×g-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0818] Further, a parity check polynomial satisfying zero of #((g-1)%2m); second expression can be used to generate a vector for row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0819] Accordingly, when g=2×f-1 (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (97-1-1) or expression (97-1-2), can be used to generate a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0820] Further, a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (97-2-1) or expression (97-2-2), can be used to generate a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0821] Further, when g=2×f (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (98-1-1) or expression (98-1-2), can be used to generate a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0822] Further, a parity check polynomial satisfying zero of #(((2×f)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (98-2-1) or expression (98-2-2), can be used to generate a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0823] Accordingly, (1) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-1-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-1-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[0824] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[0825] The following holds true for X1. In the following, w=1.
[Math. 99]





[0826] The following holds true for X2. In the following, z=2, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 100]



[0827] The following holds true for P1.
[Math. 101]



[0828] The following holds true for P2.
[Math. 102]



[0829] Further, (2) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-1-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-1-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[0830] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[0831] The following holds true for X1. In the following, w=1.
[Math. 103]



[0832] The following holds true for X2. In the following, z=2, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 104]



[0833] The following holds true for P1.
[Math. 105]



[0834] The following holds true for P2.
[Math. 106]



[0835] Further, (3) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-2-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-2-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[0836] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[0837] The following holds true for X1. In the following, z=1, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 107]



[0838] The following holds true for X2. In the following, w=2.
[Math. 108]



[0839] The following holds true for P1.
[Math. 109]



[0840] The following holds true for P2.
[Math. 110]





[0841] Further, (4) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-2-2), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-2-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[0842] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[0843] The following holds true for X1. In the following, z=1, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 111]



[0844] The following holds true for X2. In the following, w=2.
[Math. 112]



[0845] The following holds true for P1.
[Math. 113]



[0846] The following holds true for P2.
[Math. 114]



[0847] Further, (5) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-1-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-1-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[0848] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[0849] The following holds true for X1. In the following, z=1, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 115]



[0850] The following holds true for X2. In the following, w=2.
[Math. 116]



[0851] The following holds true for P1.
[Math. 117]



[0852] The following holds true for P2.
[Math. 118]



[0853] Further, (6) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-1-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-1-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[0854] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[0855] The following holds true for X1. In the following, z=1, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 119]



[0856] The following holds true for X2. In the following, w=2.
[Math. 120]



[0857] The following holds true for P1.
[Math. 121]



[0858] The following holds true for P2.
[Math. 122]



[0859] Further, (7) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-2-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-2-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[0860] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[0861] The following holds true for X1. In the following, w=1.
[Math. 123]



[0862] The following holds true for X2. In the following, z=2, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 124]



[0863] The following holds true for P1.
[Math. 125]



[0864] The following holds true for P2.
[Math. 126]



[0865] Further, (8) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-2-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-2-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[0866] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[0867] The following holds true for X1. In the following, w=1.
[Math. 127]



[0868] The following holds true for X2. In the following, z=2, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 128]



[0869] The following holds true for P1.
[Math. 129]



[0870] The following holds true for P2.
[Math. 130]



[0871] As such, an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial can be generated by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, and the code so generated achieves high error correction capability.

(Embodiment 2)



[0872] In the present embodiment, description is provided of a method of code configuration that is a generalization of the method described in embodiment 1 of configuring an LDPC-CC of coding rate 2/4 that is based on a parity check polynomial.

[0873] Bits of information bits X1, X2 and parity bits P1, P2, at time point j, are expressed X1,j, X2,j and P1,j, P2,j, respectively.

[0874] A vector uj, at time point j, is expressed uj = (X1,j, X2,j, P1,j, P2,j).

[0875] Given a delay operator D, polynomial expressions of the information bits X1, X2 are X1(D), X2(D), and polynomial expressions of the parity bits P1, P2 are P1(D), P2(D).

[0876] Further, consideration is given to an LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial.

[0877] The following mathematical expressions are provided as parity check polynomials satisfying zero for an LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial.

[0878] First, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1×P2(D).
[Math. 131]





[0879] In expression (131-1-1), (131-1-2), (131-2-1), (131-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[0880] In expression (131-1-1), (131-1-2), (131-2-1), (131-2-2), α#(2i),p,q (where p is an integer no smaller than one and no greater than two, q is an integer no smaller than one and no greater than r#(2i),p (where r#(2i),p is a natural number)) and β#(2i),0 is a natural number, β#(2i),1 is a natural number, β#(2i),2 is an integer no smaller than zero, and β#(2i),3 is a natural number.

[0881] Further, R#(2i),p is a natural number satisfying 1≤R#(2i),p<r#(2i),p.

[0882] Further, y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for all y and all z satisfying y≠z.

[0883] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (131-1-1) or expression (131-1-2) is referred to as "#(2i); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (131-2-1) or expression (131-2-2) is referred to as "#(2i); second expression" for realizing a time-varying period 2m.

[0884] Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (131-1-1) or expression (131-1-2) is prepared.

[0885] That is, for i=0, a parity check polynomial satisfying zero provided by expression (131-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (131-1-2) where i=0 is prepared.

[0886] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (131-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (131-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (131-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (131-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (131-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (131-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (131-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (131-1-2) where i=m-1 is prepared.



[0887] Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (131-2-1) or expression (131-2-2) is prepared.

[0888] That is, for i=0, a parity check polynomial satisfying zero provided by expression (131-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (131-2-2) where i=0 is prepared.

[0889] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (131-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (131-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (131-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (131-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (131-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (131-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (131-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (131-2-2) where i=m-1 is prepared.



[0890] Similarly, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1×P2(D).
[Math. 132]







[0891] In expression (132-1-1), (132-1-2), (132-2-1), (132-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[0892] In expression (132-1-1), (132-1-2), (132-2-1), (132-2-2), α#(2i+1),p,q (where p is an integer no smaller than one and no greater than two, q is an integer no smaller than one and no greater than r#(2i+1),p (where r#(2i+1),p is a natural number)) and β#(2i+1),0 is a natural number, β#(2i+1),1 is a natural number, β#(2i+1),2 is an integer no smaller than zero, and β#(2i+1),3 is a natural number.

[0893] Further, R#(2i+1),p is a natural number satisfying 1≤R#(2i+1),p<r#(2i+1),p.

[0894] Further, y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for all y and all z satisfying y ≠ z.)

[0895] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (132-1-1) or expression (132-1-2) is referred to as "#(2i+1); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (132-2-1) or expression (132-2-2) is referred to as "#(2i+1); second expression" for realizing a time-varying period 2m.

[0896] Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (132-1-1) or expression (132-1-2) is prepared.

[0897] That is, for i=0, a parity check polynomial satisfying zero provided by expression (132-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (132-1-2) where i=0 is prepared.

[0898] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (132-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (132-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (132-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (132-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (132-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (132-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (132-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (132-1-2) where i=m-1 is prepared.



[0899] Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (132-2-1) or expression (132-2-2) is prepared.

[0900] That is, for i=0, a parity check polynomial satisfying zero provided by expression (132-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (132-2-2) where i=0 is prepared.

[0901] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (132-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (132-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (132-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (132-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (132-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (132-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (132-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (132-2-2) where i=m-1 is prepared.



[0902] As such, an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0903] Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (131-1-1) or expression (131-1-2), parity check polynomials satisfying zero provided by expression (131-2-1) or expression (131-2-2), parity check polynomials satisfying zero provided by expression (132-1-1) or expression (132-1-2), and parity check polynomials satisfying zero provided by expression (132-2-1) or expression (132-2-2).

[0904] For example, the time varying period 2×m can be formed by preparing a 4×m number of different parity check polynomials satisfying zero.

[0905] Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

[0906] The following describes the relationship between time point j and expression (131-1-1), (131-1-2), (131-2-1), (131-2-2), (132-1-1), (132-1-2), (132-2-1), and (132-2-2) (where j is an integer no smaller than zero).

[0907] The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m-1).

[0908] Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i = k in #(2i); first expression and #(2i); second expression, hold true.

[0909] Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m-1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

[0910] The following describes a method of configuring a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0911] As already described above, a vector uj at time point j is expressed as uj=(X1,j, X2,j, P1,j, P2,j) (where j is an integer no smaller than zero). In the following, a case where u is a transmission vector is considered. Note that in the following, j is an integer no smaller than one, and thus j differs between the description having been provided above and the description provided in the following. (j is set as such to facilitate understanding of the correspondence between the column numbers and the row numbers of the parity check matrix.)

[0912] Accordingly, u=(u1, u2, u3, ..., uy-1, uy, uy+1, ...)T=(X1,1, X2,1, P1,1, P2,1, X1,2, X2,2, P1,2, P2,2, X1,3, X2,3, P1,3, P2,3, ..., X1,y-1, X2,y-1, P1,y-1, P2,y-1, X1,y, X2,y, P1,y, P2,y, X1,y+1, X2,y+1, P1,y+1, P2,y+1, ...)T. Further, when using H to denote a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, Hu=0 holds true (here, Hu=0 indicates that all elements of the vector Hu are zeroes).

[0913] FIG. 37 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the topmost row of the parity check matrix is considered as the first row. Further, row number is incremented by one each time moving to a lower row. Accordingly, the topmost row is considered as the first row, the row immediately below the first row is considered as the second row, and the subsequent rows are considered as the third row, the fourth row, and so on.

[0914] As illustrated in FIG. 37:

"a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";
"a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×(2m-1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression";

"a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression";

"a vector for the 2×(2m+1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the 2×(2m+2)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×i-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); first expression"; and

"a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); second expression", and so on (where i is an integer no smaller than one).



[0915] FIG. 38 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the leftmost column of the parity check matrix Hpro_m is considered as the first column. Further, column number is incremented by one each time moving to a rightward column. Accordingly, the leftmost column is considered as the first column, the column immediately to the right of the first column is considered as the second column, and the subsequent columns are considered as the third column, the fourth column, and so on.

[0916] As illustrated in FIG. 38:

"a vector for the first column of the parity check matrix H is related to X1 at time point 1";

"a vector for the second column of the parity check matrix H is related to X2 at time point 1";

"a vector for the third column of the parity check matrix H is related to P1 at time point 1";

"a vector for the fourth column of the parity check matrix H is related to P2 at time point 1";

"a vector for the 4×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 4×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 4×(j-1)+3th column of the parity check matrix H is related to P1 at time point j"; and

"a vector for the 4×(j-1)+4th column of the parity check matrix H is related to P2 at time point j", and so on (where j is an integer no smaller than one).



[0917] FIG. 39 indicates a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0918] The following focuses on 1×X1(D), 1×X2(D), 1×P1(D), 1×P2(D) in the parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0919] The parity check polynomials at time point j=1 are parity check polynomials when i=0 in expression (131-1-1), (131-1-2), (131-2-1), (131-2-2).

[0920] A vector for the first row in FIG. 39 can be generated from a parity check polynomial when i=0 in expression (131-1-1) or expression (131-1-2) (refer to FIG. 37).

[0921] In expression (131-1-1) and (131-1-2):
  • a term for 1×X1(D) exists;
  • a term for 1×X2(D) does not exist; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[0922] Further, the relationship between column numbers and X1, X2, P1, P2 is as indicated in FIG. 38. Based on the relationship indicated in FIG. 38 and the fact that an item for 1×X1(D) exists, a column related to X1 in the vector for the first row in FIG. 39 is "1". Further, based on the relationship indicated in FIG. 38 and the fact that an item for 1×X2(D) does not exist, a column related to X2 in the vector for the first row in FIG. 39 is "0". In addition, based on the relationship indicated in FIG. 38 and the fact that an item for 1×P1(D) exists but an item for 1×P2(D) does not exist, a column related to P1 in the vector for the first row in FIG. 39 is "1", and a column related to P2 in the vector for the first row in FIG. 39 is "0".

[0923] As such, the vector for the first row in Fig, 39 is "1010", as indicated by 3900-1 in FIG. 39.

[0924] A vector for the second row in FIG. 39 can be generated from a parity check polynomial when i=0 in expression (131-2-1) or expression (131-2-2) (refer to FIG. 37).

[0925] In expression (131-2-1) and (131-2-2):
  • a term for 1×X1(D) does not exist;
  • a term for 1×X2(D) exists; and
  • a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists.


[0926] Further, the relationship between column numbers and X1, X2, P1, P2 is as indicated in FIG. 38. Based on the relationship indicated in FIG. 38 and the fact that an item for 1×X1(D) does not exist, a column related to X1 in the vector for the second row in FIG. 39 is "0". Further, based on the relationship indicated in FIG. 38 and the fact that an item for 1×X2(D) exists, a column related to X2 in the vector for the second row in FIG. 39 is "1". In addition, based on the relationship indicated in FIG. 38 and the fact that an item for 1×P1(D) may or may not exist but an item for 1×P2(D) exists, a column related to P1 in the vector for the second row in FIG. 39 is "Y", and a column related to P2 in the vector for the second row in FIG. 39 is "1", where Y is either "0" or "1".

[0927] As such, the vector for the second row in Fig, 39 is "01Y1", as indicated by 3900-2 in FIG. 39.

[0928] The parity check polynomials at time point j = 2 are parity check polynomials when i=0 in expression (132-1-1), (132-1-2), (132-2-1), (132-2-2).

[0929] A vector for the third row in FIG. 39 can be generated from a parity check polynomial when i=0 in expression (132-1-1) or expression (132-1-2) (refer to FIG. 37).

[0930] In expression (132-1-1) and (132-1-2):
  • a term for 1×X1(D) does not exist;
  • a term for 1×X2(D) exists; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[0931] Further, the relationship between column numbers and X1, X2, P1, P2 is as indicated in FIG. 38. Based on the relationship indicated in FIG. 38 and the fact that an item for 1×X1(D) does not exist, a column related to X1 in the vector for the third row in FIG. 39 is "0". Further, based on the relationship indicated in FIG. 38 and the fact that an item for 1×X2(D) exists, a column related to X2 in the vector for the third row in FIG. 39 is "1". In addition, based on the relationship indicated in FIG. 38 and the fact that an item for 1×P1(D) exists but an item for 1×P2(D) does not exist, a column related to P1 in the vector for the third row in FIG. 39 is "1", and a column related to P2 in the vector for the third row in FIG. 39 is "0".

[0932] As such, the vector for the third row in Fig, 39 is "0110", as indicated by 3901-1 in FIG. 39.

[0933] A vector for the fourth row in FIG. 39 can be generated from a parity check polynomial when i=0 in expression (132-2-1) or expression (132-2-2) (refer to FIG. 37).

[0934] In expression (132-2-1) and (132-2-2):
  • a term for 1×X1(D) exists;
  • a term for 1×X2(D) does not exist; and
  • a term for 1 ×P1(D) may or may not exist but a term for 1×P2(D) exists.


[0935] Further, the relationship between column numbers and X1, X2, P1, P2 is as indicated in FIG. 38. Based on the relationship indicated in FIG. 38 and the fact that an item for 1×X1(D) exists, a column related to X1 in the vector for the fourth row in FIG. 39 is "1". Further, based on the relationship indicated in FIG. 38 and the fact that an item for 1×X2(D) does not exist, a column related to X2 in the vector for the fourth row in FIG. 39 is "0". In addition, based on the relationship indicated in FIG. 38 and the fact that an item for 1×P1(D) may or may not exist but an item for 1×P2(D) exists, a column related to P1 in the vector for the fourth row in FIG. 39 is "Y", and a column related to P2 in the vector for the fourth row in FIG. 39 is "1".

[0936] As such, the vector for the fourth row in Fig, 39 is "10Y1", as indicated by 3901-2 in FIG. 39.

[0937] Because it can be considered that the above similarly applies to cases where time point j=3, 4, 5, the parity check matrix H has the configuration indicated in FIG. 39.

[0938] That is, due to the parity check polynomials of expression (131-1-1), (131-1-2), (131-2-1), (131-2-2) being used at time point j=2k+1 (where k is an integer no smaller than zero), "1010" exists in the 2×(2k+1)-1th row of the parity check matrix H, and "01Y1" exists in the 2×(2k+1)th row of the parity check matrix H, as illustrated in FIG. 39.

[0939] Further, due to the parity check polynomials of expression (132-1-1), (132-1-2), (132-2-1), (132-2-2) being used at time point j=2k+2 (where k is an integer no smaller than zero), "0110" exists in the 2×(2k+2)-1th row of the parity check matrix H, and "10Y1" exists in the 2×(2k+2)th row of the parity check matrix H, as illustrated in FIG. 39.

[0940] Accordingly, as illustrated in FIG. 39, when denoting a column number of a leftmost column corresponding to "1" in "1010" in a row where "1010" exists (e.g., 3900-1 in FIG. 39) as "a", "0110" (e.g., 3901-1 in FIG. 39) exists in a row that is two rows below the row where "1010" exists, starting from column "a+4".

[0941] Similarly, as illustrated in FIG. 39, when denoting a column number of a leftmost column corresponding to "1" in "01Y1" in a row where "01Y1" exists (e.g., 3900-2 in FIG. 39) as "b", "10Y1" (e.g., 3901-2 in FIG. 39) exists in a row that is two rows below the row where "01Y1" exists, starting from column "b+4".

[0942] Similarly, as illustrated in FIG. 39, when denoting a column number of a leftmost column corresponding to "1" in "0110" in a row where "0110" exists (e.g., 3901-1 in FIG. 39) as "c", "1010" (e.g., 3902-1 in FIG. 39) exists in a row that is two rows below the row where "0110" exists, starting from column "c+4".

[0943] Similarly, as illustrated in FIG. 39, when denoting a column number of a leftmost column corresponding to "1" in "10Y1" in a row where "10Y1" exists (e.g., 3901-2 in FIG. 39) as "d", "01Y1" (e.g., 3902-2 in FIG. 39) exists in a row that is two rows below the row where "0110" exists, starting from column "d+4".

[0944] The following describes a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial when tail-biting is not performed, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0945] In the following, Hcom[u][v] (where u and v are integers no smaller than one) denotes an element at row "u" column "v" of a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0946] Based on description above provided with reference to FIG. 37:

"a vector for the 2×g-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); first expression"; and

"a vector for the (2×g)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); second expression" (where g is an integer no smaller than one).



[0947]  Based on description above provided with reference to FIG. 38:

"a vector for the 4×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 4×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 4×(j-1)+3th column of the parity check matrix H is related to P1 at time point j"; and

"a vector for the 4×(j-1)+4th column of the parity check matrix H is related to P2 at time point j" (where j is an integer no smaller than one).



[0948] Based on the above, the following describes component Hcom[2×g-1][v] in row 2×g-1 (where g is an integer no smaller than one) and component Hcom[2×g][v] in row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0949] As already described above, a parity check polynomial satisfying zero of #((g-1)%2m); first expression can be used to generate a vector for row 2×g-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0950] Further, a parity check polynomial satisfying zero of #((g-1)%2m); second expression can be used to generate a vector for row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0951] Accordingly, when g=2×f-1 (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (131-1-1) or expression (131-1-2), can be used to generate a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0952] Further, a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (131-2-1) or expression (131-2-2), can be used to generate a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0953] Further, when g=2×f (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (132-1-1) or expression (132-1-2), can be used to generate a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0954] Further, a parity check polynomial satisfying zero of #(((2×f)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (132-2-1) or expression (132-2-2), can be used to generate a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[0955] Accordingly, (1) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (131-1-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (131-1-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[0956] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[0957] The following holds true for X1. In the following, w=1.
[Math. 133]



[0958] The following holds true for X2. In the following, z=2, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 134]



[0959] The following holds true for P1.
[Math. 135]



[0960] The following holds true for P2.
[Math. 136]



[0961] Further, (2) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (131-1-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (131-1-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[0962] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[0963] The following holds true for X1. In the following, w=1.
[Math. 137]



[0964] The following holds true for X2. In the following, z=2, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 138]



[0965] The following holds true for P1.
[Math. 139]





[0966] The following holds true for P2.
[Math. 140]



[0967] Further, (3) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (131-2-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (131-2-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[0968] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[0969] The following holds true for X1. In the following, z=1, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 141]





[0970] The following holds true for X2. In the following, w=2.
[Math. 142]



[0971] The following holds true for P1.
[Math. 143]



[0972] The following holds true for P2.
[Math. 144]

Further, (4) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (131-2-2), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (131-2-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[0973] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[0974] The following holds true for X1. In the following, z=1, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 145]



[0975] The following holds true for X2. In the following, w=2.
[Math. 146]



[0976] The following holds true for P1.
[Math. 147]



[0977] The following holds true for P2.
[Math. 114]



[0978] Further, (5) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (132-1-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (132-1-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[0979] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[0980] The following holds true for X1. In the following, z=1, and y is an integer no smaller than R#(2d+1),z+1 and no greater than r#(2d+1),z.
[Math. 149]



[0981] The following holds true for X2. In the following, w=2.
[Math. 150]



[0982] The following holds true for P1.
[Math. 151]



[0983] The following holds true for P2.
[Math. 152]



[0984] Further, (6) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (132-1-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (132-1-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[0985] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[0986] The following holds true for X1. In the following, z=1, and y is an integer no smaller than R#(2d+1),z+1 and no greater than r#(2d+1),z.
[Math. 153]



[0987] The following holds true for X2. In the following, w=2.
[Math. 154]





[0988] The following holds true for P1.
[Math. 155]



[0989] The following holds true for P2.
[Math. 156]



[0990] Further, (7) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (132-2-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (132-2-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[0991] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[0992] The following holds true for X1. In the following, w=1.
[Math. 157]



[0993] The following holds true for X2. In the following, z=2, and y is an integer no smaller than R#(2d+1),z+1 and no greater than r#(2d+1),z.
[Math. 158]



[0994] The following holds true for P1.
[Math. 159]



[0995] The following holds true for P2.
[Math. 160]



[0996] Further, (8) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (132-2-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (132-2-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[0997] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[0998] The following holds true for X1. In the following, w=1.
[Math. 161]



[0999] The following holds true for X2. In the following, z=2, and y is an integer no smaller than R#(2d+1),z+1 and no greater than r#(2d+1),z.
[Math. 162]



[1000] The following holds true for P1.
[Math. 163]



[1001] The following holds true for P2.
[Math. 164]



[1002] As such, an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial can be generated by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, and the code so generated achieves high error correction capability.

(Embodiment 3)



[1003] In the present embodiment, description is provided of a device that uses the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2.

[1004] As one example, description is provided of a case where the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2, is applied to a communication device.

[1005] FIG. 22 illustrates the structures of a transmitting device 2200 and a receiving device 2210 in the communication device pertaining to the present embodiment.

[1006] An encoder 2201 receives information to be transmitted as input, and is capable of performing various types of encoding. In particular, when receiving a specification to perform encoding by using the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2, the encoder 2201 performs encoding by using the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2, to calculate parities P1 and P2. Further, the encoder 2201 outputs the information to be transmitted and the parities P1 and P2 as a transmission sequence.

[1007] A modulator 2202 receives the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, performs mapping based on a predetermined modulation scheme (e.g., BPSK, QPSK, 16QAM, 64QAM), and outputs a baseband signal. Further, the modulator 2202 may also receive information other than the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, as input, perform mapping, and output a baseband signal. For example, the modulator 2202 may receive control information as input.

[1008] The transmitting device outputs a transmission signal after performing predetermined signal processing (e.g., signal processing for generation of an OFDM signal, frequency conversion, amplification) with respect to such signals (e.g., baseband signals, pilot signals). The transmitting device may transmit the transmission signal over a wireless transmission path utilizing electromagnetic waves, or over a wired transmission path utilizing a coaxial cable, a power line, an optical cable, or the like.

[1009] The transmission signal is received by the receiving device 2210 after travelling over the transmission path. A receiver 2211 receives a reception signal as input, performs predetermined signal processing (e.g., bandwidth limitation, frequency conversion, signal processing for OFDM, frequency offset estimation, signal detection, channel estimation), and outputs a baseband signal and a channel estimation signal.

[1010] A log-likelihood ratio generation section 2212 receives the baseband signal and the channel estimation signal as input (may receive other signals as input), and for example, calculates and outputs a log-likelihood ratio for each bit (may calculate and output a hard value (hard decision value)).

[1011] A decoder 2213 receives the log-likelihood ratio for each bit as input, performs belief propagation decoding (e.g., sum-product decoding, scheduled sum-product decoding (Layered BP (belief propagation) decoding), min-sum decoding, Normalized BP decoding, offset BP decoding), and outputs an estimation sequence. The decoder 2213 performs the belief propagation decoding based on the parity check matrix for the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2.

[1012] FIG. 40 illustrates one example of the structure of an encoder for the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2. Description on such an encoder has been provided with reference to the encoder 2201 in FIG. 22.

[1013] In FIG. 40, an Xz computation section 4001-z (where z is an integer no smaller than one and no greater than two) includes a plurality of shift registers that are connected in series and a calculator that performs XOR calculation on bits collected from some of the shift registers (refer to FIGs. 2 and 22).

[1014] The Xz computation section 4001-z receives an information bit Xz,j at time point j as input, performs the XOR calculation, and outputs bits 4002-z-1 and 4002-z-2, which are acquired through the Xz calculation.

[1015] A P1 computation section 4004-1 includes a plurality of shift registers that are connected in series and a calculator that that performs XOR calculation on bits collected from some of the shift registers (refer to FIGs. 2 and 22).

[1016] The P1 computation section 4004-1 receives a bit P1,j of parity P1 at time point j as input, performs the XOR calculation, and outputs bits 4005-1-1 and 4005-1-2, which are acquired through the P1 calculation.

[1017] A P2 computation section 4004-2 includes a plurality of shift registers that are connected in series and a calculator that that performs XOR calculation on bits collected from some of the shift registers (refer to FIGs. 2 and 22).

[1018] The P2 computation section 4004-2 receives a bit P2,j of parity P2 at time point j as input, performs the XOR calculation, and outputs bits 4005-2-1 and 4005-2-2, which are acquired through the P2 calculation.

[1019] An XOR (calculator) 4005-1 receives the bit 4002-1-1 acquired by X1 calculation, the bit 4002-2-1 acquired by X2 calculation, the bit 4005-1-1 acquired by P1 calculation, and the bit 4005-2-1 acquired by the P2 calculation as input, performs XOR calculation, and outputs a bit P1,j of parity P1 at time point j.

[1020] An XOR (calculator) 4005-2 receives the bit 4002-1-2 acquired by X1 calculation, the bit 4002-2-2 acquired by X2 calculation, the bit 4005-1-2 acquired by P1 calculation, and the bit 4005-2-2 acquired by the P2 calculation as input, performs XOR calculation, and outputs a bit P2,j of parity P2 at time point j.

[1021] It is preferable that initial values of the shift registers of the Xz computation section 4001-z, the P1 computation section 4004-1, and the P2 computation section 4004-2 illustrated in FIG. 40 be set to "0" (zero). By making such a configuration, it becomes unnecessary to transmit to the receiving device parities P1 and P2 before the setting of initial values.

[1022] The following describes a method of information-zero termination.

[1023] Suppose that in FIG. 41, information X1 and information X2 exist from time point 0, and information X2 at time point s (where s is an integer no smaller than zero) is the last information bit. That is, suppose that the information to be transmitted from the transmitting device to the receiving device is information X1,j and information X2,j, being information X1 and information X2 at time point j, respectively, where j is an integer no smaller than zero and no greater than s.

[1024] In such a case, the transmitting device transmits information X1, information X2, parity P1, and parity P2 from time point 0 to time point s, or that is, transmits X1,j, X2,j, P1,j, P2,j, where j is an integer no smaller than zero and no greater than s. (Note that P1,j and P2,j denote parity P1 and parity P2 at time point j, respectively.)

[1025] Further, suppose that information X1 and information X2 from time point s+1 to time point s+g (where g is an integer no smaller than one) is "0", or that is, when denoting information X1 and information X2 at time point t as X1,t, X2,t, respectively, X1,t=0 and X2,t=0 hold true for t being an integer no smaller than s+1 and no greater than s+g. The transmitting device, by performing encoding, acquires parities P1,t and P2,t for t being an integer no smaller than s+1 and no greater than s+g. The transmitting device, in addition to the information and parities described above, transmits parities P1,t and P2,t for t being an integer no smaller than s+1 and no greater than s+g.

[1026] Meanwhile, the receiving device performs decoding by using log-likelihood ratios for the information and the parities transmitted by the transmitting device, and log-likelihood ratios corresponding to X1,t=0 and X2,t=0 for t being an integer no smaller than s+1 and no greater than s+g, and thereby acquires an estimation sequence of information.

[1027] FIG. 42 illustrates an example differing from that illustrated in FIG. 41. Suppose that information X1 and information X2 exist from time point 0, and information Xf for time point s (where s is an integer no smaller than zero) is the last information bit. Here, f equals one. In FIG. 41, f equals 2. That is, suppose that the information to be transmitted from the transmitting device to the receiving device is information Xi,s, where i is an integer no smaller than one and no greater than f, and information X1,j and information X2,j, being information X1 and information X2 at time point j, respectively, where j is an integer no smaller than zero and no greater than s-1.

[1028] In such a case, the transmitting device transmits information X1, information X2, parity P1, and parity P2 from time point 0 to time point s-1, or that is, transmits X1,j, X2,j, P1,j, P2,j, where j is an integer no smaller than zero and no greater than s-1. (Note that P1,j and P2,j denote parity P1 and parity P2 at time point j, respectively.)

[1029] Further, suppose that at time point s, information Xi,s, when i is an integer no smaller than one and no greater than f, is information that the transmitting device is to transmit, and suppose that Xk,s, when k is an integer equaling f+1, equals "0" (zero).

[1030] Further, suppose that information X1 and information X2 from time point s+1 to time point s+g-1 (where g is an integer no smaller than two) is "0", or that is, when denoting information X1 and information X2 at time point t as X1,t, X2,t, respectively, X1,t=0 and X2,t=0 hold true when t is an integer no smaller than s+1 and no greater than s+g-1. The transmitting device, by performing encoding from time point s to time point s+g-1, acquires parities P1,u and P2,u for u being an integer no smaller than s and no greater than s+g-1. The transmitting device, in addition to the information and parities described above, transmits Xi,s for i being an integer no smaller than one and no greater than f, and parities P1,u and P2,u for u being an integer no smaller than s and no greater than s+g-1.

[1031] Meanwhile, the receiving device performs decoding by using log-likelihood ratios for the information and the parities transmitted by the transmitting device, log-likelihood ratios corresponding to Xk,s=0 (where k is an integer equaling f+1) and log-likelihood ratios corresponding to X1,t=0 and X2,t=0 for t being an integer no smaller than s+1 and no greater than s+g-1, and thereby acquires an estimation sequence of information.

[1032] Although description is provided above taking an example where error correction coding is introduced to a communication device, the error correction coding described above is not limited to being introduced to a communication device, and for example, may be introduced to a storage medium (storage). When making such a modification, information that is to be stored to a storage medium (storage) is encoded by using the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2, and resultant information and parities are stored to the storage medium (storage). When making such a modification, it is preferable that information-zero termination be introduced as described above and that a data sequence as described above corresponding to a data sequence (information and parities) transmitted by the transmitting device when information-zero termination is applied be stored to the storage medium (storage).

[1033] Further, the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2, is applicable to any device that requires error correction coding (e.g., a memory, a hard disk).

(Embodiment 4)



[1034] In the present embodiment, description is provided of a method of configuring an LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). The LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme described in the present embodiment is based on the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2.

[1035] Patent Literature 2 includes explanation regarding an LDPC-CC of coding rate (n-1)/n (where n is an integer no smaller than two) that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). However, Patent Literature 2 poses a problem for not disclosing an LDPC-CC of a coding rate not satisfying (n-1)/n that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1036] In the present embodiment, as one example of an LDPC-CC of a coding rate not satisfying (n-1)/n that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), description is provided of a method of configuring an LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1037] Although coding rate 2/4 equals coding rate 1/2, the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme pertaining to the present embodiment differs, in terms of generation method, from a conventional LDPC-CC of coding rate (n-1)/n or a conventional LDPC-CC of coding rate (n-1)/n that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[Periodic Time-varying LDPC-CC of Coding Rate 2/4 Using Improved Tail-biting Scheme and Based on Parity Check Polynomial]



[1038] The following describes a periodic time-varying LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme and is based on a parity check polynomial, based on the configuration of the LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2.

[1039] The following describes a method of configuring an LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial. Such method has already been described in embodiment 2.

[1040] First, the following parity check polynomials satisfying zero are prepared.
[Math. 165]







[1041] In expressions (165-1-1), (165-1-2), (165-2-1), (165-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[1042] In expressions (165-1-1), (165-1-2), (165-2-1), (165-2-2), α#(2i),p,q (where p is an integer no smaller than one and no greater than two, q is an integer no smaller than one and no greater than r#(2i),p (where r#(2i),p is a natural number)) and β#(2i),0 is a natural number, β#(2i),1 is a natural number, β#(2i),2 is an integer no smaller than zero, and β#(2i),3 is a natural number.

[1043] Further, R#(2i),p is a natural number satisfying 1≤R#(2i),p<r#(2i),p.

[1044] Further, y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier, (y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for all y and all z satisfying y≠z.)

[1045] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (165-1-1) or expression (165-1-2) is referred to as "#(2i); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (165-2-1) or expression (165-2-2) is referred to as "#(2i); second expression" for realizing a time-varying period 2m.

[1046] Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (165-1-1) or expression (165-1-2) is prepared.

[1047] That is, for i=0, a parity check polynomial satisfying zero provided by expression (165-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (165-1-2) where i=0 is prepared.

[1048] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (165-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (165-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (165-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (165-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (165-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (165-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (165-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (165-1-2) where i=m-1 is prepared.



[1049] Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (165-2-1) or expression (165-2-2) is prepared.

[1050] That is, for i=0, a parity check polynomial satisfying zero provided by expression (165-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (165-2-2) where i=0 is prepared.

[1051] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (165-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (165-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (165-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (165-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (165-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (165-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (165-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (165-2-2) where i=m-1 is prepared.



[1052] Similarly, the following parity check polynomials satisfying zero are provided.
[Math. 166]







[1053] In expression (166-1-1), (166-1-2), (166-2-1), (166-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[1054] In expression (166-1-1), (166-1-2), (166-2-1), (166-2-2), α#(2i+1),p,q (where p is an integer no smaller than one and no greater than two, q is an integer no smaller than one and no greater than r#(2i+1),p (where r#(2i+1),p is a natural number)) and β#(2i+1),0 is a natural number, β#(2i+1),1 is a natural number, β#(2i+1),2 is an integer no smaller than zero, and β#(2i+1),3 is a natural number.

[1055] Further, R#(2i+1),p is a natural number satisfying 1≤R#(2i+1),p<r#(2i+1),p.

[1056] Further, y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for all y and all z satisfying y≠z.)

[1057] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (166-1-1) or expression (166-1-2) is referred to as "#(2i+1); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (166-2-1) or expression (166-2-2) is referred to as "#(2i+1); second expression" for realizing a time-varying period 2m.

[1058] Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (166-1-1) or expression (166-1-2) is prepared.

[1059] That is, for i=0, a parity check polynomial satisfying zero provided by expression (166-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (166-1-2) where i=0 is prepared.

[1060] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (166-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (166-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (166-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (166-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (166-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (166-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (166-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (166-1-2) where i=m-1 is prepared.



[1061] Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (166-2-1) or expression (166-2-2) is prepared.

[1062] That is, for i=0, a parity check polynomial satisfying zero provided by expression (166-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (166-2-2) where i=0 is prepared.

[1063] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (166-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (166-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (166-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (166-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (166-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (166-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (166-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (166-2-2) where i=m-1 is prepared.



[1064] As such, an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1065] Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (165-1-1) or expression (165-1-2), parity check polynomials satisfying zero provided by expression (165-2-1) or expression (165-2-2), parity check polynomials satisfying zero provided by expression (166-1-1) or expression (166-1-2), and parity check polynomials satisfying zero provided by expression (166-2-1) or expression (166-2-2).

[1066] For example, the time varying period 2×m is formed by preparing a 4×m number of different parity check polynomials satisfying zero.

[1067] Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

[1068] The following describes the relationship between time point j and expression (165-1-1), (165-1-2), (165-2-1), (165-2-2), (166-1-1), (166-1-2), (166-2-1), and (166-2-2) (where j is an integer no smaller than zero).

[1069] The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m-1).

[1070] Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i = k in #(2i); first expression and #(2i); second expression, hold true.

[1071] Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m-1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

[1072] Note that in the parity check polynomials satisfying zero of expression (165-1-1), (165-1-2), (165-2-1), (165-2-2), (166-1-1), (166-1-2), (166-2-1), and (166-2-2), a sum of the number of terms of P1(D) and the number of terms of P2(D) equals two. This realizes sequentially finding parities P1 and P2 when applying an improved tail-biting scheme, and thus, is a significant factor realizing a reduction in computation amount (circuit scale).

[1073] The following describes the relationship between the time-varying period of the parity check polynomials satisfying zero for the LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2 and on which the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, and block size in the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) proposed in the present embodiment.

[1074] Regarding this point, in order to achieve error correction capability of even higher level, a configuration is preferable where a Tanner graph formed by the LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2 and on which the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, resembles a Tanner graph of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). Thus, the following conditions are significant.

<Condition #N1>



[1075] 
  • The number of rows in a parity check matrix for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is a multiple of 4×m.
    • Accordingly, the number of columns in the parity check matrix for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is a multiple of 4×2×m. According to this condition, (for example) a log-likelihood ratio that is necessary in decoding is a log-likelihood ratio of the number of columns in the parity check matrix for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).


[1076] Note that the relationship between the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and the LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2 and on which the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, is described in detail later in the present disclosure.

[1077] Thus, when denoting the parity check matrix for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as Hpro, the number of columns of Hpro can be expressed as 4×2×m×z (where z is a natural number).

[1078] Accordingly, a transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as vs=(Xs,1,1, Xs,2,1, Ppros,1,1, PPros,2,1, Xs,1,2, Xs,2,2, Ppros,1,2, PPros,2,2, ..., Xs,1,k, Xs,2,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T (where k=1, 2, ..., 2×m×z-1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×z)), and Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes).

[1079] Xs,j,k (where j is an integer no smaller than one and no greater than two) is a bit of information Xj, Ppros,1,k is a bit of parity P1 of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and PPros,2,k is a bit of parity P2 of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1080] Further, λpro,s,k=(Xs,1,k, Xs,2,k, Ppros,1,k, PPros,2,k) holds true.

[1081] In addition, the number of rows in the parity check matrix Hpro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is 4×m×z.

[1082] It has been indicated above that the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based on the LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2. This is explained in the following.

[1083] First, consideration is made of a parity check matrix when configuring a periodic time-varying LDPC-CC using tail-biting by using only parity check polynomials satisfying zero for the LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2.

[1084] FIG. 43 illustrates a configuration of a parity check matrix H when configuring a periodic time-varying LDPC-CC using tail-biting by performing tail-biting by using only parity check polynomials satisfying zero for an LDPC-CC of coding rate 2/4 and time-varying period 2m.

[1085] Since Condition #N1 is satisfied in FIG. 43, the number of rows of the parity check matrix is m×z and the number of columns of the parity check matrix is 4×2×m×z.

[1086] As illustrated in FIG. 43:

"a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×(2m-1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression";

"a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression";

"a vector for the 2×(2m+1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the 2×(2m+2)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×i-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); first expression";

"a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); second expression" (where i is an integer no smaller than one and no greater than 2×m×z);

"a vector for the 2×(2m-1)×z-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)×zth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)×z-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression"; and

"a vector for the 2×(2m)×zth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression".



[1087] To prepare for the explanation to be provided in the following, a mathematical expression is provided of the parity check matrix H in FIG. 43, which is a parity check matrix when configuring a periodic time-varying LDPC-CC by performing tail-biting by using only parity check polynomials satisfying zero for the LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial, description of which is provided in embodiments 1 and 2. When denoting a vector having one row and 4×2×m×z columns in row k of the parity check matrix H as hk, the parity check matrix H in FIG. 43 is expressed as follows.
[Math. 167]



[1088] The following describes a parity check matrix for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1089] FIG. 44 illustrates one example of a configuration of a parity check matrix Hpro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1090] The parity check matrix Hpro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) satisfies Condition #N1.

[1091] When denoting a vector having one row and 4×2×m×z columns in row k of the parity check matrix Hpro in FIG. 44, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), as gk, the parity check matrix Hpro in FIG. 44 is expressed as follows.
[Math. 168]



[1092] A transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as vs=(Xs,1,1, Xs,2,1, Ppros,1,1, PPros,2,1, Xs,1,2, Xs,2,2, Ppros,1,2, PPros,2,2, ..., Xs,1,k, Xs,2,k, Ppros,1k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T (where k=1, 2, ..., 2×m×z-1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×z)), and Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes).

[1093] Xs,j,k (where j is an integer no smaller than one and no greater than two) is a bit of information Xj, Ppros,1,k is a bit of parity P1 of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and PPros,2,k is a bit of parity P2 of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1094] In the parity check matrix Hpro in FIG. 44, which illustrates one example of a configuration of a parity check matrix Hpro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), rows other than row one, or that is, rows between row two to row 2×(2×m)×z in the parity check matrix Hpro in FIG. 44, have the same configuration as rows between row two and row 2×(2×m)×z in the parity check matrix H in FIG. 43 (refer to FIGs. 43 and 44). Accordingly, FIG. 44 includes an indication of #0'; first expression at 4401 in the first row. (This point is explained later in the present disclosure.) Accordingly, the following relational expression holds true based on expression 167 and 168.
[Math. 169]



[1095] Further, the following holds true when i=1.
[Math. 170]



[1096] Accordingly, the parity check matrix Hpro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as follows.
[Math. 171]



[1097] In expression 171, expression 170 holds true.

[1098] Next, explanation is provided of a method of configuring g1 in expression 171 so that parities can be found sequentially and high error correction capability can be achieved.

[1099] One example of a method of configuring g1 in expression 171, so that parities can be found sequentially and high error correction capability can be achieved, is using a parity check polynomial satisfying zero of #0; first expression of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), which serves as the basis.

[1100] Since g1 is row one of the parity check matrix Hpro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), g1 is generated from a parity check polynomial satisfying zero that is obtained by transforming a parity check polynomial satisfying zero of #0; first expression. As described above, a parity check polynomial satisfying zero of #0; first expression is expressed by either expression (172-1-1) or expression (172-1-2).
[Math. 172]





[1101] As one example of a parity check polynomial satisfying zero for generating vector g1 in row one of the parity check matrix Hpro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), a parity check polynomial satisfying zero of #0; first expression is expressed as follows, for either expression (172-1-1) or expression (172-1-2).
[Math. 173]





[1102] Accordingly, vector g1 is a vector having one row and 4×2×m×z columns that is obtained by performing tail-biting with respect to expression 173.

[1103] Note that in the following, a parity check polynomial that satisfies zero provided by expression 173 is referred to as #0'; first expression.

[1104] Accordingly, row one of the parity check matrix Hpro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be obtained by transforming #0'; first expression of expression 173 (that is, a vector g1 corresponding to one row and 4×2×m×z columns can be obtained).

[1105] A transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is vs=(Xs,1,1, Xs,2,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, Ppros,1,2, PPros,2,2, ..., Xs,1,k, Xs,2,k, PPros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T, and the number of parity check polynomials satisfying zero necessary for obtaining this transmission sequence is 2×(2×m)×z.

[1106] Here, when arranging such 2×(2×m)×z number of parity check polynomials satisfying zero in order, a parity check polynomial satisfying zero appearing eth is referred to in the following as an "eth parity check polynomial satisfying zero" (where e is an integer no smaller than zero and no greater than 2×(2×m)×z-1).

[1107] As such, the parity check polynomials satisfying zero are arranged in the following order:

zeroth: zeroth parity check polynomial satisfying zero;

first: first parity check polynomial satisfying zero;

second: second parity check polynomial satisfying zero;

eth: eth parity check polynomial satisfying zero;

2×(2×m)×z-2th: 2×(2×m)×z-2th parity check polynomial satisfying zero; and

2×(2×m)×z-1th: 2×(2×m)×z-1th parity check polynomial satisfying zero.



[1108] Accordingly, the transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is obtained. (As can be seen from description provided above, when expressing the parity check matrix Hpro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as provided in expression 168, a vector composed of row e+1 of the parity check matrix Hpro corresponds to the eth parity check polynomial satisfying zero.)

[1109] Accordingly, in the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the second parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the third parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression;

the 2×(2m)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression;

the 2×(2m+1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; first expression;

the 2×(2m+1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×(2m+2)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the 2×(2m+2)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression; and

the 2×(2m)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression.



[1110] That is,
the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;
the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;
the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression; and
the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).

[1111] As description has been provided above, the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), at the same time as achieving high error correction capability, enables finding multiple parities sequentially, and therefore, achieves an advantageous effect of reducing circuit scale of an encoder.

[1112] In the following, explanation is provided of what is meant by "finding parities sequentially".

[1113] In the example described above, since bits of information X1 and information X2 are pre-acquired, Ppros,1,1 can be calculated by using the 0th parity check polynomial satisfying zero of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), or that is, by using the parity check polynomial satisfying zero of #0'; first expression provided by expression 173.

[1114] Then, from the bits of information X1 and information X2 and Ppros,1,1, another parity (denoted as Pc=1) can be calculated by using another parity check polynomial satisfying zero.

[1115] Further, from the bits of information X1 and information X2 and Pc=1, another parity (denoted as Pc=2) can be calculated by using another parity check polynomial satisfying zero.

[1116] By repeating such operation, from the bits of information X1 and information X2 and Pc=h, another parity (denoted as Pc=h+1) can be calculated by using a given parity check polynomial satisfying zero.

[1117] This is referred to as "finding parities sequentially", and when parities can be found sequentially, multiple parities can be obtained without calculation of complex simultaneous equations, whereby an advantageous effect is achieved of reducing circuit scale (computation amount) of an encoder.

[1118] Next, explanation is provided of configurations and operations of an encoder and a decoder for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1119] In the following, one example case is considered where the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is used in a communication system. When applying the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) to a communication system, the encoder and the decoder for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) are characterized for each being configured and each operating based on the parity check matrix Hpro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and based on the relationship Hprovs=0.

[1120] The following provides explanation while referring to FIG. 25, which is an overall diagram of a communication system. An encoder 2511 of a transmitting device 2501 receives an information sequence of block s (Xs,1,1, Xs,2,1, Xs,1,2, Xs,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z) as input. The encoder 2511 performs encoding based on the parity check matrix Hpro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and based on the relationship Hprovs=0. The encoder 2511 generates a transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), denoted as vs=(Xs,1,1, Xs,2,1, Ppros,1,1, PPros,2,1, Xs,1,2, Xs,2,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T, and outputs the transmission sequence vs. As already described above, the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is characterized for enabling parities to be found sequentially.

[1121] A decoder 2523 of a receiving device 2520 in FIG. 25 receives, as input, a log-likelihood ratio of each bit of, for example, the transmission sequence vs=(Xs,1,1, Xs,2,1, Ppros,1,1, PPros,2,1, Xs,1,2, Xs,2,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T. The log-likelihood ratios are output from a log-likelihood ratio generator 2522. The decoder 2523 performs decoding for an LDPC code according to the parity check matrix Hpro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). For example, the decoding may be decoding disclosed in Non-Patent Literature 4, Non-Patent Literature 6, Non-Patent Literature 7, Non-Patent Literature 8, etc., i.e., simple BP decoding such as min-sum decoding, offset BP decoding, or Normalized BP decoding, or Belief Propagation (BP) decoding in which scheduling is performed with respect to the row operations (Horizontal operations) and the column operations (Vertical operations) such as Shuffled BP decoding or Layered BP decoding. The decoding may also be decoding such as bit-flipping decoding disclosed in Non-Patent Literature 17, for example. The decoder 2523 obtains an estimation transmission sequence (estimation encoded sequence) (reception sequence) of block s through the decoding, and outputs the estimation transmission sequence.

[1122] In the above, explanation is provided on operations of the encoder and the decoder in a communication system as one example. Alternatively, the encoder and the decoder may be used in technical fields related to storages, memories, etc.

[1123] The following describes a specific example of a configuration of a parity check matrix for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1124] When denoting the parity check matrix for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as Hpro as described above, the number of columns of Hpro can be expressed as 4×2×m×z (where z is a natural number). (Note that m denotes a time-varying period of the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, which serves as the basis.)

[1125] Accordingly, as already described above, a transmission sequence (encoded sequence (codeword)) vs composed of a 4×2×m×z number of bits in block s of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as vs=(Xs,1,1, Xs,2,1,Ppros,1,1,Ppros,2,1, Xs,1,2, Xs,2,2, Ppros,1,2, PPros,2,2, ..., Xs,1,k, Xs,2,k, Ppros,1,k, PPros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T (where k=1, 2, ..., 2×m×z-1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×z)), and Hprovs=0 holds true (here, HproVs=0 indicates that all elements of the vector Hprovs are zeroes).

[1126] Xs,j,k (where j is an integer no smaller than one and no greater than two) is a bit of information Xj, Ppros,1,k is a bit of parity P1 of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and PPros,2,k is a bit of parity P2 of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1127] Further, λpro,s,k=(Xs,1,k, Xs,2,k, Ppros,1,k, Ppros,2,k) holds true.

[1128] In addition, the number of rows in the parity check matrix Hpro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is 4×m×z.

[1129] Note that the method of configuring parity check polynomials satisfying zero for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) has already been described above.

[1130] In the above, description has been provided of a parity check matrix Hpro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), whose transmission sequence (encoded sequence (codeword)) vs of block s is vs=(Xs,1,1, Xs,2,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T and for which Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes). The following provides description of a configuration of a parity check matrix Hpro_m for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), for which Hpro_mus=0 holds true (here, Hpro_mus=0 indicates that all elements of the vector Hpro_mus are zeroes) when expressing a transmission sequence (encoded sequence (codeword)) us of block s as us=(Xs,1,1 Xs,1,2, ..., Xs,1,2×m×z-1, Xs,1,2×m×z, Xs,2,1, Xs,2,2, ..., Xs,2,2×m×z-1, Xs,2,2×m×z, Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z, Ppros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, Ppros,2,2×m×z)T=(ΛX1,s ΛX2,s, Λpro1,s, Λpro2,s)T.

[1131] Note that ΛXf,s (where f is an integer no smaller than one and no greater than two) satisfies ΛXf,s=(Xs,f,1, Xs,f,2, Xs,f,3, ..., Xs,f,2×m×z-2, Xs,f,2×m×z-1, Xs,f,2×m×z) (ΛXf,s is a vector having one row and 2×m×z columns), and Λpro1,s and Λpro2,s satisfy Λpro1,s=(Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z) and Λpro2,s=(Ppros,2,1, PPros,2,2, ..., PPros,2,2×m×z-1, Ppros,2,2×m×z), respectively (Λpro1,s and Λpro2,s are both vectors having one row and 2×m×z columns).

[1132] Here, the number of bits of information X1 included in one block is 2×m×z, the number of bits of information X2 included in one block is 2×m×z, the number of bits of parity bits P1 included in one block is 2×m×z, and the number of bits of parity bits P2 included in one block is 2×m×z. Accordingly, the parity check matrix Hpro_m for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as Hpro_m=[Hx,1, Hx,2, Hp1, Hp2], as illustrated in FIG. 45. Since a transmission sequence (encoded sequence (codeword)) us of block s is us=(Xs,1,1 Xs,1,2, ..., Xs,1,2×m×z-1, Xs,1,2×m×z, Xs,2,1, Xs,2,2, ..., Xs,2,2×m×z-1, Xs,2,2×m×z, Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z, Ppros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, Ppros,2,2×m×z)T=(ΛX1,s, ΛX2,s, Λpro1,s, Λpro2,s)T, Hx,1 is a partial matrix related to information X1, Hx,2 is a partial matrix related to information X2, Hp1 is a partial matrix related to parity P1, and Hp2 is a partial matrix related to parity P2. As illustrated in FIG. 45, the parity check matrix Hpro_m has 4×m×z rows and 4×2×m×z columns, the partial matrix Hx,1 related to information X1 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,2 related to information X2 has 4×m×z rows and 2×m×z columns, the partial matrix Hp1 related to parity P1 has 4×m×z rows and 2×m×z columns, and the partial matrix Hp2 related to parity P2 has 4×m×z rows and 2×m×z columns.

[1133] The transmission sequence (encoded sequence (codeword)) us composed of a 4×2×m×z number of bits in block s of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is us=(Xs,1,1 Xs,1,2, ..., Xs,1,2×m×z-1, Xs,1,2×m×z, Xs,2,1, Xs,2,2, ..., Xs,2,2×m×z-1, Xs,2,2×m×z, Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z, PPros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, Ppros,2,2×m×z)T=(ΛX1,s, ΛX2,s, Λpro1,s, Λpro2,s)T, and the number of parity check polynomials satisfying zero necessary for obtaining this transmission sequence is 4×m×z.

[1134] Here, when arranging such 2×(2×m)×z number of parity check polynomials satisfying zero in order, a parity check polynomial satisfying zero appearing eth is referred to in the following as an "eth parity check polynomial satisfying zero" (where e is an integer no smaller than zero and no greater than 2×(2×m)×z-1).

[1135] As such, the parity check polynomials satisfying zero are arranged in the following order:

zeroth: zeroth parity check polynomial satisfying zero;

first: first parity check polynomial satisfying zero;

second: second parity check polynomial satisfying zero;

eth: eth parity check polynomial satisfying zero;

2×(2×m)×z-2th: 2×(2×m)×z-2th parity check polynomial satisfying zero; and

2×(2×m)×z-1th: 2×(2×m)×z-1th parity check polynomial satisfying zero.



[1136] Accordingly, the transmission sequence (encoded sequence (codeword)) us of block s of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is obtained.

[1137] Accordingly, in the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the second parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the third parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression;

the 2×(2m)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression;

the 2×(2m+1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; first expression;

the 2×(2m+1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×(2m+2)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the 2×(2m+2)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression; and

the 2×(2m)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression.



[1138] That is,
the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;
the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;
the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i- 1)%2m); first expression; and
the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).

[1139] In the present embodiment (in fact, commonly applying to the entirety of the present disclosure), % means a modulo, and for example, α%q represents a remainder after dividing α by q (where α is an integer no smaller than zero, and q is a natural number).

[1140] The following describes details of the configuration of the parity check matrix Hpro_m for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) based on what has been described above.

[1141] The parity check matrix Hpro_m for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) has 4×m×z rows and 4×2×m×z columns.

[1142] Accordingly, the parity check matrix Hpro_m for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) has rows one through 4×m×z, and columns one through 4×2×m×z.

[1143] Here, the topmost row of the parity check matrix Hpro_m is considered as the first row. Further, row number is incremented by one each time moving to a lower row. Accordingly, the topmost row is considered as the first row, the row immediately below the first row is considered as the second row, and the subsequent rows are considered as the third row, the fourth row, and so on.

[1144] Further, the leftmost column of the parity check matrix Hpro_m is considered as the first column. Further, column number is incremented by one each time moving to a rightward column. Accordingly, the leftmost column is considered as the first column, the column immediately to the right of the first column is considered as the second column, and the subsequent columns are considered as the third column, the fourth column, and so on.

[1145] In the parity check matrix Hpro_m, the partial matrix Hx,1 related to information X1 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,1 related to information X1 is denoted as Hx,1,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[1146] Similarly, in the parity check matrix Hpro_m, the partial matrix Hx,2 related to information X2 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,2 related to information X2 is denoted as Hx,2,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[1147] Further, in the parity check matrix Hpro_m, the partial matrix Hp,1 related to parity P1 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hp,1 related to parity P1 is denoted as Hp1,Comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[1148] Similarly, in the parity check matrix Hpro_m, the partial matrix Hp,2 related to parity P2 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hp,2 related to parity P2 is denoted as Hp2,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[1149] The following provides detailed description of the configuration of Hx,1,comp[u][v], Hx,2,comp[u][v], Hp1,comp[u][v], and Hp2,comp[u][v].

[1150] As already described above, in the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the second parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the third parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression;

the 2×(2m)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression;

the 2×(2m+1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; first expression;

the 2×(2m+1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×(2m+2)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the 2×(2m+2)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression; and

the 2×(2m)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression.



[1151] That is,
the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;
the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;
the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i- 1)%2m); first expression; and
the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).

[1152]  Further, a vector composed of row e+1 of the parity check matrix Hpro_m corresponds to the eth parity check polynomial satisfying zero.

[1153] Accordingly,
a vector composed of row one of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;
a vector composed of row two of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0; second expression;
a vector composed of row 2×g-1 of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); first expression; and
a vector composed of row 2×g of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); second expression (where g is an integer no smaller than two and no greater than 2×m×z).

[1154] Hx,1,comp[u][v], Hx,2,comp[u][v], Hp1,comp[u][v], and Hp2,comp[u][v] can be expressed according to the relationship described above.

[1155] First, description is provided of the configuration of Hx,1,comp[u][v], Hx,2,comp[u][v], Hp1,comp[u][v], and Hp2,comp[u][v] for row one of the parity check matrix Hpro_m, or that is, for u=1.

[1156] The vector composed of row one of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0'; first expression provided by expression 173. Accordingly, Hx,1,comp[1][v] can be expressed as follows. In the following, w=1.
[Math. 174]



[1157] Further, Hx,2,comp[1][v] can be expressed as follows. In the following, Ω=2.
[Math. 175]





[1158] Further, Hp1,comp[1][v] can be expressed as follows.
[Math. 176]



[1159] Further, Hp2,comp[1][v] can be expressed as follows.
[Math. 177]



[1160] The vector composed of row two of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0; second expression. As described above, a parity check polynomial satisfying zero of #0; second expression is expressed by either expression (165-2-1) or expression (165-2-2).

[1161] Accordingly, Hx,1,comp[2][v] can be expressed as follows.
  1. <1> When a parity check polynomial satisfying zero of #0; second expression is expressed as provided in expression (165-2-1):
    Hx,1,comp[2] [v] is expressed as follows. In the following, Ω=1.
    [Math. 178]




    Accordingly, Hx,2,comp[2][v] can be expressed as follows. In the following, w=2.
    [Math. 179]


    Further, Hp1,comp[2][v] can be expressed as follows.
    [Math. 180]


    Further, Hp2,comp[2][v] can be expressed as follows.
    [Math. 181]

  2. <2> When a parity check polynomial satisfying zero of #0; second expression is expressed as provided in expression (165-2-2):
    Hx,1,comp[2][v] is expressed as follows. In the following, Ω=1.
    [Math. 182]





[1162] Accordingly, Hx,2,comp[2][v] can be expressed as follows. In the following, w=2.
[Math. 183]



[1163] Further, Hp1,comp[2][v] can be expressed as follows.
[Math. 184]



[1164] Further, Hp2,comp[2][v] can be expressed as follows.
[Math. 185]



[1165] As already described above,
the vector composed of row 2×g-1 of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); first expression; and
the vector composed of row 2×g of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); second expression (where g is an integer no smaller than two and no greater than 2×m×z).

[1166] Accordingly, when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), a vector of row 2×(2×f-1)-1 of the parity check matrix Hpro_m for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); first expression, or that is, by using a parity check polynomial satisfying zero provided by expression (165-1-1) or expression (165-1-2).

[1167] Further, a vector of row 2×(2×f-1) of the parity check matrix Hpro_m for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); second expression, or that is, by using a parity check polynomial satisfying zero provided by expression (165-2-1) or expression (165-2-2).

[1168] Further, when g=2×f (where f is an integer no smaller than one and no greater than m×z), a vector of row 2×(2×f)-1 of the parity check matrix Hpro_m for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f)-1)%2m); first expression, or that is, by using a parity check polynomial satisfying zero provided by expression (166-1-1) or expression (166-1-2).

[1169] Further, a vector of row 2×(2×f) of the parity check matrix Hpro_m for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f)-1)%2m); second expression, or that is, by using a parity check polynomial satisfying zero provided by expression (166-2-1) or expression (166-2-2).

[1170] Accordingly, (1) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (165-1-1), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (165-1-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[1171] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f-1)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f-1)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f-1)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[1172] First, the following holds true for Hx,1,comp[2×(2×f-1)-1][v]. In the following, w=1.
[Math. 186]



[1173] Further, the following holds true for Hx,2,comp[2×(2×f-1)-1][v]. In the following, Ω=2 and y is an integer no smaller than R#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 187]



[1174] Further, the following holds true for Hp1,comp[2×(2×f-1)-1][v].
[Math. 188]



[1175] Further, the following holds true for Hp2,comp[2×(2×f-1)-1][v].
[Math. 189]



[1176] Further, (2) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2× f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (165-1-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (165-1-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[1177] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f-1)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f-1)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f-1)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[1178] First, the following holds true for Hx,1,comp[2×(2×f-1)-1][v]. In the following, w=1.
[Math. 190]





[1179] Further, the following holds true for Hx,2,comp[2×(2×f-1)-1][v]. In the following, Ω=2 and y is an integer no smaller than R#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 191]



[1180] Further, the following holds true for Hp1,comp[2×(2×f-1)-1][v].
[Math. 192]





[1181] Further, the following holds true for Hp2,comp[2×(2×f-1)-1][v].
[Math. 193]



[1182] Further, (3) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (165-2-1), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (165-2-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[1183] Accordingly, components Hx,1,comp[2×g][v]=Hx,1comp[2×(2×f-1)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2×f-1)][v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f-)][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f-1)-1][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[1184] First, the following holds true for Hx,1,comp[2×(2×f-1)][v]. In the following, Ω=1 and y is an integer no smaller than R#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 194]



[1185] Further, the following holds true for Hx,2,comp[2×(2×f-1)][v]. In the following, w=2.
[Math. 195]



[1186] Further, the following holds true for Hp1,comp[2×(2×f-1)][v].
[Math. 196]



[1187] Further, the following holds true for Hp2,comp[2×(2×f-1)][v].
[Math. 197]



[1188] Further, (4) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (165-2-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (165-2-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[1189] Accordingly, components Hx,1,comp[2×g][v]=Hx,1comp[2×(2×f-1)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2×f-)][v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f-1)][v], and Hp2,comp[2×g][v]=Hp2,comp[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[1190] First, the following holds true for Hx,1,comp[2×(2×f-1)][v]. In the following, Ω=1 and y is an integer no smaller than R#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 198]



[1191] Further, the following holds true for Hx,2,comp[2×(2×f-1)][v]. In the following, w=2.
[Math. 199]





[1192] Further, the following holds true for Hp1,comp[2×(2×f-1)][v].
[Math. 200]



[1193] Further, the following holds true for Hp2,comp[2×(2×f-1)][v].
[Math. 201]



[1194] Further, (5) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (166-1-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (166-1-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[1195] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[1196]  First, the following holds true for Hx,1,comp[2×(2×f)-1][v]. In the following, Ω=1 and y is an integer no smaller than R#(2d+1),Ω+1 and no greater than r#(2d+1),Ω.
[Math. 202]



[1197] Further, the following holds true for Hx,2,comp[2×(2×f)-1][v]. In the following, w=2.
[Math. 203]



[1198] Further, the following holds true for Hp1,comp[2×(2×f)-1][v].
[Math. 204]





[1199] Further, the following holds true for Hp2,comp[2×(2×f)-1][v].
[Math. 205]



[1200] Further, (6) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (166-1-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (166-1-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[1201] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[1202] First, the following holds true for Hx,1,comp[2×(2×f)-1][v]. In the following, Ω=1 and y is an integer no smaller than R#(2d+1),Ω+1 and no greater than r#(2d+1),Ω.
[Math. 206]





[1203] Further, the following holds true for Hx,2,comp[2×(2×f)-1][v]. In the following, w=2.
[Math. 207]



[1204] Further, the following holds true for Hp1,comp[2×(2×f)-1][v].
[Math. 208]



[1205] Further, the following holds true for Hp2,comp[2×(2×f)-1][v].
[Math. 209]



[1206] Further, (7) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (166-2-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (166-2-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[1207] Accordingly, components Hx,1,comp[2×g] [v]=Hx,1,comp[2×(2×f)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2×f)][v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f)][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f-1)-1][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[1208] The following holds true for Hx,1,comp[2x(2xf)][v]. In the following, w=1.
[Math. 210]



[1209] The following holds true for Hx,2,comp[2×(2×f)][v]. In the following, Ω=2 and y is an integer no smaller than R#(2d+1),Ω+1 and no greater than r#(2d+1),Ω.
[Math. 211]





[1210] Further, the following holds true for Hp1,comp[2×(2×f)][v].
[Math. 212]



[1211] Further, the following holds true for Hp2,comp[2×(2×f)][v].
[Math. 213]



[1212] Further, (8) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (166-2-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (166-2-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[1213] Accordingly, components Hx,1,comp[2×g][v]=Hx,1,comp[2×(2×f)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2×f)][v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f)][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f-1)-1][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[1214] The following holds true for Hx,1,comp[2×(2×f)][v]. In the following, w=1.
[Math. 214]



[1215] The following holds true for Hx,2,comp[2×(2×f)][v]. In the following, Ω=2 and y is an integer no smaller than R#(2d+1),Ω+1 and no greater than r#(2d+1),Ω.
[Math. 215]



[1216] Further, the following holds true for Hp1,comp[2×(2×f)][v].
[Math. 216]



[1217] Further, the following holds true for Hp2,comp[2×(2×f)][v].
[Math. 217]



[1218] An LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated as described above, and the code so generated achieves high error correction capability.

[1219] In the above, parity check polynomials satisfying zero for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) are set as follows:

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression; and

the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).



[1220] Based on this, the following method is conceivable as a configuration where usage of parity check polynomials satisfying zero is limited.

[1221] In this configuration, parity check polynomials satisfying zero for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) are set as follows:

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression provided by expression (165-2-1);

the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression provided by expression (165-1-1) or expression (166-1-1); and

the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression provided by expression (165-2-1) or expression (166-2-1) (where i is an integer no smaller than two and no greater than 2×m×z).



[1222] Accordingly, in the parity check matrix Hpro_m for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the vector composed of row one of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;

the vector composed of row two of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0; second expression provided by expression (165-2-1);

the vector composed of row 2×g-1 of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); first expression provided by expression (165-1-1) or expression (166-1-1); and

the vector composed of row 2×g of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); second expression provided by expression (165-2-1) or expression (166-2-1) (where g is an integer no smaller than two and no greater than 2×m×z).



[1223] Note that when making such a configuration, the above-described method of configuring the parity check matrix Hpro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is applicable.

[1224] Such a method also enables generating a code with high error correction capability.

(Embodiment 5)



[1225] In embodiment 4, description is provided of an LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and a method of configuring a parity check matrix for the code.

[1226] With regards to parity check matrices for low density parity check (block) codes, one example of which is the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), a parity check matrix equivalent to a parity check matrix defined for a given LDPC code can be generated by using the parity check matrix defined for the given LDPC code.

[1227] For example, a parity check matrix equivalent to the parity check matrix Hpro_m described in embodiment 4, which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using the parity check matrix Hpro_m.

[1228] The following describes a method of generating a parity check matrix equivalent to a parity check matrix defined for a given LDPC by using the parity check matrix defined for the given LDPC code.

[1229] Note that the method of generating an equivalent parity check matrix described in the present embodiment is not only applicable to the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) described in embodiment 4, but also is widely applicable to LDPC codes in general.

[1230] FIG. 31 illustrates the configuration of a parity check matrix H for an LDPC (block) code of coding rate (N-M)/N (N>M>0). For example, the parity check matrix of FIG. 31 has M rows and N columns. Here, to provide a general description, the parity check matrix H in FIG. 31 is considered to be a parity check matrix for defining an LDPC (block) code #A of coding rate (N-M)/N (N>M>0).

[1231] In FIG. 31, a transmission sequence (codeword) for block j is vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) (for systematic codes, Yj,k (where k is an integer no smaller than one and no greater than N) is information X or parity P (parity Ppro)).

[1232] Here, Hvj=0 holds true (where the zero in Hvj=0 indicates that all elements of the vector Hvj are zeroes. That is, row k of the vector Hvj has a value of zero for all k (where k is an integer no smaller than one and no greater than M)).

[1233] Then, an element of row k (where k is an integer no smaller than one and no greater than N) of the transmission sequence vj of block j (in FIG. 31, an element of column k in the transpose matrix vjT of the transmission sequence vj) is Yj,k, and a vector obtained by extracting column k of the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) can be expressed as ck, as illustrated in FIG. 31. Here, the parity check matrix H is expressed as follows.
[Math. 218]



[1234] FIG. 32 illustrates a configuration when interleaving is applied to the transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j. In FIG. 32, an encoding section 3202 receives information 3201 as input, performs encoding thereon, and outputs encoded data 3203. For example, when encoding the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), the encoder 3202 receives information in block j as input, performs encoding thereon based on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), and outputs the transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j.

[1235] Then, an accumulation and reordering section (interleaving section) 3204 receives the encoded data 3203 as input, accumulates the encoded data 3203, performs reordering thereon, and outputs interleaved data 3205. Accordingly, the accumulation and reordering section (interleaving section) 3204 receives the transmission sequence vj=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N)T of block j as input, and outputs a transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T, which is illustrated in FIG. 32, as a result of reordering being performed on the elements of the transmission sequence vj (v'j being an example). Here, as discussed above, the transmission sequence v'j is obtained by reordering the elements of the transmission sequence vj of block j. Accordingly, v'j is a vector having one row and n columns, and the N elements of v'j are such that one each of the terms Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N is present.

[1236] Here, an encoding section 3207 as shown in FIG. 32 having the functions of the encoding section 3202 and the accumulation and reordering section (interleaving section) 3204 is considered. Accordingly, the encoding section 3207 receives the information 3201 as input, performs encoding thereon, and outputs the encoded data 3203. For example, the encoding section 3207 receives information in block j as input, and as shown in FIG. 32, outputs the transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T. In the following, explanation is provided of a parity check matrix H' for the LDPC (block) code of coding rate (N-M)/N (N>M>0) corresponding to the encoding section 3207 (i.e., a parity check matrix H' that is equivalent to the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0)), while referring to Fig. 33. (Needless to say, the parity check matrix H' is a parity check matrix for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0).)

[1237] FIG. 33 shows a configuration of the parity check matrix H', which is a parity check matrix equivalent to the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), when the transmission sequence (codeword) is v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T. Here, an element of row one of the transmission sequence v'j of block j (an element of column one in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) is Yj,32. Accordingly, a vector obtained by extracting column one of the parity check matrix H', when using the above-described vector ck (k=1, 2, 3, ..., N-2, N-1, N), is c32. Similarly, an element of row two of the transmission sequence v'j of block j (an element of column two in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) is Yj,99. Accordingly, a vector obtained by extracting column two of the parity check matrix H' is c99. Further, as shown in FIG. 33, a vector obtained by extracting column three of the parity check matrix H' is c23, a vector obtained by extracting column N-2 of the parity check matrix H' is c234, a vector obtained by extracting column N-1 of the parity check matrix H' is c3, and a vector obtained by extracting column N of the parity check matrix H' is c43.

[1238] That is, when denoting an element of row i of the transmission sequence v'j of block j (an element of column i in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) as Yj,g (where g=1, 2, 3, ..., N-1, N-1, N), then a vector obtained by extracting column i of the parity check matrix H' is cg, when using the vector ck described above.

[1239] Accordingly, the parity check matrix H' for transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T is expressed as follows.
[Math. 219]



[1240] When denoting an element of row i of the transmission sequence v'j of block j (an element of column i in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) as Yj,g (where g=1, 2, 3, ..., N-1, N-1, N), a vector obtained by extracting column i of the parity check matrix H' is cg, when using the vector ck described above. When the above is followed to create a parity check matrix, then a parity check matrix for the transmission sequence v'j of block j can be obtained with no limitation to the above-given example.

[1241] Accordingly, when interleaving is applied to the transmission sequence (codeword) of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), a matrix for the interleaved transmission sequence is obtained by performing reordering of columns (column permutation) as described above on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0).

[1242] As such, it naturally follows that the transmission sequence (codeword) (vj) obtained by reverting the interleaved transmission sequence (codeword) (v'j) to its original order is the transmission sequence (codeword) of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Accordingly, by reverting the interleaved transmission sequence (codeword) (v'j) and a parity check matrix H' corresponding to the interleaved transmission sequence (codeword) (v'j) to their respective orders, the transmission sequence vj and a parity check matrix corresponding to the transmission sequence vj can be obtained, respectively. Further, the parity check matrix obtained by performing the reordering as described above is the parity check matrix H in FIG. 31, description of which has been provided above.

[1243] FIG. 34 illustrates an example of a decoding-related configuration of a receiving device, when encoding of FIG. 32 has been performed. The transmission sequence obtained when the encoding of FIG. 32 is performed undergoes processing such as mapping in accordance with a modulation scheme, frequency conversion, and modulated signal amplification, whereby a modulated signal is obtained. A transmitting device transmits the modulated signal. The receiving device then receives the modulated signal transmitted by the transmitting device to obtain a received signal. A log-likelihood ratio calculation section 3400 illustrated in FIG. 34 takes the received signal as input, calculates a log-likelihood ratio for each bit of the codeword, and outputs a log-likelihood ratio signal 3401.

[1244] For example, assume that the transmitting device transmits a transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T of block j. Then, the log-likelihood ratio calculation section 3400 calculates, from the received signal, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, and outputs the log-likelihood ratios.

[1245] An accumulation and reordering section (deinterleaving section) 3402 receives the log-likelihood ratio signal 3401 as input, performs accumulation and reordering thereon, and outputs a deinterleaved log-likelihood ratio signal 3403.

[1246] For example, the accumulation and reordering section (deinterleaving section) 3402 receives, as input, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, performs reordering, and outputs the log-likelihood ratios in the order of: the log-likelihood ratio for Yj,1, the log-likelihood ratio for Yj,2, the log-likelihood ratio for Yj,3, ..., the log-likelihood ratio for Yj,N-2, the log-likelihood ratio for Yj,N-1, and the log-likelihood ratio for Yj,N in the stated order.

[1247] A decoder 3404 receives the deinterleaved log-likelihood ratio signal 3403 as input, performs belief propagation (BP) decoding as disclosed in Non-Patent Literature 6 to 8, such as sum-product decoding, min-sum decoding, offset BP decoding, normalized BP decoding, shuffled BP decoding, and layered BP decoding in which scheduling is performed, based on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 31, and thereby obtains an estimation sequence 3405 (note that decoding schemes other than belief propagation decoding may be used).

[1248] For example, the decoder 3404 receives, as input, the log-likelihood ratio for Yj,1, the log-likelihood ratio for Yj,2, the log-likelihood ratio for Yj,3, ..., the log-likelihood ratio for Yj,N-2, the log-likelihood ratio for Yj,N-1, and the log-likelihood ratio for Yj,N in the stated order, performs belief propagation decoding based on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 31, and obtains the estimation sequence (note that decoding schemes other than belief propagation decoding may be used).

[1249] The following describes a decoding-related configuration that differs from that described above. The decoding-related configuration described in the following differs from the decoding-related configuration described above in that the accumulation and reordering section (deinterleaving section) 3402 is not included. The operations of the log-likelihood ratio calculation section 3400 are similar to those described above, and thus, explanation thereof is omitted in the following.

[1250] For example, assume that the transmitting device transmits a transmission sequence (codeword) v'j =(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T of block j. Then, the log-likelihood ratio calculation section 3400 calculates, from the received signal, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, and outputs the log-likelihood ratios (corresponding to 3406 in FIG. 34).

[1251] A decoder 3407 receives the log-likelihood ratio signal 3406 for each bit as input, performs belief propagation (BP) decoding as disclosed in Non-Patent Literature 6 to 8, such as sum-product decoding, min-sum decoding, offset BP decoding, normalized BP decoding, shuffled BP decoding, and layered BP decoding in which scheduling is performed, based on the parity check matrix H' for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 33, and thereby obtains an estimation sequence 3409 (note that decoding schemes other than belief propagation decoding may be used).

[1252] For example, the decoder 3407 receives, as input, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43 in the stated order, performs belief propagation decoding based on the parity check matrix H' for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 33, and obtains the estimation sequence (note that decoding schemes other than belief propagation decoding may be used).

[1253] As explained above, even when the transmitted data is reordered due to the transmitting device interleaving the transmission sequence vj=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N)T of block j, the receiving device is able to obtain the estimation sequence by using a parity check matrix corresponding to the reordered transmitted data.

[1254] Accordingly, when interleaving is applied to the transmission sequence (codeword) of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), a parity check matrix for the interleaved transmission sequence (codeword) is obtained by performing reordering of columns (i.e., column permutation) as described above on the parity check matrix for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). As such, the receiving device is able to perform belief propagation decoding and thereby obtain an estimation sequence without performing interleaving on the log-likelihood ratio for each acquired bit.

[1255] Note that in the above, explanation is provided of the relation between interleaving applied to a transmission sequence and a parity check matrix. In the following, explanation is provided of reordering of rows (row permutation) performed on a parity check matrix.

[1256] FIG. 35 illustrates a configuration of a parity check matrix H corresponding to a transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). For example, the parity check matrix H of FIG. 35 is a matrix having M rows and N columns. (for systematic codes, Yj,k (where k is an integer no smaller than one and no greater than N) is information X or parity P (parity Ppro), and is composed of (N-M) information bits and M parity bits). Here, Hvj = 0 holds true. (Here, the zero in Hvj = 0 indicates that all elements of the vector Hvj are zeroes. That is, row k of the vector Hvj has a value of zero for all k (where k is an integer no smaller than one and no greater than M.)

[1257] Further, a vector obtained by extracting column k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 35 is denoted as zk. Then, the parity check matrix H for the LDPC (block) code is expressed as follows.
[Math. 220]



[1258] Next, a parity check matrix obtained by performing reordering of rows (row permutation) on the parity check matrix H of FIG. 35 is considered.

[1259] FIG. 36 shows an example of a parity check matrix H' obtained by performing reordering of rows (row permutation) on the parity check matrix H of FIG. 35. The parity check matrix H', similar to the parity check matrix shown in FIG. 35, is a parity check matrix corresponding to the transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0).

[1260] The parity check matrix H' of FIG. 36 is composed of vectors zk obtained by extracting row k (where k is an integer no smaller one and no greater than M) of the parity check matrix H of FIG. 35. For example, in the parity check matrix H', the first row is composed of vector z130, the second row is composed of vector z24, the third row is composed of vector z45, ..., the (M-2)th row is composed of vector z33, the (M-1)th row is composed of vector z9, and the Mth row is composed of vector z3. Note that each of the M row-vectors obtained by extracting row k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H' is such that one each of z1, z2, z3, ... zM-2, zM-1, and zM is present.

[1261] Here, the parity check matrix H' for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) is expressed as follows.
[Math. 221]



[1262] Further, H'vj = 0 holds true. (Here, the zero in H'vj = 0 indicates that all elements of the vector H'vj are zeroes. That is, row k of the vector H'vj has a value of zero for all k (where k is an integer no smaller than one and no greater than M.)

[1263] That is, for the transmission sequence vjT of block j, a vector obtained by extracting row i of the parity check matrix H' in FIG. 36 is expressed as ck (where k is an integer no smaller than one and no greater than M), and each of the M row vectors obtained by extracting row k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H' in FIG. 36 is such that one each of z1, z2, z3, ... zM-2, zM-1, and zM is present.

[1264] As described above, for the transmission sequence vjT of block j, a vector obtained by extracting row i of the parity check matrix H' in FIG. 36 is expressed as ck (where k is an integer no smaller than one and no greater than M), and each of the M row vectors obtained by extracting row k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H' in FIG. 36 is such that one each of z1, z2, z3, ... zM-2, zM-1, and zM is present. Note that, when the above is followed to create a parity check matrix, then a parity check matrix for the transmission sequence parity vj of block j can be obtained with no limitation to the above-given example.

[1265] Accordingly, even when the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) is being used, it does not necessarily follow that a transmitting device and a receiving device are using the parity check matrix H. As such, a transmitting device and a receiving device may use as a parity check matrix, for example, a matrix obtained by performing reordering of columns (column permutation) as described above on the parity check matrix H or a matrix obtained by performing reordering of rows (row permutation) on the parity check matrix H.

[1266] In addition, a matrix obtained by performing both reordering of columns (column permutation) and reordering of rows (row permutation) as described above on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) may be used as a parity check matrix.

[1267] In such a case, a parity check matrix H1 is obtained by performing reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H2 is obtained by performing reordering of rows (row permutation) on the parity check matrix H1 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). A transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H2 so obtained.

[1268] Also, a parity check matrix H1,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H2,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix H1,1 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36).

[1269] Further, a parity check matrix H1,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H2,1. Finally, a parity check matrix H2,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H1,2.

[1270] As described above, a parity check matrix H2,s may be obtained by repetitively performing reordering of columns (column permutation) and reordering of rows (row permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H1,k is obtained by performing a kth (where k is an integer no smaller than two and no greater than s) reordering of columns (column permutation) on a parity check matrix H2,k-1. Then, a parity check matrix H2,k is obtained by performing a kth reordering of rows (row permutation) on the parity check matrix H1,k. Note that in the first instance, a parity check matrix H1,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H2,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H1,1.

[1271] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H2,s.

[1272] In an alternative method, a parity check matrix H3 is obtained by performing reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H4 is obtained by performing reordering of columns (column permutation) on the parity check matrix H3 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H4 so obtained.

[1273] Also, a parity check matrix H3,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H4,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix H3,1 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33).

[1274] Then, a parity check matrix H3,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H4,1. Finally, a parity check matrix H4,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H3,2.

[1275] As described above, a parity check matrix H4,s may be obtained by repetitively performing reordering of rows (row permutation) and reordering of columns (column permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H3,k is obtained by performing a kth (where k is an integer no smaller two and no greater than s) reordering of rows (row permutation) on a parity check matrix H4,k-1. Then, a parity check matrix H4,k is obtained by performing a kth reordering of columns (column permutation) on the parity check matrix H3,k. Note that in the first instance, a parity check matrix H3,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H4,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H3,1.

[1276] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H4,s.

[1277] Here, note that by performing reordering of rows (row permutation) and reordering of columns (column permutation), the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) can be obtained from each of the parity check matrix H2, the parity check matrix H2,s, the parity check matrix H4, and the parity check matrix H4,s,.

[1278] Similarly, a matrix obtained by performing both reordering of columns (column permutation) as described above and reordering of rows (row permutation) as described above on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) may be used as a parity check matrix.

[1279] In such a case, a parity check matrix H5 is obtained by performing reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H6 is obtained by performing reordering of rows (row permutation) on the parity check matrix H5 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). A transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H6 so obtained.

[1280] Also, a parity check matrix H5,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H6,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix H5,1 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36).

[1281] Further, a parity check matrix H5,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H6,1. Finally, a parity check matrix H6,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H5,2.

[1282] As described above, a parity check matrix H6,s may be obtained by repetitively performing reordering of columns (column permutation) and reordering of rows (row permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H5,k is obtained by performing a kth (where k is an integer no smaller than two and no greater than s) reordering of columns (column permutation) on a parity check matrix H6,k-1. Then, a parity check matrix H6,k is obtained by performing a kth reordering of rows (row permutation) on the parity check matrix H5,k. Note that in the first instance, a parity check matrix H5,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H6,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H5,1.

[1283] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H6,s.

[1284] In an alternative method, a parity check matrix H7 is obtained by performing reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H8 is obtained by performing reordering of columns (column permutation) on the parity check matrix H7 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H8 so obtained.

[1285] Also, a parity check matrix H7,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H8,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix H7,1 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33).

[1286] Then, a parity check matrix H7,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H8,1. Finally, a parity check matrix H8,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H7,2.

[1287] As described above, a parity check matrix H8,s may be obtained by repetitively performing reordering of rows (row permutation) and reordering of columns (column permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H7,k is obtained by performing a kth (where k is an integer no smaller two and no greater than s) reordering of rows (row permutation) on a parity check matrix H8,k-1. Then, a parity check matrix H8,k is obtained by performing a kth reordering of columns (column permutation) on the parity check matrix H7,k. Note that in the first instance, a parity check matrix H7,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H8,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H7,1.

[1288] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H8,s.

[1289] Here, note that by performing reordering of rows (row permutation) and reordering of columns (column permutation), the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) can be obtained from each of the parity check matrix H6, the parity check matrix H6,s, the parity check matrix H8, and the parity check matrix H8,s,.

[1290] In the present embodiment, description is provided of a method of generating a parity check matrix equivalent to a parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) by performing reordering of rows (row permutation) and/or reordering of columns (column permutation) with respect to the parity check matrix H. Further, description is provided of a method of applying the equivalent parity check matrix in, for example, a communication/broadcast system using an encoder and a decoder using the equivalent parity check matrix. Note that the error correction code described herein may be applied to various fields, including but not limited to communication/broadcast systems.

(Embodiment 6)



[1291] In the present embodiment, description is provided of a device that uses the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), description of which is provided in embodiment 4.

[1292] As one example, description is provided of a case where the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is applied to a communication device.

[1293] Fig. 22 illustrates the structures of a transmitting device 2200 and a receiving device 2210 in the communication device pertaining to the present embodiment.

[1294] An encoder 2201 receives information to be transmitted as input, and is capable of performing various types of encoding (e.g., various coding rates and various block lengths of block codes (for example, in systematic codes, the sum of the number of information bits and the number of parity bits)). In particular, when receiving a specification to perform encoding by using the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), the encoder 2201 performs encoding by using the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) to calculate parities P1 and P2. Further, the encoder 2201 outputs the information to be transmitted and the parities P1 and P2 as a transmission sequence.

[1295] A modulator 2202 receives the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, performs mapping based on a predetermined modulation scheme (for example, BPSK, QPSK, 16QAM, or 64QAM), and outputs a baseband signal. Further, the modulator 2202 may also receive information other than the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, as input, perform mapping, and output a baseband signal. For example, the modulator 2202 may receive control information as input.

[1296] The transmitting device outputs a transmission signal after performing predetermined signal processing (e.g., signal processing for generation of an OFDM signal, frequency conversion, amplification) with respect to such signals (e.g., baseband signals, pilot signals). The transmitting device may transmit the transmission signal over a wireless transmission path utilizing electromagnetic waves, or over a wired transmission path utilizing a coaxial cable, a power line, an optical cable, or the like.

[1297] The transmission signal is received by the receiving device 2210 after travelling over the transmission path. A receiver 2211 receives a reception signal as input, performs predetermined signal processing (e.g., bandwidth limitation, frequency conversion, signal processing for OFDM, frequency offset estimation, signal detection, channel estimation), and outputs a baseband signal and a channel estimation signal.

[1298] A log-likelihood ratio generation section 2212 receives the baseband signal and the channel estimation signal as input (may receive other signals as input), and for example, calculates and outputs a log-likelihood ratio for each bit (may calculate and output a hard value (hard decision value)).

[1299] A decoder 2213 receives the log-likelihood ratio for each bit as input, performs belief propagation decoding (e.g., sum-product decoding, scheduled sum-product decoding (Layered BP (belief propagation) decoding), min-sum decoding, Normalized BP decoding, offset BP decoding), and outputs an estimation sequence. The decoder 2213 performs the belief propagation decoding based on the parity check matrix for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1300] Although description is provided above taking an example where error correction coding is introduced to a communication device, the error correction coding described above is not limited to being introduced to a communication device, and for example, may be introduced to a storage medium (storage). When making such a modification, information that is to be stored to a storage medium (storage) is encoded by using the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and resultant information and parities are stored to the storage medium (storage).

[1301] Further, the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is applicable to any device that requires error correction coding (e.g., a memory, a hard disk).

[1302] Note that when using a block code such as the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) in a device, there as cases where special processing needs to be executed.

[1303] Assume that a block length of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) used in a device is 16000 bits (8000 information bits, and 8000 parity bits).

[1304] In such a case, the number of information bits necessary for encoding one block is 8000. Meanwhile, there are cases where the number of bits of information input to an encoding section of the device does not reach 8000. For example, assume a case where only 7000 information bits are input to the encoding section.

[1305] Here, it is assumed that the encoding section, in the above-described case, adds 1000 padding bits of information to the 7000 information bits having been input, and performs encoding by using a total of 8000 bits, composed of the 7000 information bits having been input and the 1000 padding bits, to generate 8000 parity bits. Here, assume that all of the 1000 padding bits are known bits. For example, assume that each of the 1000 padding bits is "0".

[1306] A transmitting device may output the 7000 information bits having been input, the 1000 padding bits, and the 8000 parity bits. Alternatively, a transmitting device may output the 7000 information bits having been input and the 8000 parity bits.

[1307] In addition, a transmitting device may perform puncturing with respect to the 7000 information bits having been input and the 8000 parity bits, and thereby output a number of bits smaller than 15000 in total.

[1308] Note that when performing transmission in such a manner, the transmitting device is required to transmit, to a receiving device, information notifying the receiving device that transmission has been performed in such a manner.

[1309] As described above, the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), description of which is provided in embodiment 4, is applicable to various devices.

(Embodiment 7)



[1310] In some embodiments in the present disclosure, description is provided of LDPC block codes, and encoders and decoders using the LDPC block codes. In the present embodiment, description is provided of a method of configuring a code length (block length) of an LDPC block code in a base station (or an access point or a broadcast station) of a communication device and a terminal device.

[1311] FIG. 46 is an overall diagram of a communication system (or a broadcast system). Components that operate similarly in FIG. 46 and FIG. 25 are provided with the same reference signs.

[1312] One characteristic aspect is that an encoding section 2511 in a transmitting device 2510 receives a control signal 4601 as input, and performs encoding on information based on information included in the control signal 4601 indicating coding rate and block length.

[1313] In addition, a modulating section 2512 receives the control signal 4601 as input, and performs processing such as mapping based on information included in the control signal 4601 indicating a modulation scheme. Details of operations are described later in the present embodiment.

[1314] Note that the transmitting device 2510 needs to transmit, to a receiving device 2511, information on the coding rate and block length applied in the encoding performed by the encoding section 2511, and information on the modulation scheme applied in the mapping performed by the modulating section 2512. Accordingly, the transmitting device 2510 transmits a control information symbol 4701 and a data symbol 4702, as illustrated in FIG. 47.

[1315] FIG. 47 illustrates one example of a time-domain frame configuration of transmission signal transmitted by the transmitting device 2510. In FIG. 47, the horizontal axis indicates time. In FIG. 47, information that the receiving device 2520 needs in order to perform wave detection and decoding, such as the coding rate and the block length of the code used by the transmitting device 2510, and the modulation scheme and the transmission scheme used by the transmitting device 2510, is transmitted by using the control information symbol 4701. The data symbol 4702 is a symbol transmitting data. Note that data transmitted by using this symbol is encoded.

[1316] In the receiving device 2520 in FIG. 46, a receiving unit 2521 receives a reception signal as input and extracts a control information symbol included in the reception signal, whereby the receiving unit 2521 obtains control information. Further, the receiving unit 2521 outputs a control signal 4602. Accordingly, a log-likelihood ratio generation section 2522 receives as control signal 4602 as input, and calculates log-likelihood ratios based on information on modulation scheme included in the control signal 4602. Further, a decoder 2523 receives the control signal 4602 as input and performs decoding in accordance with a code (e.g., coding rate and code length) based on the control signal 4602. Note that when an LDPC code is used, the decoder 2523 performs decoding described in, for instance, Non-Patent Literature 4, Non-Patent Literature 6, Non-Patent Literature 7, and Non-Patent Literature 8, including simple BP decoding such as min-sum decoding, offset BP decoding, and normalized BP decoding, and Belief Propagation (BP) decoding in which scheduling is performed with respect to the row operations (horizontal operations) and the column operations (vertical operations) such as shuffled BP decoding, layered BP decoding, and pipeline decoding, or decoding such as bit-flipping decoding described in Non-Patent Literature 17, etc.

[1317] The following describes a specific method of configuring a code length (block length) of an LDPC block code.

[1318] FIG. 48 illustrates one example of a configuration of a part of a transmitting device in a base station (may be a broadcast station, an access point, etc.,) that generates a modulated signal, in a configuration where switching between transmission schemes is possible.

[1319] In the present embodiment, description is provided while assuming that both a transmission scheme where a single stream is transmitted and transmission scheme where two streams are transmitted (MIMO (Multiple Input Multiple Output) scheme) are possible. When transmitting a single stream, the single stream may be transmitted by using one antenna, or by using two antennas. This is described in detail later in the present disclosure. First, description is provided on a transmission scheme where a transmitting device in a base station (may be a broadcast station, an access point, etc.,) transmits two streams, with reference to FIG. 48.

Transmission Scheme Where Two Streams Are Transmitted



[1320] An encoding section 4802 in FIG. 48 receives information 4801 and a control signal 4812 as input. The encoding section 4802 performs encoding based on information included in the control signal 4812 indicating coding rate and code length (block length). The encoding section 4802 outputs encoded data 4803.

[1321] A mapping section 4804 receives the encoded data 4803 and the control signal 4812 as input. The following assumes that the control signal 4812 specifies a transmission scheme where two streams are transmitted. Further, the following assumes that the control signal 4812 specifies, as respective modulation schemes for the two streams, modulation scheme α and modulation scheme β. Here, modulation scheme α modulates x bits of data, and modulation scheme β modulates y bits of data. (For example, when the modulation scheme is 16QAM (16 Quadrature Amplitude Modulation, 4 bits of data are modulated, and when the modulation scheme is 64QAM (64 Quadrature Amplitude Modulation), 6 bits of data are modulated.)

[1322] Based on the above, the mapping section 4804 modulates x bits of data, among x+y bits of data, according to modulation scheme α to generate and output a baseband signal s1(t)(4805A). Further, the mapping section 4804 modulates the remaining y bits of data, among x+y bits of data, according to modulation scheme β to generate and output a baseband signal s2(t)(4805B). Note that each of s1(t) and s2(t) is expressed by a complex number (may also be expressed by a real number), and t indicates time. Note that when using a multi-carrier transmission scheme such as OFDM (Orthogonal Frequency Division Multiplexing), s1 and s2 may be considered as functions of frequency f (in which case s1 and s2 are, for example, s1(f) and s2(f), respectively), or may be considered as functions of time t and frequency f (in which case s1 and s2 are, for example, s1(t, f) and s2(t, f), respectively).

[1323] A power changing section 4806A receives the baseband signal s1(t)(4805A) and the control signal 4812 as input. The power changing section 4806A sets a real number P1 (may also be a complex number) based on the control signal 4812. The power changing section 4806A outputs P1×s1(t) as a power-changed signal 4807A.

[1324] Similarly, a power changing section 4806B receives the baseband signal s2(t)(4805B) and the control signal 4812 as input. The power changing section 4806B sets a real number P2 (may also be a complex number) based on the control signal 4812. The power changing section 4806B outputs P2×S2(t) as a power-changed signal 4807B.

[1325] A weight-combining section 4808 receives the power changed-signal 4807A, the power-changed signal 4807B, and the control signal 4812 as input. The weight-combining section 4808 sets a precoding matrix F (or F(i)) based on the control signal 4812. When denoting slot number (symbol number) as i, the weight-combining section 4808 performs the following calculation.
[Math. 222]



[1326] Here, each of a(i), b(i), c(i), d(i) is expressible by using a complex number (may be expressed by using a real number), no more than two of a(i), b(i), c(i), d(i) may be "0". Further, the precoding matrix may or may not be a function of i. When the precoding matrix is a function of i, the precoding matrix switches for different slot numbers (symbol numbers).

[1327] Further, the weight-combining section 4808 outputs u1(i) in expression (A1) as a weight-combined signal 4809A, and outputs u2(i) in expression (A2) as a weight-combined signal 4809B.

[1328] A power changing section 4810A receives the weight-combined signal 4809A (u1(i)) and the control signal 4812 as input. The power changing section 4810A sets a real number Q1 (may also be a complex number) based on the control signal 4812. The power changing section 4810A outputs Q1×u1(t) as a power-changed signal 4811A (z1(i)).

[1329] Similarly, a power changing section 4810B receives the weight-combined signal 4809B (u2(i)) and the control signal 4812 as input. The power changing section 4810B sets a real number Q2 (may also be a complex number) based on the control signal 4812. The power changing section 4810A outputs Q2×u2(t) as a power-changed signal 4811B (z2(i)).

[1330] Accordingly, the following holds true.
[Math. 223]





[1331] Nest, description is provided on a transmission scheme where two streams are transmitted different from that explained with reference to FIG. 48, with reference to FIG. 49. Components that operate similarly in FIG. 48 and FIG. 49 are provided with the same reference signs.

[1332] A phase changing section 4901 receives the weight-combined signal 4809B, which corresponds to u2(i) in expression (A1), and the control signal 4812 as input. The phase changing section 4901 changes a phase of the weight-combined signal 4809B, which corresponds to u2(i) in expression (A1), based on the control signal 4812. A signal resulting from changing the phase of weight-combined signal 4809B, which corresponds to u2(i) in expression (A1), is expressible as ejθ(i)×u2(i) (where j is an imaginary unit). Accordingly, the phase changing section 4901 outputs ejθ(i)×u2(i) as a phase-changed signal 4902. Here, note that the value of the phase that is changed is a part such as θ(i) that is characterized by being a function of i.

[1333] Further, the power changing sections 4810A and 4810B in FIG. 49 change the power of the respective signals that are input. Accordingly, output z1(i) of the power changing section 4810A in FIG. 49 and output z2(i) of the power changing section 4810B in FIG. 49 are expressible as follows.
[Math. 224]



[1334] FIG. 50 illustrates a configuration that realizes expression (A3) differing from that illustrated in FIG. 49. FIG. 50 differs from FIG. 49 in terms of the order in which the power changing units and the phase changing unit are arranged. (Note that the function of the power changing units of changing power and the function of the phase changing unit of changing phase remains the same in FIG. 49 and FIG. 50.) When the configuration illustrated in FIG. 50 is applied, z1(i) and z2(i) are expressible as follows.
[Math. 225]



[1335] Note that z1(i) in expression (A3) and z1(i) in expression (A4) are equal, and z2(i) in expression (A3) and z2(i) in expression (A4) are equal.

[1336] FIG. 51 illustrates one example of a configuration of a signal processing section that performs signal processing on the signals z1(i) and z2(i) obtained in FIGs. 48 through 50.

[1337] An inserting section 5104A receives the signal z1(i) (5101A), a pilot symbol 5102A, a control information symbol 5103A, and the control signal 4812 as input. The inserting section 5104A inserts the pilot symbol 5102A and the control information symbol 5103A into the signal (symbol) z1(i) (5101A) based on the frame configuration included in the control signal 4812. The inserting section 5104A outputs a modulated signal 5105A that is in accordance with the frame configuration included in the control signal 4812.

[1338] Note that the pilot symbol 5102A and the control information symbol 5103A are symbols modulated by using a modulation scheme such as BPSK (Binary Phase Shift Keying) or QPSK (Quadrature Phase Shift Keying) (other modulation schemes may also be used).

[1339] A wireless section 5106A receives the modulated signal 5105A and the control signal 4812 as input. The wireless section 5106A performs processing such as frequency conversion and amplification (processing such as inverse Fourier transform is performed when an OFDM scheme is being used) on the modulated signal 5105A based on the control signal 4812. The wireless section 5106A outputs a transmission signal 5107A. The transmission signal 5107A is output in the form of electric waves from an antenna 5108A.

[1340] An inserting section 5104B receives the signal z2(i) (5101B), a pilot symbol 5102B, a control information symbol 5103B, and the control signal 4812 as input. The inserting section 5104B inserts the pilot symbol 5102B and the control information symbol 5103B into the signal (symbol) z2(i) (5101B) based on the frame configuration included in the control signal 4812. The inserting section 5104B outputs a modulated signal 5105B that is in accordance with the frame configuration included in the control signal 4812.

[1341] Note that the pilot symbol 5102B and the control information symbol 5103B are symbols modulated by using a modulation scheme such as BPSK (Binary Phase Shift Keying) or QPSK (Quadrature Phase Shift Keying) (other modulation schemes may also be used).

[1342] A wireless section 5106B receives the modulated signal 5105B and the control signal 4812 as input. The wireless section 5106B performs processing such as frequency conversion and amplification (processing such as inverse Fourier transform is performed when an OFDM scheme is being used) on the modulated signal 5105B based on the control signal 4812. The wireless section 5106B outputs a transmission signal 5107B. The transmission signal 5107B is output in the form of electric waves from an antenna 5108B.

[1343] Here, a signal z1(i)(5101A) and a signal z2(i)(5101B) for the same value of i are transmitted from different antennas on the same frequency and at the same time. (In other words, transmission of such signals is performed by using a MIMO scheme.)

[1344] Further, the pilot symbols 5102A and 5102B are symbols enabling a receiving device to perform signal detection, estimation of frequency offset, gain control, channel estimation, and the like. Although the term pilot symbol is used in the present embodiment to refer to such symbols, such a symbol may be referred to by using other terms, such as a reference symbol.

[1345] Further, the control information symbol 5103A and the control information symbol 5103B are symbols for transmitting, to a receiving device, information such as information on a modulation scheme used by the transmitting device, information on a transmission scheme used by the transmitting device, information on a precoding scheme used by the transmitting device, information on an error correction coding scheme used by the transmitting device, information on coding rate of an error correction code, and information on block length (code length) of the error correction code. Note that the control information symbol may be transmitted by using only one of the control information symbol 5103A and the control information symbol 5103B.

[1346] FIG. 53 illustrates one example of a time and frequency domain frame configuration when two streams are transmitted. In FIG. 53, the horizontal axis indicates frequency and the vertical axis indicates time. Further, FIG. 53 illustrates, as one example, a configuration of symbols between carrier "1" and carrier "38", and between time "$1" and time "$11".

[1347] FIG. 53 also includes illustration of a frame configuration of the transmission signal transmitted from the antenna 5108A in FIG. 51 and a frame configuration of the transmission signal transmitted from the antenna 5108B in FIG. 51.
In FIG. 53, in a frame of the transmission signal transmitted from the antenna 5108A, signal (symbol) z1(i) is a data symbol. Further, the pilot symbol 5102A is a pilot symbol.

[1348] In FIG. 53, in a frame of the transmission signal transmitted from the antenna 5108B, signal (symbol) z2(i) is a data symbol. Further, the pilot symbol 5102B is a pilot symbol.

[1349] Although FIG. 53 only includes illustration of data symbols and pilot symbols, frames may include other symbols, such as a control information symbol.

[1350] Next, description is provided on a transmission scheme where a transmitting device in a base station (may be a broadcast station, an access point, etc.,) transmits a single stream, with reference to FIG. 48.

Transmission Scheme Where One Stream Is Transmitted



[1351] An encoding section 4802 in FIG. 48 receives information 4801 and a control signal 4812 as input. The encoding section 4802 performs encoding based on information included in the control signal 4812 indicating coding rate and code length (block length). The encoding section 4802 outputs encoded data 4803.

[1352] A mapping section 4804 receives the encoded data 4803 and the control signal 4812 as input. The following assumes that the control signal 4812 specifies a transmission scheme where a single stream is transmitted. Further, the following assumes that the control signal 4812 specifies, as the modulation scheme for the single stream, modulation scheme y. Here, modulation scheme y modulates z bits of data.

[1353] Based on the above, the mapping section 4804 modulates z bits of data according to modulation scheme y to generate and output a baseband signal S(t). Further, the mapping section 4804, by utilizing s1(t)=s2(t)=S(t), outputs a baseband signal s1(t)=S(t)(4805A) and a baseband signal s2(t)=S(t)(4805B).

[1354] Note that each of s1(t) and s2(t) is expressed by a complex number (may also be expressed by a real number), and t indicates time. Note that when using a multi-carrier transmission scheme such as OFDM (Orthogonal Frequency Division Multiplexing), s1 and s2 may be considered as functions of frequency f (in which case s1 and s2 are, for example, s1(f) and s2(f), respectively), or may be considered as functions of time t and frequency f (in which case s1 and s2 are, for example, s1(t,f) and s2(t,f), respectively).

[1355] A power changing section 4806A receives the baseband signal s1(t)=S(t)(4805A) and the control signal 4812 as input. The power changing section 4806A sets a real number P1 (may also be a complex number) based on the control signal 4812. The power changing section 4806A outputs P1×s1(t) as a power-changed signal 4807A.

[1356] Similarly, a power changing section 4806B receives the baseband signal s2(t)=S(t)(4805B) and the control signal 4812 as input. The power changing section 4806B sets a real number P2 (may also be a complex number) based on the control signal 4812. The power changing section 4806B outputs P2×s2(t) as a power-changed signal 4807B.

[1357] A weighting and combining section 4808 receives the power changed-signal 4807A, the power-changed signal 4807B, and the control signal 4812 as input. The weighting and combining section 4808 sets a precoding matrix F based on the control signal 4812. When denoting slot number (symbol number) as i, the weighting and combining section 4808 performs the following calculation.
[Math. 226]



[1358] Here, a is expressible as a complex number (may also e expressible as a real number). However, a is not "0" (zero).

[1359] Further, the weight-combining section 4808 outputs u1(i) in expression (A5) as a weight-combined signal 4809A, and outputs u2(i) in expression (A5) as a weight-combined signal 4809B.

[1360] A power changing section 4810A receives the weight-combined signal 4809A (u1(i)) and the control signal 4812 as input. The power changing section 4810A sets a real number Q1 (may also be a complex number) based on the control signal 4812. The power changing section 4810A outputs Q1×u1(t) as a power-changed signal 4811A (z1(i)).

[1361] Similarly, a power changing section 4810B receives the weight-combined signal 4809B (u2(i)) and the control signal 4812 as input. The power changing section 4810B sets a real number Q2 (may also be a complex number) based on the control signal 4812. The power changing section 4810B outputs Q2×u2(t) as a power-changed signal 4811B (z2(i)).

[1362] Accordingly, the following holds true.
[Math. 227]





[1363] Next, description is provided on a transmission scheme where a single stream is transmitted different from that explained with reference to FIG. 48, with reference to FIG. 49. Components that operate similarly in FIG. 48 and FIG. 49 are provided with the same reference signs.

[1364] A phase changing section 4901 receives the weight-combined signal 4809B, which corresponds to u2(i) in expression (A5), and the control signal 4812 as input. The phase changing section 4901 changes a phase of the weight-combined signal 4809B, which corresponds to u2(i) in expression (A5), based on the control signal 4812. A signal resulting from changing the phase of weight-combined signal 4809B, which corresponds to u2(i) in expression (A5), is expressible as ejθ(i)×u2(i) (where j is an imaginary unit). Accordingly, the phase changing section 4901 outputs ejθ(i)×u2(i) as a phase-changed signal 4902. Here, note that the value of the phase that is changed is a part such as θ(i) that is characterized by being a function of i.

[1365] Further, the power changing sections 4810A and 4810B in FIG. 49 change the power of the respective signals that are input. Accordingly, output z1(i) of the power changing section 4810A in FIG. 49 and output z2(i) of the power changing section 4810B in FIG. 49 are expressible as follows.
[Math. 228]





[1366] FIG. 50 illustrates a configuration that realizes expression (A7) differing from that illustrated in FIG. 49. FIG. 50 differs from FIG. 49 in terms of the order in which the power changing units and the phase changing unit are arranged. (Note that the function of the power changing units of changing power and the function of the phase changing unit of changing phase remains the same in FIG. 49 and FIG. 50.) When the configuration illustrated in FIG. 50 is applied, z1(i) and z2(i) are expressible as follows.
[Math. 229]



[1367] Note that z1(i) in expression (A7) and z1(i) in expression (A8) are equal, and z2(i) in expression (A7) and z2(i) in expression (A8) are equal.

[1368] FIG. 51 illustrates one example of a configuration of a signal processing section that performs signal processing on the signals z1(i) and z2(i) obtained in FIGs. 48 through 50.

[1369] An inserting section 5104A receives the signal z1(i) (5101A), a pilot symbol 5102A, a control information symbol 5103A, and the control signal 4812 as input. The inserting section 5104A inserts the pilot symbol 5102A and the control information symbol 5103A into the signal (symbol) z1(i) (5101A) based on the frame configuration included in the control signal 4812. The inserting section 5104A outputs a modulated signal 5105A that is in accordance with the frame configuration included in the control signal 4812.

[1370] Note that the pilot symbol 5102A and the control information symbol 5103A are symbols modulated by using a modulation scheme such as BPSK (Binary Phase Shift Keying) or QPSK (Quadrature Phase Shift Keying) (other modulation schemes may also be used).

[1371] A wireless section 5106A receives the modulated signal 5105A and the control signal 4812 as input. The wireless section 5106A performs processing such as frequency conversion and amplification (processing such as inverse Fourier transform is performed when an OFDM scheme is being used) on the modulated signal 5105A based on the control signal 4812. The wireless section 5106A outputs a transmission signal 5107A. The transmission signal 5107A is output in the form of electric waves from an antenna 5108A.

[1372] An inserting section 5104B receives the signal z2(i) (5101B), a pilot symbol 5102B, a control information symbol 5103B, and the control signal 4812 as input. The inserting section 5104B inserts the pilot symbol 5102B and the control information symbol 5103B into the signal (symbol) z2(i) (5101B) based on the frame configuration included in the control signal 4812. The inserting section 5104B outputs a modulated signal 5105B that is in accordance with the frame configuration included in the control signal 4812.

[1373] Note that the pilot symbol 5102B and the control information symbol 5103B are symbols modulated by using a modulation scheme such as BPSK (Binary Phase Shift Keying) or QPSK (Quadrature Phase Shift Keying) (other modulation schemes may also be used).

[1374] A wireless section 5106B receives the modulated signal 5105B and the control signal 4812 as input. The wireless section 5106B performs processing such as frequency conversion and amplification (processing such as inverse Fourier transform is performed when an OFDM scheme is being used) on the modulated signal 5105B based on the control signal 4812. The wireless section 5106B outputs a transmission signal 5107B. The transmission signal 5107B is output in the form of electric waves from an antenna 5108B.

[1375] Here, a signal z1(i)(5101A) and a signal z2(i)(5101B) for the same value of i are transmitted from different antennas on the same frequency and at the same time. (In other words, transmission of such signals is performed by using a MIMO scheme.)

[1376] Further, the pilot symbols 5102A and 5102B are symbols enabling a receiving device to perform signal detection, estimation of frequency offset, gain control, channel estimation, and the like. Although the term pilot symbol is used in the present embodiment to refer to such symbols, such a symbol may be referred to by using other terms, such as a reference symbol.

[1377] Further, the control information symbol 5103A and the control information symbol 5103B are symbols for transmitting, to a receiving device, information such as information on a modulation scheme used by the transmitting device, information on a transmission scheme used by the transmitting device, information on a precoding scheme used by the transmitting device, information on an error correction coding scheme used by the transmitting device, information on coding rate of an error correction code, and information on block length (code length) of the error correction code. Note that the control information symbol may be transmitted by using only one of the control information symbol 5103A and the control information symbol 5103B.

[1378] FIG. 52 illustrates one example of a time and frequency domain frame configuration when a single stream is transmitted. In FIG. 52, the horizontal axis indicates frequency and the vertical axis indicates time. Further, FIG. 53 illustrates, as one example, a configuration of symbols between carrier "1" and carrier "38", and between time "$1" and time "$11".

[1379] FIG. 52 also includes illustration of a frame configuration of the transmission signal transmitted from the antenna 5108A in FIG. 51 and a frame configuration of the transmission signal transmitted from the antenna 5108B in FIG. 51.

[1380] In FIG. 52, in a frame of the transmission signal transmitted from the antenna 5108A, signal (symbol) z1(i) is a data symbol. Further, the pilot symbol 5102A is a pilot symbol.

[1381] In FIG. 52, in a frame of the transmission signal transmitted from the antenna 5108B, signal (symbol) z2(i) is a data symbol. Further, the pilot symbol 5102B is a pilot symbol.

[1382] Although FIG. 52 only includes illustration of data symbols and pilot symbols, frames may include other symbols, such as a control information symbol.

[1383] In the description provided above, in expression (A5) through (A8), the precoding matrix F is set as follows.
[Math. 230]



[1384] However, in expression (A5) through (A8), the precoding matrix F may be set as follows.
[Math. 231]



[1385] Here, a is expressible by using a complex number (may also be expressed by using a real number). However, a is not "0" (zero).

[1386]  z2(i)=0 holds true in this case. In this case, a modulated signal need not be transmitted from the antenna 5108B. Accordingly, the inserting section 5104B need not perform insertion of the pilot symbol 5102B and the control information symbol 5103B.

(Embodiment 8)



[1387] The following describes the configuration of an example of a system using the encoding method and the decoding method described in the above embodiment, as an example of corresponding a transmission method and reception method.

[1388] FIG. 54 is a system configuration diagram including a device executing a transmission method and a reception method applying the coding and decoding methods described in the above embodiment. As shown in FIG. 54, the transmission method and the reception method are implemented by a digital broadcasting system 7700 that includes a broadcasting station 7701 and various types of receivers, such as a television 7711, a DVD recorder 7712, a set-top box (hereinafter STB) 7713, a computer 7720, an on-board television 7741, and a mobile phone 7700. Specifically, the broadcasting station 7701 transmits multiplexed data, in which video data, audio data, and so on have been multiplexed, in a predetermined transmission band using the transmission method described in the above embodiment.

[1389] The signal transmitted by the broadcasting station 7701 is received by an antenna (e.g., an antenna 7740) equipped on each of the receivers or installed externally and connected to the receivers. Each of the receivers demodulates the signal received by the antenna to acquire the multiplexed data. Accordingly, the digital broadcasting system 7700 is capable of supplying the effect described in the above embodiment of the present invention.

[1390] Here, the video data included in the multiplexed data are, for example, encoded using a video coding method conforming to a standard such as MPEG-2 (Moving Picture Experts Group), MPEG4-AVC (Advanced Video Coding), VC-1, or similar. Similarly, the audio data included in the multiplexed data are, for example, encoded using an audio coding method such as Dolby AC-3 (Audio Coding), Dolby Digital Plus, MLP (Meridian Lossless Packing), DTS (Digital Theatre Systems), DTS-HD, Linear PCM (Pulse Coding Modulation), or similar.

[1391] FIG. 55 illustrates an example of the configuration of the receiver 7800. As shown in FIG. 55, as an example configuration for a receiver 7800 a possible configuration method involves a single LSI (or chipset) forming a modem unit, and a separate single LSI (or chipset) forming a codec unit. The receiver 7800 shown in FIG. 55 corresponds to the configuration of the television 7711, the DVD recorder 7712, the set-top box 7713, the computer 7720, the on-board television 7741, and the mobile phone 7730 shown in FIG. 54. The receiver 7800 includes a tuner 7801 converting the high-frequency signal received by the antenna 7860 into a baseband signal, and a demodulator 7802 acquiring the multiplexed data by demodulating the baseband signal so converted. The reception method described in the above embodiment is implemented by the demodulator 7802, which is thus able to provide the results described in the above embodiment of the present invention.

[1392] Also, the receiver 7800 includes a stream I/O section 7803 separating the multiplexed data obtained by the demodulator 7802 into video data and audio data, a signal processing section 7804 decoding the video data into a video signal using a video decoding method corresponding to the video data so separated, and decoding the audio data into an audio signal using an audio decoding method corresponding to the audio data so separated, an audio output section 7806 outputting the decoded audio signal to speakers or the like, and a video display section 7807 displaying the decoded video signal on a display or the like.

[1393] For example, the user uses a remote control 7850 to transmit information on a selected channel (or a selected (television) program) to an operation input section 7810. Then, the receiver 7800 demodulates a signal corresponding to the selected channel using the received signal received by the antenna 7860, and performs error correction decoding and so on to obtain received data. Here, the receiver 7800 obtains control symbol information, which includes information on the transmission method included in the signal corresponding to the selected channel, and is thus able to correctly set the methods for the receiving operation, demodulating operation, error correction decoding, and so on (when a plurality of error correction decoding methods are prepared as described in the present document (e.g., a plurality of different codes are prepared, or a plurality of codes having different coding rates are prepared), the error correction decoding method corresponding to the error correction codes set from among a plurality of error correction codes are used. As such, the data included in the data symbols transmitted by the broadcasting station (base station) are made receivable. The above describes an example where the user selects a channel using the remote control 7850. However, the above-described operations are also possible using a selection key installed on the receiver 7800 for channel selection.

[1394] According to the above configuration, the user is able to view a program received by the receiver 7800 using the reception method described in the above embodiment.

[1395] Also, the receiver 7800 of the present embodiment includes a drive 7808 recording the data obtained by processing the data included in the multiplexed data obtained through demultiplexing by the demodulator 7802 and by performing error correction decoding (i.e., performing decoding using a decoding method corresponding to the error correction decoding described in the present document) (in some circumstances, error correction decoding may not be performed on the signal obtained through the demodulation by the demodulator 7802; the receiver 7800 may apply other signal processing after the error correction decoding. These variations also apply to similarly-worded portions, below), or data corresponding thereto (e.g., data obtained by compressing such data), as well as data obtained by processing video and audio onto a magnetic disc, an optical disc, a non-volatile semiconductor memory, or other recording medium. Here, the optical disc is a recording medium from which information is read and to which information is recorded using a laser, such as a DVD (Digital Versatile Disc) or BD (Blu-ray Disc). The magnetic disc is a recording medium where information is stored by magnetising a magnetic body using a magnetic flux, such as a floppy disc or hard disc. The non-volatile semi-conductor memory is a recording medium incorporating a semiconductor, such as Flash memory or ferroelectric random access memory, for example an SD card using flash memory or a Flash SSD (Solid State Drive). The examples of recording media here given are simply examples, and no limitation is intended regarding the use of recording media other than those listed for recording.

[1396] According to the above configuration, the user is able to view a program that the receiver 7800 has received through the recording method given in the above embodiment, stored, and read as data at a freely selected time after the time of broadcast.

[1397] Although the above explanation describes the receiver 7800 as recording, onto the drive 7808, the multiplexed data obtained by having the demodulator 7802 perform demodulation and then performing error correction decoding (performing decoding with a decoding method corresponding to the error correction decoding described in the present document), a portion of the data included in the multiplexed data may also be extracted for recording. For example, when data broadcasting service content or similar data other than the video data and the audio data are included in the multiplexed data that the demodulator 7802 demodulates and to which error correction decoding is applied, the drive 7808 may extract the video data and the audio data from the multiplexed data demodulated by the demodulator 7802, and multiplex these data into new multiplexed data for recording. Also, the drive 7808 may multiplex only one of the audio data and the video data included in the multiplexed data obtained through demodulation by the demodulator 7802 and performing error correction decoding into new multiplexed data for recording. The drive 7808 may also record the aforementioned data broadcasting service content included in the multiplexed data.

[1398] Furthermore, when the television, the recording device (e.g., DVD recorder, Blu-ray recorder, HDD recorder, SD card, or similar), or the mobile phone is equipped with the receiver described in the present invention, the multiplexed data obtained through demultiplexing by the demodulator 7802 and by performing error correction decoding (i.e., performing decoding using a decoding method corresponding to the error correction decoding described in the present document) may include data for correcting software bugs using the television or the recording device, or data for correcting software bugs so as to prevent leakage of personal information or recorded data. These data may be installed so as to correct software bugs in the television or the recording device. As such, when data for correcting software bugs in the receiver 7800 are included in the data, the receiver 7800 bugs are corrected thereby. Accordingly, the television, recording device, or mobile phone equipped with the receiver 7800 is able to operate in a more stable fashion.

[1399] The process of extracting a portion of data from among the data included in the multiplexed data obtained through demultiplexing by the demodulator 7802 and by performing error correction decoding (i.e., performing decoding using a decoding method corresponding to the error correction decoding described in the present document) is performed, for example, by the stream I/O section 7803. Specifically, the stream I/O section 7803 separates the multiplexed data demodulated by the demodulator 7802 into video data, audio data, data broadcasting service content, and other types of data in accordance with instructions from a control unit in a non-diagrammed CPU or similar, and multiplexes only the data designated among the separated data to generate new multiplexed data. The question of which data to extract from among the separated data may be, for example, decided by the user, or decided in advance for each type of recording medium.

[1400] According to the above configuration, the receiver 7800 is able to record only those data extracted as needed for viewing the recorded program, and is able to reduce the size of the recorded data.

[1401] Also, although the above explanation describes the drive 7808 as recording the multiplexed data obtained through demultiplexing by the demodulator 7802 and by performing error correction decoding (i.e., performing decoding using a decoding method corresponding to the error correction decoding described in the present document), the video data included in the data obtained through demultiplexing by the demodulator 7802 and by performing error correction decoding may be converted into video data encoded with a video coding method different from the video coding method originally applied to the video data, so as to decrease the size of the data or reduce the bit rate thereof, and the converted video data may be multiplexed into new multiplexed data for recording. Here, the video coding method applied to the original video data and the video coding method applied to the converted video data may conform to different standards, or may conform to the same standard but differ only in terms of parameters. Similarly, the drive 7808 may also convert the audio data included in the data obtained through demultiplexing by the demodulator 7802 and by performing error correction decoding into audio data encoded with an audio coding method different from the audio coding method originally applied to the audio data, so as to decrease the size of the data or reduce the bit rate thereof, and the converted audio data may be multiplexed into new multiplexed data for recording

[1402] The process of converting the audio data and the video data from the multiplexed data obtained through demultiplexing by the demodulator 7802 and by performing error correction decoding (i.e., performing decoding using a decoding method corresponding to the error correction decoding described in the present document) into the audio data and the video data having decreased sizes and reduced bitrates is performed by the stream I/O section 7803 and the signal processing section 7804, for example. Specifically, the stream I/O section 7803 separates the data obtained through demultiplexing by the demodulator 7802 and by performing error correction decoding into video data, audio data, data broadcasting service content, and so on in accordance with instructions from a control unit in a CPU or similar. The signal processing section 7804 performs a process of converting the video data so separated into video data encoded with a video coding method different from the video coding method originally applied to the video data, and a process of converting the audio data so separated into audio data encoded with an audio coding method different from the audio coding method originally applied to the audio data, all in accordance with instructions from the control unit. The stream I/O section 7803 multiplexes the converted video data and the converted audio data to generate new multiplexed data, in accordance with the instructions from the control unit. In response to the instructions by the control unit, the signal processing section 7804 may perform the conversion process on only one of or on both of the video data and the audio data. Also, the size or bitrate of the converted audio data and the converted video data may be determined by the user, or may be determined in advance according to the type of recording medium involved.

[1403] According to the above configuration, the receiver 7800 is able to convert and record at a size recordable onto the recording medium, or at a size or bitrate of video data and audio data matching the speed at which the drive 7808 is able to record or read data. Accordingly, the drive is able to record the program when the data obtained through demultiplexing by the demodulator 7802 and by performing error correction decoding have a size recordable onto the recording medium, or are smaller than the multiplexed data, or when the size or bitrate of the data demodulated by the demodulator 7802 are lower than the speed at which the drive 7808 is able to record or read data. Thus, the user is able to view a program that has been stored and read as data at a freely selected time after the time of broadcast.

[1404] The receiver 7800 further includes a stream interface 7809 transmitting the multiplexed data demodulated by the demodulator 7802 to an external device through a transmission medium 7830. Examples of the stream interface 7809 include Wi-Fi™ (IEEE802.11a, IEEE802.11b, IEEE802.11g, IEEE802.11n, and so on), WiGiG, WirelessHD, Bluetooth™, Zigbee™, and other wireless communication methods conforming to wireless communication standards, used by a wireless communication device to transmit the demodulated multiplexed data to an external device through a wireless medium (corresponding to the transmission medium 7830). Further, the stream interface 7809 may be Ethernet™, USB (Universal Serial Bus, PLC (Power Line Communication), HDMI (High-Definition Multimedia Interface), or some other form of wired communication method conforming to wired communication standards, used by a wired communication device to transmit the demodulated multiplexed data to an external device connected to the stream interface 7809 through a wired channel (corresponding to the transmission medium 7830).

[1405] According to the above configuration, the user is able to use the external device with the multiplexed data received by the receiver 7800 using the reception method described in the above embodiment. The aforementioned use of the multiplexed data includes the user viewing the multiplexed data in real time using the external device, recording the multiplexed data with a drive provided on the external device, transferring the multiplexed data from the external device to another external device, and so on.

[1406] Although the above explanation describes the receiver 7800 as outputting, to the stream interface 7809, the multiplexed data obtained by having the demodulator 7802 perform demodulation and then performing error correction decoding (performing decoding with a decoding method corresponding to the error correction decoding described in the present document), a portion of the data included in the multiplexed data may also be extracted for recording. For example, when the multiplexed data obtained by having the demodulator 7802 perform demodulation and then performing error correction decoding include data broadcasting service content or other data other than the audio data and the video data, the stream interface 7809 may extract the video data and the audio data from the multiplexed data demodulated by the demodulator 7802, and multiplex these data into new multiplexed data for output. The stream interface 7809 may also multiplex only one of the audio data and the video data included in the multiplexed data obtained through demodulation by the demodulator 7802 and performing error correction decoding into new multiplexed data for output.

[1407] The process of extracting a portion of data from among the data included in the multiplexed data obtained through demultiplexing by the demodulator 7802 and by performing error correction decoding (i.e., performing decoding using a decoding method corresponding to the error correction decoding described in the present document) is performed, for example, by the stream I/O section 7803. Specifically, the stream I/O section 7803 separates the multiplexed data demodulated by the demodulator 7802 into video data, audio data, data broadcasting service content, and other types of data in accordance with instructions from a control unit in a non-diagrammed CPU or similar, and multiplexes only the data designated among the separated data to generate new multiplexed data. The question of which data to extract from among the separated data may be, for example, decided by the user, or decided in advance for each type of stream interface 7809.

[1408] According to the above configuration, the receiver 7800 is able to extract only those data required by the external device for output, and thus eliminate communication bands consumed by output of the multiplexed data.

[1409] Also, although the above explanation describes the stream interface 7809 as recording the multiplexed data obtained through demultiplexing by the demodulator 7802 and by performing error correction decoding (i.e., performing decoding using a decoding method corresponding to the error correction decoding described in the present document), the video data included in the data obtained through demultiplexing by the demodulator 7802 and by performing error correction decoding may be converted into video data encoded with a video coding method different from the video coding method originally applied to the video data, so as to decrease the size of the data or reduce the bit rate thereof, and the converted video data may be multiplexed into new multiplexed data for output. Here, the video coding method applied to the original video data and the video coding method applied to the converted video data may conform to different standards, or may conform to the same standard but differ only in terms of parameters. Similarly, the stream interface 7809 may also convert the audio data included in the data obtained through demultiplexing by the demodulator 7802 and by performing error correction decoding into audio data encoded with an audio coding method different from the audio coding method originally applied to the audio data, so as to decrease the size of the data or reduce the bit rate thereof, and the converted audio data may be multiplexed into new multiplexed data for output.

[1410] The process of converting the audio data and the video data from the multiplexed data obtained through demultiplexing by the demodulator 7802 and by performing error correction decoding (i.e., performing decoding using a decoding method corresponding to the error correction decoding described in the present document) into the audio data and the video data having decreased sizes and reduced bitrates is performed by the stream I/O section 7803 and the signal processing section 7804, for example. Specifically, the stream I/O section 7803 separates the data obtained through demultiplexing by the demodulator 7802 and by performing error correction decoding into video data, audio data, data broadcasting service content, and so on in accordance with instructions from the control unit.

[1411] The signal processing section 7804 performs a process of converting the video data so separated into video data encoded with a video coding method different from the video coding method originally applied to the video data, and a process of converting the audio data so separated into audio data encoded with an audio coding method different from the audio coding method originally applied to the audio data, all in accordance with instructions from the control unit. The stream I/O section 7803 multiplexes the converted video data and the converted audio data to generate new multiplexed data, in accordance with the instructions from the control unit. In response to the instructions by the control unit, the signal processing section 7804 may perform the conversion process on only one of or on both of the video data and the audio data. Also, the size or bitrate of the converted audio data and the converted video data may be determined by the user, or may be determined in advance according to the type of stream interface 7809 involved.

[1412] According to the above configuration, the receiver 7800 is able to convert the bitrate of the video data and the audio data for output according to the speed of communication with the external device. Accordingly, the multiplexed data can be output from the stream interface to the external device when the speed of communication with the external device is lower than the bitrate of the multiplexed data obtained by having the demodulator 7802 perform demodulation and then performing error correction decoding (performing decoding with a decoding method corresponding to the error correction decoding described in the present document). As such, the user is able to use the new multiplexed data with another communication device.

[1413] The receiver 7800 also includes an audiovisual interface 7811 that outputs the video signal and the audio signal decoded by the signal processing section 7804 to the external device via the transmission medium. Examples of the audiovisual interface 7811 include Wi-Fi™ (IEEE802.11a, IEEE802.11b, IEEE802.11g, IEEE802.11n, and so on), WiGiG, WirelessHD, Bluetooth™, Zigbee™, and other wireless communication methods conforming to wireless communication standards, used by a wireless communication device to transmit the audio signal and the video signal to the external device through a wireless medium. Also, the stream interface 7809 may be Ethernet™, USB (Universal Serial Bus, PLC, HDMI, or some other form of wired communication method conforming to wired communication standards, used by a wired communication device to transmit the audio signal and the video signal to an external device connected to the stream interface 7809. The stream interface 7809 may also be a terminal connected to a cable that outputs the audio signal and the video signal as-is, in analogue form.

[1414] According to the above configuration, the user is able to use the audio signal and the video signal decoded by the signal processing section 7804 with an external device.

[1415] The receiver 7800 further includes an operation input section 7810 receiving user operations as input. The receiver 7800 performs various types of switching in accordance with a control signal input by the operation input section 7810 in response to user operations, such as switching the main power ON or OFF, switching between received channels, switching between subtitle displays or audio languages, and switching the volume output by the audio output section 7806, and is also able to set the receivable channels and the like.

[1416] The receiver 7800 may also have a function to display the antenna level as an indicator of reception quality while the receiver 7800 is receiving signals. The antenna level is an indicator of signal quality calculated according to, for example, the RSSI (Received Signal Strength Indicator), the received field power, the C/N(Carrier-to-noise power ratio), the BER (Bit-Error Rate), the Packet Error Rate, the Frame Error Rate, the CSI (Channel State Information), or similar information on the signal received by the receiver 7800, and serves as a signal representing signal level and the presence of signal deterioration. In such circumstances, the demodulator 7802 has a reception quality estimation unit estimating the RSSI, the received field power, the C/N, the BER, the Packet Error Rate, the Frame Error Rate, the CSI, or similar information so received, and the receiver 7800 displays the antenna level (signal level, signal indicating signal degradation) in a user-readable format on the video display section 7807 in response to user operations.

[1417] The display format for the antenna level (signal level, signal indicating signal degradation) may be a displayed numerical value corresponding to the RSSI, the received field power, the C/N, the BER, the Packet Error Rate, the Frame Error Rate, the CSI, or similar information, or may be another type of display corresponding to the RSSI, the received field power, the C/N, the BER, the Packet Error Rate, the Frame Error Rate, the CSI, or similar information. The receiver 7800 may also display the antenna level (signal level, signal indicating signal degradation) as calculated for a plurality of streams s1, s2, and so on, into which the signal received using the reception method of the above embodiment is separated, or may display a single antenna level (signal level, signal indicating signal degradation) calculated for all of the streams s1, s2, and so on. Also, when the video data and the audio data making up the program are transmitted using a band segmented transmission method, the level of the signal (signal indicating signal degradation) may be indicated at each band.

[1418] According to this configuration, the user is able to know the antenna level (signal level, signal indicating signal degradation) in a quantitative and qualitative manner, when reception is performed using the reception method of the above-described embodiment.

[1419] Although the receiver 7800 is described above as including an audio output section 7806, a video display section 7807, a drive 7808, a stream interface 7809, and an audiovisual interface 7811, not all of these components are necessarily required. Provided that the receiver 7800 includes at least one of the above-listed components, the multiplexed data obtained through demultiplexing by the demodulator 7802 and by performing error correction decoding (i.e., performing decoding using a decoding method corresponding to the error correction decoding described in the present document) are usable thereby. In addition, the various uses of the receiver here described may be freely combined.

(Multiplexed Data)



[1420] Next, the details of an example configuration for the multiplexed data are described. The data structure used for broadcasting is, typically, an MPEG2-TS (Transport Stream). The following explanation uses MPEG2-TS as an example. However, the data structure for the multiplexed data communicated using the transmission method and the reception method given in the above embodiment is not limited to MPEG2-TS. Needless to say, the results described in each of the above embodiments are also attainable using any of a variety of other data structures.

[1421] FIG. 56 illustrates a sample configuration for the multiplexed data. As shown in FIG. 56, the multiplexed data are obtained by multiplexing one or more elements making up a program (or an event, which is a portion of a program) currently being supplied by services. The element streams include, for example, video streams, audio streams, presentation graphics (PG) streams, interactive graphics (IG) streams, and so on. When the program being supplied with the multiplexed data is a movie, the video streams are the main video and sub-video thereof, the audio streams are the main audio and sub-audio to be mixed therewith, and the presentation graphics stream are subtitles for the movie. Here, the main video represents video that is normally displayed on the screen, while the sub-video represents video that is displayed as a smaller screen within the main video (e.g., a video of text data giving a synopsis of the movie). The interactive graphics streams represent interactive screens created by assigning GUI components to the screen.

[1422] Each of the streams included in the multiplexed data is identified by a PID, which is an identifier assigned to each of the streams. For example, the PIDs assigned to each of the streams are 0x1011 for the video stream used as the main video of the movie, 0x1100 through 0x111F for the audio streams, 0x1200 through 0x121F for the presentation graphics, 0x1400 through 0x141F for the interactive graphics streams, 0x1B00 through 0x1B1F for the video streams serving as sub-video for the movie, and 0x1A00 through 0x1A1F for the audio streams used as sub-audio to be mixed in with the main audio.

[1423] FIG. 57 is a schematic diagram illustrating an example of the manner in which the multiplexed data are multiplexed. First, a video stream 8001, made up of a plurality of video frames, and an audio stream 8004, made up of a plurality of audio frames, are each converted into respective PES packet sequences 8002 and 8005, which are in turn respectively converted into TS packets 8003 and 8006. Similarly, a presentation graphics stream 8011 and interactive graphics data 8014 are each converted into respective PES packet sequences 8012 and 8015, which are in turn respectively converted into TS packets 8013 and 8016. The multiplexed data 8017 are formed by multiplexing these TS packets (8003, 8006, 8013, and 8016) into a single stream.

[1424] FIG. 58 illustrates the details of the manner in which the video stream is stored in the PES packets. The first tier of FIG. 58 indicates a video frame sequence of the video stream. The second tier represents a PES sequence. As the arrows labeled yy1, yy2, yy3, and yy4 in FIG. 58 indicate, a plurality of video presentation units in the video stream, namely I-pictures, B-pictures, and P-pictures, are divided into individual pictures and each stored as the payload of individual PES packets. The PES packets each have a PES header. The PES header stores a PTS (Presentation Time-Stamp), which is a time-stamp for displaying the picture, and a DTS (Decoding Time-Stamp)m which is a time-stamp for decoding the picture.

[1425] FIG. 59 illustrates the format of TS packets ultimately written into the multiplexed data. The TS packets are 188-byte fixed-length packets, each made up of a 4-byte TS header, which has the PID and other identifying information for the stream, and a 184-byte TS payload, which stores the data. The above-described PES packets are divided and each made to store the TS payload. For a BD-ROM, the TS packets also have a 4-byte TP_extra_header field assigned thereto, so as to make up 192-byte source packets which are written into the multiplexed data. The TP_extra_header field has information such as the ATS (Arrival Time Stamp) written therein. The ATS is a time-stamp for the beginning of TS packet transfer to the PID filter of the decoder. Within the multiplexed data, the source packets are arranged as indicated in the lower tier of FIG. 59. The numbers incremented from the beginning of the multiplexed data are termed SPN (Source Packet Numbers).

[1426] The TS packets included in the multiplexed data include a PAT (Program Association Table), a PMT (Program Map Table), a PCR (Program Clock Reference) and so on, in addition to the video streams, the audio streams, the presentation graphics streams, and so on. The PAT indicates the PID of the PMT to be used in the multiplexed data, and the PAT itself has a PID of 0. The PMT has the PIDs of each video, audio, subtitle, and other stream included in the multiplexed data, as well as stream attribute information (e.g., the frame rate, the aspect ratio, and so on) for the stream corresponding to each PID. The PMT also has various descriptors pertaining to the multiplexed data. The descriptors include, for example, copy control information indicating whether or not the multiplexed data may be copied. The PCR has STC time information corresponding to the ATS transferred to the decoder with each PCR packet, so as to synchronize the ATC (Arrival Time Clock), which is the ATS time axis, and the STC (System Time Clock), which is the PTS and DTS time axis.

[1427] FIG. 60 describes the details of PMT data structure. A PMT header is arranged at the head of the PMT, and describes the length and so on of the data included in the PMT. Subsequently, a plurality of descriptors pertaining to the multiplexed data are arranged. The above-described copy control information and the like are written as the descriptors. After the descriptors, stream information pertaining to the streams included in the multiplexed data is arranged in plurality. The stream information is made up of stream descriptors describing the stream type, stream PID, and stream attribute information (frame rate, aspect ratio, and so on) for identifying the compression codec of each stream. The stream descriptors are equal in number to the streams in the multiplexed data.

[1428] When recorded onto a recording medium, the above-described multiplexed data are recorded along with a multiplexed data information file.

[1429] FIG. 61 illustrates the configuration of the multiplexed data information file. As shown in FIG. 61, the multiplexed data information file is management information for the multiplexed data that is in one-to-one correspondence therewith and is made up of clip information, stream attribute information, and an entry map.

[1430]  As shown in FIG. 61, the clip information is made up of the system rate, the playback start time-stamp, and the playback end time-stamp. The system rate indicates the maximum transfer rate at which the multiplexed data are transferred to the PID filter of a later-described system target decoder. The interval between ATS included in the multiplexed data is set so as to be equal to or less than the system rate. The playback start time-stamp is the PTS of the leading video frame in the multiplexed data, and the playback end time-stamp is the PTS of the final video frame in the multiplexed data, with one frame of playback duration added thereto.

[1431] FIG. 62 illustrates the configuration of the stream attribute information included in the multiplexed data information file. As shown in FIG. 62, the stream attribute information is attribute information for each of the streams included in the multiplexed data, registered in each PID. The attribute information differs for each of the video streams, audio streams, presentation graphics streams, and interactive graphics streams. The video stream attribute information includes such information as the compression codec used to compress the video stream, the resolution of the picture data making up the video stream, the aspect ratio, the frame rate, and so on. The audio stream attribute information includes such information as the compression codec used to compress the audio stream, the number of channels included in the audio stream, the compatible languages, the sampling frequency, and so on. This information is used to initialize the decoder before the player begins playback.

[1432] In the present embodiment, the stream types included in the PMT are used, among the above-described multiplexed data. When the multiplexed data are recorded on a recording medium, the video stream attribute information included in the multiplexed data is used. Specifically, given the video coding method or device described in the above embodiments, a step or means is provided to established specific information indicating that the stream types included in the PMT or the video stream attribute information is for video data generated by the video coding method or device described in the above embodiments. According to this configuration, the video data generated by the video coding method or device described in the above embodiments is distinguished from video data conforming to some other standard.

[1433] FIG. 63 illustrates an example of the configuration of an audiovisual output device 8600 that includes a receiving device 8604 receiving a modulated signal that includes audio and video data, or data for a data broadcast, transmitted by a broadcasting station (base station). The configuration of the receiving device 8604 corresponds to that of the receiver 7800 shown in FIG. 55. The audiovisual output device 8600 is equipped with, for example, an operating system (OS), and with a communication device 8606 (such as a wireless LAN (Local Area Network) or Ethernet ™ communication device) for connecting to the Internet. Accordingly, a video display section 8601 is able to simultaneously display data video 8602 for the data broadcast and hypertext 8603 (shown as World Wide Web) supplied over the internet.

[1434] Then, by using a remote control (or a mobile phone or keyboard) 8607, one of the data video 8602 for the data broadcast and the hypertext 8603 supplied over the internet can be selected and modified. For example, when the hypertext 8603 supplied over the internet is selected, the website being displayed can be changed by using the remote control to perform an operation. Similarly, when the audio and video data, or the data for the data broadcast, are selected, information on the currently selected channel (or the selected (television) program, or the selected audio transmission) can be transmitted by using the remote control 8607. Thus, an interface 8605 acquires information transmitted by the remote control, and the receiving device 8604 then demodulates the signal corresponding to the selected channel, performs error correction decoding and similar processing thereon (i.e., performs decoding using a decoding method corresponding to the error correction decoding described in the present document), and thereby obtains received data.

[1435] Here, the receiving device 8604 acquires information on the control symbols included in the transmission method information included in the signal corresponding to the selected channel, thereby correctly setting the reception operations, demodulation method, error correction decoding method and so on, which enables acquisition of the data included in the data symbols transmitted by the broadcasting station (base station). The above describes an example where the user selects a channel using the remote control 8607. However, the above-described operations are also possible using a selection key installed on the audiovisual output device 8600 for channel selection.

[1436] The audiovisual output device 8600 may also be operated using the Internet. For example, a recording (storage) session is programmed into the audiovisual output device 8600 from a different terminal that is also connected to the Internet. (Accordingly, and as shown in FIG. 55, the audiovisual output device 8600 has a drive 7808.) Then, the channel is selected before recording begins, and the receiving device 8604 demodulates the signal corresponding to the selected channel and applies error correction decoding processing thereto to obtain received data. Here, the receiving device 8604 obtains control symbol information, which includes information on the transmission method included in the signal corresponding to the selected channel, and is thus able to correctly set the methods for the receiving operation, demodulating operation, error correction decoding, and so on (when a plurality of error correction decoding methods are prepared as described in the present document (e.g., a plurality of different codes are prepared, or a plurality of codes having different coding rates are prepared), the error correction decoding method corresponding to the error correction codes set from among a plurality of error correction codes are used. As such, the data included in the data symbols transmitted by the broadcasting station (base station) are made receivable.

(Other Addenda)



[1437] In the present document, the transmitting device is plausibly installed on, for example, a broadcasting station, a base station, an access point, a terminal, a mobile phone, or some other type of communication or broadcasting device. Likewise, the receiving device is plausibly installed on a television, a radio, a terminal, a personal computer, a mobile phone, an access point, a base station, or some other type of communication device. Also, the transmitting device and the receiving device of the present invention are devices with communication functionality. These devices each plausibly take the form of a television, a radio, a personal computer, a mobile phone, or some other device for executing applications connectable through some type of interface (e.g., USB).

[1438] Also, in the transmission and reception methods described above, symbols other than the data symbols that transmit data encoded in the encoding methods described in the present disclosure may be arranged in the frames, such as pilot symbols (preamble, unique word, postamble, reference symbols, and so on) or control information symbols. Although the pilot symbols and control information symbols are presently named as such, the symbols may take any name, as only the function thereof is relevant.

[1439] A pilot symbol is, for example, a known symbol modulated by the communicating device using PSK modulation (alternatively, the receiver may come to know the symbols transmitted by the transmitter by means of synchronization), such that the receiver uses the symbol to detect the signal by frequency synchronization, time synchronization, channel estimation (or CSI estimation) (for each modulated signal).

[1440] Similarly, a control information symbol is a symbol for communicating information (e.g., the modulation method, error correction coding method, coding rate for the error correction coding method, upper layer information, and so on used in communication) required for inter-party communication in order to realize non-data communication (i.e., of applications).

[1441] The present invention is not limited to the above-described embodiments. A number of variations thereon are also possible. For example, although the above embodiments describe the use of a communication device, this is not intended as a limitation. The communication method may also be performed using software.

[1442] Although the present document uses terms such as precoding, precoding weight, and precoding matrix, the terms may be freely modified (e.g., using the term code book) as the focus of the present invention is the signal processing itself.

[1443] Although the present document describes the receiving device as using ML operations, APP, Max-log APP, ZF, MMSE, and so on, and the results thereof are used to obtain soft decision results (log-likelihood and log-likelihood ratio) and hard decision results (zero or one) for each bit of the data transmitted by the transmitting device, these may be termed, in generality, wave detection, demodulation, detection, estimation, and separation.

[1444] Further, in a MIMO system transmitting a plurality of streams s 1(t) and s2(t) at the same time from different antennas, the streams s1(t) and s2(t) may transport different data or may transport identical data.

[1445] Also, the transmission antenna of the transmitting device and the reception antenna of the receiving device, each drawn as a single antenna in the drawings, may also be provided as a plurality of antennas.

[1446] In the present document, the universal quantifier ∀ is used, as well as the existential quantifier 3.

[1447] Also, in the present document, radians are used as the unit of phase in the complex plane, such as for arguments.

[1448] When using the complex plane, the polar coordinates of complex numbers are expressible in polar form. For a complex number z=a+jb (where a and b are real numbers and j is the imaginary unit), a point (a, b) is expressed, in the complex plane, as the polar coordinates thereof [r, θ], by satisfying a=r×cosθ and b=r×sinθ, where r is the absolute value of z (r=|z|) and θ is the argument. Thus, z=a+jb is represented as re.

[1449] Although the present document describes the baseband signals s1, s2, z1, and z2 as complex signals, the complex signals may also be represented as I+jQ (where j is the imaginary unit) by taking I as the in-phase signal and Q as the quadrature signal. Here, I may be zero, and Q may also be zero.

[1450] Also, FIG. 64 illustrates a sample broadcasting system using encoding and decoding methods described in the present document. As shown in FIG. 64, a video coding section 8701 takes video as input, performs video coding thereon, and outputs coded video data 8702. An audio coding section 8703 takes audio as input, performs audio coding thereon, and outputs coded audio data 8704. A data coding section 8705 takes data as input, performs data coding (e.g., data compression) thereon, and outputs coded data 8706. Taken together, these form an information source coding section 8700.

[1451] A transmission section 8707 takes the coded video data 8702, the coded audio data 8704, and the coded data 8706 as input, uses one or all of these as transmission data, applies error correction coding, modulation, precoding, and other processes (e.g., signal processing by the transmitting device) thereto, and outputs transmission signals 8708 _1 through 8708_N. The transmission signals 8708 _1 through 8708_N are then respectively transmitted to antennas 8709_1 through 8709 N as electrical waves.

[1452] A receiving section 8712 takes received signals 8710_1 through 8710_M received by the antennas 8711_1 through 8711_M as input, performs frequency conversion, precoding decoding, log-likelihood ratio calculation, error correction decoding, and other processing (i.e., performs decoding using a decoding method corresponding to the error correction decoding described in the present document) (e.g., processing by the receiving device) thereon, and outputs received data 8713, 8715, and 8717. An information source decoding section 8719 takes the received data 8713, 8715, and 8717 as input. A video decoding section 8714 takes received data 8713 as input, performs video decoding thereon, and outputs a video signal. The video is then displayed by a television. Similarly, an audio decoding section 8716 takes received data 8715 as input. Audio decoding is performed and an audio signal is output. The audio then plays through a speaker. Also, a data decoding section 8718 takes received data 8717 as input, performs data decoding thereon, and outputs data information.

[1453] In the above-described embodiments of the present invention, the multicarrier communication scheme, such as OFDM, may use any number of encoders installed in the transmitting device. Accordingly, for example, when the transmitting device has one encoder installed, the method for distributing the output may of course be applied to a multicarrier communication scheme such as OFDM.

[1454] Also, for example, a program for executing the above-described communication method may be stored in advance in the ROM, and may then be executed through the operations of the CPU.

[1455] Further, the program for executing the above-described communication method may be recorded onto a computer-readable recording medium, the program recorded onto the recording medium may be stored in the RAM of a computer, and the computer may operate according to the program.

[1456] The components of each of the above-described embodiments may typically be realized as LSI (Large Scale Integration), a form of integrated circuit. The components of each of the embodiments may be realized as individual chips, or may be realized in whole or in part on a common chip.

[1457] Although LSI is named above, the chip may be named an IC (integrated circuit), a system LSI, a super LSI, or an ultra LSI, depending on the degree of integration. Also, the integrated circuit method is not limited to LSI. A private circuit or a general-purpose processor may also be used. After LSI manufacture, a FPGA (Field Programmable Gate Array) or reconfigurable processor may also be used.

[1458]  Furthermore, future developments may lead to technology enhancing or surpassing LSI semiconductor technology. Such developments may, of course, be applied to the integration of all functional blocks. Biotechnology applications are also plausible.

[1459] Also, the coding method and decoding method may be realized as software. For example, a program for executing the above-described coding method and decoding method may be stored in advance in the ROM, and may then be executed through the operations of the CPU.

[1460] Further, the program for executing the above-described coding method and decoding method may be recorded onto a computer-readable recording medium, the program recorded onto the recording medium may be stored in the RAM of a computer, and the computer may operate according to the program.

[1461] The present invention is not limited to wireless communication, but obviously also applies to wired communication, including PLC, visible spectrum communication, and optical communication.

[1462] In the present document, the term time-varying period is used. This refers to the period as formatted for a time-varying LDPC-CC.

[1463] In the present embodiment, the symbol T in AT is used to indicate that a matrix AT is the transpose matrix of a matrix A. Accordingly, given a matrix A with m rows and n columns, the matrix AT has n rows and m columns in which the elements (row i, column j) of matrix A are inverted into elements (row j, column i).

(Application of Correction Coding and Decoding Method)



[1464] FIG. 65 shows an example of the configuration of parts relating to a processing system of recording data and a processing system of playing back data in an optical disc device that records data into an optical disc such as a BD and a DVD and plays back data recorded in such an optical disc, to which the correction encoding and the decoding method described in the present disclosure are applied.

[1465] The processing system of recording data shown in FIG. 65 includes an error correction coding section 14502, a modulation coding section 14503, a laser driving section 14504, and an optical pick-up 14505. The error correction coding section 14502 performs error correction coding on data recorded in an optical disc 14501 by using the error correction code described in the present disclosure, thereby to generate error correction coded data. The modulation coding section 14503 performs modulation coding by using a modulation code such as an RLL (Run Length Limited) 17 code (e.g. Non-Patent Literature 38), thereby to generate a recording pattern. The laser driving section 14504 drives the optical pick-up 14505 to form a recording mark corresponding to the recording pattern on a track of the optical disc 14501 by using laser irradiated from the optical pick-up 14505 to the track.

[1466] Also, the processing system of playing back data shown in FIG. 65 includes the optical pick-up 14505, a filter 14506, a synchronization processing section 14507, a PRML (Partial Response Maximum Likelihood) section 14508, a demodulator 14509, and an error correction decoding section 14510. Data recorded in the optical disc 14501 is played back, by taking advantage of that an amount of light reflecting off the laser, which is irradiated on the track of the optical disc 14501 by the optical pick-up 14505, varies depending on the recording mark formed on the track. The optical pick-up 14505 outputs a playback signal corresponding to the amount of light reflecting off the laser irradiated on the track of the optical disc 14501. The filter 14506 is composed of an HPF (High-pass filter), an LPF (Low-pass filter), a BPF (Band-pass filter), and the like, and removes noise components in an unnecessary frequency band that are contained in the playback signal. For example, in the case where data recorded in the optical disc 14501 is coded by using an RLL17 code, the filter 14506 is composed of an LPF and an HPF that reduce noise components in a frequency band other than a frequency band of the RLL17 code. Specifically, according to a standard linear velocity in which one channel bit has a frequency of 66 MHz, the HPF has a cut-off frequency of 10 kHz, and the LPF has a cut-off frequency of 33 MHz, which is a Nyquist frequency of one channel bit frequency.

[1467] The synchronization processing section 14507 converts a signal output by the filter 14506 to a digital signal sampled at intervals of one channel bit. The PRML (Partial Response Maximum Likelihood) section 14508 binarizes the digital signal. PRML is an art that combines partial response (PR) and wave detection, and is a signal processing scheme according to which the most probable signal sequence is selected from a waveform of digital signals based on the assumption that a known intercede interference occurs. Specifically, partial response equalization is performed on a synchronized digital signal with use of an FIR filter or the like, such that the digital signal has predetermined frequency characteristics. Then, the digital signal is converted to a corresponding binary signal by selecting the most probable state transition sequence. The demodulator 14509 demodulates the binary signal in accordance with the RLL17 code, and outputs a demodulated bit sequence (hard decision value or soft decision value such as log-likelihood ratio). The error correction decoding section 14510 reorders the demodulated bit sequence in a predetermined procedure, and then performs, on the reordered demodulated bit sequence, error correction decoding processing in accordance with the error correction code described in the present disclosure, and outputs playback data. Through the above processing, data recorded in the optical disc 14501 can be played back.

[1468] The above description has been provided using an example where the optical disc device includes both the processing system of recording data and the processing system of playing back data. However, the optical disc device may include only one of these processing systems. Also, the optical disc 14501, which is used for playing back data, is not limited to an optical disc into which recording data is recordable by the optical disc device. Alternatively, the optical disc 14501 may be an optical disc that has recorded beforehand therein data that has been error correction coded by using the error correction code described in the present disclosure, and cannot record therein new recording data.

[1469] Also, the above description has been provided using an optical disc device as an example. However, a recording medium is not limited to an optical disc. Alternatively, it is possible to apply the error correction coding and decoding method described in the present disclosure to a recording device or a playback device that uses, as the recording medium, a magnetic disc, a non-volatile semiconductor memory, or the like other than an optical disc.

[1470] The above description has been provided using an example where the processing system of recording data of the optical disc device includes the error correction coding section 14502, the modulation coding section 14503, the laser driving section 14504, and the optical pick-up 14505, and the processing system of playing back data of the optical disc device includes the optical pick-up 14505, the filter 14506, the synchronization processing section 14507, the PRML (Partial Response Maximum Likelihood) section 14508, the demodulator 14509, and the error correction decoding section 14510. Alternatively, a recording device or a playback device, which uses an optical disc and other recording media, to which the error correction coding and decoding method described in the present disclosure is applied does not need to include all these configuration elements. The recording device only needs to include at least the error correction coding section 14502 and the configuration of recording data in a recording medium corresponding to the optical pick-up 14505 in the above description. The playback device only needs to include at least the error correction decoding section 14510 and the configuration of reading data from a recording medium corresponding to the optical pick-up 14505. With the recording device and the playback device as described above, it is possible to secure high data receiving quality corresponding to high error correction capability of the error correction coding and decoding method described in the present disclosure.
The following embodiments D1 to G6 have been included for illustrative purpose.

(Embodiment D1)



[1471] The present embodiment describes a method of configuring an LDPC-CC of coding rate 3/5 that is based on a parity check polynomial, as one example of an LDPC-CC not satisfying coding rate (n-1)/n.

[1472] Bits of information bits X1, X2, X3 and parity bits P1, P2, at time point j, are expressed X1,j, X2,j, X3,j and P1,j, P2,j, respectively.

[1473] A vector uj, at time point j, is expressed uj = (X1,j, X2,j, X3,j, P1,j, P2,j).

[1474] Given a delay operator D, polynomial expressions of the information bits X1, X2, X3 are X1(D), X2(D), X3(D), and polynomial expressions of the parity bits P1, P2 are P1(D), P2(D).

[1475] Further, consideration is given to an LDPC-CC of coding rate 3/5 and time-varying period 2m that is based on a parity check polynomial.

[1476] The following mathematical expressions are provided as parity check polynomials satisfying zero for an LDPC-CC of coding rate 3/5 and time-varying period 2m that is based on a parity check polynomial.

[1477] First, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1×P2(D).
[Math. 232]









[1478] In expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[1479] In expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2), α#(2i),p,q (where p is an integer no smaller than one and no greater than three, q is an integer no smaller than one and no greater than r#(2i),p (where r#(2i),p is a natural number)) and β#(2i),0 is a natural number, β#(2i),1 is a natural number, β#(2i),2 is an integer no smaller than zero, and β#(2i),3 is a natural number.

[1480] Further, y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for (y,z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for all y and all z satisfying y≠z.)

[1481] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (97-1-1) or expression (97-1-2) is referred to as "#(2i); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (97-2-1) or expression (97-2-2) is referred to as "#(2i); second expression" for realizing a time-varying period 2m.

[1482] Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (97-1-1) or expression (97-1-2) is prepared.

[1483] That is, for i=0, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=0 is prepared.

[1484] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=m-1 is prepared.



[1485] Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (97-2-1) or expression (97-2-2) is prepared.

[1486] That is, for i=0, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=0 is prepared.

[1487] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=m-1 is prepared.



[1488] Similarly, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1 ×P2(D).
[Math. 233]







[1489] In expressions (98-1-1), (98-1-2), (98-2-1), (98-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[1490]  In expressions (98-1-1), (98-1-2), (98-2-1), (98-2-2), α#(2i+1),p,q (where p is an integer no smaller than one and no greater than three, q is an integer no smaller than one and no greater than r#(2i+1),p (where r#(2i+1),p is a natural number)) and β#(2i+1),0 is a natural number, β#(2i+1),1 is a natural number, β#(2i+1),2 is an integer no smaller than zero, and β#(2i+1),3 is a natural number.

[1491] Further, y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for (y,z) where y≠z. ∀ is a universal quantifier, (y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for all y and all z satisfying y≠z.)

[1492] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (98-1-1) or expression (98-1-2) is referred to as "#(2i+1); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (98-2-1) or expression (98-2-2) is referred to as "#(2i+1); second expression" for realizing a time-varying period 2m.

[1493] Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (98-1-1) or expression (98-1-2) is prepared.

[1494] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=0 is prepared.

[1495] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=m-1 is prepared.



[1496] Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (98-2-1) or expression (98-2-2) is prepared.

[1497] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=0 is prepared.

[1498] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=m-1 is prepared.



[1499] As such, an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1500] Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (97-1-1) or expression (97-1-2), parity check polynomials satisfying zero provided by expression (97-2-1) or expression (97-2-2), parity check polynomials satisfying zero provided by expression (98-1-1) or expression (98-1-2), and parity check polynomials satisfying zero provided by expression (98-2-1) or expression (98-2-2).

[1501] For example, the time varying period 2×m can be formed by preparing a 4×m number of different parity check polynomials satisfying zero.

[1502] Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

[1503] The following describes the relationship between time point j and expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2), (98-1-1), (98-1-2), (98-2-1), and (98-2-2) (where j is an integer no smaller than zero).

[1504] The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m-1).

[1505] Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i = k in #(2i); first expression and #(2i); second expression, hold true.

[1506] Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m-1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

[1507] The following describes a method of configuring a parity check matrix for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1508] As already described above, a vector uj at time point j is expressed as uj=(X1,j, X2,j, X3,j, P1,j, P2,j) (where j is an integer no smaller than zero). In the following, a case where u is a transmission vector is considered. Note that in the following, j is an integer no smaller than one, and thus j differs between the description having been provided above and the description provided in the following. (j is set as such to facilitate understanding of the correspondence between the column numbers and the row numbers of the parity check matrix.)

[1509] Accordingly, u=(ui, u2, u3, ..., uy-1, uy, uy+1, ...)T=(X1,1, X2,1, X3,1, P1,1, P2,1, X1,2, X2,2, X3,2, P1,2, P2,2, X1,3, X2,3, X3,3, P1,3, P2,3, ..., X1,y-1, X2,y-1, X3,y-1, P1,y-1, P2,y-1, X1,y, X2,y, X3,y, P1,y, P2,y, X1,y+1, X2,y+1, X3,y+1 P1,y+1, P2,y+1, ...)T. Further, when using H to denote a parity check matrix for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, Hu=0 holds true (here, Hu=0 indicates that all elements of the vector Hu are zeroes).

[1510] FIG. 66 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the topmost row of the parity check matrix is considered as the first row. Further, row number is incremented by one each time moving to a lower row. Accordingly, the topmost row is considered as the first row, the row immediately below the first row is considered as the second row, and the subsequent rows are considered as the third row, the fourth row, and so on.

[1511] As illustrated in FIG. 66:

"a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";
"a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2x(2m-1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression";

"a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression";

"a vector for the 2×(2m+1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the 2×(2m+2)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×i-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); first expression"; and

"a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); second expression", and so on (where i is an integer no smaller than one).



[1512] FIG. 67 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the leftmost column of the parity check matrix is considered as the first column. Further, column number is incremented by one each time moving to a rightward column. Accordingly, the leftmost column is considered as the first column, the column immediately to the right of the first column is considered as the second column, and the subsequent columns are considered as the third column, the fourth column, and so on.

[1513] As illustrated in FIG. 67:

"a vector for the first column of the parity check matrix H is related to X1 at time point 1";

"a vector for the second column of the parity check matrix H is related to X2 at time point 1";

"a vector for the third column of the parity check matrix H is related to X3 at time point 1";

"a vector for the fourth column of the parity check matrix H is related to P1 at time point 1";

"a vector for the fifth column of the parity check matrix H is related to P2 at time point 1";

"a vector for the 5×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 5×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 5×(j-1)+3th column of the parity check matrix H is related to X3 at time point j";

"a vector for the 5×(j-1)+4th column of the parity check matrix H is related to P1 at time point j"; and

"a vector for the 5×(j-1)+5th column of the parity check matrix H is related to P2 at time point j", and so on (where j is an integer no smaller than one).



[1514] FIG. 68 indicates a parity check matrix for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1515] The following focuses on 1×X1(D), 1×X2(D), 1×X3(D), 1×P1(D), 1×P2(D) in the parity check matrix for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1516] The parity check polynomials at time point j=1 are parity check polynomials when i=0 in expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2).

[1517] A vector for the first row in FIG. 68 can be generated from a parity check polynomial when i=0 in expression (97-1-1) or expression (97-1-2) (refer to FIG. 66).

[1518] In expressions (97-1-1) and (97-1-2):
  • a term for 1×X1(D) exists;
  • terms for 1×X2(D) and 1×X3(D) do not exist; and
  • a term for 1 ×P1(D) exists but a term for 1 ×P2(D) does not exist.


[1519] Further, the relationship between column numbers and X1, X2, X3, P1, P2 is as indicated in FIG. 67. Based on the relationship indicated in FIG. 67 and the fact that a term for 1×X1(D) exists, a column related to X1 in the vector for the first row in FIG. 68 is "1". Further, based on the relationship indicated in FIG. 67 and the fact that terms for 1 ×X2(D) and 1 ×X3(D) do not exist, columns related to X2 and X3 in the vector for the first row in FIG. 68 are "0". In addition, based on the relationship indicated in FIG. 67 and the fact that a term for 1 ×P1(D) exists but a term for 1×P2(D) does not exist, a column related to P1 in the vector for the first row in FIG. 68 is "1", and a column related to P2 in the vector for the first row in FIG. 68 is "0".

[1520] As such, the vector for the first row in FIG. 68 is "10010", as indicated by 3900-1 in FIG. 68.

[1521] A vector for the second row in FIG. 68 can be generated from a parity check polynomial when i=0 in expression (97-2-1) or expression (97-2-2) (refer to FIG. 66).

[1522] In expressions (97-2-1) and (97-2-2):
  • a term for 1×X1(D) does not exist;
  • terms for 1×X2(D) and 1 ×X3(D) exist; and
  • a term for 1×P1(D) may or may not exist but a term for 1 ×P2(D) exists.


[1523] Further, the relationship between column numbers and X1, X2, X3, P1, P2 is as indicated in FIG. 67. Based on the relationship indicated in FIG. 67 and the fact that a term for 1×X1(D) does not exist, a column related to X1 in the vector for the second row in FIG. 68 is "0". Further, based on the relationship indicated in FIG. 67 and the fact that terms for 1×X2(D) and 1×X3(D) exist, columns related to X2 and X3 in the vector for the second row in FIG. 68 are "1". In addition, based on the relationship indicated in FIG. 67 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the second row in FIG. 68 is "Y", and a column related to P2 in the vector for the second row in FIG. 68 is "1", where Y is either "0" or "1".

[1524] As such, the vector for the second row in FIG. 68 is "011Y1", as indicated by 3900-2 in FIG. 68.

[1525] The parity check polynomials at time point j=2 are parity check polynomials when i=0 in expressions (98-1-1), (98-1-2), (98-2-1), (98-2-2).

[1526] A vector for the third row in FIG. 68 can be generated from a parity check polynomial when i=0 in expression (98-1-1) or expression (98-1-2) (refer to FIG. 66).

[1527] In expressions (98-1-1) and (98-1-2):
  • a term for 1×X1(D) does not exist;
  • terms for 1 ×X2(D) and 1 ×X3(D) exist; and
  • a term for 1×P1(D) exists but a term for 1 ×P2(D) does not exist.


[1528] Further, the relationship between column numbers and X1, X2, X3, P1, P2 is as indicated in FIG. 67. Based on the relationship indicated in FIG. 67 and the fact that a term for 1×X1(D) does not exist, a column related to X1 in the vector for the third row in FIG. 68 is "0". Further, based on the relationship indicated in FIG. 67 and the fact that terms for 1 ×X2(D) and 1 ×X3(D) exist, columns related to X2 and X3 in the vector for the third row in FIG. 68 are "1". In addition, based on the relationship indicated in FIG. 67 and the fact that a term for 1×P1(D) exists but a term for 1 ×P2(D) does not exist, a column related to P1 in the vector for the third row in FIG. 68 is "1", and a column related to P2 in the vector for the third row in FIG. 68 is "0".

[1529] As such, the vector for the third row in FIG. 68 is "01110", as indicated by 3901-1 in FIG. 68.

[1530] A vector for the fourth row in FIG. 68 can be generated from a parity check polynomial when i=0 in expression (98-2-1) or expression (98-2-2) (refer to FIG. 66).

[1531] In expressions (98-2-1) and (98-2-2):
  • a term for 1×X1(D) exists;
  • terms for 1×X2(D) and 1×X3(D) do not exist; and
  • a term for 1 ×P1(D) may or may not exist but a term for 1 ×P2(D) exists.


[1532] Further, the relationship between column numbers and X1, X2, X3, P1, P2 is as indicated in FIG. 67. Based on the relationship indicated in FIG. 67 and the fact that a term for 1×X1(D) exists, a column related to X1 in the vector for the fourth row in FIG. 68 is "1". Further, based on the relationship indicated in FIG. 67 and the fact that terms for 1×X2(D) and 1×X3(D) do not exist, columns related to X2 and X3 in the vector for the fourth row in FIG. 68 are "0". In addition, based on the relationship indicated in FIG. 67 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the fourth row in FIG. 68 is "Y", and a column related to P2 in the vector for the fourth row in FIG. 68 is "1".

[1533] As such, the vector for the fourth row in FIG. 68 is "100Y1", as indicated by 3901-2 in FIG. 68.

[1534] Because it can be considered that the above similarly applies to cases where time point j=3, 4, 5, the parity check matrix H has the configuration indicated in FIG. 68.

[1535] That is, due to the parity check polynomials of expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2) being used at time point j=2k+1 (where k is an integer no smaller than zero), "10010" exists in the 2×(2k+1)-1th row of the parity check matrix H, and "011Y1" exists in the 2×(2k+1)th row of the parity check matrix H, as illustrated in FIG. 68.

[1536] Further, due to the parity check polynomials of expressions (98-1-1), (98-1-2), (98-2-1), (98-2-2) being used at time point j=2k+2 (where k is an integer no smaller than zero), "01110" exists in the 2×(2k+2)-1th row of the parity check matrix H, and "100Y1" exists in the 2×(2k+2)th row of the parity check matrix H, as illustrated in FIG. 68.

[1537] Accordingly, as illustrated in FIG. 68, when denoting a column number of a leftmost column corresponding to "1" in "10010" in a row where "10010" exists (e.g., 3900-1 in FIG. 68) as "a", "01110" (e.g., 3901-1 in FIG. 68) exists in a row that is two rows below the row where "10010" exists, starting from column "a+5".

[1538] Similarly, as illustrated in FIG. 68, when denoting a column number of a leftmost column corresponding to "1" in "011Y1" in a row where "011Y1" exists (e.g., 3900-2 in FIG. 68) as "b", "100Y1" (e.g., 3901-2 in FIG. 68) exists in a row that is two rows below the row where "011Y1" exists, starting from column "b+5".

[1539] Similarly, as illustrated in FIG. 68, when denoting a column number of a leftmost column corresponding to "1" in "01110" in a row where "01110" exists (e.g., 3901-1 in FIG. 68) as "c", "10010" (e.g., 3902-1 in FIG. 68) exists in a row that is two rows below the row where "01110" exists, starting from column "c+5".

[1540] Similarly, as illustrated in FIG. 68, when denoting a column number of a leftmost column corresponding to "1" in "100Y1" in a row where "100Y1" exists (e.g., 3901-2 in FIG. 68) as "d", "011Y1" (e.g., 3902-2 in FIG. 68) exists in a row that is two rows below the row where "100Y1" exists, starting from column "d+5".

[1541] The following describes a parity check matrix for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial when tail-biting is not performed, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1542] In the following, Hcom[u][v] (where u and v are integers no smaller than one) denotes an element at row "u" column "v" of a parity check matrix for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1543] Based on description above provided with reference to FIG. 66:

"a vector for the 2×g-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); first expression"; and

"a vector for the (2×g)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); second expression" (where g is an integer no smaller than one).



[1544] Based on description above provided with reference to FIG. 67:

"a vector for the 5×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 5×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 5×(j-1)+3th column of the parity check matrix H is related to X3 at time point j";

"a vector for the 5×(j-1)+4th column of the parity check matrix H is related to P1 at time point j"; and

"a vector for the 5×(j-1)+5th column of the parity check matrix H is related to P2 at time point j" (where j is an integer no smaller than one).



[1545] Based on the above, the following describes component Hcom[2×g-1][v] in row 2×g-1 (where g is an integer no smaller than one) and component Hcom[2×g][v] in row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1546] As already described above, a parity check polynomial satisfying zero of #((g-1)%2m); first expression can be used to generate a vector for row 2×g-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1547] Further, a parity check polynomial satisfying zero of #((g-1)%2m); second expression can be used to generate a vector for row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1548] Accordingly, when g=2×f-1 (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (97-1-1) or expression (97-1-2), can be used to generate a vector for row 2x(2xf-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1549] Further, a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (97-2-1) or expression (97-2-2), can be used to generate a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1550] Further, when g=2×f (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (98-1-1) or expression (98-1-2), can be used to generate a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1551] Further, a parity check polynomial satisfying zero of #(((2xf)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (98-2-1) or expression (98-2-2), can be used to generate a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1552] Accordingly, (1) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2x(2xf-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-1-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-1-1) where 2i=2c holds true.

[1553] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[1554] The following holds true for X1.
[Math. 234]



[1555] The following holds true for Xz. In the following, z is an integer no smaller than two and no greater than three, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 235]



[1556] The following holds true for P1.
[Math. 236]



[1557] The following holds true for P2.
[Math. 237]



[1558] Further, (2) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2x(2xf-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-1-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-1-2) where 2i=2c holds true.

[1559] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[1560] The following holds true for X1.
[Math. 238]



[1561] The following holds true for Xz. In the following, z is an integer no smaller than two and no greater than three, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 239]



[1562] The following holds true for P1.
[Math. 240]



[1563] The following holds true for P2.
[Math. 241]



[1564] Further, (3) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-2-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-2-1) where 2i=2c holds true.

[1565] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[1566] The following holds true for X1. In the following, and y is an integer no smaller than three and no greater than r#(2c),1.
[Math. 242]



[1567] The following holds true for Xw. In the following, w is an integer no smaller than two and no greater than three.
[Math. 243]



[1568] The following holds true for P1.
[Math. 244]



[1569] The following holds true for P2.
[Math. 245]





[1570] Further, (4) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-2-2), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-2-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[1571] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[1572] The following holds true for X1. In the following, y is an integer no smaller than three and no greater than r#(2c),1.
[Math. 246]



[1573] The following holds true for Xw. In the following, w is an integer no smaller than two and no greater than three.
[Math. 247]



[1574] The following holds true for P1.
[Math. 248]



[1575] The following holds true for P2.
[Math. 249]



[1576] Further, (5) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-1-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-1-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[1577] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[1578] The following holds true for X1.In the following, y is an integer no smaller than three and no greater than r#(2d+1),1.
[Math. 250]



[1579] The following holds true for Xw. In the following, w is an integer no smaller than two and no greater than three.
[Math. 251]



[1580] The following holds true for P1.
[Math. 252]



[1581] The following holds true for P2.
[Math. 253]



[1582] Further, (6) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-1-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-1-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[1583] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[1584] The following holds true for X1. In the following, y is an integer no smaller than three and no greater than r#(2d+1),1.
[Math. 254]



[1585] The following holds true for Xw. In the following, w is an integer no smaller than two and no greater than three.
[Math. 255]



[1586] The following holds true for P1.
[Math. 256]



[1587] The following holds true for P2.
[Math. 257]



[1588] Further, (7) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-2-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-2-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[1589] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[1590] The following holds true for X1.
[Math. 258]





[1591] The following holds true for Xz. In the following, z is an integer no smaller than two and no greater than three, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 259]



[1592] The following holds true for P1.
[Math. 260]



[1593] The following holds true for P2.
[Math. 261]



[1594] Further, (8) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-2-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-2-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[1595] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[1596] The following holds true for X1.
[Math. 262]



[1597] The following holds true for Xz. In the following, z is an integer no smaller than two and no greater than three, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 263]



[1598] The following holds true for P1.
[Math. 264]



[1599] The following holds true for P2.
[Math. 265]



[1600] As such, an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial can be generated by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, and the code so generated achieves high error correction capability.

(Embodiment D2)



[1601] In the present embodiment, description is provided of a method of code configuration that is a generalization of the method described in embodiment D1 of configuring an LDPC-CC of coding rate 3/5 that is based on a parity check polynomial.

[1602] Bits of information bits X1, X2, X3 and parity bits P1, P2, at time point j, are expressed X1,j, X2,j, X3,j and Pi,j, P2,j, respectively.

[1603] A vector uj, at time point j, is expressed uj = (X1,j, X2,j, X3,j, P1,j, P2,j).

[1604] Given a delay operator D, polynomial expressions of the information bits X1, X2, X3 are X1(D), X2(D), X3(D), and polynomial expressions of the parity bits P1, P2 are P1(D), P2(D).

[1605] Further, consideration is given to an LDPC-CC of coding rate 3/5 and time-varying period 2m that is based on a parity check polynomial.

[1606] The following mathematical expressions are provided as parity check polynomials satisfying zero for an LDPC-CC of coding rate 3/5 and time-varying period 2m that is based on a parity check polynomial.

[1607] First, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1 xP1(D) and two for 1 ×P2(D).
[Math. 266-1]



[Math. 266-2]







[1608] In expressions (131-1-1), (131-1-2), (131-2-1), (131-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[1609] In expressions (131-1-1), (131-1-2), (131-2-1), (131-2-2), α#(2i),p,q (where p is an integer no smaller than one and no greater than three, q is an integer no smaller than one and no greater than r#(2i),p (where r#(2i),p is a natural number)) and β#(2i),0 is a natural number, β#(2i),1 is a natural number, β#(2i),2 is an integer no smaller than zero, and β#(2i),3 is a natural number.

[1610] Further, R#(2i),p is a natural number satisfying 1≤R#(2i),p<r#(2i),p.

[1611] Further, y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for (y,z) where y≠z. ∀ is a universal quantifier, (y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for all y and all z satisfying y≠z. )

[1612] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (131-1-1) or expression (131-1-2) is referred to as "#(2i); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (131-2-1) or expression (131-2-2) is referred to as "#(2i); second expression" for realizing a time-varying period 2m.

[1613] Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (131-1-1) or expression (131-1-2) is prepared.

[1614] That is, for i=0, a parity check polynomial satisfying zero provided by expression (131-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (131-1-2) where i=0 is prepared.

[1615] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (131-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (131-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (131-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (131-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (131-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (131-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (131-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (131-1-2) where i=m-1 is prepared.



[1616] Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (131-2-1) or expression (131-2-2) is prepared.

[1617] That is, for i=0, a parity check polynomial satisfying zero provided by expression (131-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (131-2-2) where i=0 is prepared.

[1618] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (131-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (131-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (131-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (131-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (131-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (131-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (131-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (131-2-2) where i=m-1 is prepared.



[1619] Similarly, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1 ×P2(D).
[Math. 267-1]



[Math. 267-2]





[1620] In expressions (132-1-1), (132-1-2), (132-2-1), (132-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[1621] In expressions (132-1-1), (132-1-2), (132-2-1), (132-2-2), α#(2i+1),p,q (where p is an integer no smaller than one and no greater than three, q is an integer no smaller than one and no greater than r#(2i+1),p (where r#(2i+1),p is a natural number)) and β#(2i+1),0 is a natural number, β#(2i+1),1 is a natural number, β#(2i+1),2 is an integer no smaller than zero, and β#(2i+1),3 is a natural number.

[1622] Further, R#(2i+1),p is a natural number satisfying 1≤R#(2i+1),p<r#(2i+1),p.

[1623] Further, y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for (y,z) where y≠z. ∀ is a universal quantifier, (y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and a#(2i+1),p,y≠α#(2i+1),p,z holds true for all y and all z satisfying y≠z.)

[1624] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (132-1-1) or expression (132-1-2) is referred to as "#(2i+1); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (132-2-1) or expression (132-2-2) is referred to as "#(2i+1); second expression" for realizing a time-varying period 2m.

[1625] Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (132-1-1) or expression (132-1-2) is prepared.

[1626] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (132-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (132-1-2) where i=0 is prepared.

[1627] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (132-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (132-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (132-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (132-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (132-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (132-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (132-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (132-1-2) where i=m-1 is prepared.



[1628] Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (132-2-1) or expression (132-2-2) is prepared.

[1629] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (132-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (132-2-2) where i=0 is prepared.

[1630] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (132-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (132-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (132-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (132-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (132-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (132-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (132-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (132-2-2) where i=m-1 is prepared.



[1631] As such, an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1632] Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (131-1-1) or expression (131-1-2), parity check polynomials satisfying zero provided by expression (131-2-1) or expression (131-2-2), parity check polynomials satisfying zero provided by expression (132-1-1) or expression (132-1-2), and parity check polynomials satisfying zero provided by expression (132-2-1) or expression (132-2-2).

[1633] For example, the time varying period 2×m can be formed by preparing a 4×m number of different parity check polynomials satisfying zero.

[1634] Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

[1635] The following describes the relationship between time point j and expressions (131-1-1), (131-1-2), (131-2-1), (131-2-2), (132-1-1), (132-1-2), (132-2-1), and (132-2-2) (where j is an integer no smaller than zero).

[1636] The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m-1).

[1637] Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i = k in #(2i); first expression and #(2i); second expression, hold true.

[1638] Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m-1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

[1639] The following describes a method of configuring a parity check matrix for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1640] As already described above, a vector uj at time point j is expressed as uj=(X2,j, X2,j, X3,j, P1,j, P2,j) (where j is an integer no smaller than zero). In the following, a case where u is a transmission vector is considered. Note that in the following, j is an integer no smaller than one, and thus j differs between the description having been provided above and the description provided in the following. (j is set as such to facilitate understanding of the correspondence between the column numbers and the row numbers of the parity check matrix.)

[1641] Accordingly, u=(u1, u2, u3, ..., uy-1, uy, uy+i, ...)T=(X1,1, X2,1, X3,1, P1,1, P2,1, X1,2, X2,2, X3,2, P1,2, P2,2, X1,3, X2,3, X3,3, P1,3, P2,3, ..., X1,y-1, X2,y-1, X3,y-1, P1,y-1, P2,y-1, X1,y, X2,y, X3,y, P1,y, P2,y, X1,y+1, X2,y+1, X3,y+1 P1,y+1, P2,y+1, ...)T Further, when using H to denote a parity check matrix for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, Hu=0 holds true (here, Hu=0 indicates that all elements of the vector Hu are zeroes).

[1642] FIG. 66 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the topmost row of the parity check matrix is considered as the first row. Further, row number is incremented by one each time moving to a lower row. Accordingly, the topmost row is considered as the first row, the row immediately below the first row is considered as the second row, and the subsequent rows are considered as the third row, the fourth row, and so on.

[1643] As illustrated in FIG. 66:

"a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";
"a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×(2m-1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression";

"a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression";

"a vector for the 2×(2m+1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the 2×(2m+2)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×i-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); first expression"; and

"a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); second expression", and so on (where i is an integer no smaller than one).



[1644] FIG. 67 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the leftmost column of the parity check matrix Hpro_m is considered as the first column. Further, column number is incremented by one each time moving to a rightward column. Accordingly, the leftmost column is considered as the first column, the column immediately to the right of the first column is considered as the second column, and the subsequent columns are considered as the third column, the fourth column, and so on.

[1645] As illustrated in FIG. 67:

"a vector for the first column of the parity check matrix H is related to X1 at time point 1";

"a vector for the second column of the parity check matrix H is related to X2 at time point 1";

"a vector for the third column of the parity check matrix H is related to X3 at time point 1";

"a vector for the fourth column of the parity check matrix H is related to P1 at time point 1";

"a vector for the fifth column of the parity check matrix H is related to P2 at time point 1";

"a vector for the 5×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 5×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 5×(j-1)+3th column of the parity check matrix H is related to X3 at time point j";

"a vector for the 5×(j-1)+4th column of the parity check matrix H is related to P1 at time point j"; and

"a vector for the 5×(j-1)+5th column of the parity check matrix H is related to P2 at time point j", and so on (where j is an integer no smaller than one).



[1646] FIG. 68 indicates a parity check matrix for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1647] The following focuses on 1×X1(D), 1×X2(D), 1×X3(D), 1×P1(D), 1×P2(D) in the parity check matrix for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1648] The parity check polynomials at time point j=1 are parity check polynomials when i=0 in expressions (131-1-1), (131-1-2), (131-2-1), (131-2-2).

[1649] A vector for the first row in FIG. 68 can be generated from a parity check polynomial when i=0 in expression (131-1-1) or expression (131-1-2) (refer to FIG. 66).

[1650] In expressions (131-1-1) and (131-1-2):
  • a term for 1×X1(D) exists;
  • terms for 1×X2(D) and 1×X3(D) do not exist; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[1651] Further, the relationship between column numbers and X1, X2, X3, P1, P2 is as indicated in FIG. 67. Based on the relationship indicated in FIG. 67 and the fact that a term for 1×X1(D) exists, a column related to X1 in the vector for the first row in FIG. 68 is "1". Further, based on the relationship indicated in FIG. 67 and the fact that terms for 1×X2(D) and 1×X3(D) do not exist, columns related to X2 and X3 in the vector for the first row in FIG. 68 are "0". In addition, based on the relationship indicated in FIG. 67 and the fact that a term for 1×P1(D) exists but a term for 1×P2(D) does not exist, a column related to P1 in the vector for the first row in FIG. 68 is "1", and a column related to P2 in the vector for the first row in FIG. 68 is "0".

[1652]  As such, the vector for the first row in FIG. 68 is "10010", as indicated by 3900-1 in FIG. 68.

[1653] A vector for the second row in FIG. 68 can be generated from a parity check polynomial when i=0 in expression (131-2-1) or expression (131-2-2) (refer to FIG. 66).

[1654] In expressions (131-2-1) and (131-2-2):
  • a term for 1×X1(D) does not exist;
  • terms for 1×X2(D) and 1×X3(D) exist; and
  • a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists.


[1655] Further, the relationship between column numbers and X1, X2, X3, P1, P2 is as indicated in FIG. 67. Based on the relationship indicated in FIG. 67 and the fact that a term for 1×X1(D) does not exist, a column related to X1 in the vector for the second row in FIG. 68 is "0". Further, based on the relationship indicated in FIG. 67 and the fact that terms for 1×X2(D) and 1×X3(D) exist, columns related to X2 and X3 in the vector for the second row in FIG. 68 are "1". In addition, based on the relationship indicated in FIG. 67 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the second row in FIG. 68 is "Y", and a column related to P2 in the vector for the second row in FIG. 68 is "1", where Y is either "0" or "1".

[1656] As such, the vector for the second row in FIG. 68 is "011Y1", as indicated by 3900-2 in FIG. 68.

[1657] The parity check polynomials at time point j=2 are parity check polynomials when i=0 in expressions (132-1-1), (132-1-2), (132-2-1), (132-2-2).

[1658] A vector for the third row in FIG. 68 can be generated from a parity check polynomial when i=0 in expression (132-1-1) or expression (132-1-2) (refer to FIG. 66).

[1659] In expressions (132-1-1) and (132-1-2):
  • a term for 1×X1(D) does not exist;
  • terms for 1×X2(D) and 1×X3(D) exist; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[1660] Further, the relationship between column numbers and X1, X2, X3, P1, P2 is as indicated in FIG. 67. Based on the relationship indicated in FIG. 67 and the fact that a term for 1×X1(D) does not exist, a column related to X1 in the vector for the third row in FIG. 68 is "0". Further, based on the relationship indicated in FIG. 67 and the fact that terms for 1×X2(D) and 1×X3(D) exist, columns related to X2 and X3 in the vector for the third row in FIG. 68 are "1". In addition, based on the relationship indicated in FIG. 67 and the fact that a term for 1×P1(D) exists but a term for 1 ×P2(D) does not exist, a column related to P1 in the vector for the third row in FIG. 68 is "1", and a column related to P2 in the vector for the third row in FIG. 68 is "0".

[1661] As such, the vector for the third row in FIG. 68 is "01110", as indicated by 3901-1 in FIG. 68.

[1662] A vector for the fourth row in FIG. 68 can be generated from a parity check polynomial when i=0 in expression (132-2-1) or expression (132-2-2) (refer to FIG. 66).

[1663] In expressions (132-2-1) and (132-2-2):
  • a term for 1×X1(D) exists;
  • terms for 1×X2(D) and 1×X3(D) do not exist; and
  • a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists.


[1664] Further, the relationship between column numbers and X1, X2, X3, P1, P2 is as indicated in FIG. 67. Based on the relationship indicated in FIG. 67 and the fact that a term for 1×X1(D) exists, a column related to X1 in the vector for the fourth row in FIG. 68 is "1". Further, based on the relationship indicated in FIG. 67 and the fact that terms for 1×X2(D) and 1×X3(D) do not exist, columns related to X2 and X3 in the vector for the fourth row in FIG. 68 are "0". In addition, based on the relationship indicated in FIG. 67 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the fourth row in FIG. 68 is "Y", and a column related to P2 in the vector for the fourth row in FIG. 68 is "1".

[1665] As such, the vector for the fourth row in FIG. 68 is "100Y1", as indicated by 3901-2 in FIG. 68.

[1666] Because it can be considered that the above similarly applies to cases where time point j=3, 4, 5, the parity check matrix H has the configuration indicated in FIG. 68.

[1667] That is, due to the parity check polynomials of expressions (131-1-1), (131-1-2), (131-2-1), (131-2-2) being used at time point j=2k+1 (where k is an integer no smaller than zero), "10010" exists in the 2×(2k+1)-1th row of the parity check matrix H, and "011Y1" exists in the 2×(2k+1)throw of the parity check matrix H, as illustrated in FIG. 68.

[1668] Further, due to the parity check polynomials of expressions (132-1-1), (132-1-2), (132-2-1), (132-2-2) being used at time point j=2k+2 (where k is an integer no smaller than zero), "01110" exists in the 2×(2k+2)-1th row of the parity check matrix H, and "100Y1" exists in the 2×(2k+2)th row of the parity check matrix H, as illustrated in FIG. 68.

[1669] Accordingly, as illustrated in FIG. 68, when denoting a column number of a leftmost column corresponding to "1" in "10010" in a row where "10010" exists (e.g., 3900-1 in FIG. 68) as "a", "01110" (e.g., 3901-1 in FIG. 68) exists in a row that is two rows below the row where "10010" exists, starting from column "a+5".

[1670] Similarly, as illustrated in FIG. 68, when denoting a column number of a leftmost column corresponding to "1" in "011Y1" in a row where "011Y1" exists (e.g., 3900-2 in FIG. 68) as "b", "100Y1" (e.g., 3901-2 in FIG. 68) exists in a row that is two rows below the row where "011Y1" exists, starting from column "b+5".

[1671] Similarly, as illustrated in FIG. 68, when denoting a column number of a leftmost column corresponding to "1" in "01110" in a row where "01110" exists (e.g., 3901-1 in FIG. 68) as "c", "10010" (e.g., 3902-1 in FIG. 68) exists in a row that is two rows below the row where "01110" exists, starting from column "c+5".

[1672] Similarly, as illustrated in FIG. 68, when denoting a column number of a leftmost column corresponding to "1" in "100Y1" in a row where "100Y1" exists (e.g., 3901-2 in FIG. 68) as "d", "011Y1" (e.g., 3902-2 in FIG. 68) exists in a row that is two rows below the row where "100Y1" exists, starting from column "d+5".

[1673] The following describes a parity check matrix for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial when tail-biting is not performed, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1674] In the following, Hcom[u][v] (where u and v are integers no smaller than one) denotes an element at row "u" column "v" of a parity check matrix for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1675] Based on description above provided with reference to FIG. 66:

"a vector for the 2×g-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); first expression"; and

"a vector for the (2×g)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); second expression" (where g is an integer no smaller than one).



[1676] Based on description above provided with reference to FIG. 67:

"a vector for the 5×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 5×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 5×(j-1)+3th column of the parity check matrix H is related to X3 at time point j";

"a vector for the 5×(j-1)+4th column of the parity check matrix H is related to P1 at time point j"; and

"a vector for the 5×(j-1)+5th column of the parity check matrix H is related to P2 at time point j" (where j is an integer no smaller than one).



[1677] Based on the above, the following describes component Hcom[2×g-1][v] in row 2×g-1 (where g is an integer no smaller than one) and component Hcom[2×g][v] in row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1678] As already described above, a parity check polynomial satisfying zero of #((g-1)%2m); first expression can be used to generate a vector for row 2×g-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1679] Further, a parity check polynomial satisfying zero of #((g-1)%2m); second expression can be used to generate a vector for row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1680]  Accordingly, when g=2×f-1 (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (131-1-1) or expression (131-1-2), can be used to generate a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1681] Further, a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (131-2-1) or expression (131-2-2), can be used to generate a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1682] Further, when g=2×f (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (132-1-1) or expression (132-1-2), can be used to generate a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1683] Further, a parity check polynomial satisfying zero of #(((2×f)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (132-2-1) or expression (132-2-2), can be used to generate a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1684] Accordingly, (1) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (131-1-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (131-1-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[1685] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[1686] The following holds true for X1.
[Math. 268]



[1687] The following holds true for Xz. In the following, z is an integer no smaller than two and no greater than three, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 269]



[1688] The following holds true for P1.
[Math. 270]



[1689] The following holds true for P2.
[Math. 271]



[1690] Further, (2) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (131-1-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (131-1-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[1691] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[1692] The following holds true for X1.
[Math. 272]



[1693] The following holds true for Xz. In the following, z is an integer no smaller than two and no greater than three, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 273]



[1694] The following holds true for P1.
[Math. 274]





[1695] The following holds true for P2.
[Math. 275]



[1696] Further, (3) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (131-2-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (131-2-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[1697] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[1698] The following holds true for X1. In the following, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),1.
[Math. 276]





[1699] The following holds true for Xw. In the following, w is an integer no smaller than two and no greater than three.
[Math. 277]



[1700] The following holds true for P1.
[Math. 278]



[1701] The following holds true for P2.
[Math. 279]



[1702] Further, (4) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (131-2-2), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (131-2-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[1703] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[1704] The following holds true for X1. In the following, y is an integer no smaller than R#(2c),i+1 and no greater than r#(2c),1.
[Math. 280]



[1705] The following holds true for Xw. In the following, w is an integer no smaller than two and no greater than three.
[Math. 281]





[1706] The following holds true for P1.
[Math. 282]



[1707] The following holds true for P2.
[Math. 283]



[1708] Further, (5) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (132-1-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (132-1-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[1709] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[1710]  The following holds true for X1. In the following, y is an integer no smaller than R#(2d+1),1+1 and no greater than r#(2d+1),1.
[Math. 284]



[1711] The following holds true for Xw. In the following, w is an integer no smaller than two and no greater than three.
[Math. 285]



[1712] The following holds true for P1.
[Math. 286]



[1713] The following holds true for P2.
[Math. 287]





[1714] Further, (6) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (132-1-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (132-1-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[1715] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[1716] The following holds true for X1. In the following, y is an integer no smaller than R#(2d+1),1+1 and no greater than r#(2d+1),1.
[Math. 288]



[1717] The following holds true for Xw. In the following, w is an integer no smaller than two and no greater than three.
[Math. 289]



[1718] The following holds true for P1.
[Math. 290]



[1719] The following holds true for P2.
[Math. 291]



[1720] Further, (7) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (132-2-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (132-2-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[1721] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[1722] The following holds true for X1.
[Math. 292]



[1723] The following holds true for Xz. In the following, z is an integer no smaller than two and no greater than three, and y is an integer no smaller than R#(2d+1),z+1 and no greater than r#(2d+1),z.
[Math. 293]



[1724] The following holds true for P1.
[Math. 294]





[1725] The following holds true for P2.
[Math. 295]



[1726] Further, (8) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (132-2-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (132-2-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[1727] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[1728] The following holds true for X1.
[Math. 296]





[1729] The following holds true for Xz. In the following, z is an integer no smaller than two and no greater than three, and y is an integer no smaller than R#(2d+1),z+1 and no greater than r#(2d+1),z.
[Math. 297]



[1730] The following holds true for P1.
[Math. 298]



[1731] The following holds true for P2.
[Math. 299]



[1732] As such, an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial can be generated by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, and the code so generated achieves high error correction capability.

(Embodiment D3)



[1733] In the present embodiment, description is provided of a device that uses the LDPC-CC of coding rate 3/5 that is based on a parity check polynomial, description of which has been provided in embodiments D1 and D2.

[1734] As one example, description is provided of a case where the LDPC-CC of coding rate 3/5 that is based on a parity check polynomial, description of which has been provided in embodiments D1 and D2, is applied to a communication device.

[1735] FIG. 22 illustrates the structures of a transmitting device 2200 and a receiving device 2210 in the communication device pertaining to the present embodiment.

[1736] An encoder 2201 receives information to be transmitted as input, and is capable of performing various types of encoding. In particular, when receiving a specification to perform encoding by using the LDPC-CC of coding rate 3/5 that is based on a parity check polynomial, description of which has been provided in embodiments D1 and D2, the encoder 2201 performs encoding by using the LDPC-CC of coding rate 3/5 that is based on a parity check polynomial, description of which has been provided in embodiments D1 and D2, to calculate parities P1 and P2. Further, the encoder 2201 outputs the information to be transmitted and the parities P1 and P2 as a transmission sequence.

[1737] A modulator 2202 receives the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, performs mapping based on a predetermined modulation scheme (e.g., BPSK, QPSK, 16QAM, 64QAM), and outputs a baseband signal. Further, the modulator 2202 may also receive information other than the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, as input, perform mapping, and output a baseband signal. For example, the modulator 2202 may receive control information as input.

[1738] The transmitting device outputs a transmission signal after performing predetermined signal processing (e.g., signal processing for generation of an OFDM signal, frequency conversion, amplification) with respect to such signals (e.g., baseband signals, pilot signals). The transmitting device may transmit the transmission signal over a wireless transmission path utilizing electromagnetic waves, or over a wired transmission path utilizing a coaxial cable, a power line, an optical cable, or the like.

[1739] The transmission signal is received by the receiving device 2210 after travelling over the transmission path. A receiver 2211 receives a reception signal as input, performs predetermined signal processing (e.g., bandwidth limitation, frequency conversion, signal processing for OFDM, frequency offset estimation, signal detection, channel estimation), and outputs a baseband signal and a channel estimation signal.

[1740] A log-likelihood ratio generation section 2212 receives the baseband signal and the channel estimation signal as input (may receive other signals as input), and for example, calculates and outputs a log-likelihood ratio for each bit (may calculate and output a hard value (hard decision value)).

[1741] A decoder 2213 receives the log-likelihood ratio for each bit as input, performs belief propagation decoding (e.g., sum-product decoding, scheduled sum-product decoding (Layered BP (belief propagation) decoding), min-sum decoding, Normalized BP decoding, offset BP decoding), and outputs an estimation sequence. The decoder 2213 performs the belief propagation decoding based on the parity check matrix for the LDPC-CC of coding rate 3/5 that is based on a parity check polynomial, description of which has been provided in embodiments D1 and D2.

[1742] FIG. 69 illustrates one example of the structure of an encoder for the LDPC-CC of coding rate 3/5 that is based on a parity check polynomial, description of which has been provided in embodiments D1 and D2. Description on such an encoder has been provided with reference to the encoder 2201 in FIG. 22.

[1743] In FIG. 69, an Xz computation section 4001-z (where z is an integer no smaller than one and no greater than three) includes a plurality of shift registers that are connected in series and a calculator that performs XOR calculation on bits collected from some of the shift registers (refer to FIGs. 2 and 22).

[1744] The Xz computation section 4001-z receives an information bit Xz,j at time point j as input, performs the XOR calculation, and outputs bits 4002-z-1 and 4002-z-2, which are acquired through the Xz calculation.

[1745] A P1 computation section 4004-1 includes a plurality of shift registers that are connected in series and a calculator that that performs XOR calculation on bits collected from some of the shift registers (refer to FIGs. 2 and 22).

[1746] The P1 computation section 4004-1 receives a bit P1,j of parity P1 at time point j as input, performs the XOR calculation, and outputs bits 4005-1-1 and 4005-1-2, which are acquired through the P1 calculation.

[1747] A P2 computation section 4004-2 includes a plurality of shift registers that are connected in series and a calculator that that performs XOR calculation on bits collected from some of the shift registers (refer to FIGs. 2 and 22).

[1748] The P2 computation section 4004-2 receives a bit P2,j of parity P2 at time point j as input, performs the XOR calculation, and outputs bits 4005-2-1 and 4005-2-2, which are acquired through the P2 calculation.

[1749] An XOR (calculator) 4005-1 receives the bits 4002-1-1 through 4002-3-1 acquired by X1 calculation through X3 calculation, respectively, the bit 4005-1-1 acquired by P1 calculation, and the bit 4005-2-1 acquired by the P2 calculation as input, performs XOR calculation, and outputs a bit P1,j of parity P1 at time point j.

[1750] An XOR (calculator) 4005-2 receives the bits 4002-1-2 through 4002-3-2 acquired by X1 calculation through X3 calculation, respectively, the bit 4005-1-2 acquired by P1 calculation, and the bit 4005-2-2 acquired by the P2 calculation as input, performs XOR calculation, and outputs a bit P2,j of parity P2 at time point j.

[1751] It is preferable that initial values of the shift registers of the Xz computation section 4001-z, the P1 computation section 4004-1, and the P2 computation section 4004-2 illustrated in FIG. 69 be set to "0" (zero). By making such a configuration, it becomes unnecessary to transmit to the receiving device parities P1 and P2 before the setting of initial values.

[1752] The following describes a method of information-zero termination.

[1753] Suppose that in FIG. 70, information X1 through X3 exist from time point 0, and information X3 at time point s (where s is an integer no smaller than zero) is the last information bit. That is, suppose that the information to be transmitted from the transmitting device to the receiving device is information X1,j through X3,j, being information X1 through X3 at time point j, respectively, where j is an integer no smaller than zero and no greater than s.

[1754] In such a case, the transmitting device transmits information X1 through X3, parity P1, and parity P2 from time point 0 to time point s, or that is, transmits X1,j, X2,j, X3,j, P1,j, P2,j, where j is an integer no smaller than zero and no greater than s. (Note that P1,j and P2,j denote parity P1 and parity P2 at time point j, respectively.)

[1755] Further, suppose that information X1 through X3 from time point s+1 to time point s+g (where g is an integer no smaller than one) is "0", or that is, when denoting information X1 through X3 at time point t as X1,t, X2,t, X3,t, respectively, X1,t=0, X2,t=0, X3,t=0 hold true for t being an integer no smaller than s+1 and no greater than s+g. The transmitting device, by performing encoding, acquires parities P1,t and P2,t for t being an integer no smaller than s+1 and no greater than s+g. The transmitting device, in addition to the information and parities described above, transmits parities P1,t and P2,t for t being an integer no smaller than s+1 and no greater than s+g.

[1756] Meanwhile, the receiving device performs decoding by using log-likelihood ratios for the information and the parities transmitted by the transmitting device, and log-likelihood ratios corresponding to X1,t=0, X2,t=0, X3,i=0, for t being an integer no smaller than s+1 and no greater than s+g, and thereby acquires an estimation sequence of information.

[1757] FIG. 71 illustrates an example differing from that illustrated in FIG. 70. Suppose that information X1 through X3 exist from time point 0, and information Xf for time point s (where s is an integer no smaller than zero) is the last information bit. Here, f is an integer no smaller than one and no greater than two. In FIG. 70, f equals 2, for example. That is, suppose that the information to be transmitted from the transmitting device to the receiving device is information Xi,s, where i is an integer no smaller than one and no greater than f, and information X1,j, information X2,j, and information X3,j, being information X1 through X3 at time point j, respectively, where j is an integer no smaller than zero and no greater than s-1.

[1758] In such a case, the transmitting device transmits information X1 through X3, parity P1, and parity P2 from time point 0 to time point s-1, or that is, transmits X1,j, X2,j, X3,j, P1,j, P2,j, where j is an integer no smaller than zero and no greater than s-1. (Note that P1,j and P2,j denote parity P1 and parity P2 at time point j, respectively.)

[1759] Further, suppose that at time point s, information Xi,s, when i is an integer no smaller than one and no greater than f, is information that the transmitting device is to transmit, and suppose that Xk,s, when k is an integer so smaller than f+1 and no greater than three, equals "0" (zero).

[1760] Further, suppose that information X1 through X3 from time point s+1 to time point s+g-1 (where g is an integer no smaller than two) is "0", or that is, when denoting information X1 through X3 at time point t as X1,t, X2,t, X3,t, respectively, X1,t=0, X2,t=0, X3,t=0 hold true when t is an integer no smaller than s+1 and no greater than s+g-1. The transmitting device, by performing encoding from time point s to time point s+g-1, acquires parities P1,u and P2,u for u being an integer no smaller than s and no greater than s+g-1. The transmitting device, in addition to the information and parities described above, transmits Xi,s for i being an integer no smaller than one and no greater than f, and parities P1,u and P2,u for u being an integer no smaller than s and no greater than s+g-1.

[1761] Meanwhile, the receiving device performs decoding by using log-likelihood ratios for the information and the parities transmitted by the transmitting device, log-likelihood ratios corresponding to Xk,s=0 (where k is an integer no smaller than f+1 and no greater than three) and log-likelihood ratios corresponding to X1,t=0, X2,t=0, X3,t=0 for t being an integer no smaller than s+1 and no greater than s+g-1, and thereby acquires an estimation sequence of information.

[1762] Although description is provided above taking an example where error correction coding is introduced to a communication device, the error correction coding described above is not limited to being introduced to a communication device, and for example, may be introduced to a storage medium (storage). When making such a modification, information that is to be stored to a storage medium (storage) is encoded by using the LDPC-CC of coding rate 3/5 that is based on a parity check polynomial, description of which has been provided in embodiments D1 and D2, and resultant information and parities are stored to the storage medium (storage). When making such a modification, it is preferable that information-zero termination be introduced as described above and that a data sequence as described above corresponding to a data sequence (information and parities) transmitted by the transmitting device when information-zero termination is applied be stored to the storage medium (storage).

[1763] Further, the LDPC-CC of coding rate 3/5 that is based on a parity check polynomial, description of which has been provided in embodiments D1 and D2, is applicable to any device that requires error correction coding (e.g., a memory, a hard disk).

(Embodiment D4)



[1764] In the present embodiment, description is provided of a method of configuring an LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). The LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme described in the present embodiment is based on the LDPC-CC of coding rate 3/5 that is based on a parity check polynomial, description of which has been provided in embodiments D1 and D2.

[1765] Patent Literature 2 includes explanation regarding an LDPC-CC of coding rate (n-1)/n (where n is an integer no smaller than two) that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). However, Patent Literature 2 poses a problem for not disclosing an LDPC-CC of a coding rate not satisfying (n-1)/n that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1766] In the present embodiment, as one example of an LDPC-CC of a coding rate not satisfying (n-1)/n that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), description is provided of a method of configuring an LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[Periodic Time-varying LDPC-CC of Coding rate 3/5 Using Improved Tail-biting Scheme and Based on Parity Check Polynomial]



[1767] The following describes a periodic time-varying LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme and is based on a parity check polynomial, based on the configuration of the LDPC-CC of coding rate 3/5 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments D1 and D2.

[1768] The following describes a method of configuring an LDPC-CC of coding rate 3/5 and time-varying period 2m that is based on a parity check polynomial. Such method has already been described in embodiment D2.

[1769] First, the following parity check polynomials satisfying zero are prepared.
[Math. 300-1]



[Math. 300-2]







[1770] In expressions (165-1-1), (165-1-2), (165-2-1), (165-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[1771] In expressions (165-1-1), (165-1-2), (165-2-1), (165-2-2), α#(2i),p,q (where p is an integer no smaller than one and no greater than three, q is an integer no smaller than one and no greater than r#(2i),p (where r#(2i),p is a natural number)) and β#(2i),0 is a natural number, β#(2i),1 is a natural number, β#(2i),2 is an integer no smaller than zero, and β#(2i),3 is a natural number.

[1772] Further, R#(2i),p is a natural number satisfying 1≤R#(2i),p<r#(2i),p.

[1773] Further, y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for all y and all z satisfying y≠z.)

[1774] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (165-1-1) or expression (165-1-2) is referred to as "#(2i); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (165-2-1) or expression (165-2-2) is referred to as "#(2i); second expression" for realizing a time-varying period 2m.

[1775] Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (165-1-1) or expression (165-1-2) is prepared.

[1776] That is, for i=0, a parity check polynomial satisfying zero provided by expression (165-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (165-1-2) where i=0 is prepared.

[1777] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (165-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (165-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (165-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (165-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (165-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (165-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (165-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (165-1-2) where i=m-1 is prepared.



[1778] Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (165-2-1) or expression (165-2-2) is prepared.

[1779] That is, for i=0, a parity check polynomial satisfying zero provided by expression (165-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (165-2-2) where i=0 is prepared.

[1780] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (165-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (165-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (165-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (165-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (165-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (165-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (165-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (165-2-2) where i=m-1 is prepared.



[1781] Similarly, the following parity check polynomials satisfying zero are provided.
[Math. 301-1]



[Math. 301-2]





[1782] In expressions (166-1-1), (166-1-2), (166-2-1), (166-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[1783] In expressions (166-1-1), (166-1-2), (166-2-1), (166-2-2), α#(2i+1),p,q (where p is an integer no smaller than one and no greater than three, q is an integer no smaller than one and no greater than r#(2i+1),p (where r#(2i+1),p is a natural number)) and β#(2i+1),0 is a natural number, β#(2i+1),1 is a natural number, β#(2i+1),2 is an integer no smaller than zero, and β#(2i+1),3 is a natural number.

[1784] Further, R#(2i+1),p is a natural number satisfying 1≤R#(2i+i),p<r#(2i+1),p.

[1785] Further, y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α≠(2i+1),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α≠(2i+1),p,z holds true for all y and all z satisfying y≠z.)

[1786] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (166-1-1) or expression (166-1-2) is referred to as "#(2i+1); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (166-2-1) or expression (166-2-2) is referred to as "#(2i+1); second expression" for realizing a time-varying period 2m.

[1787] Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (166-1-1) or expression (166-1-2) is prepared.

[1788] That is, for i=0, a parity check polynomial satisfying zero provided by expression (166-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (166-1-2) where i=0 is prepared.

[1789] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (166-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (166-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (166-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (166-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (166-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (166-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (166-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (166-1-2) where i=m-1 is prepared.



[1790] Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (166-2-1) or expression (166-2-2) is prepared.

[1791] That is, for i=0, a parity check polynomial satisfying zero provided by expression (166-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (166-2-2) where i=0 is prepared.

[1792] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (166-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (166-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (166-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (166-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (166-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (166-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (166-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (166-2-2) where i=m-1 is prepared.



[1793] As such, an LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[1794] Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (165-1-1) or expression (165-1-2), parity check polynomials satisfying zero provided by expression (165-2-1) or expression (165-2-2), parity check polynomials satisfying zero provided by expression (166-1-1) or expression (166-1-2), and parity check polynomials satisfying zero provided by expression (166-2-1) or expression (166-2-2).

[1795] For example, the time varying period 2×m is formed by preparing a 4×m number of different parity check polynomials satisfying zero.

[1796] Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

[1797] The following describes the relationship between time point j and expressions (165-1-1), (165-1-2), (165-2-1), (165-2-2), (166-1-1), (166-1-2), (166-2-1), and (166-2-2) (where j is an integer no smaller than zero).

[1798] The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, a%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m-1).

[1799] Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i = k in #(2i); first expression and #(2i); second expression, hold true.

[1800] Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m-1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

[1801] Note that in the parity check polynomials satisfying zero of expressions (165-1-1), (165-1-2), (165-2-1), (165-2-2), (166-1-1), (166-1-2), (166-2-1), and (166-2-2), a sum of the number of terms of P1(D) and the number of terms of P2(D) equals two. This realizes sequentially finding parities P1 and P2 when applying an improved tail-biting scheme, and thus, is a significant factor realizing a reduction in computation amount (circuit scale).

[1802] The following describes the relationship between the time-varying period of the parity check polynomials satisfying zero for the LDPC-CC of coding rate 3/5 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments D1 and D2 and on which the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, and block size in the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) proposed in the present embodiment.

[1803] Regarding this point, in order to achieve error correction capability of even higher level, a configuration is preferable where a Tanner graph formed by the LDPC-CC of coding rate 3/5 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments D1 and D2 and on which the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, resembles a Tanner graph of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). Thus, the following conditions are significant.

<Condition #N1>



[1804] 
  • The number of rows in a parity check matrix for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is a multiple of 4×m.
    • Accordingly, the number of columns in the parity check matrix for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is a multiple of 5×2×m. According to this condition, (for example) a log-likelihood ratio that is necessary in decoding is a log-likelihood ratio of the number of columns in the parity check matrix for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).


[1805] Note that the relationship between the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and the LDPC-CC of coding rate 3/5 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments D1 and D2 and on which the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, is described in detail later in the present disclosure.

[1806] Thus, when denoting the parity check matrix for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as Hpro, the number of columns of Hpro can be expressed as 5×2×m×z (where z is a natural number).

[1807] Accordingly, a transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as vs=(Xs,1,1, Xs,2,1, Xs,3,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, Xs,3,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, Xs,3,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, Xs,3,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T (where k=1, 2, ..., 2×m×z-1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×z)), and Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes).

[1808] Xs,j,k (where j is an integer no smaller than one and no greater than three) is a bit of information Xj, Ppros,1,k is a bit of parity P1 of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and Ppros,2,k is a bit of parity P2 of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1809]  Further, λpro,s,k=(Xs,1,k, Xs,2,k, Xs,3,k, Ppros,i,k, Ppros,2,k) holds true.

[1810] In addition, the number of rows in the parity check matrix Hpro for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is 4×m×z.

[1811] It has been indicated above that the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based on the LDPC-CC of coding rate 3/5 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments D1 and D2. This is explained in the following.

[1812] First, consideration is made of a parity check matrix when configuring a periodic time-varying LDPC-CC using tail-biting by using only parity check polynomials satisfying zero for the LDPC-CC of coding rate 3/5 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments D1 and D2.

[1813] FIG. 72 illustrates a configuration of a parity check matrix H when configuring a periodic time-varying LDPC-CC using tail-biting by performing tail-biting by using only parity check polynomials satisfying zero for an LDPC-CC of coding rate 3/5 and time-varying period 2m.

[1814] Since Condition #N1 is satisfied in FIG. 72, the number of rows of the parity check matrix is m×z and the number of columns of the parity check matrix is 5×2×m×z.

[1815] As illustrated in FIG. 72:

"a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×(2m-1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression";

"a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression";

"a vector for the 2×(2m+1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the 2×(2m+2)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×i-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); first expression";

"a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); second expression" (where i is an integer no smaller than one and no greater than 2×m×z);

"a vector for the 2×(2m-1)×z-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)×zth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)×z-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression"; and

"a vector for the 2×(2m)×zth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression".



[1816] To prepare for the explanation to be provided in the following, a mathematical expression is provided of the parity check matrix H in FIG. 72, which is a parity check matrix when configuring a periodic time-varying LDPC-CC by performing tail-biting by using only parity check polynomials satisfying zero for the LDPC-CC of coding rate 3/5 and time-varying period 2m that is based on a parity check polynomial, description of which is provided in embodiments D1 and D2. When denoting a vector having one row and 5×2×m×z columns in row k of the parity check matrix H as hk, the parity check matrix H in FIG. 72 is expressed as follows.
[Math. 302]

The following describes a parity check matrix for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1817] FIG. 73 illustrates one example of a configuration of a parity check matrix Hpro for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1818] The parity check matrix Hpro for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) satisfies Condition #N1.

[1819] When denoting a vector having one row and 5×2×m×z columns in row k of the parity check matrix Hpro in FIG. 73, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), as gk, the parity check matrix Hpro in FIG. 73 is expressed as follows.
[Math. 303]



[1820] A transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as vs=(Xs,1,1, Xs,2,1, Xs,3,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, Xs,3,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, Xs,3,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, Xs,3,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T (where k=1, 2, ..., 2×m×z-1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×z)), and Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes).

[1821] Xs,j,k (where j is an integer no smaller than one and no greater than three) is a bit of information Xj, Ppros,1,k is a bit of parity P1 of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and Ppros,2,k is a bit of parity P2 of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1822] In the parity check matrix Hpro in FIG. 73, which illustrates one example of a configuration of a parity check matrix Hpro for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), rows other than row one, or that is, rows between row two to row 2×(2×m)×z in the parity check matrix Hpro in FIG. 73, have the same configuration as rows between row two and row 2×(2×m)×z in the parity check matrix H in FIG. 72 (refer to FIGs. 72 and 73). Accordingly, FIG. 73 includes an indication of #0'; first expression at 4401 in the first row. (This point is explained later in the present disclosure.) Accordingly, the following relational expression holds true based on expressions 167 and 168.
[Math. 304]



[1823] Further, the following holds true when i=1.
[Math. 305]



[1824] Accordingly, the parity check matrix Hpro for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as follows.
[Math. 306]



[1825] In expression 171, expression 170 holds true.

[1826] Next, explanation is provided of a method of configuring g1 in expression 171 so that parities can be found sequentially and high error correction capability can be achieved.

[1827] One example of a method of configuring g1 in expression 171, so that parities can be found sequentially and high error correction capability can be achieved, is using a parity check polynomial satisfying zero of #0; first expression of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), which serves as the basis.

[1828] Since g1 is row one of the parity check matrix Hpro for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), g1 is generated from a parity check polynomial satisfying zero that is obtained by transforming a parity check polynomial satisfying zero of #0; first expression. As described above, a parity check polynomial satisfying zero of #0; first expression is expressed by either expression (172-1-1) or expression (172-1-2).
[Math. 307]





[1829] As one example of a parity check polynomial satisfying zero for generating vector g1 in row one of the parity check matrix Hpro for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), a parity check polynomial satisfying zero of #0; first expression is expressed as follows, for either expression (172-1-1) or expression (172-1-2).
[Math. 308]





[1830] Accordingly, vector g1 is a vector having one row and 5×2×m×z columns that is obtained by performing tail-biting with respect to expression 173.

[1831] Note that in the following, a parity check polynomial that satisfies zero provided by expression 173 is referred to as #0'; first expression.

[1832] Accordingly, row one of the parity check matrix Hpro for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be obtained by transforming #0'; first expression of expression 173 (that is, a vector g1 corresponding to one row and 5×2×m×z columns can be obtained).

[1833] A transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is vs=(Xs,1,1, Xs,2,1, Xs,3,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, Xs,3,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, Xs,3,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, Xs,3,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T, and the number of parity check polynomials satisfying zero necessary for obtaining this transmission sequence is 2×(2×m)×z.

[1834] Here, when arranging such 2×(2×m)×z number of parity check polynomials satisfying zero in order, a parity check polynomial satisfying zero appearing eth is referred to in the following as an "eth parity check polynomial satisfying zero" (where e is an integer no smaller than zero and no greater than 2×(2×m)×z-1).

[1835] As such, the parity check polynomials satisfying zero are arranged in the following order:

zeroth: zeroth parity check polynomial satisfying zero;

first: first parity check polynomial satisfying zero;

second: second parity check polynomial satisfying zero;

eth: eth parity check polynomial satisfying zero;

2×(2×m)×z-2th: 2×(2×m)×z-2th parity check polynomial satisfying zero; and

2×(2×m)×z-1th: 2×(2×m)×z-1th parity check polynomial satisfying zero.



[1836] Accordingly, the transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is obtained. (As can be seen from description provided above, when expressing the parity check matrix Hpro for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as provided in expression 168, a vector composed of row e+1 of the parity check matrix Hpro corresponds to the eth parity check polynomial satisfying zero.)

[1837] Accordingly, in the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the second parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the third parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression;

the 2×(2m)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression;

the 2×(2m+1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; first expression;

the 2×(2m+1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×(2m+2)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the 2×(2m+2)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression; and

the 2×(2m)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression.



[1838] That is,
the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;
the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;
the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression; and
the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).

[1839] As description has been provided above, the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), at the same time as achieving high error correction capability, enables finding multiple parities sequentially, and therefore, achieves an advantageous effect of reducing circuit scale of an encoder.

[1840] In the following, explanation is provided of what is meant by "finding parities sequentially".

[1841] In the example described above, since bits of information X1 through X3 are pre-acquired, Ppros,1,1 can be calculated by using the 0th parity check polynomial satisfying zero of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), or that is, by using the parity check polynomial satisfying zero of #0'; first expression provided by expression 173.

[1842] Then, from the bits of information X1 through X3 and Ppros,1,1, another parity (denoted as Pc=1) can be calculated by using another parity check polynomial satisfying zero.

[1843] Further, from the bits of information X1 through X3 and Pc=1, another parity (denoted as Pc=2) can be calculated by using another parity check polynomial satisfying zero.

[1844] By repeating such operation, from the bits of information X1 through X3 and Pc=h, another parity (denoted as Pc=h+1) can be calculated by using a given parity check polynomial satisfying zero.

[1845] This is referred to as "finding parities sequentially", and when parities can be found sequentially, multiple parities can be obtained without calculation of complex simultaneous equations, whereby an advantageous effect is achieved of reducing circuit scale (computation amount) of an encoder.

[1846] Next, explanation is provided of configurations and operations of an encoder and a decoder for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1847] In the following, one example case is considered where the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is used in a communication system. When applying the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) to a communication system, the encoder and the decoder for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) are characterized for each being configured and each operating based on the parity check matrix Hpro for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and based on the relationship Hprovs=0.

[1848] The following provides explanation while referring to FIG. 25, which is an overall diagram of a communication system. An encoder 2511 of a transmitting device 2501 receives an information sequence of block s (Xs,1,1, Xs,2,1, Xs,3,1, Xs,1,2, Xs,2,2, Xs,3,2, ..., Xs,1,k, Xs,2,k, Xs,3,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, Xs,3,2×m×z) as input. The encoder 2511 performs encoding based on the parity check matrix Hpro for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and based on the relationship Hprovs=0. The encoder 2511 generates a transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), denoted as vs=(Xs,1,1, Xs,2,1, Xs,3,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, Xs,3,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, Xs,3,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, Xs,3,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T, and outputs the transmission sequence vs. As already described above, the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is characterized for enabling parities to be found sequentially.

[1849] A decoder 2523 of a receiving device 2520 in FIG. 25 receives, as input, a log-likelihood ratio of each bit of, for example, the transmission sequence vs=(Xs,1,1, Xs,2,1, Xs,3,1, Pros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, Xs,3,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, Xs,3,k, Ps,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, Xs,3,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T. The log-likelihood ratios are output from a log-likelihood ratio generator 2522. The decoder 2523 performs decoding for an LDPC code according to the parity check matrix Hpro for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). For example, the decoding may be decoding disclosed in Non-Patent Literature 4, Non-Patent Literature 6, Non-Patent Literature 7, Non-Patent Literature 8, etc., i.e., simple BP decoding such as min-sum decoding, offset BP decoding, or Normalized BP decoding, or Belief Propagation (BP) decoding in which scheduling is performed with respect to the row operations (Horizontal operations) and the column operations (Vertical operations) such as Shuffled BP decoding or Layered BP decoding. The decoding may also be decoding such as bit-flipping decoding disclosed in Non-Patent Literature 17, for example. The decoder 2523 obtains an estimation transmission sequence (estimation encoded sequence) (reception sequence) of block s through the decoding, and outputs the estimation transmission sequence.

[1850] In the above, explanation is provided on operations of the encoder and the decoder in a communication system as one example. Alternatively, the encoder and the decoder may be used in technical fields related to storages, memories, etc.

[1851] The following describes a specific example of a configuration of a parity check matrix for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1852] When denoting the parity check matrix for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as Hpro as described above, the number of columns of Hpro can be expressed as 5×2×m×z (where z is a natural number). (Note that m denotes a time-varying period of the LDPC-CC of coding rate 3/5 that is based on a parity check polynomial, which serves as the basis.)

[1853] Accordingly, as already described above, a transmission sequence (encoded sequence (codeword)) vs composed of a 5×2×m×z number of bits in block s of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as Vs=(Xs,1,1, Xs,2,1, Xs,3,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, Xs,3,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, Xs,3,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, Xs,3,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T (where k=1, 2, ..., 2×m×z-1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×z)), and Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes).

[1854] Xs,j,k (where j is an integer no smaller than one and no greater than three) is a bit of information Xj, Ppros,1,k is a bit of parity P1 of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and Ppros,2,k is a bit of parity P2 of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[1855] Further, λpro,s,k=(Xs,1,k, Xs,2,k, Xs,3,k, Ppros,1,k, PPros,2,k) holds true.

[1856] In addition, the number of rows in the parity check matrix Hpro for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is 4×m×z.

[1857] Note that the method of configuring parity check polynomials satisfying zero for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) has already been described above.

[1858] In the above, description has been provided of a parity check matrix Hpro for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), whose transmission sequence (encoded sequence (codeword)) vs of block s is vs=(Xs,1,1, Xs,2,1, Xs,3,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, Xs,3,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, Xs,3,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, Xs,3,2×m×z, PPros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λprο,s,2, ..., λpro,s,2×m×z)T and for which Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes). The following provides description of a configuration of a parity check matrix Hpro_m for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), for which Hpro_mus=0 holds true (here, Hpro_mus=0 indicates that all elements of the vector Hpro_mus are zeroes) when expressing a transmission sequence (encoded sequence (codeword)) us of block s as us=(Xs,1,1, Xs,1,2, ..., Xs,1,2×m×z-1, Xs,1,2×m×z, Xs,2,1, Xs,2,2, ..., Xs,2×m×z-1,Xs,2,2×m×z, Xs,3,1, Xs,3,2, ..., Xs,3,2×m×z-1, Xs,3,2×m×z, Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z, Ppros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, Ppros,2,2×m×z)T=(ΛX1,s, ΛX2,s, ΛX3,s, Λprol,s, Λpro2,s)T.

[1859] Note that ΛXf,s (where f is an integer no smaller than one and no greater than three) satisfies ΛXf,s=(Xs,f,1, Xs,f,2, Xs,f,3, ..., Xs,f,2×m×z-2, Xs,f,2×m×z-1, Xs,f,2×m×z) (ΛXf,s is a vector having one row and 2×m×z columns), and Λprol,s and Λpro2,s satisfy Λprol,s=(Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z) andΛpro2,s=(Ppros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, Ppros,2,2×m×z), respectively (Λpro1,s and Λpro2,s are both vectors having one row and 2×m×z columns).

[1860] Here, the number of bits of information X1 included in one block is 2×m×z, the number of bits of information X2 included in one block is 2×m×z, the number of bits of information X3 included in one block is 2×m×z, the number of bits of parity bits P1 included in one block is 2×m×z, and the number of bits of parity bits P2 included in one block is 2×m×z. Accordingly, the parity check matrix Hpro_m for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as Hpro_m=[Hx,1, Hx,2, Hx,3, Hp1, Hp2, as illustrated in FIG. 74. Since a transmission sequence (encoded sequence (codeword)) us of block s is us=(Xs,1,1, Xs,1,2, ..., Xs,1,2×m×z-1, Xs,1,2×m×z, Xs,2,1, Xs,2,2, ..., Xs,2,2×m×z-1, Xs,2,2×m×z, Xs,3,1, Xs,3,2, ..., Xs,3,2×m×z-1, Xs,3,2×m×z, Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z, Ppros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, Ppros,2,2×m×z)T=(ΛX1,s, ΛX2,s, ΛX3,s, Λpro1,s, Λpro2,s)T, Hx,1 is a partial matrix related to information X1, Hx,2 is a partial matrix related to information X2, Hx,3 is a partial matrix related to information X3, Hp1 is a partial matrix related to parity P1, and Hp2 is a partial matrix related to parity P2. As illustrated in FIG. 74, the parity check matrix Hpro_m has 4×m×z rows and 5×2×m×z columns, the partial matrix Hx,1 related to information X1 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,2 related to information X2 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,3 related to information X3 has 4×m×z rows and 2×m×z columns, the partial matrix Hp1 related to parity P1 has 4×m×z rows and 2×m×z columns, and the partial matrix Hp2 related to parity P2 has 4×m×z rows and 2×m×z columns.

[1861] The transmission sequence (encoded sequence (codeword)) us composed of a 5×2×m×z number of bits in block s of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is us=(Xs,1,1, Xs,1,2, ..., Xs,1,2×m×z-1, Xs,1,2×m×z, Xs,2,1, Xs,2,2, ..., 0 Xs,2,2×m×z-1, Xs,2,2×m×z, Xs,3,1, Xs,3,2, ..., Xs,3,2×m×z-1, Xs,3,2×m×z, Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, PproXs,1,2×m×z, PPros,2,1, PPros,2,2, ..., Ppros,2,2×m×z-1, Ppros,2,2×m×z)T=(ΛX1,s, ΛX2,s, ΛX3,s, Λpro1,s, Λpro2,s)T, and the number of parity check polynomials satisfying zero necessary for obtaining this transmission sequence is 4×m×z.

[1862] Here, when arranging such 2×(2×m)×z number of parity check polynomials satisfying zero in order, a parity check polynomial satisfying zero appearing eth is referred to in the following as an "eth parity check polynomial satisfying zero" (where e is an integer no smaller than zero and no greater than 2×(2×m)×z-1).

[1863] As such, the parity check polynomials satisfying zero are arranged in the following order:

zeroth: zeroth parity check polynomial satisfying zero;

first: first parity check polynomial satisfying zero;

second: second parity check polynomial satisfying zero;

eth: eth parity check polynomial satisfying zero;

2×(2×m)×z-2th: 2×(2×m)×z-2th parity check polynomial satisfying zero; and

2×(2×m)×z-1th: 2×(2×m)×z-1th parity check polynomial satisfying zero.



[1864] Accordingly, the transmission sequence (encoded sequence (codeword)) us of block s of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is obtained.

[1865] Accordingly, in the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the second parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the third parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression;

the 2×(2m)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression;

the 2×(2m+1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; first expression;

the 2×(2m+1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×(2m+2)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the 2×(2m+2)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression; and

the 2×(2m)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression.



[1866] That is,
the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;
the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;
the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i- 1)%2m); first expression; and
the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).

[1867] In the present embodiment (in fact, commonly applying to the entirety of the present disclosure), % means a modulo, and for example, α%q represents a remainder after dividing α by q (where α is an integer no smaller than zero, and q is a natural number).

[1868] The following describes details of the configuration of the parity check matrix Hpro_m for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) based on what has been described above.

[1869] The parity check matrix Hpro_m for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) has 4×m×z rows and 5×2×m×z columns.

[1870] Accordingly, the parity check matrix Hpro_m for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) has rows one through 4×m×z, and columns one through 5×2×m×z.

[1871] Here, the topmost row of the parity check matrix Hpro_m is considered as the first row. Further, row number is incremented by one each time moving to a lower row. Accordingly, the topmost row is considered as the first row, the row immediately below the first row is considered as the second row, and the subsequent rows are considered as the third row, the fourth row, and so on.

[1872] Further, the leftmost column of the parity check matrix Hpro_m is considered as the first column. Further, column number is incremented by one each time moving to a rightward column. Accordingly, the leftmost column is considered as the first column, the column immediately to the right of the first column is considered as the second column, and the subsequent columns are considered as the third column, the fourth column, and so on.

[1873] In the parity check matrix Hpro_m, the partial matrix Hx,1 related to information X1 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,1 related to information X1 is denoted as Hx,1,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[1874] Similarly, in the parity check matrix Hpro_m, the partial matrix Hx,2 related to information X2 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,2 related to information X2 is denoted as Hx,2,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[1875] Further, in the parity check matrix Hpro_m, the partial matrix Hx,3 related to information X3 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,3 related to information X3 is denoted as Hx,3,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[1876] Further, in the parity check matrix Hpro_m, the partial matrix Hp,1 related to parity P1 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hp,1 related to parity P1 is denoted as Hp1,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[1877] Similarly, in the parity check matrix Hpro_m, the partial matrix Hp,2 related to parity P2 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hp,2 related to parity P2 is denoted as Hp2,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[1878] The following provides detailed description of the configuration of Hx,1,comp[u][v], Hx,2,comp[u][v], Hx,3,comp[u][v], Hp1,comp[u][v], and Hp2,comp[u][v].

[1879] As already described above, in the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the second parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the third parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression;

the 2×(2m)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression;

the 2×(2m+1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; first expression;

the 2×(2m+1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×(2m+2)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the 2×(2m+2)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression; and

the 2×(2m)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression.



[1880] That is,
the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;
the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;
the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i- 1)%2m); first expression; and
the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).

[1881] Further, a vector composed of row e+1 of the parity check matrix Hpro_m corresponds to the eth parity check polynomial satisfying zero.

[1882] Accordingly,
a vector composed of row one of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;
a vector composed of row two of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0; second expression;
a vector composed of row 2×g-1 of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); first expression; and
a vector composed of row 2×g of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); second expression (where g is an integer no smaller than two and no greater than 2×m×z).

[1883] Hx,1,comp[u][v], Hx,2,comp[u][v], Hx,3,comp[u][v], Hp1,comp[u][v], and Hp2,comp[u][v], can be expressed according to the relationship described above.

[1884] First, description is provided of the configuration of Hx,1,comp[u][v], Hx,2,comp[u][v], Hx,3,comp[u][v], Hp1,comp[u][v], and Hp2,comp[u][v] for row one of the parity check matrix Hpro_m, or that is, for u=1.

[1885] The vector composed of row one of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0'; first expression provided by expression 173. Accordingly, Hx,1,comp[1][v], can be expressed as follows.
[Math. 309]



[1886] The following holds true for Hx,Ω,comp[1][v], where Ω is an integer no smaller than two and no greater than three.
[Math. 310]



[1887] Further, Hp1,comp[1][v] can be expressed as follows.
[Math. 311]



[1888] Further, Hp2,comp[1][v] can be expressed as follows.
[Math. 312]



[1889] The vector composed of row two of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0; second expression. As described above, a parity check polynomial satisfying zero of #0; second expression is expressed by either expression (165-2-1) or expression (165-2-2).

[1890] Accordingly, Hx,1,comp[2][v] can be expressed as follows.
  1. <1> When a parity check polynomial satisfying zero of #0; second expression is expressed as provided in expression (165-2-1):
    Hx,1,comp[2][v], is expressed as follows.
    [Math. 313]




    The following holds true for Hx,w,comp[2][v], where w is an integer no smaller than two and no greater than three.
    [Math. 314]


    Further, Hp1,comp[2][v] can be expressed as follows.
    [Math. 315]


    Further, Hp2,comp[2][v] can be expressed as follows.
    [Math. 316]

  2. <2> When a parity check polynomial satisfying zero of #0; second expression is expressed as provided in expression (165-2-2):
    Hx,1,comp[2][v] is expressed as follows.
    [Math. 317]



[1891] The following holds true for Hx,w,comp[2][v], where w is an integer no smaller than two and no greater than three.
[Math. 318]



[1892] Further, Hp1,comp[2][v] can be expressed as follows.
[Math. 319]



[1893] Further, Hp2,comp[2][v] can be expressed as follows.
[Math. 320]





[1894] As already described above,
the vector composed of row 2×g-1 of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); first expression; and
the vector composed of row 2×g of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); second expression (where g is an integer no smaller than two and no greater than 2×m×z).

[1895] Accordingly, when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), a vector of row 2×(2×f-1)-1 of the parity check matrix Hpro_m for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); first expression, or that is, by using a parity check polynomial satisfying zero provided by expression (165-1-1) or expression (165-1-2).

[1896] Further, a vector of row 2×(2×f-1) of the parity check matrix Hpro_m for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); second expression, or that is, by using a parity check polynomial satisfying zero provided by expression (165-2-1) or expression (165-2-2).

[1897] Further, when g=2×f (where f is an integer no smaller than one and no greater than m×z), a vector of row 2×(2×f)-1 of the parity check matrix Hpro_m for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f)-1)%2m); first expression, or that is, by using a parity check polynomial satisfying zero provided by expression (166-1-1) or expression (166-1-2).

[1898] Further, a vector of row 2×(2×f) of the parity check matrix Hpro_m for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f)-1)%2m); second expression, or that is, by using a parity check polynomial satisfying zero provided by expression (166-2-1) or expression (166-2-2).

[1899] Accordingly, (1) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (165-1-1), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (165-1-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[1900] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f-1)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f-1)-1][v], Hx,3,comp[2×g-1][v]=Hx,3,comp[2×(2×f-1)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f-1)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[1901] First, the following holds true for Hx,1,comp[2×(2×f-1)-1][v].
[Math. 321]



[1902] The following holds true for Hx,Ω,comp[2×(2×f-1)-1][v]. In the following, Ω is an integer no smaller than two and no greater than three, and y is an integer no smaller than R#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 322]





[1903] Further, the following holds true for Hp1,comp[2×(2×f-1)-1][v].
[Math. 323]



[1904] Further, the following holds true for Hp2,comp[2×(2×f-1)-1][v].
[Math. 324]



[1905] Further, (2) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (165-1-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (165-1-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[1906] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f-1)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f-1)[v], Hx,3,comp[2×g-1][v]=Hx,3,comp[2×(2×f-1)[v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f-1)[v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f-1)[v], in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[1907] First, the following holds true for Hx,1,comp[2×(2×f-1)-1][v]
[Math. 325]



[1908] Further, the following holds true for Hx,Ω,comp[2×(2×f-1)-1][v]. In the following, Ω is an integer no smaller than two and no greater than three, and y is an integer no smaller than R#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 326]



[1909] Further, the following holds true for Hp1,comp[2×(2×f-1)-1][v].
[Math. 327]



[1910] Further, the following holds true for Hp2,comp[2×(2×f-1)-1][v].
[Math. 328]



[1911] Further, (3) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (165-2-1), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (165-2-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[1912] Accordingly, components Hx,1,comp[2×g][v]=Hx,1,comp[2×(2×f-1)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2×f-1)] [v], Hx,3,comp[2×g][v]=Hx,3,comp[2×(2×f-1)][v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f-1)][v], and Hp2,comp[2×g][v]=Hp2,comp[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[1913] First, the following holds true for Hx,1,comp[2×(2×f-1)][v]. In the following, y is an integer no smaller than R#(2c),1+1 and no greater than r#(2c),1.
[Math. 329]





[1914] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f-1)-1][v]. In the following, w is an integer no smaller than two and no greater than three.
[Math. 330]



[1915] Further, the following holds true for Hp1,comp[2×(2×f-1)-1][v].
[Math. 331]





[1916] Further, the following holds true for Hp2,comp[2×(2×f-1)-1][v].
[Math. 332]



[1917] Further, (4) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (165-2-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (165-2-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[1918] Accordingly, components Hx,1,comp[2×g][v]=Hx,1,comp[2×(2×f-1)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2×f-1)][v], Hx,3,comp[2×g][v]=Hx,3,comp[2×(2×f-1)][v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f-1)[v], and Hp2,comp[2×g][v]=Hp2,comp[2×(2×f-1)[v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[1919] First, the following holds true for Hx,1,comp[2×(2×f-1)][v]. In the following, y is an integer no smaller than R#(2c),1+1 and no greater than r#(2c),1.
[Math. 333]



[1920] Further, the following holds true for Hx,w,comp[2×(2×f-1)][v]. In the following, w is an integer no smaller than two and no greater than three.
[Math. 334]



[1921] Further, the following holds true for Hp1,comp[2×(2×f-1)][v].
[Math. 335]



[1922] Further, the following holds true for Hp2,comp[2×(2×f-1)][v].
[Math. 336]





[1923] Further, (5) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (166-1-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (166-1-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[1924] Accordingly, components Hx,1,comp[2×g-1][v=Hx,1,comp[2×(2×f)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[1925] First, the following holds true for Hx,1,comp[2×(2×f)-1][v]. In the following, y is an integer no smaller than R#(2d+1),1+1 and no greater than r#(2d+1),1.
[Math. 337]



[1926] Further, the following holds true for Hx,w,comp[2×(2×f)-1][v]. In the following, w is an integer no smaller than two and no greater than three.
[Math. 338]





[1927] Further, the following holds true for Hp1,comp[2×(2×f)-1][v].
[Math. 339]



[1928] Further, the following holds true for Hp2,comp[2×(2×f)-1][v].
[Math. 340]



[1929] Further, (6) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (166-1-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (166-1-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[1930] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f)-1][v], Hx,3,comp[2×g-1][v]=Hx,3,comp[2×(2×f)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f)-1][v], in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[1931] First, the following holds true for Hx,1,comp[2×(2×f)-1][v]. In the following, y is an integer no smaller than R#(2d+i),1+1 and no greater than r#(2d+i),1.
[Math. 341]



[1932] Further, the following holds true for Hx,w,comp[2×(2×f)-1][v]. In the following, w is an integer no smaller than two and no greater than three.
[Math. 342]





[1933] Further, the following holds true for Hp1,comp[2×(2×f)-1][v].
[Math. 343]



[1934] Further, the following holds true for Hp2,comp[2×(2×f)-1[v].

[1935] [Math. 344]



[1936] Further, (7) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (166-2-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (166-2-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[1937] Accordingly, components Hx,1,comp[2×g][v]=Hx,1,comp[2×(2× f)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2×f)][v], Hx,3,comp[2×g][v]=Hx,3comp[2×(2×f)][v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f)][v], and Hp2,comp[2×g][v]=Hp2,comp[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[1938] The following holds true for Hx,1,comp[2×(2×f)][v].
[Math. 345]



[1939] The following holds true for Hx,Ω,comp[2×(2×f)][v]. In the following, Ω is an integer no smaller than two and no greater than three, and y is an integer no smaller than R#(2d+1),Ω+1 and no greater than r#(2d+1),Ω.
[Math. 346]



[1940] Further, the following holds true for Hp1,comp[2×(2×f)][v].
[Math. 347]





[1941] Further, the following holds true for Hp2,comp[2×(2×f)][v].
[Math. 348]



[1942] Further, (8) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (166-2-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (166-2-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[1943] Accordingly, components Hx,1,comp[2×g][v]=Hx,1,comp[2×(2×f)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2×f)][v], Hx,3,comp[2×g][v]=Hx,3comp[2×(2×f)][v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f)][v], and Hp2,comp[2×g][v]=Hp2,comp[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[1944] The following holds true for Hx,1,comp[2×(2×f)][v].
[Math. 349]





[1945] The following holds true for Hx,2,comp[2×(2×f)][v]. In the following, Ω is an integer no smaller than two and no greater than three, and y is an integer no smaller than F#(2d+1),Ω+1 and no greater than r#(2d+1),Ω.
[Math. 350]



[1946] Further, the following holds true for Hp1,comp[2×(2×f)][v].
[Math. 351]



[1947] Further, the following holds true for Hp2,comp[2×(2×f)][v].
[Math. 352]





[1948] An LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated as described above, and the code so generated achieves high error correction capability.

[1949] In the above, parity check polynomials satisfying zero for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) are set as follows:

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression; and

the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).



[1950] Based on this, the following method is conceivable as a configuration where usage of parity check polynomials satisfying zero is limited.

[1951] In this configuration, parity check polynomials satisfying zero for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) are set as follows:

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression provided by expression (165-2-1);

the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression provided by expression (165-1-1) or expression (166-1-1); and

the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression provided by expression (165-2-1) or expression (166-2-1) (where i is an integer no smaller than two and no greater than 2×m×z).



[1952] Accordingly, in the parity check matrix Hpro_m for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the vector composed of row one of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0'; first expression provided by expression 173;

the vector composed of row two of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0; second expression provided by expression (165-2-1);

the vector composed of row 2×g-1 of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); first expression provided by expression (165-1-1) or expression (166-1-1); and

the vector composed of row 2×g of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); second expression provided by expression (165-2-1) or expression (166-2-1) (where g is an integer no smaller than two and no greater than 2×m×z).



[1953] Note that when making such a configuration, the above-described method of configuring the parity check matrix Hpro for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is applicable.

[1954] Such a method also enables generating a code with high error correction capability.

(Embodiment D5)



[1955] In embodiment D4, description is provided of an LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and a method of configuring a parity check matrix for the code.

[1956] With regards to parity check matrices for low density parity check (block) codes, one example of which is the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), a parity check matrix equivalent to a parity check matrix defined for a given LDPC code can be generated by using the parity check matrix defined for the given LDPC code.

[1957] For example, a parity check matrix equivalent to the parity check matrix Hpro_m described in embodiment D4, which is for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using the parity check matrix Hpro_m.

[1958] The following describes a method of generating a parity check matrix equivalent to a parity check matrix defined for a given LDPC by using the parity check matrix defined for the given LDPC code.

[1959] Note that the method of generating an equivalent parity check matrix described in the present embodiment is not only applicable to the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) described in embodiment D4, but also is widely applicable to LDPC codes in general.

[1960] FIG. 31 illustrates the configuration of a parity check matrix H for an LDPC (block) code of coding rate (N-M)/N (N>M>0). For example, the parity check matrix of FIG. 31 has M rows and N columns. Here, to provide a general description, the parity check matrix H in FIG. 31 is considered to be a parity check matrix for defining an LDPC (block) code #A of coding rate (N-M)/N (N>M>0).

[1961] In FIG. 31, a transmission sequence (codeword) for block j is vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) (for systematic codes, Yj,k (where k is an integer no smaller than one and no greater than N) is information X or parity P (parity Ppro)).

[1962] Here, Hvj=0 holds true (where the zero in Hvj=0 indicates that all elements of the vector Hvj are zeroes. That is, row k of the vector Hvj has a value of zero for all k (where k is an integer no smaller than one and no greater than M)).

[1963] Then, an element of row k (where k is an integer no smaller than one and no greater than N) of the transmission sequence vj of block j (in FIG. 31, an element of column k in the transpose matrix vjT of the transmission sequence vj) is Yj,k, and a vector obtained by extracting column k of the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) can be expressed as ck, as illustrated in FIG. 31. Here, the parity check matrix H is expressed as follows.
[Math. 353]



[1964] FIG. 32 illustrates a configuration when interleaving is applied to the transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j. In FIG. 32, an encoding section 3202 receives information 3201 as input, performs encoding thereon, and outputs encoded data 3203. For example, when encoding the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), the encoder 3202 receives information in block j as input, performs encoding thereon based on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), and outputs the transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j.

[1965] Then, an accumulation and reordering section (interleaving section) 3204 receives the encoded data 3203 as input, accumulates the encoded data 3203, performs reordering thereon, and outputs interleaved data 3205. Accordingly, the accumulation and reordering section (interleaving section) 3204 receives the transmission sequence vj=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N)T of block j as input, and outputs a transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T, which is illustrated in FIG. 32, as a result of reordering being performed on the elements of the transmission sequence vj (v'j being an example). Here, as discussed above, the transmission sequence v'j is obtained by reordering the elements of the transmission sequence vj of block j. Accordingly, v'j is a vector having one row and n columns, and the N elements of v'j are such that one each of the terms Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N is present.

[1966] Here, an encoding section 3207 as shown in FIG. 32 having the functions of the encoding section 3202 and the accumulation and reordering section (interleaving section) 3204 is considered. Accordingly, the encoding section 3207 receives the information 3201 as input, performs encoding thereon, and outputs the encoded data 3203. For example, the encoding section 3207 receives information in block j as input, and as shown in FIG. 32, outputs the transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T. In the following, explanation is provided of a parity check matrix H' for the LDPC (block) code of coding rate (N-M)/N (N>M>0) corresponding to the encoding section 3207 (i.e., a parity check matrix H' that is equivalent to the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0)), while referring to Fig. 33. (Needless to say, the parity check matrix H' is a parity check matrix for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0).)

[1967] FIG. 33 shows a configuration of the parity check matrix H', which is a parity check matrix equivalent to the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), when the transmission sequence (codeword) is v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T. Here, an element of row one of the transmission sequence v'j of block j (an element of column one in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) is Yj,32. Accordingly, a vector obtained by extracting column one of the parity check matrix H', when using the above-described vector ck (k=1, 2, 3, ..., N-2, N-1, N), is c32. Similarly, an element of row two of the transmission sequence v'j of block j (an element of column two in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) is Yj,99. Accordingly, a vector obtained by extracting column two of the parity check matrix H' is c99. Further, as shown in FIG. 33, a vector obtained by extracting column three of the parity check matrix H' is c23, a vector obtained by extracting column N-2 of the parity check matrix H' is c234, a vector obtained by extracting column N-1 of the parity check matrix H' is c3, and a vector obtained by extracting column N of the parity check matrix H' is c43.

[1968] That is, when denoting an element of row i of the transmission sequence v'j of block j (an element of column i in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) as Yj,g (where g=1, 2, 3, ..., N-1, N-1, N), then a vector obtained by extracting column i of the parity check matrix H' is cg, when using the vector ck described above.

[1969] Accordingly, the parity check matrix H' for transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T is expressed as follows.
[Math. 354]



[1970] When denoting an element of row i of the transmission sequence v'j of block j (an element of column i in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) as Yj,g (where g=1, 2, 3, ..., N-1, N-1, N), a vector obtained by extracting column i of the parity check matrix H' is cg, when using the vector ck described above. When the above is followed to create a parity check matrix, then a parity check matrix for the transmission sequence v'j of block j can be obtained with no limitation to the above-given example.

[1971] Accordingly, when interleaving is applied to the transmission sequence (codeword) of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), a matrix for the interleaved transmission sequence is obtained by performing reordering of columns (column permutation) as described above on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0).

[1972] As such, it naturally follows that the transmission sequence (codeword) (vj) obtained by reverting the interleaved transmission sequence (codeword) (v'j) to its original order is the transmission sequence (codeword) of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Accordingly, by reverting the interleaved transmission sequence (codeword) (v'j) and a parity check matrix H' corresponding to the interleaved transmission sequence (codeword) (v'j) to their respective orders, the transmission sequence vj and a parity check matrix corresponding to the transmission sequence vj can be obtained, respectively. Further, the parity check matrix obtained by performing the reordering as described above is the parity check matrix H in FIG. 31, description of which has been provided above.

[1973] FIG. 34 illustrates an example of a decoding-related configuration of a receiving device, when encoding of FIG. 32 has been performed. The transmission sequence obtained when the encoding of FIG. 32 is performed undergoes processing such as mapping in accordance with a modulation scheme, frequency conversion, and modulated signal amplification, whereby a modulated signal is obtained. A transmitting device transmits the modulated signal. The receiving device then receives the modulated signal transmitted by the transmitting device to obtain a received signal. A log-likelihood ratio calculation section 3400 illustrated in FIG. 34 takes the received signal as input, calculates a log-likelihood ratio for each bit of the codeword, and outputs a log-likelihood ratio signal 3401.

[1974] For example, assume that the transmitting device transmits a transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T of block j. Then, the log-likelihood ratio calculation section 3400 calculates, from the received signal, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, and outputs the log-likelihood ratios.

[1975] An accumulation and reordering section (deinterleaving section) 3402 receives the log-likelihood ratio signal 3401 as input, performs accumulation and reordering thereon, and outputs a deinterleaved log-likelihood ratio signal 3403.

[1976] For example, the accumulation and reordering section (deinterleaving section) 3402 receives, as input, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, performs reordering, and outputs the log-likelihood ratios in the order of: the log-likelihood ratio for Yj,1, the log-likelihood ratio for Yj,2, the log-likelihood ratio for Yj,3, ..., the log-likelihood ratio for Yj,N-2, the log-likelihood ratio for Yj,N-1, and the log-likelihood ratio for Yj,N in the stated order.

[1977] A decoder 3404 receives the deinterleaved log-likelihood ratio signal 3403 as input, performs belief propagation (BP) decoding as disclosed in Non-Patent Literature 6 to 8, such as sum-product decoding, min-sum decoding, offset BP decoding, normalized BP decoding, shuffled BP decoding, and layered BP decoding in which scheduling is performed, based on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 31, and thereby obtains an estimation sequence 3405 (note that decoding schemes other than belief propagation decoding may be used).

[1978] For example, the decoder 3404 receives, as input, the log-likelihood ratio for Yj,1, the log-likelihood ratio for Yj,2, the log-likelihood ratio for Yj,3, ..., the log-likelihood ratio for Yj,N-2, the log-likelihood ratio for Yj,N-1, and the log-likelihood ratio for Yj,N in the stated order, performs belief propagation decoding based on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 31, and obtains the estimation sequence (note that decoding schemes other than belief propagation decoding may be used).

[1979] The following describes a decoding-related configuration that differs from that described above. The decoding-related configuration described in the following differs from the decoding-related configuration described above in that the accumulation and reordering section (deinterleaving section) 3402 is not included. The operations of the log-likelihood ratio calculation section 3400 are similar to those described above, and thus, explanation thereof is omitted in the following.

[1980] For example, assume that the transmitting device transmits a transmission sequence (codeword) v'j =(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T of block j. Then, the log-likelihood ratio calculation section 3400 calculates, from the received signal, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, and outputs the log-likelihood ratios (corresponding to 3406 in FIG. 34).

[1981] A decoder 3407 receives the log-likelihood ratio signal 3406 for each bit as input, performs belief propagation (BP) decoding as disclosed in Non-Patent Literature 6 to 8, such as sum-product decoding, min-sum decoding, offset BP decoding, normalized BP decoding, shuffled BP decoding, and layered BP decoding in which scheduling is performed, based on the parity check matrix H' for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 33, and thereby obtains an estimation sequence 3409 (note that decoding schemes other than belief propagation decoding may be used).

[1982] For example, the decoder 3407 receives, as input, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43 in the stated order, performs belief propagation decoding based on the parity check matrix H' for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 33, and obtains the estimation sequence (note that decoding schemes other than belief propagation decoding may be used).

[1983] As explained above, even when the transmitted data is reordered due to the transmitting device interleaving the transmission sequence vj=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N)T of block j, the receiving device is able to obtain the estimation sequence by using a parity check matrix corresponding to the reordered transmitted data.

[1984] Accordingly, when interleaving is applied to the transmission sequence (codeword) of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), a parity check matrix for the interleaved transmission sequence (codeword) is obtained by performing reordering of columns (i.e., column permutation) as described above on the parity check matrix for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). As such, the receiving device is able to perform belief propagation decoding and thereby obtain an estimation sequence without performing interleaving on the log-likelihood ratio for each acquired bit.

[1985] Note that in the above, explanation is provided of the relation between interleaving applied to a transmission sequence and a parity check matrix. In the following, explanation is provided of reordering of rows (row permutation) performed on a parity check matrix.

[1986] FIG. 35 illustrates a configuration of a parity check matrix H corresponding to a transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). For example, the parity check matrix H of FIG. 35 is a matrix having M rows and N columns. (for systematic codes, Yj,k (where k is an integer no smaller than one and no greater than N) is information X or parity P (parity Ppro), and is composed of (N-M) information bits and M parity bits). Here, Hvj = 0 holds true. (Here, the zero in Hvj = 0 indicates that all elements of the vector Hvj are zeroes. That is, row k of the vector Hvj has a value of zero for all k (where k is an integer no smaller than one and no greater than M.)

[1987] Further, a vector obtained by extracting column k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 35 is denoted as zk. Then, the parity check matrix H for the LDPC (block) code is expressed as follows.
[Math. 355]



[1988] Next, a parity check matrix obtained by performing reordering of rows (row permutation) on the parity check matrix H of FIG. 35 is considered.

[1989] FIG. 36 shows an example of a parity check matrix H' obtained by performing reordering of rows (row permutation) on the parity check matrix H of FIG. 35. The parity check matrix H', similar to the parity check matrix shown in FIG. 35, is a parity check matrix corresponding to the transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0).

[1990] The parity check matrix H' of FIG. 36 is composed of vectors zk obtained by extracting row k (where k is an integer no smaller one and no greater than M) of the parity check matrix H of FIG. 35. For example, in the parity check matrix H', the first row is composed of vector z130, the second row is composed of vector z24, the third row is composed of vector z45, ..., the (M-2)th row is composed of vector z33, the (M-1)th row is composed of vector z9, and the Mth row is composed of vector z3. Note that each of the M row-vectors obtained by extracting row k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H' is such that one each of z1, z2, z3, ... zM-2, zM-1, and zM is present.

[1991] Here, the parity check matrix H' for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) is expressed as follows.
[Math. 356]



[1992] Further, H'vj = 0 holds true. (Here, the zero in H'vj = 0 indicates that all elements of the vector H'vj are zeroes. That is, row k of the vector H'vj has a value of zero for all k (where k is an integer no smaller than one and no greater than M.)

[1993] That is, for the transmission sequence vjT of block j, a vector obtained by extracting row i of the parity check matrix H' in FIG. 36 is expressed as ck (where k is an integer no smaller than one and no greater than M), and each of the M row vectors obtained by extracting row k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H' in FIG. 36 is such that one each of z1, z2, z3, ... zM-2, zM-1, and zM is present.

[1994] As described above, for the transmission sequence vjT of block j, a vector obtained by extracting row i of the parity check matrix H' in FIG. 36 is expressed as ck (where k is an integer no smaller than one and no greater than M), and each of the M row vectors obtained by extracting row k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H' in FIG. 36 is such that one each of z1, z2, z3, ... zM-2, zM-1, and zM is present. Note that, when the above is followed to create a parity check matrix, then a parity check matrix for the transmission sequence parity vj of block j can be obtained with no limitation to the above-given example.

[1995] Accordingly, even when the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) is being used, it does not necessarily follow that a transmitting device and a receiving device are using the parity check matrix H. As such, a transmitting device and a receiving device may use as a parity check matrix, for example, a matrix obtained by performing reordering of columns (column permutation) as described above on the parity check matrix H or a matrix obtained by performing reordering of rows (row permutation) on the parity check matrix H.

[1996] In addition, a matrix obtained by performing both reordering of columns (column permutation) and reordering of rows (row permutation) as described above on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) may be used as a parity check matrix.

[1997] In such a case, a parity check matrix H1 is obtained by performing reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H2 is obtained by performing reordering of rows (row permutation) on the parity check matrix H1 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). A transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H2 so obtained.

[1998] Also, a parity check matrix H1,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H2,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix H1,1 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36).

[1999] Further, a parity check matrix H1,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H2,1. Finally, a parity check matrix H2,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H1,2.

[2000] As described above, a parity check matrix H2,s may be obtained by repetitively performing reordering of columns (column permutation) and reordering of rows (row permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H1,k is obtained by performing a kth (where k is an integer no smaller than two and no greater than s) reordering of columns (column permutation) on a parity check matrix H2,k-1. Then, a parity check matrix H2,k is obtained by performing a kth reordering of rows (row permutation) on the parity check matrix H1,k. Note that in the first instance, a parity check matrix H1,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H2,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H1,1.

[2001] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H2,s.

[2002] In an alternative method, a parity check matrix H3 is obtained by performing reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H4 is obtained by performing reordering of columns (column permutation) on the parity check matrix H3 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H4 so obtained.

[2003] Also, a parity check matrix H3,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H4,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix H3,1 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33).

[2004] Then, a parity check matrix H3,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H4,1. Finally, a parity check matrix H4,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H3,2.

[2005] As described above, a parity check matrix H4,s may be obtained by repetitively performing reordering of rows (row permutation) and reordering of columns (column permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H3,k is obtained by performing a kth (where k is an integer no smaller two and no greater than s) reordering of rows (row permutation) on a parity check matrix H4,k-1. Then, a parity check matrix H4,k is obtained by performing a kth reordering of columns (column permutation) on the parity check matrix H3,k. Note that in the first instance, a parity check matrix H3,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H4,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H3,1.

[2006] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H4,s.

[2007] Here, note that by performing reordering of rows (row permutation) and reordering of columns (column permutation), the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) can be obtained from each of the parity check matrix H2, the parity check matrix H2,s, the parity check matrix H4, and the parity check matrix H4,s,.

[2008] Similarly, a matrix obtained by performing both reordering of columns (column permutation) as described above and reordering of rows (row permutation) as described above on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) may be used as a parity check matrix.

[2009] In such a case, a parity check matrix H5 is obtained by performing reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H6 is obtained by performing reordering of rows (row permutation) on the parity check matrix H5 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). A transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H6 so obtained.

[2010] Also, a parity check matrix H5,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H6,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix H5,1 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36).

[2011] Further, a parity check matrix H5,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H6,1. Finally, a parity check matrix H6,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H5,2.

[2012] As described above, a parity check matrix H6,s may be obtained by repetitively performing reordering of columns (column permutation) and reordering of rows (row permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H5,k is obtained by performing a kth (where k is an integer no smaller than two and no greater than s) reordering of columns (column permutation) on a parity check matrix H6,k-1. Then, a parity check matrix H6,k is obtained by performing a kth reordering of rows (row permutation) on the parity check matrix H5,k. Note that in the first instance, a parity check matrix H5,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H6,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H5,1.

[2013] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H6,s.

[2014] In an alternative method, a parity check matrix H7 is obtained by performing reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H8 is obtained by performing reordering of columns (column permutation) on the parity check matrix H7 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H8 so obtained.

[2015] Also, a parity check matrix H7,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H8,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix H7,1 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33).

[2016] Then, a parity check matrix H7,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H8,1. Finally, a parity check matrix H8,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H7,2.

[2017] As described above, a parity check matrix H8,s may be obtained by repetitively performing reordering of rows (row permutation) and reordering of columns (column permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H7,k is obtained by performing a kth (where k is an integer no smaller two and no greater than s) reordering of rows (row permutation) on a parity check matrix H8,k-1. Then, a parity check matrix H8,k is obtained by performing a kth reordering of columns (column permutation) on the parity check matrix H7,k. Note that in the first instance, a parity check matrix H7,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H8,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H7,1.

[2018] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H8,s.

[2019] Here, note that by performing reordering of rows (row permutation) and reordering of columns (column permutation), the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) can be obtained from each of the parity check matrix H6, the parity check matrix H6,s, the parity check matrix H8, and the parity check matrix H8,s,.

[2020] In the present embodiment, description is provided of a method of generating a parity check matrix equivalent to a parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) by performing reordering of rows (row permutation) and/or reordering of columns (column permutation) with respect to the parity check matrix H. Further, description is provided of a method of applying the equivalent parity check matrix in, for example, a communication/broadcast system using an encoder and a decoder using the equivalent parity check matrix. Note that the error correction code described herein may be applied to various fields, including but not limited to communication/broadcast systems.

(Embodiment D6)



[2021] In the present embodiment, description is provided of a device that uses the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), description of which is provided in embodiment D4.

[2022] As one example, description is provided of a case where the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is applied to a communication device.

[2023] Fig. 22 illustrates the structures of a transmitting device 2200 and a receiving device 2210 in the communication device pertaining to the present embodiment.

[2024] An encoder 2201 receives information to be transmitted as input, and is capable of performing various types of encoding (e.g., various coding rates and various block lengths of block codes (for example, in systematic codes, the sum of the number of information bits and the number of parity bits)). In particular, when receiving a specification to perform encoding by using the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), the encoder 2201 performs encoding by using the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) to calculate parities P1 and P2. Further, the encoder 2201 outputs the information to be transmitted and the parities P1 and P2 as a transmission sequence.

[2025] A modulator 2202 receives the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, performs mapping based on a predetermined modulation scheme (for example, BPSK, QPSK, 16QAM, or 64QAM), and outputs a baseband signal. Further, the modulator 2202 may also receive information other than the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, as input, perform mapping, and output a baseband signal. For example, the modulator 2202 may receive control information as input.

[2026] The transmitting device outputs a transmission signal after performing predetermined signal processing (e.g., signal processing for generation of an OFDM signal, frequency conversion, amplification) with respect to such signals (e.g., baseband signals, pilot signals). The transmitting device may transmit the transmission signal over a wireless transmission path utilizing electromagnetic waves, or over a wired transmission path utilizing a coaxial cable, a power line, an optical cable, or the like.

[2027] The transmission signal is received by the receiving device 2210 after travelling over the transmission path. A receiver 2211 receives a reception signal as input, performs predetermined signal processing (e.g., bandwidth limitation, frequency conversion, signal processing for OFDM, frequency offset estimation, signal detection, channel estimation), and outputs a baseband signal and a channel estimation signal.

[2028] A log-likelihood ratio generation section 2212 receives the baseband signal and the channel estimation signal as input (may receive other signals as input), and for example, calculates and outputs a log-likelihood ratio for each bit (may calculate and output a hard value (hard decision value)).

[2029] A decoder 2213 receives the log-likelihood ratio for each bit as input, performs belief propagation decoding (e.g., sum-product decoding, scheduled sum-product decoding (Layered BP (belief propagation) decoding), min-sum decoding, Normalized BP decoding, offset BP decoding), and outputs an estimation sequence. The decoder 2213 performs the belief propagation decoding based on the parity check matrix for the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[2030] Although description is provided above taking an example where error correction coding is introduced to a communication device, the error correction coding described above is not limited to being introduced to a communication device, and for example, may be introduced to a storage medium (storage). When making such a modification, information that is to be stored to a storage medium (storage) is encoded by using the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and resultant information and parities are stored to the storage medium (storage).

[2031] Further, the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is applicable to any device that requires error correction coding (e.g., a memory, a hard disk).

[2032] Note that when using a block code such as the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) in a device, there as cases where special processing needs to be executed.

[2033] Assume that a block length of the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) used in a device is 10000 bits (6000 information bits, and 4000 parity bits).

[2034] In such a case, the number of information bits necessary for encoding one block is 6000. Meanwhile, there are cases where the number of bits of information input to an encoding section of the device does not reach 6000. For example, assume a case where only 5000 information bits are input to the encoding section.

[2035] Here, it is assumed that the encoding section, in the above-described case, adds 1000 padding bits of information to the 5000 information bits having been input, and performs encoding by using a total of 6000 bits, composed of the 5000 information bits having been input and the 1000 padding bits, to generate 4000 parity bits. Here, assume that all of the 1000 padding bits are known bits. For example, assume that each of the 1000 padding bits is "0".

[2036] A transmitting device may output the 5000 information bits having been input, the 1000 padding bits, and the 4000 parity bits. Alternatively, a transmitting device may output the 5000 information bits having been input and the 4000 parity bits.

[2037] In addition, a transmitting device may perform puncturing with respect to the 5000 information bits having been input and the 4000 parity bits, and thereby output a number of bits smaller than 10000 in total.

[2038] Note that when performing transmission in such a manner, the transmitting device is required to transmit, to a receiving device, information notifying the receiving device that transmission has been performed in such a manner.

[2039] As described above, the LDPC-CC of coding rate 3/5 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), description of which is provided in embodiment D4, is applicable to various devices.

(Embodiment E1)



[2040] The present embodiment describes a method of configuring an LDPC-CC of coding rate 5/7 that is based on a parity check polynomial, as one example of an LDPC-CC not satisfying coding rate (n-1)/n.

[2041] Bits of information bits X1, X2, X3, X4, X5 and parity bits P1, P2, at time point j, are expressed X1,j, X2,j, X3,j, X4,j, X5.j and P1,j, P2,j, respectively.

[2042] A vector uj, at time point j, is expressed uj = (X1j, X2,j, X3,j, X4,j, X5.j, P1,j, P2,j).

[2043] Given a delay operator D, polynomial expressions of the information bits X1, X2, X3, X4, X5 are X1(D), X2(D), X3(D), X4(D), X5(D), and polynomial expressions of the parity bits P1, P2 are P1(D), P2(D).

[2044] Further, consideration is given to an LDPC-CC of coding rate 5/7 and time-varying period 2m that is based on a parity check polynomial.

[2045] The following mathematical expressions are provided as parity check polynomials satisfying zero for an LDPC-CC of coding rate 5/7 and time-varying period 2m that is based on a parity check polynomial.

[2046] First, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1×P2(D).
[Math. 357-1]



[Math. 357-2]







[2047] In expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[2048] In expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2), α#(2i),p,q (where p is an integer no smaller than one and no greater than five, q is an integer no smaller than one and no greater than r#(2i),p (where r#(2i),p is a natural number)) and β#(2i),0 is a natural number, β#(2i),1 is a natural number, β#(2i),2 is an integer no smaller than zero, and β#(2i),3 is a natural number.

[2049] Further, y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for all y and all z satisfying y≠z.)

[2050] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (97-1-1) or expression (97-1-2) is referred to as "#(2i); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (97-2-1) or expression (97-2-2) is referred to as "#(2i); second expression" for realizing a time-varying period 2m.

[2051] Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (97-1-1) or expression (97-1-2) is prepared.

[2052] That is, for i=0, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=0 is prepared.

[2053] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=m-1 is prepared.



[2054] Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (97-2-1) or expression (97-2-2) is prepared.

[2055] That is, for i=0, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=0 is prepared.

[2056] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=m-1 is prepared.



[2057] Similarly, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1×P2(D).
[Math. 358-1]





[Math. 358-2]







[2058] In expressions (98-1-1), (98-1-2), (98-2-1), (98-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[2059] In expressions (98-1-1), (98-1-2), (98-2-1), (98-2-2), α#(2i+1),p,q (where p is an integer no smaller than one and no greater than five, q is an integer no smaller than one and no greater than r#(2i+1),p (where r#(2i+1),p is a natural number)) and β#(2i+1),0 is a natural number, β#(2i+1),1 is a natural number, β#(2i+1),2 is an integer no smaller than zero, and β#(2i+1),3 is a natural number.

[2060] Further, y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and a#(2i+1),p,ya#(2i+1),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for all y and all z satisfying y≠z.)

[2061] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (98-1-1) or expression (98-1-2) is referred to as "#(2i+1); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (98-2-1) or expression (98-2-2) is referred to as "#(2i+1); second expression" for realizing a time-varying period 2m.

[2062] Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (98-1-1) or expression (98-1-2) is prepared.

[2063] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=0 is prepared.

[2064] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=m-1 is prepared.



[2065] Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (98-2-1) or expression (98-2-2) is prepared.

[2066] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=0 is prepared.

[2067] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=m-1 is prepared.



[2068] As such, an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2069] Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (97-1-1) or expression (97-1-2), parity check polynomials satisfying zero provided by expression (97-2-1) or expression (97-2-2), parity check polynomials satisfying zero provided by expression (98-1-1) or expression (98-1-2), and parity check polynomials satisfying zero provided by expression (98-2-1) or expression (98-2-2).

[2070] For example, the time varying period 2×m can be formed by preparing a 4×m number of different parity check polynomials satisfying zero.

[2071] Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

[2072] The following describes the relationship between time point j and expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2), (98-1-1), (98-1-2), (98-2-1), and (98-2-2) (where j is an integer no smaller than zero).

[2073] The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m-1).

[2074] Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i = k in #(2i); first expression and #(2i); second expression, hold true. Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m-1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

[2075] The following describes a method of configuring a parity check matrix for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2076] As already described above, a vector uj at time point j is expressed as uj=(X1,j, X2,j, X3,j, X4,j, X5,j, P1,j, P2,j) (where j is an integer no smaller than zero). In the following, a case where u is a transmission vector is considered. Note that in the following, j is an integer no smaller than one, and thus j differs between the description having been provided above and the description provided in the following. (j is set as such to facilitate understanding of the correspondence between the column numbers and the row numbers of the parity check matrix.)

[2077] Accordingly, u=(u1, u2, u3, ..., uy-1, uy, uy+1, ...)T=(X1,1, X2,1, X3,1, X4,1, X5,1, P1,1, P2,1, X1,2, X2,2, X3,2, X4,2, X5,2, P1,2, P2,2, X1,3, X2,3, X3,3, X4,3, X5,3, P1,3, P2,3, ..., X1,y-1, X2,y-1, X3,y-1, X4,y-1, X5,y-1, P1,y-1, P2,y-1, X1,y, X2,y, X3,y, X4,y,X5,y, P1,y, P2,y, X1,y+1, X2,y+1, X3,y+1, X4,y+1, X5,y+1, P1,y+1, P2,y+1, ...)T. Further, when using H to denote a parity check matrix for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, Hu=0 holds true (here, Hu=0 indicates that all elements of the vector Hu are zeroes).

[2078] FIG. 75 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the topmost row of the parity check matrix is considered as the first row. Further, row number is incremented by one each time moving to a lower row. Accordingly, the topmost row is considered as the first row, the row immediately below the first row is considered as the second row, and the subsequent rows are considered as the third row, the fourth row, and so on.

[2079] As illustrated in FIG. 75:

"a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";
"a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×(2m-1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression";

"a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression";

"a vector for the 2×(2m+1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the 2×(2m+2)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×i-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); first expression"; and

"a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); second expression", and so on (where i is an integer no smaller than one).



[2080] FIG. 76 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the leftmost column of the parity check matrix is considered as the first column. Further, column number is incremented by one each time moving to a rightward column. Accordingly, the leftmost column is considered as the first column, the column immediately to the right of the first column is considered as the second column, and the subsequent columns are considered as the third column, the fourth column, and so on.

[2081] As illustrated in FIG. 76:

"a vector for the first column of the parity check matrix H is related to X1 at time point 1";

"a vector for the second column of the parity check matrix H is related to X2 at time point 1";

"a vector for the third column of the parity check matrix H is related to X3 at time point 1";

"a vector for the fourth column of the parity check matrix H is related to X4 at time point 1";

"a vector for the fifth column of the parity check matrix H is related to X5 at time point 1";

"a vector for the sixth column of the parity check matrix H is related to P1 at time point 1";

"a vector for the seventh column of the parity check matrix H is related to P2 at time point 1";

"a vector for the 7×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 7×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 7×(j-1)+3th column of the parity check matrix H is related to X3 at time point j";

"a vector for the 7×(j-1)+4th column of the parity check matrix H is related to X4 at time point j";

"a vector for the 7×(j-1)+5th column of the parity check matrix H is related to X5 at time point j";

"a vector for the 7×(j-1)+6th column of the parity check matrix H is related to P1 at time point j"; and

"a vector for the 7×(j-1)+7th column of the parity check matrix H is related to P2 at time point j"; and so on (where j is an integer no smaller than one).



[2082] FIG. 77 indicates a parity check matrix for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2083] The following focuses on 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×P1(D), 1×P2(D) in the parity check matrix for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2084] The parity check polynomials at time point j=1 are parity check polynomials when i=0 in expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2).

[2085] A vector for the first row in FIG. 77 can be generated from a parity check polynomial when i=0 in expression (97-1-1) or expression (97-1-2) (refer to FIG. 75).

[2086] In expressions (97-1-1) and (97-1-2):
  • terms for 1×X1(D) and 1×X2(D) exist;
  • terms for 1×X3(D), 1×X4(D), and 1×X5(D) do not exist; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[2087] Further, the relationship between column numbers and X1, X2, X3, X4, X5, P1, P2 is as indicated in FIG. 76. Based on the relationship indicated in FIG. 76 and the fact that terms for 1×X1(D) and 1×X2(D) exist, columns related to X1 and X2 in the vector for the first row in FIG. 77 are "1". Further, based on the relationship indicated in FIG. 76 and the fact that terms for 1×X3(D), 1×X4(D), and 1×X5(D) do not exist, columns related to X3, X4, X5 in the vector for the first row in FIG. 77 are "0". In addition, based on the relationship indicated in FIG. 76 and the fact that a term for 1×P1(D) exists but a term for 1×P2(D) does not exist, a column related to P1 in the vector for the first row in FIG. 77 is "1", and a column related to P2 in the vector for the first row in FIG. 77 is "0".

[2088] As such, the vector for the first row in FIG. 77 is "1100010", as indicated by 3900-1 in FIG. 77.

[2089] A vector for the second row in FIG. 77 can be generated from a parity check polynomial when i=0 in expression (97-2-1) or expression (97-2-2) (refer to FIG. 75).

[2090] In expressions (97-2-1) and (97-2-2):
  • terms for 1×X1(D) and 1×X2(D) do not exist;
  • terms for 1×X3(D), 1×X4(D), and 1×X5(D) exist; and
  • a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists.


[2091] Further, the relationship between column numbers and X1, X2, X3, X4, X5, P1, P2 is as indicated in FIG. 76. Based on the relationship indicated in FIG. 76 and the fact that terms for 1×X1(D) and 1×X2(D) do not exist, columns related to X1 and X2 in the vector for the second row in FIG. 77 are "0". Further, based on the relationship indicated in FIG. 76 and the fact that terms for 1×X3(D), 1×X4(D), and 1×X5(D) exist, columns related to X3, X4, X5 in the vector for the second row in FIG. 77 are "1". In addition, based on the relationship indicated in FIG. 76 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the second row in FIG. 77 is "Y", and a column related to P2 in the vector for the second row in FIG. 77 is "1", where Y is either "0" or "1".

[2092] As such, the vector for the second row in FIG. 77 is "00111Y1", as indicated by 3900-2 in FIG. 77.

[2093] The parity check polynomials at time point j=2 are parity check polynomials when i=0 in expressions (98-1-1), (98-1-2), (98-2-1), (98-2-2).

[2094] A vector for the third row in FIG. 77 can be generated from a parity check polynomial when i=0 in expression (98-1-1) or expression (98-1-2) (refer to FIG. 75).

[2095] In expressions (98-1-1) and (98-1-2):
  • terms for 1×X1(D) and 1×X2(D) do not exist;
  • terms for 1×X3(D), 1×X4(D), and 1×X5(D) exist; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[2096] Further, the relationship between column numbers and X1, X2, X3, P1, P2 is as indicated in FIG. 76. Based on the relationship indicated in FIG. 76 and the fact that terms for 1×X1(D) and 1×X2(D) do not exist, columns related to X1 and X2 in the vector for the third row in FIG. 77 are "0". Further, based on the relationship indicated in FIG. 76 and the fact that terms for 1×X3(D), 1×X4(D), and 1×X5(D) exist, columns related to X3, X4, X5 in the vector for the third row in FIG. 77 are "1". In addition, based on the relationship indicated in FIG. 76 and the fact that a term for 1×P1(D) exists but a term for 1×P2(D) does not exist, a column related to P1 in the vector for the third row in FIG. 77 is "1", and a column related to P2 in the vector for the third row in FIG. 77 is "0".

[2097] As such, the vector for the third row in FIG. 77 is "0011110", as indicated by 3901-1 in FIG. 77.

[2098] A vector for the fourth row in FIG. 77 can be generated from a parity check polynomial when i=0 in expression (98-2-1) or expression (98-2-2) (refer to FIG. 75).

[2099] In expressions (98-2-1) and (98-2-2):
  • terms for 1×X1(D) and 1×X2(D) exist;
  • terms for 1×X3(D), 1×X4(D), and 1×X5(D) do not exist; and
  • a term for 1 ×P1(D) may or may not exist but a term for 1×P2(D) exists.


[2100] Further, the relationship between column numbers and X1, X2, X3, P1, P2 is as indicated in FIG. 76. Based on the relationship indicated in FIG. 76 and the fact that terms for 1×X1(D) and 1×X2(D) exist, columns related to X1 and X2 in the vector for the fourth row in FIG. 77 are "1". Further, based on the relationship indicated in FIG. 76 and the fact that terms for 1×X3(D), 1×X4(D), and 1×X5(D) do not exist, columns related to X3, X4, X5 in the vector for the fourth row in FIG. 77 are "0". In addition, based on the relationship indicated in FIG. 76 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the fourth row in FIG. 77 is "Y", and a column related to P2 in the vector for the fourth row in FIG. 77 is "1".

[2101] As such, the vector for the fourth row in FIG. 77 is "11000Y1", as indicated by 3901-2 in FIG. 77.

[2102] Because it can be considered that the above similarly applies to cases where time point j=3, 4, 5, the parity check matrix H has the configuration indicated in FIG. 77.

[2103] That is, due to the parity check polynomials of expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2) being used at time point j=2k+1 (where k is an integer no smaller than zero), "1100010" exists in the 2×(2k+1)-1th row of the parity check matrix H, and "00111Y1" exists in the 2×(2k+1)th row of the parity check matrix H, as illustrated in FIG. 77.

[2104] Further, due to the parity check polynomials of expressions (98-1-1), (98-1-2), (98-2-1), (98-2-2) being used at time point j=2k+2 (where k is an integer no smaller than zero), "0011110" exists in the 2×(2k+2)-1th row of the parity check matrix H, and "11000Y1" exists in the 2×(2k+2)th row of the parity check matrix H, as illustrated in FIG. 77.

[2105] Accordingly, as illustrated in FIG. 77, when denoting a column number of a leftmost column corresponding to "1" in "1100010" in a row where "1100010" exists (e.g., 3900-1 in FIG. 77) as "a", "0011110" (e.g., 3901-1 in FIG. 77) exists in a row that is two rows below the row where "1100010" exists, starting from column "a+7".

[2106] Similarly, as illustrated in FIG. 77, when denoting a column number of a leftmost column corresponding to "1" in "00111Y1" in a row where "00111Y1" exists (e.g., 3900-2 in FIG. 77) as "b", "11000Y1" (e.g., 3901-2 in FIG. 77) exists in a row that is two rows below the row where "00111Y1" exists, starting from column "b+7".

[2107] Similarly, as illustrated in FIG. 77, when denoting a column number of a leftmost column corresponding to "1" in "0011110" in a row where "0011110" exists (e.g., 3901-1 in FIG. 77) as "c", "1100010" (e.g., 3902-1 in FIG. 77) exists in a row that is two rows below the row where "0011110" exists, starting from column "c+7".

[2108] Similarly, as illustrated in FIG. 77, when denoting a column number of a leftmost column corresponding to "1" in "11000Y1" in a row where "11000Y1" exists (e.g., 3901-2 in FIG. 77) as "d", "00111Y1" (e.g., 3902-2 in FIG. 77) exists in a row that is two rows below the row where "11000Y1" exists, starting from column "d+7".

[2109] The following describes a parity check matrix for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial when tail-biting is not performed, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2110] In the following, Hcom[u][v] (where u and v are integers no smaller than one) denotes an element at row "u" column "v" of a parity check matrix for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2111] Based on description above provided with reference to FIG. 75:

"a vector for the 2×g-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); first expression"; and

"a vector for the (2×g)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); second expression" (where g is an integer no smaller than one).



[2112] Based on description above provided with reference to FIG. 76:

"a vector for the 7×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 7×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 7×(j-1)+3th column of the parity check matrix H is related to X3 at time point j";

"a vector for the 7×(j-1)+4th column of the parity check matrix H is related to X4 at time point j";

"a vector for the 7×(j-1)+5th column of the parity check matrix H is related to X5 at time point j";

"a vector for the 7×(j-1)+6th column of the parity check matrix H is related to P1 at time point j"; and

"a vector for the 7×(j-1)+7th column of the parity check matrix H is related to P2 at time point j"; (where j is an integer no smaller than one).



[2113] Based on the above, the following describes component Hcom[2×g-1][v] in row 2×g-1 (where g is an integer no smaller than one) and component Hcom[2×g][v] in row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2114] As already described above, a parity check polynomial satisfying zero of #((g-1)%2m); first expression can be used to generate a vector for row 2×g-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2115] Further, a parity check polynomial satisfying zero of #((g-1)%2m); second expression can be used to generate a vector for row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2116]  Accordingly, when g=2×f-1 (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (97-1-1) or expression (97-1-2), can be used to generate a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2117] Further, a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (97-2-1) or expression (97-2-2), can be used to generate a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2118] Further, when g=2×f (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (98-1-1) or expression (98-1-2), can be used to generate a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2119] Further, a parity check polynomial satisfying zero of #(((2×f)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (98-2-1) or expression (98-2-2), can be used to generate a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2120] Accordingly, (1) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-1-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-1-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2121] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2122] The following holds true for X1.
[Math. 359]





[2123] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than two.
[Math. 360]



[2124] Further, the following holds true for X3. In the following, y is an integer no smaller than three and no greater than r#(2c),3.
[Math. 361]



[2125] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than three and no greater than five, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 362]





[2126] The following holds true for P1.
[Math. 363]



[2127] The following holds true for P2.
[Math. 364]



[2128] Further, (2) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-1-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-1-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2129] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2130] The following holds true for X1.
[Math. 365]



[2131] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than two.
[Math. 366]



[2132] Further, the following holds true for X3. In the following, y is an integer no smaller than three and no greater than r#(2c),3.
[Math. 367]





[2133] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than three and no greater than five, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 368]



[2134] The following holds true for P1.
[Math. 369]



[2135] The following holds true for P2.
[Math. 370]



[2136] Further, (3) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-2-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-2-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2137] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2138] The following holds true for X1. In the following, and y is an integer no smaller than three and no greater than r#(2c),1.
[Math. 371]



[2139] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than two, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 372]





[2140] Further, the following holds true for X3.
[Math. 373]



[2141] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than three and no greater than five.
[Math. 374]



[2142] The following holds true for P1.
[Math. 375]





[2143] The following holds true for P2.
[Math. 376]



[2144] Further, (4) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-2-2), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-2-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2145] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2146] The following holds true for X1. In the following, y is an integer no smaller than three and no greater than r#(2c),1.
[Math. 377]





[2147] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than two, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 378]



[2148] Further, the following holds true for X3.
[Math. 379]



[2149] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than three and no greater than five.
[Math. 380]





[2150] The following holds true for P1.
[Math. 381]



[2151] The following holds true for P2.
[Math. 382]



[2152] Further, (5) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-1-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-1-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2153] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2154] The following holds true for X1. In the following, y is an integer no smaller than three and no greater than r#(2d+1),1.
[Math. 383]



[2155] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than two, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 384]



[2156] Further, the following holds true for X3.
[Math. 385]





[2157] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than three and no greater than five.
[Math. 386]



[2158] The following holds true for P1.
[Math. 387]



[2159] The following holds true for P2.
[Math. 388]





[2160] Further, (6) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-1-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-1-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2161] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2162] The following holds true for X1. In the following, y is an integer no smaller than three and no greater than r#(2d+1),1.
[Math. 389]



[2163] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than two, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 390]



[2164] Further, the following holds true for X3.
[Math. 391]



[2165] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than three and no greater than five.
[Math. 392]





[2166] The following holds true for P1.
[Math. 393]



[2167] The following holds true for P2.
[Math. 394]



[2168] Further, (7) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-2-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-2-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2169] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2170]  The following holds true for X1.
[Math. 395]



[2171] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than two.
[Math. 396]



[2172] Further, the following holds true for X3. In the following, y is an integer no smaller than three and no greater than r#(2d+1),3.
[Math. 397]





[2173] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than three and no greater than five, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 398]



[2174] The following holds true for P1.
[Math. 399]



[2175] The following holds true for P2.
[Math. 400]



[2176] Further, (8) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-2-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-2-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2177] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2178] The following holds true for X1.
[Math. 401]



[2179] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than two.
[Math. 402]





[2180] Further, the following holds true for X3. In the following, y is an integer no smaller than three and no greater than r#(2d+1),3.
[Math. 403]



[2181] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than three and no greater than five, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 404]



[2182] The following holds true for P1.
[Math. 405]



[2183] The following holds true for P2.
[Math. 406]



[2184] As such, an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial can be generated by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, and the code so generated achieves high error correction capability.

(Embodiment E2)



[2185] In the present embodiment, description is provided of a method of code configuration that is a generalization of the method described in embodiment E1 of configuring an LDPC-CC of coding rate 5/7 that is based on a parity check polynomial.

[2186] Bits of information bits X1, X2, X3, X4, X5 and parity bits P1, P2, at time point j, are expressed X1,j, X2,j, X3,j, X4,j, X5.j and P1,j, P2,j, respectively.

[2187] A vector uj, at time point j, is expressed uj = (X1,j, X2,j, X3,j, X4,j, X5.j, P1,j, P2,j).

[2188] Given a delay operator D, polynomial expressions of the information bits X1, X2, X3, X4, X5 are X1(D), X2(D), X3(D), X4(D), X5(D), and polynomial expressions of the parity bits P1, P2 are P1(D), P2(D).

[2189] Further, consideration is given to an LDPC-CC of coding rate 5/7 and time-varying period 2m that is based on a parity check polynomial.

[2190] The following mathematical expressions are provided as parity check polynomials satisfying zero for an LDPC-CC of coding rate 5/7 and time-varying period 2m that is based on a parity check polynomial.

[2191] First, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1×P2(D).
[Math. 407-1]



[Math. 407-2]







[2192] In expressions (147-1-1), (147-1-2), (147-2-1), (147-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[2193] In expressions (147-1-1), (147-1-2), (147-2-1), (147-2-2), a#(2i),p,q (where p is an integer no smaller than one and no greater than five, q is an integer no smaller than one and no greater than r#(2i),p (where r#(2i),p is a natural number)) and β#(2i),0 is a natural number, β#(2i),1 is a natural number, β#(2i),2 is an integer no smaller than zero, and β#(2i),3 is a natural number.

[2194] Further, R#(2i),p is a natural number satisfying 1≤R#(2i),p<r#(2i),p.

[2195] Further, y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for all y and all z satisfying y≠z.)

[2196] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (147-1-1) or expression (147-1-2) is referred to as "#(2i); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (147-2-1) or expression (147-2-2) is referred to as "#(2i); second expression" for realizing a time-varying period 2m.

[2197] Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (147-1-1) or expression (147-1-2) is prepared.

[2198] That is, for i=0, a parity check polynomial satisfying zero provided by expression (147-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (147-1-2) where i=0 is prepared.

[2199] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (147-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (147-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (147-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (147-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (147-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (147-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (147-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (147-1-2) where i=m-1 is prepared.



[2200] Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (147-2-1) or expression (147-2-2) is prepared.

[2201] That is, for i=0, a parity check polynomial satisfying zero provided by expression (147-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (147-2-2) where i=0 is prepared.

[2202] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (147-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (147-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (147-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (147-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (147-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (147-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (147-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (147-2-2) where i=m-1 is prepared.



[2203] Similarly, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1 ×P1(D) and two for 1×P2(D).
[Math. 408-1]



[Math. 408-2]







[2204] In expressions (148-1-1), (148-1-2), (148-2-1), (148-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[2205] In expressions (148-1-1), (148-1-2), (148-2-1), (148-2-2), α#(2i+1),p,q (where p is an integer no smaller than one and no greater than five, q is an integer no smaller than one and no greater than r#(2i+1),p (where r#(2i+1),p is a natural number)) and β#(2i+1),0 is a natural number, β#(2i+1),1 is a natural number, β#(2i+1),2 is an integer no smaller than zero, and β#(2i+1),3 is a natural number.

[2206] Further, R#(2i),p is a natural number satisfying 1≤R#(2i+1),p<r#(2i+1),p.

[2207] Further, y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for all y and all z satisfying y≠z.)

[2208] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (148-1-1) or expression (148-1-2) is referred to as "#(2i+1); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (148-2-1) or expression (148-2-2) is referred to as "#(2i+1); second expression" for realizing a time-varying period 2m.

[2209] Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (148-1-1) or expression (148-1-2) is prepared.

[2210] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (148-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (148-1-2) where i=0 is prepared.

[2211] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (148-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (148-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (148-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (148-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (148-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (148-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (148-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (148-1-2) where i=m-1 is prepared.



[2212] Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (148-2-1) or expression (148-2-2) is prepared.

[2213] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (148-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (148-2-2) where i=0 is prepared.

[2214] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (148-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (148-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (148-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (148-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (148-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (148-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (148-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (148-2-2) where i=m-1 is prepared.



[2215] As such, an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2216] Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (147-1-1) or expression (147-1-2), parity check polynomials satisfying zero provided by expression (147-2-1) or expression (147-2-2), parity check polynomials satisfying zero provided by expression (148-1-1) or expression (148-1-2), and parity check polynomials satisfying zero provided by expression (148-2-1) or expression (148-2-2).

[2217] For example, the time varying period 2×m can be formed by preparing a 4×m number of different parity check polynomials satisfying zero.

[2218] Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

[2219] The following describes the relationship between time point j and expressions (147-1-1), (147-1-2), (147-2-1), (147-2-2), (148-1-1), (148-1-2), (148-2-1), and (148-2-2) (where j is an integer no smaller than zero).

[2220] The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m-1).

[2221] Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i = k in #(2i); first expression and #(2i); second expression, hold true.

[2222] Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m-1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

[2223] The following describes a method of configuring a parity check matrix for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2224] As already described above, a vector uj at time point j is expressed as uj=(X1,j, X2,j, X3,j, X4,j, X5,j, P1,j, P2,j) (where j is an integer no smaller than zero). In the following, a case where u is a transmission vector is considered. Note that in the following, j is an integer no smaller than one, and thus j differs between the description having been provided above and the description provided in the following. (j is set as such to facilitate understanding of the correspondence between the column numbers and the row numbers of the parity check matrix.)

[2225] Accordingly, u=(u1, u2, u3, ..., uy-1, uy, uy+1, ...)T=(X1,1, X2,1, X3,1, X4,1, X5,1, P1,1, P2,1, X1,2, X2,2, X3,2, X4,2, X5,2, P1,2, P2,2, X1,3, X2,3, X3,3, X4,3, X5,3, P1,3, P2,3, ..., X1,y-1, X2,y-1, X3,y-1, X4,y-1, X5,y-1, P1,y-1, P2,y-1, X1,y, X2,y, X3,y, X4-y, X5,y, P1,y, P2,y, X1,y+1, X2,y+1, X3,y+1, X4,y+1, X5,y+1, P1,y+1, P2,y+1, ...)T. Further, when using H to denote a parity check matrix for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, Hu=0 holds true (here, Hu=0 indicates that all elements of the vector Hu are zeroes).

[2226] FIG. 75 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the topmost row of the parity check matrix is considered as the first row. Further, row number is incremented by one each time moving to a lower row. Accordingly, the topmost row is considered as the first row, the row immediately below the first row is considered as the second row, and the subsequent rows are considered as the third row, the fourth row, and so on.

[2227] As illustrated in FIG. 75:

"a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";
"a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×(2m-1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression";

"a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression";

"a vector for the 2×(2m+1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the 2×(2m+2)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×i-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); first expression"; and

"a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); second expression", and so on (where i is an integer no smaller than one).



[2228] FIG. 76 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the leftmost column of the parity check matrix Hpro_m is considered as the first column. Further, column number is incremented by one each time moving to a rightward column. Accordingly, the leftmost column is considered as the first column, the column immediately to the right of the first column is considered as the second column, and the subsequent columns are considered as the third column, the fourth column, and so on.

[2229] As illustrated in FIG. 76:

"a vector for the first column of the parity check matrix H is related to X1 at time point 1";

"a vector for the second column of the parity check matrix H is related to X2 at time point 1";

"a vector for the third column of the parity check matrix H is related to X3 at time point 1";

"a vector for the fourth column of the parity check matrix H is related to X4 at time point 1";

"a vector for the fifth column of the parity check matrix H is related to X5 at time point 1";

"a vector for the sixth column of the parity check matrix H is related to P1 at time point 1";

"a vector for the seventh column of the parity check matrix H is related to P2 at time point 1";

"a vector for the 7×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 7×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 7×(j-1)+3th column of the parity check matrix H is related to X3 at time point j";

"a vector for the 7×(j-1)+4th column of the parity check matrix H is related to X4 at time point j";

"a vector for the 7×(j-1)+5th column of the parity check matrix H is related to X5 at time point j";

"a vector for the 7×(j-1)+6th column of the parity check matrix H is related to P1 at time point j"; and

"a vector for the 7×(j-1)+7th column of the parity check matrix H is related to P2 at time point j"; and so on (where j is an integer no smaller than one).



[2230] FIG. 77 indicates a parity check matrix for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2231] The following focuses on 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×P1(D), 1×P2(D) in the parity check matrix for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2232] The parity check polynomials at time point j=1 are parity check polynomials when i=0 in expressions (147-1-1), (147-1-2), (147-2-1), (147-2-2).

[2233] A vector for the first row in FIG. 77 can be generated from a parity check polynomial when i=0 in expression (147-1-1) or expression (147-1-2) (refer to FIG. 75).

[2234] In expressions (147-1-1) and (147-1-2):
  • terms for 1×X1(D) and 1×X2(D) exist;
  • terms for 1×X3(D), 1×X4(D), and 1×X5(D) do not exist; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[2235] Further, the relationship between column numbers and X1, X2, X3, X4, X5, P1, P2 is as indicated in FIG. 76. Based on the relationship indicated in FIG. 76 and the fact that terms for 1×X1(D) and 1×X2(D) exist, columns related to X1 and X2 in the vector for the first row in FIG. 77 are "1". Further, based on the relationship indicated in FIG. 76 and the fact that terms for 1×X3(D), 1×X4(D), and 1×X5(D) do not exist, columns related to X3, X4, X5 in the vector for the first row in FIG. 77 are "0". In addition, based on the relationship indicated in FIG. 76 and the fact that a term for 1×P1(D) exists but a term for 1×P2(D) does not exist, a column related to P1 in the vector for the first row in FIG. 77 is "1", and a column related to P2 in the vector for the first row in FIG. 77 is "0".

[2236] As such, the vector for the first row in FIG. 77 is "1100010", as indicated by 3900-1 in FIG. 77.

[2237] A vector for the second row in FIG. 77 can be generated from a parity check polynomial when i=0 in expression (147-2-1) or expression (147-2-2) (refer to FIG. 75).

[2238] In expressions (147-2-1) and (147-2-2):
  • terms for 1×X1(D) and 1×X2(D) do not exist;
  • terms for 1×X3(D), 1×X4(D), and 1×X5(D) exist; and
  • a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists.


[2239] Further, the relationship between column numbers and X1, X2, X3, X4, X5, P1, P2 is as indicated in FIG. 76. Based on the relationship indicated in FIG. 76 and the fact that terms for 1×X1(D) and 1×X2(D) do not exist, columns related to X1 and X2 in the vector for the second row in FIG. 77 are "0". Further, based on the relationship indicated in FIG. 76 and the fact that terms for 1×X3(D), 1×X4(D), and 1×X5(D) exist, columns related to X3, X4, X5 in the vector for the second row in FIG. 77 are "1". In addition, based on the relationship indicated in FIG. 76 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the second row in FIG. 77 is "Y", and a column related to P2 in the vector for the second row in FIG. 77 is "1", where Y is either "0" or "1".

[2240] As such, the vector for the second row in FIG. 77 is "00111Y1", as indicated by 3900-2 in FIG. 77.

[2241] The parity check polynomials at time point j=2 are parity check polynomials when i=0 in expressions (148-1-1), (148-1-2), (148-2-1), (148-2-2).

[2242] A vector for the third row in FIG. 77 can be generated from a parity check polynomial when i=0 in expression (148-1-1) or expression (148-1-2) (refer to FIG. 75).

[2243] In expressions (148-1-1) and (148-1-2):
  • terms for 1×X1(D)and 1×X2(D) do not exist;
  • terms for 1×X3(D), 1×X4(D), and 1×X5(D) exist; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[2244] Further, the relationship between column numbers and X1, X2, X3, P1, P2 is as indicated in FIG. 76. Based on the relationship indicated in FIG. 76 and the fact that terms for 1×X1(D) and 1×X2(D) do not exist, columns related to X1 and X2 in the vector for the third row in FIG. 77 are "0". Further, based on the relationship indicated in FIG. 76 and the fact that terms for 1×X3(D), 1×X4(D), and 1×X5(D) exist, columns related to X3, X4, X5 in the vector for the third row in FIG. 77 are "1". In addition, based on the relationship indicated in FIG. 76 and the fact that a term for 1×P1(D) exists but a term for 1×P2(D) does not exist, a column related to P1 in the vector for the third row in FIG. 77 is "1", and a column related to P2 in the vector for the third row in FIG. 77 is "0".

[2245] As such, the vector for the third row in FIG. 77 is "0011110", as indicated by 3901-1 in FIG. 77.

[2246] A vector for the fourth row in FIG. 77 can be generated from a parity check polynomial when i=0 in expression (148-2-1) or expression (148-2-2) (refer to FIG. 75).

[2247] In expressions (148-2-1) and (148-2-2):
  • terms for 1×X1(D) and 1×X2(D) exist;
  • terms for 1×X3(D), 1×X4(D), and 1×X5(D) do not exist; and
  • a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists.


[2248] Further, the relationship between column numbers and X1, X2, X3, P1, P2 is as indicated in FIG. 76. Based on the relationship indicated in FIG. 76 and the fact that terms for 1×X1(D) and 1×X2(D) exist, columns related to X1 and X2 in the vector for the fourth row in FIG. 77 are "1". Further, based on the relationship indicated in FIG. 76 and the fact that terms for 1×X3(D), 1×X4(D), and 1×X5(D) do not exist, columns related to X3, X4, X5 in the vector for the fourth row in FIG. 77 are "0". In addition, based on the relationship indicated in FIG. 76 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the fourth row in FIG. 77 is "Y", and a column related to P2 in the vector for the fourth row in FIG. 77 is "1".

[2249] As such, the vector for the fourth row in FIG. 77 is "11000Y1", as indicated by 3901-2 in FIG. 77.

[2250] Because it can be considered that the above similarly applies to cases where time point j=3, 4, 5, the parity check matrix H has the configuration indicated in FIG. 77.

[2251] That is, due to the parity check polynomials of expressions (147-1-1), (147-1-2), (147-2-1), (147-2-2) being used at time point j=2k+1 (where k is an integer no smaller than zero), "1100010" exists in the 2×(2k+1)-1th row of the parity check matrix H, and "00111Y1" exists in the 2×(2k+1)th row of the parity check matrix H, as illustrated in FIG. 77.

[2252] Further, due to the parity check polynomials of expressions (148-1-1), (148-1-2), (148-2-1), (148-2-2) being used at time point j=2k+2 (where k is an integer no smaller than zero), "0011110" exists in the 2×(2k+2)-1th row of the parity check matrix H, and "11000Y1" exists in the 2×(2k+2)th row of the parity check matrix H, as illustrated in FIG. 77.

[2253] Accordingly, as illustrated in FIG. 77, when denoting a column number of a leftmost column corresponding to "1" in "1100010" in a row where "1100010" exists (e.g., 3900-1 in FIG. 77) as "a", "0011110" (e.g., 3901-1 in FIG. 77) exists in a row that is two rows below the row where "1100010" exists, starting from column "a+7".

[2254] Similarly, as illustrated in FIG. 77, when denoting a column number of a leftmost column corresponding to "1" in "00111Y1" in a row where "00111Y1" exists (e.g., 3900-2 in FIG. 77) as "b", "11000Y1" (e.g., 3901-2 in FIG. 77) exists in a row that is two rows below the row where "00111Y1" exists, starting from column "b+7".

[2255] Similarly, as illustrated in FIG. 77, when denoting a column number of a leftmost column corresponding to "1" in "0011110" in a row where "0011110" exists (e.g., 3901-1 in FIG. 77) as "c", "1100010" (e.g., 3902-1 in FIG. 77) exists in a row that is two rows below the row where "0011110" exists, starting from column "c+7".

[2256] Similarly, as illustrated in FIG. 77, when denoting a column number of a leftmost column corresponding to "1" in "11000Y1" in a row where "11000Y1" exists (e.g., 3901-2 in FIG. 77) as "d", "00111Y1" (e.g., 3902-2 in FIG. 77) exists in a row that is two rows below the row where "11000Y1" exists, starting from column "d+7".

[2257] The following describes a parity check matrix for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial when tail-biting is not performed, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2258] In the following, Hcom[u][v] (where u and v are integers no smaller than one) denotes an element at row "u" column "v" of a parity check matrix for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2259] Based on description above provided with reference to FIG. 75:

"a vector for the 2×g-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); first expression"; and

"a vector for the (2×g)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); second expression" (where g is an integer no smaller than one).



[2260] Based on description above provided with reference to FIG. 76:

"a vector for the 7×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 7×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 7×(j-1)+3th column of the parity check matrix H is related to X3 at time point j";

"a vector for the 7×(j-1)+4th column of the parity check matrix H is related to X4 at time point j";

"a vector for the 7×(j-1)+5th column of the parity check matrix H is related to P5 at time point j";

"a vector for the 7×(j-1)+6th column of the parity check matrix H is related to P1 at time point j"; and

"a vector for the 7×(j-1)+7th column of the parity check matrix H is related to P2 at time point j"; (where j is an integer no smaller than one).



[2261] Based on the above, the following describes component Hcom[2×g-1][v] in row 2×g-1 (where g is an integer no smaller than one) and component Hcom[2×g][v] in row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2262] As already described above, a parity check polynomial satisfying zero of #((g-1)%2m); first expression can be used to generate a vector for row 2×g-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2263] Further, a parity check polynomial satisfying zero of #((g-1)%2m); second expression can be used to generate a vector for row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2264] Accordingly, when g=2×f-1 (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (147-1-1) or expression (147-1-2), can be used to generate a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2265] Further, a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (147-2-1) or expression (147-2-2), can be used to generate a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2266] Further, when g=2×f (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (148-1-1) or expression (148-1-2), can be used to generate a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2267] Further, a parity check polynomial satisfying zero of #(((2×f)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (148-2-1) or expression (148-2-2), can be used to generate a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2268] Accordingly, (1) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (147-1-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (147-1-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2269] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2270] The following holds true for X1.
[Math. 409]



[2271] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than two.
[Math. 410]



[2272] Further, the following holds true for X3. In the following, y is an integer no smaller than R#(2c),3+1 and no greater than r#(2c),3.
[Math. 411]



[2273] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than three and no greater than five, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 412]



[2274] The following holds true for P1.
[Math. 413]





[2275] The following holds true for P2.
[Math. 414]



[2276] Further, (2) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (147-1-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (147-1-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2277] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2278] The following holds true for X1.
[Math. 415]





[2279] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than two.
[Math. 416]



[2280] Further, the following holds true for X3. In the following, y is an integer no smaller than R#(2c),3+1 and no greater than r#(2c),3.
[Math. 417]



[2281] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than three and no greater than five, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 418]





[2282] The following holds true for P1.
[Math. 419]



[2283] The following holds true for P2.
[Math. 420]



[2284] Further, (3) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (147-2-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (147-2-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2285] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2286] The following holds true for X1. In the following, and y is an integer no smaller than R#(2c),1+1 and no greater than r#(2c),1.
[Math. 421]



[2287] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than two, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 422]



[2288] Further, the following holds true for X3.
[Math. 423]



[2289] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than three and no greater than five.
[Math. 424]



[2290] The following holds true for P1.
[Math. 425]



[2291] The following holds true for P2.
[Math. 426]



[2292] Further, (4) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (147-2-2), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (147-2-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2293] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2294] The following holds true for X1. In the following, y is an integer no smaller than R#(2,),1+1 and no greater than r#(2c),1.
[Math. 427]



[2295] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than two, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 428]



[2296] Further, the following holds true for X3.
[Math. 429]





[2297] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than three and no greater than five.
[Math. 430]



[2298] The following holds true for P1.
[Math. 431]



[2299] The following holds true for P2.
[Math. 432]



[2300] Further, (5) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (148-1-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (148-1-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2301] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2302] The following holds true for X1. In the following, y is an integer no smaller than R#(2d+1),1+1 and no greater than r#(2d+1),1.
[Math. 433]



[2303] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than two, and y is an integer no smaller than R#(2d+1),z+1 and no greater than r#(2d+1),z.
[Math. 434]





[2304] Further, the following holds true for X3.
[Math. 435]



[2305] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than three and no greater than five.
[Math. 436]



[2306] The following holds true for P1.
[Math. 437]



[2307] The following holds true for P2.
[Math. 438]



[2308] Further, (6) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (148-1-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (148-1-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2309] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2310] The following holds true for X1. In the following, y is an integer no smaller than R#(2d+1),1+1 and no greater than r#(2d+1),1.
[Math. 439]





[2311] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than two, and y is an integer no smaller than R#(2d+1),z+1 and no greater than r#(2d+1),z.
[Math. 440]



[2312] Further, the following holds true for X3.
[Math. 441]



[2313] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than three and no greater than five.
[Math. 442]





[2314] The following holds true for P1.
[Math. 443]



[2315] The following holds true for P2.
[Math. 444]



[2316] Further, (7) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (148-2-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (148-2-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2317] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2318]  The following holds true for X1.
[Math. 445]



[2319] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than two.
[Math. 446]



[2320] Further, the following holds true for X3. In the following, y is an integer no smaller than R#(2d+1),3+1 and no greater than r#(2d+1),3.
[Math. 447]



[2321] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than three and no greater than five, and y is an integer no smaller than R#(2d+1),3+1 and no greater than r#(2d+1),z.
[Math. 448]



[2322] The following holds true for P1.
[Math. 449]



[2323] The following holds true for P2.
[Math. 450]



[2324] Further, (8) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (148-2-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (148-2-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2325] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2326] The following holds true for X1.
[Math. 451]



[2327] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than two.
[Math. 452]



[2328] Further, the following holds true for X3. In the following, y is an integer no smaller than R#(2d+1),3+1 and no greater than r#(2d+1),3.
[Math. 453]



[2329] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than three and no greater than five, and y is an integer no smaller than R#(2d+1),z+1 and no greater than r#(2d+1),z.
[Math. 454]



[2330] The following holds true for P1.
[Math. 455]



[2331] The following holds true for P2.
[Math. 456]



[2332] As such, an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial can be generated by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, and the code so generated achieves high error correction capability.

(Embodiment E3)



[2333] In the present embodiment, description is provided of a device that uses the LDPC-CC of coding rate 5/7 that is based on a parity check polynomial, description of which has been provided in embodiments E1 and E2.

[2334] As one example, description is provided of a case where the LDPC-CC of coding rate 5/7 that is based on a parity check polynomial, description of which has been provided in embodiments E1 and E2, is applied to a communication device.

[2335] FIG. 22 illustrates the structures of a transmitting device 2200 and a receiving device 2210 in the communication device pertaining to the present embodiment.

[2336] An encoder 2201 receives information to be transmitted as input, and is capable of performing various types of encoding. In particular, when receiving a specification to perform encoding by using the LDPC-CC of coding rate 5/7 that is based on a parity check polynomial, description of which has been provided in embodiments E1 and E2, the encoder 2201 performs encoding by using the LDPC-CC of coding rate 5/7 that is based on a parity check polynomial, description of which has been provided in embodiments E1 and E2, to calculate parities P1 and P2. Further, the encoder 2201 outputs the information to be transmitted and the parities P1 and P2 as a transmission sequence.

[2337] A modulator 2202 receives the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, performs mapping based on a predetermined modulation scheme (e.g., BPSK, QPSK, 16QAM, 64QAM), and outputs a baseband signal. Further, the modulator 2202 may also receive information other than the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, as input, perform mapping, and output a baseband signal. For example, the modulator 2202 may receive control information as input.

[2338] The transmitting device outputs a transmission signal after performing predetermined signal processing (e.g., signal processing for generation of an OFDM signal, frequency conversion, amplification) with respect to such signals (e.g., baseband signals, pilot signals). The transmitting device may transmit the transmission signal over a wireless transmission path utilizing electromagnetic waves, or over a wired transmission path utilizing a coaxial cable, a power line, an optical cable, or the like.

[2339] The transmission signal is received by the receiving device 2210 after travelling over the transmission path. A receiver 2211 receives a reception signal as input, performs predetermined signal processing (e.g., bandwidth limitation, frequency conversion, signal processing for OFDM, frequency offset estimation, signal detection, channel estimation), and outputs a baseband signal and a channel estimation signal.

[2340] A log-likelihood ratio generation section 2212 receives the baseband signal and the channel estimation signal as input (may receive other signals as input), and for example, calculates and outputs a log-likelihood ratio for each bit (may calculate and output a hard value (hard decision value)).

[2341] A decoder 2213 receives the log-likelihood ratio for each bit as input, performs belief propagation decoding (e.g., sum-product decoding, scheduled sum-product decoding (Layered BP (belief propagation) decoding), min-sum decoding, Normalized BP decoding, offset BP decoding), and outputs an estimation sequence. The decoder 2213 performs the belief propagation decoding based on the parity check matrix for the LDPC-CC of coding rate 5/7 that is based on a parity check polynomial, description of which has been provided in embodiments E1 and E2.

[2342] FIG. 78 illustrates one example of the structure of an encoder for the LDPC-CC of coding rate 5/7 that is based on a parity check polynomial, description of which has been provided in embodiments E1 and E2. Description on such an encoder has been provided with reference to the encoder 2201 in FIG. 22.

[2343] In FIG. 78, an Xz computation section 4001-z (where z is an integer no smaller than one and no greater than five) includes a plurality of shift registers that are connected in series and a calculator that performs XOR calculation on bits collected from some of the shift registers (refer to FIGs. 2 and 22).

[2344] The Xz computation section 4001-z receives an information bit Xz,j at time point j as input, performs the XOR calculation, and outputs bits 4002-z-1 and 4002-z-2, which are acquired through the Xz calculation.

[2345] A P1 computation section 4004-1 includes a plurality of shift registers that are connected in series and a calculator that that performs XOR calculation on bits collected from some of the shift registers (refer to FIGs. 2 and 22).

[2346] The P1 computation section 4004-1 receives a bit P1,j of parity P1 at time point j as input, performs the XOR calculation, and outputs bits 4005-1-1 and 4005-1-2, which are acquired through the P1 calculation.

[2347] A P2 computation section 4004-2 includes a plurality of shift registers that are connected in series and a calculator that that performs XOR calculation on bits collected from some of the shift registers (refer to FIGs. 2 and 22).

[2348] The P2 computation section 4004-2 receives a bit P2,j of parity P2 at time point j as input, performs the XOR calculation, and outputs bits 4005-2-1 and 4005-2-2, which are acquired through the P2 calculation.

[2349] An XOR (calculator) 4005-1 receives the bits 4002-1-1 through 4002-5-1 acquired by X1 calculation through X5 calculation, respectively, the bit 4005-1-1 acquired by P1 calculation, and the bit 4005-2-1 acquired by the P2 calculation as input, performs XOR calculation, and outputs a bit P1,j of parity P1 at time point j.

[2350] An XOR (calculator) 4005-2 receives the bits 4002-1-2 through 4002-5-2 acquired by X1 calculation through X5 calculation, respectively, the bit 4005-1-2 acquired by P1 calculation, and the bit 4005-2-2 acquired by the P2 calculation as input, performs XOR calculation, and outputs a bit P2,j of parity P2 at time point j.

[2351] It is preferable that initial values of the shift registers of the Xz computation section 4001-z, the P1 computation section 4004-1, and the P2 computation section 4004-2 illustrated in FIG. 78 be set to "0" (zero). By making such a configuration, it becomes unnecessary to transmit to the receiving device parities P1 and P2 before the setting of initial values.

[2352] The following describes a method of information-zero termination.

[2353] Suppose that in FIG. 79, information X1 through X5 exist from time point 0, and information X5 at time point s (where s is an integer no smaller than zero) is the last information bit. That is, suppose that the information to be transmitted from the transmitting device to the receiving device is information X1,j through X5,j, being information X1 through X5 at time point j, respectively, where j is an integer no smaller than zero and no greater than s.

[2354] In such a case, the transmitting device transmits information X1 through X5, parity P1, and parity P2 from time point 0 to time point s, or that is, transmits X1,j, X2,j, X3,j, X4,j, X5,j, P1,j, P2,j, where j is an integer no smaller than zero and no greater than s. (Note that P1,j and P2,j denote parity P1 and parity P2 at time point j, respectively.)

[2355] Further, suppose that information X1 through X5 from time point s+1 to time point s+g (where g is an integer no smaller than one) is "0", or that is, when denoting information X1 through X5 at time point t as X1,t, X2,t, X3,t, X4,t, X5,t, respectively, X1,t=0, X2,t=0, X3,t=0, X4,t=0, X5,t=0 hold true for t being an integer no smaller than s+1 and no greater than s+g. The transmitting device, by performing encoding, acquires parities P1,t and P2,t for t being an integer no smaller than s+1 and no greater than s+g. The transmitting device, in addition to the information and parities described above, transmits parities P1,t and P2,t for t being an integer no smaller than s+1 and no greater than s+g.

[2356] Meanwhile, the receiving device performs decoding by using log-likelihood ratios for the information and the parities transmitted by the transmitting device, and log-likelihood ratios corresponding to X1,t=0, X2,t=0, X3,t=0, X4,t=0, X5,t=0, for t being an integer no smaller than s+1 and no greater than s+g, and thereby acquires an estimation sequence of information.

[2357] FIG. 80 illustrates an example differing from that illustrated in FIG. 79. Suppose that information X1 through X5 exist from time point 0, and information Xf for time point s (where s is an integer no smaller than zero) is the last information bit. Here, f is an integer no smaller than one and no greater than four. In FIG. 79, f equals 3, for example. That is, suppose that the information to be transmitted from the transmitting device to the receiving device is information Xi,s, where i is an integer no smaller than one and no greater than f, and information X1,j, information X2,j, information X3,j, information X4,j, and information X5,j, being information X1 through X5 at time point j, respectively, where j is an integer no smaller than zero and no greater than s-1.

[2358] In such a case, the transmitting device transmits information X1 through X5, parity P1, and parity P2 from time point 0 to time point s-1, or that is, transmits X1,j, X2,j, X3,j, X4,j, X5,j, P1,j, P2,j, where j is an integer no smaller than zero and no greater than s-1. (Note that P1,j and P2,j denote parity P1 and parity P2 at time point j, respectively.)

[2359] Further, suppose that at time point s, information Xi,s, when i is an integer no smaller than one and no greater than f, is information that the transmitting device is to transmit, and suppose that Xk,s, when k is an integer so smaller than f+1 and no greater than five, equals "0" (zero).

[2360] Further, suppose that information X1 through X5 from time point s+1 to time point s+g-1 (where g is an integer no smaller than two) is "0", or that is, when denoting information X1 through X5 at time point t as X1,t, X2,t, X3,t, X4,t, X5,t, respectively, X1,t=0, X2,t=0, X3,t=0, X4,t=0, X5,t=0 hold true when t is an integer no smaller than s+1 and no greater than s+g-1. The transmitting device, by performing encoding from time point s to time point s+g-1, acquires parities P1,u and P2,u for u being an integer no smaller than s and no greater than s+g-1. The transmitting device, in addition to the information and parities described above, transmits Xi,s for i being an integer no smaller than one and no greater than f, and parities P1,u and P2,u for u being an integer no smaller than s and no greater than s+g-1.

[2361] Meanwhile, the receiving device performs decoding by using log-likelihood ratios for the information and the parities transmitted by the transmitting device, log-likelihood ratios corresponding to Xk,s=0 (where k is an integer no smaller than f+1 and no greater than five) and log-likelihood ratios corresponding to X1,t=0, X2,t=0, X3,t=0, X4,t=0, X5,t=0 for t being an integer no smaller than s+1 and no greater than s+g-1, and thereby acquires an estimation sequence of information.

[2362] Although description is provided above taking an example where error correction coding is introduced to a communication device, the error correction coding described above is not limited to being introduced to a communication device, and for example, may be introduced to a storage medium (storage). When making such a modification, information that is to be stored to a storage medium (storage) is encoded by using the LDPC-CC of coding rate 5/7 that is based on a parity check polynomial, description of which has been provided in embodiments E1 and E2, and resultant information and parities are stored to the storage medium (storage). When making such a modification, it is preferable that information-zero termination be introduced as described above and that a data sequence as described above corresponding to a data sequence (information and parities) transmitted by the transmitting device when information-zero termination is applied be stored to the storage medium (storage).

[2363] Further, the LDPC-CC of coding rate 5/7 that is based on a parity check polynomial, description of which has been provided in embodiments E1 and E2, is applicable to any device that requires error correction coding (e.g., a memory, a hard disk).

(Embodiment E4)



[2364] In the present embodiment, description is provided of a method of configuring an LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). The LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme described in the present embodiment is based on the LDPC-CC of coding rate 5/7 that is based on a parity check polynomial, description of which has been provided in embodiments E1 and E2.

[2365] Patent Literature 2 includes explanation regarding an LDPC-CC of coding rate (n-1)/n (where n is an integer no smaller than two) that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). However, Patent Literature 2 poses a problem for not disclosing an LDPC-CC of a coding rate not satisfying (n-1)/n that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[2366] In the present embodiment, as one example of an LDPC-CC of a coding rate not satisfying (n-1)/n that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), description is provided of a method of configuring an LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[Periodic Time-varying LDPC-CC of Coding rate 5/7 Using Improved Tail-biting Scheme and Based on Parity Check Polynomial]



[2367] The following describes a periodic time-varying LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme and is based on a parity check polynomial, based on the configuration of the LDPC-CC of coding rate 5/7 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments E1 and E2.

[2368] The following describes a method of configuring an LDPC-CC of coding rate 5/7 and time-varying period 2m that is based on a parity check polynomial. Such method has already been described in embodiment E2.

[2369] First, the following parity check polynomials satisfying zero are prepared.
[Math. 457-1]





[Math. 457-2]







[2370] In expressions (197-1-1), (197-1-2), (197-2-1), (197-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[2371] In expressions (197-1-1), (197-1-2), (197-2-1), (197-2-2), α#(2i),p,q (where p is an integer no smaller than one and no greater than five, q is an integer no smaller than one and no greater than r#(2i),p (where r#(2i),p is a natural number)) and β#(2i),0 is a natural number, β#(2i),1 is a natural number, β#(2i),2 is an integer no smaller than zero, and β#(2i),3 is a natural number.

[2372] Further, R#(2i),p is a natural number satisfying 1≤R#(2i),p<r#(2i),p.

[2373] Further, y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for all y and all z satisfying y≠z.)

[2374] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (197-1-1) or expression (197-1-2) is referred to as "#(2i); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (197-2-1) or expression (197-2-2) is referred to as "#(2i); second expression" for realizing a time-varying period 2m.

[2375] Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (197-1-1) or expression (197-1-2) is prepared.

[2376] That is, for i=0, a parity check polynomial satisfying zero provided by expression (197-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (197-1-2) where i=0 is prepared.

[2377] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (197-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (197-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (197-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (197-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (197-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (197-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (197-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (197-1-2) where i=m-1 is prepared.



[2378] Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (197-2-1) or expression (197-2-2) is prepared.

[2379] That is, for i=0, a parity check polynomial satisfying zero provided by expression (197-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (197-2-2) where i=0 is prepared.

[2380] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (197-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (197-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (197-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (197-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (197-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (197-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (197-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (197-2-2) where i=m-1 is prepared.



[2381] Similarly, the following parity check polynomials satisfying zero are provided.
[Math. 458-1]





[Math. 458-2]







[2382] In expressions (198-1-1), (198-1-2), (198-2-1), (198-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[2383] In expressions (198-1-1), (198-1-2), (198-2-1), (198-2-2), α#(2i+1),p,q (where p is an integer no smaller than one and no greater than five, q is an integer no smaller than one and no greater than r#(2i+1),p (where r#(2i+1),p is a natural number)) and β#(2i+1),0 is a natural number, β#(2i+1),1 is a natural number, β#(2i+1),2 is an integer no smaller than zero, and β#(2i+1),3 is a natural number.

[2384] Further, R#(2i+1),p is a natural number satisfying 1≤R#(2i+1),p<r#(2i+1),p.

[2385] Further, y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for all y and all z satisfying y≠z.)

[2386] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (198-1-1) or expression (198-1-2) is referred to as "#(2i+1); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (198-2-1) or expression (198-2-2) is referred to as "#(2i+1); second expression" for realizing a time-varying period 2m.

[2387] Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (198-1-1) or expression (198-1-2) is prepared.

[2388] That is, for i=0, a parity check polynomial satisfying zero provided by expression (198-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (198-1-2) where i=0 is prepared.

[2389] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (198-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (198-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (198-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (198-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (198-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (198-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (198-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (198-1-2) where i=m-1 is prepared.



[2390] Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (198-2-1) or expression (198-2-2) is prepared.

[2391] That is, for i=0, a parity check polynomial satisfying zero provided by expression (198-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (198-2-2) where i=0 is prepared.

[2392] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (198-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (198-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (198-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (198-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (198-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (198-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (198-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (198-2-2) where i=m-1 is prepared.



[2393] As such, an LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2394] Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (197-1-1) or expression (197-1-2), parity check polynomials satisfying zero provided by expression (197-2-1) or expression (197-2-2), parity check polynomials satisfying zero provided by expression (198-1-1) or expression (198-1-2), and parity check polynomials satisfying zero provided by expression (198-2-1) or expression (198-2-2).

[2395] For example, the time varying period 2×m is formed by preparing a 4×m number of different parity check polynomials satisfying zero.

[2396] Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

[2397] The following describes the relationship between time point j and expressions (197-1-1), (197-1-2), (197-2-1), (197-2-2), (198-1-1), (198-1-2), (198-2-1), and (198-2-2) (where j is an integer no smaller than zero).

[2398] The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m-1).

[2399] Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i = k in #(2i); first expression and #(2i); second expression, hold true.

[2400] Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m-1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

[2401] Note that in the parity check polynomials satisfying zero of expressions (197-1-1), (197-1-2), (197-2-1), (197-2-2), (198-1-1), (198-1-2), (198-2-1), and (198-2-2), a sum of the number of terms of P1(D) and the number of terms of P2(D) equals two. This realizes sequentially finding parities P1 and P2 when applying an improved tail-biting scheme, and thus, is a significant factor realizing a reduction in computation amount (circuit scale).

[2402] The following describes the relationship between the time-varying period of the parity check polynomials satisfying zero for the LDPC-CC of coding rate 5/7 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments E1 and E2 and on which the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, and block size in the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) proposed in the present embodiment.

[2403] Regarding this point, in order to achieve error correction capability of even higher level, a configuration is preferable where a Tanner graph formed by the LDPC-CC of coding rate 5/7 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments E1 and E2 and on which the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, resembles a Tanner graph of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). Thus, the following conditions are significant.

<Condition #N1>



[2404] 
  • The number of rows in a parity check matrix for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is a multiple of 4×m.
    • Accordingly, the number of columns in the parity check matrix for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is a multiple of 7×2×m. According to this condition, (for example) a log-likelihood ratio that is necessary in decoding is a log-likelihood ratio of the number of columns in the parity check matrix for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).


[2405] Note that the relationship between the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and the LDPC-CC of coding rate 5/7 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments E1 and E2 and on which the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, is described in detail later in the present disclosure.

[2406] Thus, when denoting the parity check matrix for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as Hpro, the number of columns of Hpro can be expressed as 7×2×m×Z (where z is a natural number).

[2407] Accordingly, a transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as vs=(Xs,1,1 Xs,2,1, ..., Xs,5,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,5,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,5,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,5,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T (where k=1, 2, ..., 2×m×z-1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×Z)), and Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes).

[2408] Xs,j,k (where j is an integer no smaller than one and no greater than five) is a bit of information Xj, Ppros,1,k is a bit of parity P1 of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and Ppros,2,k is a bit of parity P2 of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[2409] Further, λpro,s,k=(Xs,1,k, Xs,2,k, Xs,3,k, Xs,4,k, Xs,5,k, Ppros,1,k, Ppros,2,k) holds true.

[2410] In addition, the number of rows in the parity check matrix Hpro for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is 4×m×z.

[2411] It has been indicated above that the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based on the LDPC-CC of coding rate 5/7 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments E1 and E2. This is explained in the following.

[2412] First, consideration is made of a parity check matrix when configuring a periodic time-varying LDPC-CC using tail-biting by using only parity check polynomials satisfying zero for the LDPC-CC of coding rate 5/7 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments E1 and E2.

[2413] FIG. 81 illustrates a configuration of a parity check matrix H when configuring a periodic time-varying LDPC-CC using tail-biting by performing tail-biting by using only parity check polynomials satisfying zero for an LDPC-CC of coding rate 5/7 and time-varying period 2m.

[2414] Since Condition #N1 is satisfied in FIG. 81, the number of rows of the parity check matrix is m×z and the number of columns of the parity check matrix is 7×2×m×z.

[2415] As illustrated in FIG. 81:

"a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×(2m-1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression";

"a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression";

"a vector for the 2×(2m+1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the 2×(2m+2)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2xi-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); first expression";

"a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); second expression" (where i is an integer no smaller than one and no greater than 2×m×z);

"a vector for the 2×(2m-1)×z-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)×zth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)×xz-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression"; and

"a vector for the 2×(2m)×zth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression".



[2416] To prepare for the explanation to be provided in the following, a mathematical expression is provided of the parity check matrix H in FIG. 81, which is a parity check matrix when configuring a periodic time-varying LDPC-CC by performing tail-biting by using only parity check polynomials satisfying zero for the LDPC-CC of coding rate 5/7 and time-varying period 2m that is based on a parity check polynomial, description of which is provided in embodiments E1 and E2. When denoting a vector having one row and 7×2×m×z columns in row k of the parity check matrix H as hk, the parity check matrix H in FIG. 81 is expressed as follows.
[Math. 459]



[2417] The following describes a parity check matrix for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[2418] FIG. 82 illustrates one example of a configuration of a parity check matrix Hpro for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[2419] The parity check matrix Hpro for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) satisfies Condition #N1.

[2420] When denoting a vector having one row and 7×2×m×z columns in row k of the parity check matrix Hpro in FIG. 82, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), as gk, the parity check matrix Hpro in FIG. 82 is expressed as follows.
[Math. 460]

A transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as vs=(Xs,1,1, Xs,2,1, ..., Xs,5,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,5,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,5,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,5,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λprο,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T (where k=1, 2, ..., 2×m×z-1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×Z)), and Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes).

[2421] Xs,j,k (where j is an integer no smaller than one and no greater than five) is a bit of information Xj, Ppros,1,k is a bit of parity P1 of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and Ppros,2,k is a bit of parity P2 of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[2422] In the parity check matrix Hpro in FIG. 82, which illustrates one example of a configuration of a parity check matrix Hpro for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), rows other than row one, or that is, rows between row two to row 2×(2×m)×z in the parity check matrix Hpro in FIG. 82, have the same configuration as rows between row two and row 2×(2×m)×z in the parity check matrix H in FIG. 81 (refer to FIGs. 81 and 82). Accordingly, FIG. 82 includes an indication of #0'; first expression at 4401 in the first row. (This point is explained later in the present disclosure.) Accordingly, the following relational expression holds true based on expressions 199 and 200.
[Math. 461]



[2423] Further, the following holds true when i=1.
[Math. 462]



[2424] Accordingly, the parity check matrix Hpro for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as follows.
[Math. 463]



[2425] In expression 203, expression 202 holds true.

[2426] Next, explanation is provided of a method of configuring g1 in expression 203 so that parities can be found sequentially and high error correction capability can be achieved.

[2427] One example of a method of configuring g1 in expression 203, so that parities can be found sequentially and high error correction capability can be achieved, is using a parity check polynomial satisfying zero of #0; first expression of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), which serves as the basis.

[2428] Since g1 is row one of the parity check matrix Hpro for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), g1 is generated from a parity check polynomial satisfying zero that is obtained by transforming a parity check polynomial satisfying zero of #0; first expression. As described above, a parity check polynomial satisfying zero of #0; first expression is expressed by either expression (204-1-1) or expression (204-1-2).
[Math. 464]







[2429] As one example of a parity check polynomial satisfying zero for generating vector g1 in row one of the parity check matrix Hpro for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), a parity check polynomial satisfying zero of #0; first expression is expressed as follows, for either expression (204-1-1) or expression (204-1-2).
[Math. 465]





[2430] Accordingly, vector g1 is a vector having one row and 7×2×m×z columns that is obtained by performing tail-biting with respect to expression 205.

[2431] Note that in the following, a parity check polynomial that satisfies zero provided by expression 205 is referred to as #0'; first expression.

[2432] Accordingly, row one of the parity check matrix Hpro for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be obtained by transforming #0'; first expression of expression 205 (that is, a vector g1 corresponding to one row and 7×2×m×z columns can be obtained).

[2433] A transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is vs=(Xs,1,1, Xs,2,1, ..., Xs,5,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,5,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,5,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,5,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)Tpro,s,1, λpro,s,2, ..., λprο,s,2×m×z-1, λpro,s,2×m×z)T, and the number of parity check polynomials satisfying zero necessary for obtaining this transmission sequence is 2×(2×m)×z.

[2434] Here, when arranging such 2×(2×m)×z number of parity check polynomials satisfying zero in order, a parity check polynomial satisfying zero appearing eth is referred to in the following as an "eth parity check polynomial satisfying zero" (where e is an integer no smaller than zero and no greater than 2×(2×m)×z-1).

[2435] As such, the parity check polynomials satisfying zero are arranged in the following order:

zeroth: zeroth parity check polynomial satisfying zero;

first: first parity check polynomial satisfying zero;

second: second parity check polynomial satisfying zero;

eth: eth parity check polynomial satisfying zero;

2×(2×m)×z-2th: 2×(2×m)×z-2th parity check polynomial satisfying zero; and

2×(2×m)×z-1th: 2×(2×m)×z-1th parity check polynomial satisfying zero.



[2436] Accordingly, the transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is obtained. (As can be seen from description provided above, when expressing the parity check matrix Hpro for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as provided in expression 200, a vector composed of row e+1 of the parity check matrix Hpro corresponds to the eth parity check polynomial satisfying zero.)

[2437] Accordingly, in the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the second parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the third parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression;

the 2×(2m)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression;

the 2×(2m+1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; first expression;

the 2×(2m+1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×(2m+2)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the 2×(2m+2)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression; and

the 2×(2m)xz-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression.



[2438] That is,
the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;
the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;
the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i- 1)%2m); first expression; and
the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).

[2439] As description has been provided above, the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), at the same time as achieving high error correction capability, enables finding multiple parities sequentially, and therefore, achieves an advantageous effect of reducing circuit scale of an encoder.

[2440] In the following, explanation is provided of what is meant by "finding parities sequentially".

[2441] In the example described above, since bits of information X1 through X5 are pre-acquired, Ppros,1,1 can be calculated by using the 0th parity check polynomial satisfying zero of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), or that is, by using the parity check polynomial satisfying zero of #0'; first expression provided by expression 205.

[2442] Then, from the bits of information X1 through X5 and Ppros,1,1, another parity (denoted as Pc=1) can be calculated by using another parity check polynomial satisfying zero.

[2443] Further, from the bits of information X1 through X5 and Pc=1, another parity (denoted as Pc=2) can be calculated by using another parity check polynomial satisfying zero.

[2444] By repeating such operation, from the bits of information X1 through X5 and Pc=h, another parity (denoted as Pc=h+1) can be calculated by using a given parity check polynomial satisfying zero.

[2445] This is referred to as "finding parities sequentially", and when parities can be found sequentially, multiple parities can be obtained without calculation of complex simultaneous equations, whereby an advantageous effect is achieved of reducing circuit scale (computation amount) of an encoder.

[2446] Next, explanation is provided of configurations and operations of an encoder and a decoder for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[2447] In the following, one example case is considered where the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is used in a communication system. When applying the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) to a communication system, the encoder and the decoder for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) are characterized for each being configured and each operating based on the parity check matrix Hpro for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and based on the relationship Hprovs=0.

[2448] The following provides explanation while referring to FIG. 25, which is an overall diagram of a communication system. An encoder 2511 of a transmitting device 2501 receives an information sequence of block s (Xs,1,1, Xs,2,1, ..., Xs,5,1, Xs,1,2, Xs,2,2, ..., Xs,5,2, ..., Xs,1,k, Xs,2,k, ..., Xs,5,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,5,2×m×z) as input. The encoder 2511 performs encoding based on the parity check matrix Hpro for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and based on the relationship Hprovs=0. The encoder 2511 generates a transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), denoted as vs=(Xs,1,1, Xs,2,1, ..., Xs,5,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,5,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,5,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,5,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T, and outputs the transmission sequence vs. As already described above, the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is characterized for enabling parities to be found sequentially.

[2449] A decoder 2523 of a receiving device 2520 in FIG. 25 receives, as input, a log-likelihood ratio of each bit of, for example, the transmission sequence vs=(Xs,1,1, Xs,2,1, ..., Xs,5,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,5,2, Ppros,1,2, Ps,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,5,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,5,2×m×z, Ppros,1,2×m×z, PPros,2,2×m×z)T. The log-likelihood ratios are output from a log-likelihood ratio generator 2522. The decoder 2523 performs decoding for an LDPC code according to the parity check matrix Hpro for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). For example, the decoding may be decoding disclosed in Non-Patent Literature 4, Non-Patent Literature 6, Non-Patent Literature 7, Non-Patent Literature 8, etc., i.e., simple BP decoding such as min-sum decoding, offset BP decoding, or Normalized BP decoding, or Belief Propagation (BP) decoding in which scheduling is performed with respect to the row operations (Horizontal operations) and the column operations (Vertical operations) such as Shuffled BP decoding or Layered BP decoding. The decoding may also be decoding such as bit-flipping decoding disclosed in Non-Patent Literature 17, for example. The decoder 2523 obtains an estimation transmission sequence (estimation encoded sequence) (reception sequence) of block s through the decoding, and outputs the estimation transmission sequence.

[2450] In the above, explanation is provided on operations of the encoder and the decoder in a communication system as one example. Alternatively, the encoder and the decoder may be used in technical fields related to storages, memories, etc.

[2451] The following describes a specific example of a configuration of a parity check matrix for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[2452] When denoting the parity check matrix for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as Hpro as described above, the number of columns of Hpro can be expressed as 7×2×m×z (where z is a natural number). (Note that m denotes a time-varying period of the LDPC-CC of coding rate 5/7 that is based on a parity check polynomial, which serves as the basis.)

[2453] Accordingly, as already described above, a transmission sequence (encoded sequence (codeword)) vs composed of a 7×2×m×z number of bits in block s of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as vs=(Xs,1,1, Xs,2,1, ..., Xs,5,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,5,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,5,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,5,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T (where k=1, 2, ..., 2×m×z-1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×z)), and Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes).

[2454] Xs,j,k (where j is an integer no smaller than one and no greater than five) is a bit of information Xj, Ppros,1,k is a bit of parity P1 of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and Ppros,2,k is a bit of parity P2 of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[2455] Further, λpro,s,k=(Xs,1,k, Xs,2,k, Xs,3,k, Xs,4,k, Xs,5,k, Ppros,1,k, Ppros,2,k) holds true.

[2456] In addition, the number of rows in the parity check matrix Hpro for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is 4×m×z.

[2457] Note that the method of configuring parity check polynomials satisfying zero for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) has already been described above.

[2458] In the above, description has been provided of a parity check matrix Hpro for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), whose transmission sequence (encoded sequence (codeword)) vs of block s is vs=(Xs,1,1, Xs,2,1, ..., Xs,5,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,5,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,5,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,5,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T and for which Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes). The following provides description of a configuration of a parity check matrix Hpro_m for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), for which Hpro_mus=0 holds true (here, Hpro_mus=0 indicates that all elements of the vector Hpro_mus are zeroes) when expressing a transmission sequence (encoded sequence (codeword)) us of block s as us=(Xs,1,1, Xs,1,2, ..., Xs,1,2×m×z-1, Xs,1,2×m×z, Xs,2,1, Xs,2,2, ..., Xs,2,2×m×z-1, Xs,2,2×m×z, Xs,3,1, Xs,3,2, ..., Xs,3,2×m×z-1, Xs,3,2×m×z, Xs,4,1, Xs,4,2, ..., Xs,4,2×m×z-1, Xs,4,2×m×z, Xs,5,1, Xs,5,2, ..., Xs,5,2×m×z-1, Xs,5,2×m×z, Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z, Ppros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, Ppros,2,2×m×z)T= (ΛX1,s, ΛX2,s, ΛX3,s, ΛX4,s, ΛX5,s, Λpro1,s, Λpro2,s)T.

[2459] Note that ΛXf,s (where f is an integer no smaller than one and no greater than five) satisfies ΛXf,s=(Xs,f,1, Xs,f,2, Xs,f,3, ..., Xs,f,2×m×z-2, Xs,f,2×m×z-1, Xs,f,2×m×z) (ΛXf,s is a vector having one row and 2×m×z columns), and Λpro1,s and Λpro2,s satisfy Λpro1,s=(Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z) and Λpro2,s=(Ppros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, Ppros,2,2×m×z), respectively (Λpro1,s and Λpro2,s are both vectors having one row and 2×m×z columns).

[2460] Here, the number of bits of information X1 included in one block is 2×m×z, the number of bits of information X2 included in one block is 2×m×z, the number of bits of information X3 included in one block is 2×m×z, the number of bits of information X4 included in one block is 2×m×z, the number of bits of information X5 included in one block is 2×m×z, the number of bits of parity bits P1 included in one block is 2×m×z, and the number of bits of parity bits P2 included in one block is 2×m×z. Accordingly, the parity check matrix Hpro_m for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as Hpro_m=[Hx,1, Hx,2, Hx,3, Hx,4, Hx,5, Hp1, Hp2], as illustrated in FIG. 83. Since a transmission sequence (encoded sequence (codeword)) us of block s is us=(Xs,1,1, Xs,1,2, ..., Xs,1,2×m×z-1, Xs,1,2×m×z, Xs,2,1, Xs,2,2, ..., Xs,2,2×m×z-1, Xs,2,2×m×z, Xs,3,1, Xs,3,2, ..., Xs,3,2×m×z-1, Xs,3,2×m×z, Xs,4,1, Xs,4,2, ..., Xs,4,2×m×z-1, Xs,4,2×m×z, Xs,5,1, Xs,5,2, ..., Xs,5,2×m×z-1, Xs,5,2×m×z, Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z, Ppros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, Ppros,2,2×m×z)T=(ΛX1,s, ΛX2,s, ΛX3,s, ΛX4,s, ΛX5,s, Λpro1,s, Λpro2,s)T, Hx,1 is a partial matrix related to information X1, Hx,2 is a partial matrix related to information X2, Hx,3 is a partial matrix related to information X3, Hx,4 is a partial matrix related to information X4, Hx,5 is a partial matrix related to information X5, Hp1 is a partial matrix related to parity P1, and Hp2 is a partial matrix related to parity P2. As illustrated in FIG. 83, the parity check matrix Hpro_m has 4×m×z rows and 7×2×m×z columns, the partial matrix Hx,1 related to information X1 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,2 related to information X2 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,3 related to information X3 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,4 related to information X4 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,5 related to information X5 has 4×m×z rows and 2×m×z columns, the partial matrix Hp1 related to parity P1 has 4×m×z rows and 2×m×z columns, and the partial matrix Hp2 related to parity P2 has 4×m×z rows and 2×m×z columns.

[2461] The transmission sequence (encoded sequence (codeword)) us composed of a 7×2×m×z number of bits in block s of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is us=(Xs,1,1, Xs,1,2, ..., Xs,1,2×m×z-1, Xs,1,2×m×z, Xs,2,1, Xs,2,2, ..., Xs,2,2×m×z-1, Xs,2,2×m×z, Xs,3,1, Xs,3,2, ..., Xs,3,2vm×z-1, Xs,3,2×m×z, Xs,4,1, Xs,4,2, ..., Xs,4,2×m×z-1, Xs,4,2×m×z, Xs,5,1, Xs,5,2, ..., Xs,5,2×m×z-1, Xs,5,2×m×z, Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z, Ppros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, Ppros,2,2×m×z)T=(ΛX1,s, ΛX2,s, ΛX3,s, ΛX4,s, ΛX5,s, Λpro1,s, Λpro2,s)T, and the number of parity check polynomials satisfying zero necessary for obtaining this transmission sequence is 4×m×z.

[2462] Here, when arranging such 2×(2×m)×z number of parity check polynomials satisfying zero in order, a parity check polynomial satisfying zero appearing eth is referred to in the following as an "eth parity check polynomial satisfying zero" (where e is an integer no smaller than zero and no greater than 2×(2×m)×z-1).

[2463] As such, the parity check polynomials satisfying zero are arranged in the following order:

zeroth: zeroth parity check polynomial satisfying zero;

first: first parity check polynomial satisfying zero;

second: second parity check polynomial satisfying zero;

eth: eth parity check polynomial satisfying zero;

2×(2×m)×z-2th: 2×(2×m)×z-2th parity check polynomial satisfying zero; and

2×(2×m)×z-1th: 2×(2×m)×z-1th parity check polynomial satisfying zero.



[2464] Accordingly, the transmission sequence (encoded sequence (codeword)) us of block s of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is obtained.

[2465] Accordingly, in the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the second parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the third parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression;

the 2×(2m)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression;

the 2×(2m+1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; first expression;

the 2×(2m+1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×(2m+2)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the 2×(2m+2)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression; and

the 2×(2m)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression.



[2466] That is,
the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;
the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;
the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression; and
the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).

[2467] In the present embodiment (in fact, commonly applying to the entirety of the present disclosure), % means a modulo, and for example, α%q represents a remainder after dividing α by q (where α is an integer no smaller than zero, and q is a natural number).

[2468] The following describes details of the configuration of the parity check matrix Hpro_m for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) based on what has been described above.

[2469] The parity check matrix Hpro_m for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) has 4×m×z rows and 7×2×m×z columns.

[2470] Accordingly, the parity check matrix Hpro_m for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) has rows one through 4×m×z, and columns one through 7×2×m×z.

[2471]  Here, the topmost row of the parity check matrix Hpro_m is considered as the first row. Further, row number is incremented by one each time moving to a lower row. Accordingly, the topmost row is considered as the first row, the row immediately below the first row is considered as the second row, and the subsequent rows are considered as the third row, the fourth row, and so on.

[2472] Further, the leftmost column of the parity check matrix Hpro_m is considered as the first column. Further, column number is incremented by one each time moving to a rightward column. Accordingly, the leftmost column is considered as the first column, the column immediately to the right of the first column is considered as the second column, and the subsequent columns are considered as the third column, the fourth column, and so on.

[2473] In the parity check matrix Hpro_m, the partial matrix Hx,1 related to information X1 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,1 related to information X1 is denoted as Hx,1,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[2474] Similarly, in the parity check matrix Hpro_m, the partial matrix Hx,2 related to information X2 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,2 related to information X2 is denoted as Hx,2,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[2475] Further, in the parity check matrix Hpro_m, the partial matrix Hx,3 related to information X3 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,3 related to information X3 is denoted as Hx,3,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[2476] Further, in the parity check matrix Hpro_m, the partial matrix Hx,4 related to information X4 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,4 related to information X4 is denoted as Hx,4,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[2477] Further, in the parity check matrix Hpro_m, the partial matrix Hx,5 related to information X5 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,5 related to information X5 is denoted as Hx,5,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[2478] Further, in the parity check matrix Hpro_m, the partial matrix Hp,1 related to parity P1 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hp,1 related to parity P1 is denoted as Hp1,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[2479]  Similarly, in the parity check matrix Hpro_m, the partial matrix Hp,2 related to parity P2 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hp,2 related to parity P2 is denoted as Hp2,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[2480] The following provides detailed description of the configuration of Hx,1,comp[u][v], Hx,2,comp[u][v], Hx,3,comp[u][v], Hx,4,comp[u][v], Hx,5,comp[u][v], Hp1,comp[u][v], and Hp2,comp[u][v].

[2481] As already described above, in the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the second parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the third parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression;

the 2×(2m)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression;

the 2×(2m+1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; first expression;

the 2×(2m+1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×(2m+2)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the 2×(2m+2)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression; and

the 2×(2m)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression.



[2482] That is,
the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;
the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;
the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression; and
the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).

[2483] Further, a vector composed of row e+1 of the parity check matrix Hpro_m corresponds to the eth parity check polynomial satisfying zero.

[2484] Accordingly,
a vector composed of row one of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;
a vector composed of row two of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0; second expression;
a vector composed of row 2×g-1 of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); first expression; and
a vector composed of row 2×g of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); second expression (where g is an integer no smaller than two and no greater than 2×m×z).

[2485] Hx,1,comp[u][v], Hx,2,comp[u][v], Hx,3,comp[u][v], Hx,4,comp[u][v], Hx,5,comp[u][v], Hp1,comp[u][v], and Hp2,comp[u][v] can be expressed according to the relationship described above.

[2486] First, description is provided of the configuration of Hx,1,comp[u][v], Hx,2,comp[u][v], Hx,3,comp[u][v], Hx,4,comp[u][v], Hx,5,comp[u][v], Hp1,comp[u][v], and Hp2,comp[u][v] for row one of the parity check matrix Hpro_m, or that is, for u=1.

[2487] The vector composed of row one of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0'; first expression provided by expression 205. Accordingly, Hx,1,comp[1][v] can be expressed as follows.
[Math. 466]



[2488] Considered in a similar manner, the following holds true for Hx,w,comp[1][v], where w is an integer no smaller than one and no greater than two.
[Math. 467]



[2489] Further, Hx3,comp[1][v] can be expressed as follows.
[Math. 468]





[2490] Considered in a similar manner, the following holds true for HxΩ,comp[1][v]. In the following, Ω is an integer no smaller than three and no greater than five.
[Math. 469]



[2491] Further, Hp1,comp[1][v] can be expressed as follows.
[Math. 470]



[2492] Further, Hp2,comp[1][v] can be expressed as follows.
[Math. 471]



[2493] The vector composed of row two of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0; second expression. As described above, a parity check polynomial satisfying zero of #0; second expression is expressed by either expression (197-2-1) or expression (197-2-2).

[2494] Accordingly, Hx,1,comp[2][v] can be expressed as follows.
  1. <1> When a parity check polynomial satisfying zero of #0; second expression is expressed as provided in expression (197-2-1):
    Hx,1,comp[2][v] is expressed as follows.
    [Math. 472]


    Considered in a similar manner, the following holds true for Hx,Ω,comp[2][v], where Ω is an integer no smaller than one and no greater than two.
    [Math. 473]


    Further, Hx,3,comp[2][v] is expressed as follows.
    [Math. 474]


    Considered in a similar manner, the following holds true for Hx,w,comp[2][v], where w is an integer no smaller than three and no greater than five.
    [Math. 475]




    Further, Hp1,comp[2][v] can be expressed as follows.
    [Math. 476]


    Further, Hp2,comp[2][v] can be expressed as follows.
    [Math. 477]

  2. <2> When a parity check polynomial satisfying zero of #0; second expression is expressed as provided in expression (197-2-2):
    Hx,1,comp[2][v] is expressed as follows.
    [Math. 478]





[2495] Considered in a similar manner, the following holds true for Hx,Ω,comp[2][v], where Ω is an integer no smaller than one and no greater than two.
[Math. 479]



[2496] Further, Hx,3,comp[2][v] is expressed as follows.
[Math. 480]



[2497] Considered in a similar manner, the following holds true for Hx,w,comp[2][v], where w is an integer no smaller than three and no greater than five.
[Math. 481]





[2498] Further, Hp1,comp[2][v] can be expressed as follows.
[Math. 482]



[2499] Further, Hp2,comp[2][v] can be expressed as follows.
[Math. 483]



[2500] As already described above,
the vector composed of row 2×g-1 of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); first expression; and
the vector composed of row 2×g of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); second expression (where g is an integer no smaller than two and no greater than 2×m×z).

[2501] Accordingly, when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), a vector of row 2×(2×f-1)-1 of the parity check matrix Hpro_m for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); first expression, or that is, by using a parity check polynomial satisfying zero provided by expression (197-1-1) or expression (197-1-2).

[2502] Further, a vector of row 2×(2×f-1) of the parity check matrix Hpro_m for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); second expression, or that is, by using a parity check polynomial satisfying zero provided by expression (197-2-1) or expression (197-2-2).

[2503]  Further, when g=2×f (where f is an integer no smaller than one and no greater than m×z), a vector of row 2×(2×f)-1 of the parity check matrix Hpro_m for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f)-1)%2m); first expression, or that is, by using a parity check polynomial satisfying zero provided by expression (198-1-1) or expression (198-1-2).

[2504] Further, a vector of row 2×(2×f) of the parity check matrix Hpro_m for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f)-1)%2m); second expression, or that is, by using a parity check polynomial satisfying zero provided by expression (198-2-1) or expression (198-2-2).

[2505] Accordingly, (1) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (197-1-1), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (197-1-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2506] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f-1)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f-1)-1][v], Hx,3,comp[2×g-1][v]=Hx,3,comp[2×(2×f-1)-1][v], Hx,4,comp[2×g-1][v]=Hx,4,comp[2×(2×f-1)-1][v], Hx,5,comp[2×g-1][v]=Hx,5,comp[2×(2×f-1)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f-1)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[2507] First, the following holds true for Hx,1,comp[2×(2×f-1)-1][v].
[Math. 484]





[2508] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f-1)-1][v]. In the following, w is an integer no smaller than one and no greater than two.
[Math. 485]



[2509] Further, the following holds true for Hx,3,comp[2×(2×f-1)-1][v]. In the following, y is an integer no smaller than R#(2c),3+1 and no greater than r#(2c),3.
[Math. 486]



[2510] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f-1)-1][v]. In the following, Ω is an integer no smaller than three and no greater than five, and y is an integer no smaller than K#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 487]



[2511] Further, the following holds true for Hp1,comp[2×(2×f-1)-1][v].
[Math. 488]



[2512] Further, the following holds true for Hp2,comp[2×(2×f-1)-1][v].
[Math. 489]



[2513] Further, (2) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (197-1-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (197-1-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2514] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f-1)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f-1)-1][v], Hx,3,comp[2×g-1][v]=Hx,3,comp[2×(2×f-1)-1][v], Hx,4,comp[2×g-1][v]=Hx,4,comp[2×(2×f-1)-1][v], Hx,5,comp[2×g-1][v]=Hx,5,comp[2×(2×f-1)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f-1)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[2515] First, the following holds true for Hx,1,comp[2×(2×f-1)-1][v]
[Math. 490]



[2516] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f-1)-1][v]. In the following, w is an integer no smaller than one and no greater than two.
[Math. 491]





[2517] Further, the following holds true for Hx,3,comp[2×(2×f-1)-1][v]. In the following, y is an integer no smaller than R#(2c),3+1 and no greater than r#(2c),3.
[Math. 492]



[2518] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f-1)-1][v]. In the following, Ω is an integer no smaller than three and no greater than five, and y is an integer no smaller than R#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 493]



[2519] Further, the following holds true for Hp1,comp[2×(2×f-1)-1][v].
[Math. 494]



[2520] Further, the following holds true for Hp2,comp[2×(2×f-1)-1][v].
[Math. 495]



[2521] Further, (3) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (197-2-1), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (197-2-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2522] Accordingly, components Hx,1,comp[2×g][v]=Hx,1,comp[2×(2×f-1)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2×f-1)][v], Hx,3,comp[2×g][v]=Hx,3,comp[2×(2×f-1[v], Hx,4,comp[2×g][v]=Hx,4,comp[2×(2×f-1)][v], Hx,5,comp[2×g][v]=Hx,s,comp[2×(2×f-1)][v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f-1)][v], and Hp2,comp[2×g][v]=Hp2,comp[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[2523] First, the following holds true for Hx,1,comp[2×(2×f-1)][v]. In the following, y is an integer no smaller than R#(2c),1+1 and no greater than r#(2c),1.
[Math. 496]



[2524] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f-1)][v]. In the following, Ω is an integer no smaller than one and no greater than two, and y is an integer no smaller than P#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 497]



[2525] Further, the following holds true for Hx,3,comp[2×(2×f-1)][v].
[Math. 498]





[2526] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f-1)][v]. In the following, w is an integer no smaller than three and no greater than five.
[Math. 499]



[2527] Further, the following holds true for Hp1,comp[2×(2×f-1)][v].
[Math. 500]



[2528] Further, the following holds true for Hp2,comp[2×(2×f-1)][v].
[Math. 501]



[2529] Further, (4) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (197-2-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (197-2-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2530] Accordingly, components Hx,1,comp[2×g][v]=Hx,1,comp[2×(2×f-1)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2×f-1)][v], Hx,3,comp[2×g][v]=Hx,3,comp[2×(2×f-1)][v], Hx,4,comp[2×g][v]=Hx,4,comp[2×(2×f-1)][v], Hx,5,comp[2×g][v]=Hx,5,comp[2×(2×f-1)][v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f-1)][v], and Hp2,comp[2×g][v]=Hp2,comp[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[2531] First, the following holds true for Hx,1,comp[2×(2×f-1)][v]. In the following, y is an integer no smaller than R#(2c),1+1 and no greater than r#(2c),1.
[Math. 502]



[2532] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f-1)][v]. In the following, Ω is an integer no smaller than one and no greater than two, and y is an integer no smaller than R#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 503]



[2533] Further, the following holds true for Hx,3,comp[2×(2×f-1)][v].
[Math. 504]



[2534] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f-1)][v]. In the following, w is an integer no smaller than three and no greater than five.
[Math. 505]





[2535] Further, the following holds true for Hp1,comp[2×(2×f-1)][v].
[Math.506]



[2536] Further, the following holds true for Hp2,comp[2×(2×f-1)][v].
[Math. 507]



[2537] Further, (5) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (198-1-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (198-1-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2538] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f)-1][v], Hx,3,comp[2×g-1][v]=Hx,3,comp[2×(2×f)-1][v], Hx,4,comp[2×g-1][v]=Hx,4,comp[2×(2×f)-1][v], Hx,5,comp[2×g-1][v]=Hx,5,comp[2×(2×f)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[2539] First, the following holds true for Hx,1,comp[2×(2×f)-1][v]. In the following, y is an integer no smaller than R#(2d+1),1+1 and no greater than r#(2d+1),1.
[Math. 508]



[2540] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f)-1)][v]. In the following, Ω is an integer no smaller than one and no greater than two, and y is an integer no smaller than R#(2d+1),Ω+1 and no greater than r#(2d+1),Ω.
[Math. 509]





[2541] Further, the following holds true for Hx,3,comp[2×(2×f)-1][v].
[Math. 510]



[2542] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f)-1][v]. In the following, w is an integer no smaller than three and no greater than five.
[Math. 511]



[2543] Further, the following holds true for Hp1,comp[2×(2×f)-1][v].
[Math. 512]



[2544] Further, the following holds true for Hp2,comp[2×(2×f)-1][v].
[Math. 513]



[2545] Further, (6) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (198-1-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (198-1-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2546] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f)-1][v], Hx,3,comp[2×g-1][v]=Hx,3,comp[2×(2×f)-1][v], Hx,4,comp[2×g-1][v]=Hx,4,comp[2×(2×f)-1][v], Hx,5,comp[2×g-1][v]=Hx,5,comp[2×(2×f)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[2547] First, the following holds true for Hx,1,comp[2×(2×f)-1][v]. In the following, y is an integer no smaller than R#(2d+1),1+1 and no greater than r#(2d+1),1.
[Math. 514]



[2548] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f)-1)][v]. In the following, Ω is an integer no smaller than one and no greater than two, and y is an integer no smaller than R#(2d+1),Ω+1 and no greater than r#(2d+1),Ω.
[Math. 515]



[2549] Further, the following holds true for Hx,3,comp[2×(2×f)-1][v].
[Math. 516]





[2550] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f)-1][v]. In the following, w is an integer no smaller than three and no greater than five.
[Math. 517]



[2551] Further, the following holds true for Hp1,comp[2×(2×f)-1][v].
[Math. 518]



[2552] Further, the following holds true for Hp2,comp[2×(2×f)-1][v].
[Math. 519]



[2553] Further, (7) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (198-2-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (198-2-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2554] Accordingly, components Hx,1,comp[2×g][v]=Hx,1,comp[2×(2×f)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2×f)][v], Hx,3,comp[2×g][v]=Hx,3,comp[2×(2×f)][v], Hx,4,comp[2×g][v]=Hx,4,comp[2×(2×f)][v], Hx,5,comp[2×g][v]=Hx,5,comp[2×(2×f)][v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f)][v] and Hp2,comp[2×g][v]=Hp2,comp[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[2555] The following holds true for Hx,1,comp[2×(2×f)][v].
[Math. 520]



[2556] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f)][v]. In the following, w is an integer no smaller than one and no greater than two.
[Math. 521]



[2557] Further, the following holds true for Hx,3,comp[2×(2×f)][v]. In the following, y is an integer no smaller than R#(2d+1),3+1 and no greater than r#(2d+1),3.
[Math. 522]



[2558] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f)][v]. In the following, Ω is an integer no smaller than three and no greater than five, and y is an integer no smaller than R#(2d+1),Ω+1 and no greater than r#(2d+1),Ω.
[Math. 523]





[2559] Further, the following holds true for Hp1,comp[2×(2×f)][v].
[Math. 524]



[2560] Further, the following holds true for Hp2,comp[2×(2×f)][v].
[Math. 525]



[2561] Further, (8) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (198-2-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (198-2-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2562] Accordingly, components Hx,1,comp[2×g][v]=Hx,1,comp[2×(2×f)][v], Hx,2,comp[2×g][v]=Hx,comp[2×(2×f)][v], Hx,3,comp[2×g][v]=Hx,3,comp[2×(2×f)][v], Hx,4,comp[2×g][v]=Hx,4,comp[2×(2×f)][v], Hx,5,comp[2×g][v]=Hx,5,comp[2×(2×f)][v], Hp1,comp[2×g][V]=Hp1,comp[2×(2×f)][v], and Hp2,comp[2×g][v]=Hp2,comp[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[2563] The following holds true for Hx,1,comp[2×(2×f)][v].
[Math. 526]



[2564] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f)][v]. In the following, w is an integer no smaller than one and no greater than two.
[Math. 527]



[2565] Further, the following holds true for Hx,3,comp[2×(2×f)][v]. In the following, y is an integer no smaller than R#(2d+1),3+1 and no greater than r#(2d+1),3.
[Math. 528]



[2566] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f)][v]. In the following, Ω is an integer no smaller than three and no greater than five, and y is an integer no smaller than R#(2d+1),Ω+1 and no greater than r#(2d+1),Ω.
[Math. 529]



[2567] Further, the following holds true for Hp1,comp[2×(2×f)][v].
[Math. 530]



[2568] Further, the following holds true for Hp2,comp[2×(2×f)][v].
[Math. 531]



[2569] An LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated as described above, and the code so generated achieves high error correction capability.

[2570] In the above, parity check polynomials satisfying zero for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) are set as follows:

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression; and

the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).



[2571] Based on this, the following method is conceivable as a configuration where usage of parity check polynomials satisfying zero is limited.

[2572] In this configuration, parity check polynomials satisfying zero for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) are set as follows:

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression provided by expression (197-2-1);

the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression provided by expression (197-1-1) or expression (198-1-1); and

the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression provided by expression (197-2-1) or expression (198-2-1) (where i is an integer no smaller than two and no greater than 2×m×z).



[2573] Accordingly, in the parity check matrix Hpro_m for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the vector composed of row one of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the vector composed of row two of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0; second expression provided by expression (197-2-1);

the vector composed of row 2×g-1 of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); first expression provided by expression (197-1-1) or expression (198-1-1); and

the vector composed of row 2×g of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); second expression provided by expression (197-2-1) or expression (198-2-1) (where g is an integer no smaller than two and no greater than 2×m×z).

Note that when making such a configuration, the above-described method of configuring the parity check matrix Hpro for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is applicable.



[2574] Such a method also enables generating a code with high error correction capability.

(Embodiment E5)



[2575] In embodiment E4, description is provided of an LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and a method of configuring a parity check matrix for the code.

[2576] With regards to parity check matrices for low density parity check (block) codes, one example of which is the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), a parity check matrix equivalent to a parity check matrix defined for a given LDPC code can be generated by using the parity check matrix defined for the given LDPC code.

[2577]  For example, a parity check matrix equivalent to the parity check matrix Hpro_m described in embodiment E4, which is for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using the parity check matrix Hpro_m.

[2578] The following describes a method of generating a parity check matrix equivalent to a parity check matrix defined for a given LDPC by using the parity check matrix defined for the given LDPC code.

[2579] Note that the method of generating an equivalent parity check matrix described in the present embodiment is not only applicable to the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) described in embodiment E4, but also is widely applicable to LDPC codes in general.

[2580] FIG. 31 illustrates the configuration of a parity check matrix H for an LDPC (block) code of coding rate (N-M)/N (N>M>0). For example, the parity check matrix of FIG. 31 has M rows and N columns. Here, to provide a general description, the parity check matrix H in FIG. 31 is considered to be a parity check matrix for defining an LDPC (block) code #A of coding rate (N-M)/N (N>M>0).

[2581] In FIG. 31, a transmission sequence (codeword) for block j is vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) (for systematic codes, Yj,k (where k is an integer no smaller than one and no greater than N) is information X or parity P (parity Ppro)).

[2582] Here, Hvj=0 holds true (where the zero in Hvj=0 indicates that all elements of the vector Hvj are zeroes. That is, row k of the vector Hvj has a value of zero for all k (where k is an integer no smaller than one and no greater than M)).

[2583] Then, an element of row k (where k is an integer no smaller than one and no greater than N) of the transmission sequence vj of block j (in FIG. 31, an element of column k in the transpose matrix vjT of the transmission sequence vj) is Yj,k, and a vector obtained by extracting column k of the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) can be expressed as ck, as illustrated in FIG. 31. Here, the parity check matrix H is expressed as follows.
[Math. 532]



[2584] FIG. 32 illustrates a configuration when interleaving is applied to the transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j. In FIG. 32, an encoding section 3202 receives information 3201 as input, performs encoding thereon, and outputs encoded data 3203. For example, when encoding the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), the encoder 3202 receives information in block j as input, performs encoding thereon based on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), and outputs the transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j.

[2585] Then, an accumulation and reordering section (interleaving section) 3204 receives the encoded data 3203 as input, accumulates the encoded data 3203, performs reordering thereon, and outputs interleaved data 3205. Accordingly, the accumulation and reordering section (interleaving section) 3204 receives the transmission sequence vj=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N)T of block j as input, and outputs a transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T, which is illustrated in FIG. 32, as a result of reordering being performed on the elements of the transmission sequence vj (v'j being an example). Here, as discussed above, the transmission sequence v'j is obtained by reordering the elements of the transmission sequence vj of block j. Accordingly, v'j is a vector having one row and n columns, and the N elements of v'j are such that one each of the terms Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N is present.

[2586] Here, an encoding section 3207 as shown in FIG. 32 having the functions of the encoding section 3202 and the accumulation and reordering section (interleaving section) 3204 is considered. Accordingly, the encoding section 3207 receives the information 3201 as input, performs encoding thereon, and outputs the encoded data 3203. For example, the encoding section 3207 receives information in block j as input, and as shown in FIG. 32, outputs the transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T. In the following, explanation is provided of a parity check matrix H' for the LDPC (block) code of coding rate (N-M)/N (N>M>0) corresponding to the encoding section 3207 (i.e., a parity check matrix H' that is equivalent to the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0)), while referring to Fig. 33. (Needless to say, the parity check matrix H' is a parity check matrix for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0).)

[2587] FIG. 33 shows a configuration of the parity check matrix H', which is a parity check matrix equivalent to the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), when the transmission sequence (codeword) is v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T. Here, an element of row one of the transmission sequence v'j of block j (an element of column one in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) is Yj,32. Accordingly, a vector obtained by extracting column one of the parity check matrix H', when using the above-described vector ck (k=1, 2, 3, ..., N-2, N-1, N), is c32. Similarly, an element of row two of the transmission sequence v'j of block j (an element of column two in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) is Yj,99. Accordingly, a vector obtained by extracting column two of the parity check matrix H' is c99. Further, as shown in FIG. 33, a vector obtained by extracting column three of the parity check matrix H' is c23, a vector obtained by extracting column N-2 of the parity check matrix H' is c234, a vector obtained by extracting column N-1 of the parity check matrix H' is c3, and a vector obtained by extracting column N of the parity check matrix H' is c43.

[2588] That is, when denoting an element of row i of the transmission sequence v'j of block j (an element of column i in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) as Yj,g (where g=1, 2, 3, ..., N-1, N-1, N), then a vector obtained by extracting column i of the parity check matrix H' is cg, when using the vector ck described above.

[2589] Accordingly, the parity check matrix H' for transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T is expressed as follows.
[Math. 533]



[2590] When denoting an element of row i of the transmission sequence v'j of block j (an element of column i in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) as Yj,g (where g=1, 2, 3, ..., N-1, N-1, N), a vector obtained by extracting column i of the parity check matrix H' is cg, when using the vector ck described above. When the above is followed to create a parity check matrix, then a parity check matrix for the transmission sequence v'j of block j can be obtained with no limitation to the above-given example.

[2591] Accordingly, when interleaving is applied to the transmission sequence (codeword) of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), a matrix for the interleaved transmission sequence is obtained by performing reordering of columns (column permutation) as described above on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0).

[2592] As such, it naturally follows that the transmission sequence (codeword) (vj) obtained by reverting the interleaved transmission sequence (codeword) (v'j) to its original order is the transmission sequence (codeword) of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Accordingly, by reverting the interleaved transmission sequence (codeword) (v'j) and a parity check matrix H' corresponding to the interleaved transmission sequence (codeword) (v'j) to their respective orders, the transmission sequence vj and a parity check matrix corresponding to the transmission sequence vj can be obtained, respectively. Further, the parity check matrix obtained by performing the reordering as described above is the parity check matrix H in FIG. 31, description of which has been provided above.

[2593] FIG. 34 illustrates an example of a decoding-related configuration of a receiving device, when encoding of FIG. 32 has been performed. The transmission sequence obtained when the encoding of FIG. 32 is performed undergoes processing such as mapping in accordance with a modulation scheme, frequency conversion, and modulated signal amplification, whereby a modulated signal is obtained. A transmitting device transmits the modulated signal. The receiving device then receives the modulated signal transmitted by the transmitting device to obtain a received signal. A log-likelihood ratio calculation section 3400 illustrated in FIG. 34 takes the received signal as input, calculates a log-likelihood ratio for each bit of the codeword, and outputs a log-likelihood ratio signal 3401.

[2594] For example, assume that the transmitting device transmits a transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T of block j. Then, the log-likelihood ratio calculation section 3400 calculates, from the received signal, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, and outputs the log-likelihood ratios.

[2595] An accumulation and reordering section (deinterleaving section) 3402 receives the log-likelihood ratio signal 3401 as input, performs accumulation and reordering thereon, and outputs a deinterleaved log-likelihood ratio signal 3403.

[2596] For example, the accumulation and reordering section (deinterleaving section) 3402 receives, as input, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, performs reordering, and outputs the log-likelihood ratios in the order of: the log-likelihood ratio for Yj,1, the log-likelihood ratio for Yj,2, the log-likelihood ratio for Yj,3, ..., the log-likelihood ratio for Yj,N-2, the log-likelihood ratio for Yj,N-1, and the log-likelihood ratio for Yj,N in the stated order.

[2597] A decoder 3404 receives the deinterleaved log-likelihood ratio signal 3403 as input, performs belief propagation (BP) decoding as disclosed in Non-Patent Literature 6 to 8, such as sum-product decoding, min-sum decoding, offset BP decoding, normalized BP decoding, shuffled BP decoding, and layered BP decoding in which scheduling is performed, based on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 31, and thereby obtains an estimation sequence 3405 (note that decoding schemes other than belief propagation decoding may be used).

[2598] For example, the decoder 3404 receives, as input, the log-likelihood ratio for Yj,1, the log-likelihood ratio for Yj,2, the log-likelihood ratio for Yj,3, ..., the log-likelihood ratio for Yj,N-2, the log-likelihood ratio for Yj,N-1, and the log-likelihood ratio for Yj,N in the stated order, performs belief propagation decoding based on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 31, and obtains the estimation sequence (note that decoding schemes other than belief propagation decoding may be used).

[2599] The following describes a decoding-related configuration that differs from that described above. The decoding-related configuration described in the following differs from the decoding-related configuration described above in that the accumulation and reordering section (deinterleaving section) 3402 is not included. The operations of the log-likelihood ratio calculation section 3400 are similar to those described above, and thus, explanation thereof is omitted in the following.

[2600] For example, assume that the transmitting device transmits a transmission sequence (codeword) v'j =(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T of block j. Then, the log-likelihood ratio calculation section 3400 calculates, from the received signal, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, and outputs the log-likelihood ratios (corresponding to 3406 in FIG. 34).

[2601] A decoder 3407 receives the log-likelihood ratio signal 3406 for each bit as input, performs belief propagation (BP) decoding as disclosed in Non-Patent Literature 6 to 8, such as sum-product decoding, min-sum decoding, offset BP decoding, normalized BP decoding, shuffled BP decoding, and layered BP decoding in which scheduling is performed, based on the parity check matrix H' for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 33, and thereby obtains an estimation sequence 3409 (note that decoding schemes other than belief propagation decoding may be used).

[2602] For example, the decoder 3407 receives, as input, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43 in the stated order, performs belief propagation decoding based on the parity check matrix H' for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 33, and obtains the estimation sequence (note that decoding schemes other than belief propagation decoding may be used).

[2603] As explained above, even when the transmitted data is reordered due to the transmitting device interleaving the transmission sequence vj=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N)T of block j, the receiving device is able to obtain the estimation sequence by using a parity check matrix corresponding to the reordered transmitted data.

[2604] Accordingly, when interleaving is applied to the transmission sequence (codeword) of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), a parity check matrix for the interleaved transmission sequence (codeword) is obtained by performing reordering of columns (i.e., column permutation) as described above on the parity check matrix for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). As such, the receiving device is able to perform belief propagation decoding and thereby obtain an estimation sequence without performing interleaving on the log-likelihood ratio for each acquired bit.

[2605] Note that in the above, explanation is provided of the relation between interleaving applied to a transmission sequence and a parity check matrix. In the following, explanation is provided of reordering of rows (row permutation) performed on a parity check matrix.

[2606] FIG. 35 illustrates a configuration of a parity check matrix H corresponding to a transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). For example, the parity check matrix H of FIG. 35 is a matrix having M rows and N columns. (for systematic codes, Yj,k (where k is an integer no smaller than one and no greater than N) is information X or parity P (parity Ppro), and is composed of (N-M) information bits and M parity bits). Here, Hvj = 0 holds true. (Here, the zero in Hvj = 0 indicates that all elements of the vector Hvj are zeroes. That is, row k of the vector Hvj has a value of zero for all k (where k is an integer no smaller than one and no greater than M.)

[2607] Further, a vector obtained by extracting column k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 35 is denoted as zk. Then, the parity check matrix H for the LDPC (block) code is expressed as follows.
[Math. 534]



[2608] Next, a parity check matrix obtained by performing reordering of rows (row permutation) on the parity check matrix H of FIG. 35 is considered.

[2609] FIG. 36 shows an example of a parity check matrix H' obtained by performing reordering of rows (row permutation) on the parity check matrix H of FIG. 35. The parity check matrix H', similar to the parity check matrix shown in FIG. 35, is a parity check matrix corresponding to the transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0).

[2610] The parity check matrix H' of FIG. 36 is composed of vectors zk obtained by extracting row k (where k is an integer no smaller one and no greater than M) of the parity check matrix H of FIG. 35. For example, in the parity check matrix H', the first row is composed of vector z130, the second row is composed of vector z24, the third row is composed of vector z45, ..., the (M-2)th row is composed of vector z33, the (M-1)th row is composed of vector z9, and the Mth row is composed of vector z3. Note that each of the M row-vectors obtained by extracting row k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H' is such that one each of z1, z2, z3, ... zM-2, zM-1, and zM is present.

[2611] Here, the parity check matrix H' for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) is expressed as follows.
[Math. 535]



[2612] Further, H'vj = 0 holds true. (Here, the zero in H'vj = 0 indicates that all elements of the vector H'vj are zeroes. That is, row k of the vector H'vj has a value of zero for all k (where k is an integer no smaller than one and no greater than M.)

[2613] That is, for the transmission sequence VjT of block j, a vector obtained by extracting row i of the parity check matrix H' in FIG. 36 is expressed as ck (where k is an integer no smaller than one and no greater than M), and each of the M row vectors obtained by extracting row k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H' in FIG. 36 is such that one each of z1, z2, z3, ... zM-2, zM-1, and zM is present.

[2614] As described above, for the transmission sequence VjT of block j, a vector obtained by extracting row i of the parity check matrix H' in FIG. 36 is expressed as ck (where k is an integer no smaller than one and no greater than M), and each of the M row vectors obtained by extracting row k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H' in FIG. 36 is such that one each of z1, z2, z3, ... zM-2, zM-1, and zM is present. Note that, when the above is followed to create a parity check matrix, then a parity check matrix for the transmission sequence parity vj of block j can be obtained with no limitation to the above-given example.

[2615] Accordingly, even when the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) is being used, it does not necessarily follow that a transmitting device and a receiving device are using the parity check matrix H. As such, a transmitting device and a receiving device may use as a parity check matrix, for example, a matrix obtained by performing reordering of columns (column permutation) as described above on the parity check matrix H or a matrix obtained by performing reordering of rows (row permutation) on the parity check matrix H.

[2616] In addition, a matrix obtained by performing both reordering of columns (column permutation) and reordering of rows (row permutation) as described above on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) may be used as a parity check matrix.

[2617]  In such a case, a parity check matrix H1 is obtained by performing reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H2 is obtained by performing reordering of rows (row permutation) on the parity check matrix H1 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). A transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H2 so obtained.

[2618] Also, a parity check matrix H1,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H2,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix H1,1 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36).

[2619] Further, a parity check matrix H1,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H2,1. Finally, a parity check matrix H2,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H1,2.

[2620] As described above, a parity check matrix H2,s may be obtained by repetitively performing reordering of columns (column permutation) and reordering of rows (row permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H1,k is obtained by performing a kth (where k is an integer no smaller than two and no greater than s) reordering of columns (column permutation) on a parity check matrix H2,k-1. Then, a parity check matrix H2,k is obtained by performing a kth reordering of rows (row permutation) on the parity check matrix H1,k. Note that in the first instance, a parity check matrix H1,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H2,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H1,1.

[2621] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H2,s.

[2622] In an alternative method, a parity check matrix H3 is obtained by performing reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H4 is obtained by performing reordering of columns (column permutation) on the parity check matrix H3 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H4 so obtained.

[2623] Also, a parity check matrix H3,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H4,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix H3,1 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33).

[2624] Then, a parity check matrix H3,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H4,1. Finally, a parity check matrix H4,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H3,2.

[2625] As described above, a parity check matrix H4,s may be obtained by repetitively performing reordering of rows (row permutation) and reordering of columns (column permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H3,k is obtained by performing a kth (where k is an integer no smaller two and no greater than s) reordering of rows (row permutation) on a parity check matrix H4,k-1. Then, a parity check matrix H4,k is obtained by performing a kth reordering of columns (column permutation) on the parity check matrix H3,k. Note that in the first instance, a parity check matrix H3,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H4,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H3,1.

[2626] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H4,s.

[2627] Here, note that by performing reordering of rows (row permutation) and reordering of columns (column permutation), the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) can be obtained from each of the parity check matrix H2, the parity check matrix H2,s, the parity check matrix H4, and the parity check matrix H4,s,.

[2628] Similarly, a matrix obtained by performing both reordering of columns (column permutation) as described above and reordering of rows (row permutation) as described above on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) may be used as a parity check matrix.

[2629] In such a case, a parity check matrix H5 is obtained by performing reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H6 is obtained by performing reordering of rows (row permutation) on the parity check matrix H5 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). A transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H6 so obtained.

[2630] Also, a parity check matrix H5,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H6,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix H5,1 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36).

[2631] Further, a parity check matrix H5,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H6,1. Finally, a parity check matrix H6,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H5,2.

[2632] As described above, a parity check matrix H6,s may be obtained by repetitively performing reordering of columns (column permutation) and reordering of rows (row permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H5,k is obtained by performing a kth (where k is an integer no smaller than two and no greater than s) reordering of columns (column permutation) on a parity check matrix H6,k-1. Then, a parity check matrix H6,k is obtained by performing a kth reordering of rows (row permutation) on the parity check matrix H5,k. Note that in the first instance, a parity check matrix H5,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H6,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H5,1

[2633] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H6,s.

[2634]  In an alternative method, a parity check matrix H7 is obtained by performing reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H8 is obtained by performing reordering of columns (column permutation) on the parity check matrix H7 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H8 so obtained.

[2635] Also, a parity check matrix H7,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H8,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix H7,1 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33).

[2636] Then, a parity check matrix H7,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H8,1. Finally, a parity check matrix H8,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H7,2.

[2637] As described above, a parity check matrix H8,s may be obtained by repetitively performing reordering of rows (row permutation) and reordering of columns (column permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H7,k is obtained by performing a kth (where k is an integer no smaller two and no greater than s) reordering of rows (row permutation) on a parity check matrix H8,k-1. Then, a parity check matrix H8,k is obtained by performing a kth reordering of columns (column permutation) on the parity check matrix H7,k. Note that in the first instance, a parity check matrix H7,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H8,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H7,1.

[2638] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H8,s.

[2639] Here, note that by performing reordering of rows (row permutation) and reordering of columns (column permutation), the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) can be obtained from each of the parity check matrix H6, the parity check matrix H6,s, the parity check matrix H8, and the parity check matrix H8,s,.

[2640] In the present embodiment, description is provided of a method of generating a parity check matrix equivalent to a parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) by performing reordering of rows (row permutation) and/or reordering of columns (column permutation) with respect to the parity check matrix H. Further, description is provided of a method of applying the equivalent parity check matrix in, for example, a communication/broadcast system using an encoder and a decoder using the equivalent parity check matrix. Note that the error correction code described herein may be applied to various fields, including but not limited to communication/broadcast systems.

(Embodiment E6)



[2641] In the present embodiment, description is provided of a device that uses the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), description of which is provided in embodiment E4.

[2642] As one example, description is provided of a case where the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is applied to a communication device.

[2643] Fig. 22 illustrates the structures of a transmitting device 2200 and a receiving device 2210 in the communication device pertaining to the present embodiment.

[2644] An encoder 2201 receives information to be transmitted as input, and is capable of performing various types of encoding (e.g., various coding rates and various block lengths of block codes (for example, in systematic codes, the sum of the number of information bits and the number of parity bits)). In particular, when receiving a specification to perform encoding by using the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), the encoder 2201 performs encoding by using the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) to calculate parities P1 and P2. Further, the encoder 2201 outputs the information to be transmitted and the parities P1 and P2 as a transmission sequence.

[2645] A modulator 2202 receives the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, performs mapping based on a predetermined modulation scheme (for example, BPSK, QPSK, 16QAM, or 64QAM), and outputs a baseband signal. Further, the modulator 2202 may also receive information other than the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, as input, perform mapping, and output a baseband signal. For example, the modulator 2202 may receive control information as input.

[2646]  The transmitting device outputs a transmission signal after performing predetermined signal processing (e.g., signal processing for generation of an OFDM signal, frequency conversion, amplification) with respect to such signals (e.g., baseband signals, pilot signals). The transmitting device may transmit the transmission signal over a wireless transmission path utilizing electromagnetic waves, or over a wired transmission path utilizing a coaxial cable, a power line, an optical cable, or the like.

[2647] The transmission signal is received by the receiving device 2210 after travelling over the transmission path. A receiver 2211 receives a reception signal as input, performs predetermined signal processing (e.g., bandwidth limitation, frequency conversion, signal processing for OFDM, frequency offset estimation, signal detection, channel estimation), and outputs a baseband signal and a channel estimation signal.

[2648] A log-likelihood ratio generation section 2212 receives the baseband signal and the channel estimation signal as input (may receive other signals as input), and for example, calculates and outputs a log-likelihood ratio for each bit (may calculate and output a hard value (hard decision value)).

[2649] A decoder 2213 receives the log-likelihood ratio for each bit as input, performs belief propagation decoding (e.g., sum-product decoding, scheduled sum-product decoding (Layered BP (belief propagation) decoding), min-sum decoding, Normalized BP decoding, offset BP decoding), and outputs an estimation sequence. The decoder 2213 performs the belief propagation decoding based on the parity check matrix for the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[2650] Although description is provided above taking an example where error correction coding is introduced to a communication device, the error correction coding described above is not limited to being introduced to a communication device, and for example, may be introduced to a storage medium (storage). When making such a modification, information that is to be stored to a storage medium (storage) is encoded by using the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and resultant information and parities are stored to the storage medium (storage).

[2651] Further, the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is applicable to any device that requires error correction coding (e.g., a memory, a hard disk).

[2652] Note that when using a block code such as the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) in a device, there as cases where special processing needs to be executed.

[2653] Assume that a block length of the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) used in a device is 14000 bits (10000 information bits, and 4000 parity bits).

[2654] In such a case, the number of information bits necessary for encoding one block is 10000. Meanwhile, there are cases where the number of bits of information input to an encoding section of the device does not reach 10000. For example, assume a case where only 9000 information bits are input to the encoding section.

[2655] Here, it is assumed that the encoding section, in the above-described case, adds 1000 padding bits of information to the 9000 information bits having been input, and performs encoding by using a total of 10000 bits, composed of the 9000 information bits having been input and the 1000 padding bits, to generate 4000 parity bits. Here, assume that all of the 1000 padding bits are known bits. For example, assume that each of the 1000 padding bits is "0".

[2656] A transmitting device may output the 9000 information bits having been input, the 1000 padding bits, and the 4000 parity bits. Alternatively, a transmitting device may output the 9000 information bits having been input and the 4000 parity bits.

[2657] In addition, a transmitting device may perform puncturing with respect to the 9000 information bits having been input and the 4000 parity bits, and thereby output a number of bits smaller than 13000 in total.

[2658] Note that when performing transmission in such a manner, the transmitting device is required to transmit, to a receiving device, information notifying the receiving device that transmission has been performed in such a manner.

[2659] As described above, the LDPC-CC of coding rate 5/7 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), description of which is provided in embodiment E4, is applicable to various devices.

(Embodiment F1)



[2660] The present embodiment describes a method of configuring an LDPC-CC of coding rate 7/9 that is based on a parity check polynomial, as one example of an LDPC-CC not satisfying coding rate (n-1)/n.

[2661] Bits of information bits X1, X2, X3, X4, X5, X6, X7 and parity bits P1, P2, at time point j, are expressed X1,j, X2,j, X3,j, X4,j, X5.j, X6,j, X7,j and P1,j, P2,j, respectively.

[2662]  A vector uj, at time point j, is expressed uj = (X1,j, X2,j, X3,j, X4,j, X5.j, X6,j, X7,j, P1,j, P2,j).

[2663] Given a delay operator D, polynomial expressions of the information bits X1, X2, X3, X4, X5, X6, X7 are X1(D), X2(D), X3(D), X4(D), X5(D), X6(D), X7(D), and polynomial expressions of the parity bits P1, P2 are P1(D), P2(D).

[2664] Further, consideration is given to an LDPC-CC of coding rate 7/9 and time-varying period 2m that is based on a parity check polynomial.

[2665] The following mathematical expressions are provided as parity check polynomials satisfying zero for an LDPC-CC of coding rate 7/9 and time-varying period 2m that is based on a parity check polynomial.

[2666] First, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1×P2(D).
[Math. 536-1]





[Math. 536-2]







[2667] In expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[2668] In expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2), α#(2i),p,q (where p is an integer no smaller than one and no greater than seven, q is an integer no smaller than one and no greater than r#(2i),p (where r#(2i),p is a natural number)) and β#(2i),0 is a natural number, β#(2i),1 is a natural number, β#(2i),2 is an integer no smaller than zero, and β#(2i),3 is a natural number.

[2669] Further, y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y(2i),p,z holds true for (y, z) where y#z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y(2i),p,z holds true for all y and all z satisfying y≠z.)

[2670] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (97-1-1) or expression (97-1-2) is referred to as "#(2i); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (97-2-1) or expression (97-2-2) is referred to as "#(2i); second expression" for realizing a time-varying period 2m.

[2671] Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (97-1-1) or expression (97-1-2) is prepared.

[2672] That is, for i=0, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=0 is prepared.

[2673] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=m-1 is prepared.



[2674] Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (97-2-1) or expression (97-2-2) is prepared.

[2675] That is, for i=0, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=0 is prepared.

[2676] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=m-1 is prepared.



[2677] Similarly, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1×P2(D).
[Math. 537-1]





[Math. 537-2]







[2678] In expressions (98-1-1), (98-1-2), (98-2-1), (98-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[2679] In expressions (98-1-1), (98-1-2), (98-2-1), (98-2-2), α#(2i+1),p,q (where p is an integer no smaller than one and no greater than seven, q is an integer no smaller than one and no greater than r#(2i+1),p (where r#(2i+1),p is a natural number)) and β#(2i+1),0 is a natural number, β#(2i+1),1 is a natural number, β#(2i+1),2 is an integer no smaller than zero, and β#(2i+1),3 is a natural number.

[2680] Further, y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y#α#(2i+1),p,z holds true for (y, z) where y#z. ∀ is a universal quantifier, (y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for all y and all z satisfying y≠z.)

[2681] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (98-1-1) or expression (98-1-2) is referred to as "#(2i+1); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (98-2-1) or expression (98-2-2) is referred to as "#(2i+1); second expression" for realizing a time-varying period 2m.

[2682] Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (98-1-1) or expression (98-1-2) is prepared.

[2683] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=0 is prepared.

[2684] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=m-1 is prepared.



[2685] Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (98-2-1) or expression (98-2-2) is prepared.

[2686] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=0 is prepared.

[2687] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=m-1 is prepared.



[2688] As such, an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2689] Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (97-1-1) or expression (97-1-2), parity check polynomials satisfying zero provided by expression (97-2-1) or expression (97-2-2), parity check polynomials satisfying zero provided by expression (98-1-1) or expression (98-1-2), and parity check polynomials satisfying zero provided by expression (98-2-1) or expression (98-2-2).

[2690] For example, the time varying period 2×m can be formed by preparing a 4×m number of different parity check polynomials satisfying zero.

[2691] Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

[2692] The following describes the relationship between time point j and expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2), (98-1-1), (98-1-2), (98-2-1), and (98-2-2) (where j is an integer no smaller than zero).

[2693] The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m-1).

[2694] Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i = k in #(2i); first expression and #(2i); second expression, hold true.

[2695] Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m-1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

[2696] The following describes a method of configuring a parity check matrix for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2697] As already described above, a vector uj at time point j is expressed as uj=(X1,j, X2,j, X3,j, X4,j, X5,j, X6,j, X7,j, P1,j, P2,j) (where j is an integer no smaller than zero). In the following, a case where u is a transmission vector is considered. Note that in the following, j is an integer no smaller than one, and thus j differs between the description having been provided above and the description provided in the following. (j is set as such to facilitate understanding of the correspondence between the column numbers and the row numbers of the parity check matrix.)

[2698] Accordingly, u=(u1, u2, u3, ..., uy-1, uy, uy+1, ...)T=(X1,1, X2,1, X3,1, X4,1, X5,1, X6,1, X7,1, P1,1, P2,1, X1,2, X2,2, X3,2, X4,2, X5,2, X6,2, X7,2, P1,2, P2,2, X1,3, X2,3, X3,3, X4,3, X5,3, X6,3, X7,3, P1,3, P2,3, ..., X1,y-1, X2,y-1, X3,y-1 X4,y-1, X5,y-1, X6,y-1, X7,y-1, P1,y-1, P2,y-1, X1,y, X2,y, X3,y, X4,y, X5,y, X6,y, X7,y, P1,y, P2,y, X1,y+1, X2,y+1, X3,y+1, X4,y+1, X5,y+1, X6,y+1, X7,y+1, P1,y+1, P2,y+1, ...)T. Further, when using H to denote a parity check matrix for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, Hu=0 holds true (here, Hu=0 indicates that all elements of the vector Hu are zeroes).

[2699] FIG. 84 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the topmost row of the parity check matrix is considered as the first row. Further, row number is incremented by one each time moving to a lower row. Accordingly, the topmost row is considered as the first row, the row immediately below the first row is considered as the second row, and the subsequent rows are considered as the third row, the fourth row, and so on.

[2700] As illustrated in FIG. 84:

"a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";
"a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×(2m-1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression";

"a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression";

"a vector for the 2×(2m+1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the 2×(2m+2)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×i-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); first expression"; and

"a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); second expression", and so on (where i is an integer no smaller than one).



[2701] FIG. 85 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the leftmost column of the parity check matrix is considered as the first column. Further, column number is incremented by one each time moving to a rightward column. Accordingly, the leftmost column is considered as the first column, the column immediately to the right of the first column is considered as the second column, and the subsequent columns are considered as the third column, the fourth column, and so on.

[2702] As illustrated in FIG. 85:

"a vector for the first column of the parity check matrix H is related to X1 at time point 1";

"a vector for the second column of the parity check matrix H is related to X2 at time point 1";

"a vector for the third column of the parity check matrix H is related to X3 at time point 1";

"a vector for the fourth column of the parity check matrix H is related to X4 at time point 1";

"a vector for the fifth column of the parity check matrix H is related to X5 at time point 1";

"a vector for the sixth column of the parity check matrix H is related to X6 at time point 1";

"a vector for the seventh column of the parity check matrix H is related to X7 at time point 1";

"a vector for the eighth column of the parity check matrix H is related to P1 at time point 1";

"a vector for the ninth column of the parity check matrix H is related to P2 at time point 1";

"a vector for the 9×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 9×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 9×(j-1)+3th column of the parity check matrix H is related to X3 at time point j";

"a vector for the 9×(j-1)+4th column of the parity check matrix H is related to X4 at time point j";

"a vector for the 9×(j-1)+5th column of the parity check matrix H is related to X5 at time point j";

"a vector for the 9×(j-1)+6th column of the parity check matrix H is related to X6 at time point j";

"a vector for the 9×(j-1)+7th column of the parity check matrix H is related to X7 at time point j";

"a vector for the 9×(j-1)+8th column of the parity check matrix H is related to P1 at time point j";

"a vector for the 9×(j-1)+9th column of the parity check matrix H is related to P1 at time point j" and so on (where j is an integer no smaller than one).



[2703] FIG. 86 indicates a parity check matrix for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2704] The following focuses on 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D), 1×P1(D), 1×P2(D) in the parity check matrix for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2705] The parity check polynomials at time point j=1 are parity check polynomials when i=0 in expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2).

[2706] A vector for the first row in FIG. 86 can be generated from a parity check polynomial when i=0 in expression (97-1-1) or expression (97-1-2) (refer to FIG. 84).

[2707] In expressions (97-1-1) and (97-1-2):
  • terms for 1×X1(D), 1×X2(D), 1×X3(D) exist;
  • terms for 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D) do not exist; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[2708] Further, the relationship between column numbers and X1, X2, X3, X4, X5, X6, X7, P1, P2 is as indicated in FIG. 85. Based on the relationship indicated in FIG. 85 and the fact that terms for 1×X1(D), 1×X2(D), 1×X3(D) exist, columns related to X1, X2, X3 in the vector for the first row in FIG. 86 are "1". Further, based on the relationship indicated in FIG. 85 and the fact that terms for 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D) do not exist, columns related to X4, X5, X6, X7 in the vector for the first row in FIG. 86 are "0". In addition, based on the relationship indicated in FIG. 85 and the fact that a term for 1×P1(D) exists but a term for 1×P2(D) does not exist, a column related to P1 in the vector for the first row in FIG. 86 is "1", and a column related to P2 in the vector for the first row in FIG. 86 is "0".

[2709] As such, the vector for the first row in FIG. 86 is "111000010", as indicated by 3900-1 in FIG. 86.

[2710] A vector for the second row in FIG. 86 can be generated from a parity check polynomial when i=0 in expression (97-2-1) or expression (97-2-2) (refer to FIG. 84).

[2711] In expressions (97-2-1) and (97-2-2):
  • terms for 1×X1(D), 1×X2(D), 1×X3(D) do not exist;
  • terms for 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D) exist; and
  • a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists.


[2712] Further, the relationship between column numbers and X1, X2, X3, X4, X5, X6, X7, P1, P2 is as indicated in FIG. 85. Based on the relationship indicated in FIG. 85 and the fact that terms for 1×X1(D), 1×X2(D), 1×X3(D) do not exist, columns related to X1, X2, X3 in the vector for the second row in FIG. 86 are "0". Further, based on the relationship indicated in FIG. 85 and the fact that terms for 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D) exist, columns related to X4, X5, X6, X7 in the vector for the second row in FIG. 86 are "1". In addition, based on the relationship indicated in FIG. 85 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the second row in FIG. 86 is "Y", and a column related to P2 in the vector for the second row in FIG. 86 is "1", where Y is either "0" or "1".

[2713] As such, the vector for the second row in FIG. 86 is "0001111Y1", as indicated by 3900-2 in FIG. 86.

[2714] The parity check polynomials at time point j=2 are parity check polynomials when i=0 in expressions (98-1-1), (98-1-2), (98-2-1), (98-2-2).

[2715] A vector for the third row in FIG. 86 can be generated from a parity check polynomial when i=0 in expression (98-1-1) or expression (98-1-2) (refer to FIG. 84).

[2716] In expressions (98-1-1) and (98-1-2):
  • terms for 1×X1(D), 1×X2(D), 1×X3(D) do not exist;
  • terms for 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D) exist; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[2717] Further, the relationship between column numbers and X1, X2, X3, X4, X5, X6, X7, P1, P2 is as indicated in FIG. 85. Based on the relationship indicated in FIG. 85 and the fact that terms for 1×X1(D), 1×X2(D), 1×X3(D) do not exist, columns related to X1, X2, X3 in the vector for the third row in FIG. 86 are "0". Further, based on the relationship indicated in FIG. 85 and the fact that terms for 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D) exist, columns related to X4, X5, X6, X7 in the vector for the third row in FIG. 86 are "1". In addition, based on the relationship indicated in FIG. 85 and the fact that a term for 1×P1(D) exists but a term for 1×P2(D) does not exist, a column related to P1 in the vector for the third row in FIG. 86 is "1", and a column related to P2 in the vector for the third row in FIG. 86 is "0".

[2718] As such, the vector for the third row in FIG. 86 is "000111110", as indicated by 3901-1 in FIG. 86.

[2719] A vector for the fourth row in FIG. 86 can be generated from a parity check polynomial when i=0 in expression (98-2-1) or expression (98-2-2) (refer to FIG. 84).

[2720] In expressions (98-2-1) and (98-2-2):
  • terms for 1×X1(D), 1×X2(D), 1×X3(D) exist;
  • terms for 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D) do not exist; and
  • a term for 1 ×P1(D) may or may not exist but a term for 1×P2(D) exists.


[2721] Further, the relationship between column numbers and X1, X2, X3, X4, X5, X6, X7, P1, P2 is as indicated in FIG. 85. Based on the relationship indicated in FIG. 85 and the fact that terms for 1×X1(D), 1×X2(D), 1×X3(D) exist, columns related to X1, X2, X3 in the vector for the fourth row in FIG. 86 are "1". Further, based on the relationship indicated in FIG. 85 and the fact that terms for 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D) do not exist, columns related to X4, X5, X6, X7 in the vector for the fourth row in FIG. 86 are "0". In addition, based on the relationship indicated in FIG. 85 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the fourth row in FIG. 86 is "Y", and a column related to P2 in the vector for the fourth row in FIG. 86 is "1".

[2722] As such, the vector for the fourth row in FIG. 86 is "1110000Y1", as indicated by 3901-2 in FIG. 86.

[2723] Because it can be considered that the above similarly applies to cases where time point j =3, 4, 5, the parity check matrix H has the configuration indicated in FIG. 86.

[2724] That is, due to the parity check polynomials of expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2) being used at time point j=2k+1 (where k is an integer no smaller than zero), "111000010" exists in the 2×(2k+1)-1throw of the parity check matrix H, and "0001111Y1" exists in the 2×(2k+1)th row of the parity check matrix H, as illustrated in FIG. 86.

[2725] Further, due to the parity check polynomials of expressions (98-1-1), (98-1-2), (98-2-1), (98-2-2) being used at time point j=2k+2 (where k is an integer no smaller than zero), "000111110" exists in the 2×(2k+2)-1th row of the parity check matrix H, and "1110000Y1" exists in the 2×(2k+2)th row of the parity check matrix H, as illustrated in FIG. 86.

[2726] Accordingly, as illustrated in FIG. 86, when denoting a column number of a leftmost column corresponding to "1" in "111000010" in a row where "111000010" exists (e.g., 3900-1 in FIG. 86) as "a", "000111110" (e.g., 3901-1 in FIG. 86) exists in a row that is two rows below the row where "111000010" exists, starting from column "a+9".

[2727] Similarly, as illustrated in FIG. 86, when denoting a column number of a leftmost column corresponding to "1" in "0001111Y1" in a row where "0001111Y1" exists (e.g., 3900-2 in FIG. 86) as "b", "1110000Y1" (e.g., 3901-2 in FIG. 86) exists in a row that is two rows below the row where "0001111Y1" exists, starting from column "b+9".

[2728] Similarly, as illustrated in FIG. 86, when denoting a column number of a leftmost column corresponding to "1" in "000111110" in a row where "000111110" exists (e.g., 3901-1 in FIG. 86) as "c", "111000010" (e.g., 3902-1 in FIG. 86) exists in a row that is two rows below the row where "000111110" exists, starting from column "c+9".

[2729] Similarly, as illustrated in FIG. 86, when denoting a column number of a leftmost column corresponding to "1" in "1110000Y1" in a row where "1110000Y1" exists (e.g., 3901-2 in FIG. 86) as "d", "0001111Y1" (e.g., 3902-2 in FIG. 86) exists in a row that is two rows below the row where "1110000Y1" exists, starting from column "d+9".

[2730] The following describes a parity check matrix for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial when tail-biting is not performed, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2731] In the following, Hcom[u][v] (where u and v are integers no smaller than one) denotes an element at row "u" column "v" of a parity check matrix for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2732] Based on description above provided with reference to FIG. 84:

"a vector for the 2×g-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); first expression"; and

"a vector for the (2×g)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); second expression" (where g is an integer no smaller than one).



[2733] Based on description above provided with reference to FIG. 85:

"a vector for the 9×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 9×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 9×(j-1)+3th column of the parity check matrix H is related to X3 at time point j";

"a vector for the 9×(j-1)+4th column of the parity check matrix H is related to X4 at time point j";

"a vector for the 9×(j-1)+5th column of the parity check matrix H is related to X5 at time point j";

"a vector for the 9×(j-1)+6th column of the parity check matrix H is related to X6 at time point j";

"a vector for the 9×(j-1)+7th column of the parity check matrix H is related to X7 at time point j";

"a vector for the 9×(j-1)+8th column of the parity check matrix H is related to P1 at time point j";

"a vector for the 9×(j-1)+9th column of the parity check matrix H is related to P2 at time point j"; (where j is an integer no smaller than one).



[2734] Based on the above, the following describes component Hcom[2×g-1][v] in row 2×g-1 (where g is an integer no smaller than one) and component Hcom[2×g][v] in row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2735]  As already described above, a parity check polynomial satisfying zero of #((g-1)%2m); first expression can be used to generate a vector for row 2×g-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2736] Further, a parity check polynomial satisfying zero of #((g-1)%2m); second expression can be used to generate a vector for row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2737] Accordingly, when g=2×f-1 (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (97-1-1) or expression (97-1-2), can be used to generate a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2738] Further, a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (97-2-1) or expression (97-2-2), can be used to generate a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2739] Further, when g=2×f (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (98-1-1) or expression (98-1-2), can be used to generate a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2740] Further, a parity check polynomial satisfying zero of #(((2×f)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (98-2-1) or expression (98-2-2), can be used to generate a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2741] Accordingly, (1) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-1-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-1-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2742] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2743] The following holds true for X1.
[Math. 538]



[2744] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than three.
[Math. 539]



[2745] Further, the following holds true for X4. In the following, y is an integer no smaller than three and no greater than r#(2c),4.
[Math. 540]



[2746] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than four and no greater than seven, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 541]



[2747] The following holds true for P1.
[Math. 542]



[2748] The following holds true for P2.
[Math. 543]



[2749] Further, (2) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-1-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-1-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2750] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2751] The following holds true for X1.
[Math. 544]



[2752] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than three.
[Math. 545]



[2753] Further, the following holds true for X4. In the following, y is an integer no smaller than three and no greater than r#(2c),4.
[Math. 546]



[2754] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than four and no greater than seven, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 547]



[2755] The following holds true for P1.
[Math. 548]



[2756] The following holds true for P2.
[Math. 549]



[2757] Further, (3) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-2-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-2-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2758] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2759] The following holds true for X1. In the following, and y is an integer no smaller than three and no greater than r#(2c),1.
[Math. 550]



[2760] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than three, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 551]



[2761] Further, the following holds true for X4.
[Math. 552]



[2762] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than four and no greater than seven.
[Math. 553]



[2763] The following holds true for P1.
[Math. 554]



[2764] The following holds true for P2.
[Math. 555]



[2765] Further, (4) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-2-2), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-2-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2766] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2767] The following holds true for X1. In the following, y is an integer no smaller than three and no greater than r#(2c),1.
[Math. 556]



[2768] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than three, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 557]



[2769] Further, the following holds true for X4.
[Math. 558]





[2770] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than four and no greater than seven.
[Math. 559]



[2771] The following holds true for P1.
[Math. 560]



[2772] The following holds true for P2.
[Math. 561]





[2773] Further, (5) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-1-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-1-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2774] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2775] The following holds true for X1. In the following, y is an integer no smaller than three and no greater than r#(2d+1),1.
[Math. 562]



[2776] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than three, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 563]



[2777] Further, the following holds true for X4.
[Math. 564]



[2778] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than four and no greater than seven.
[Math. 565]





[2779] The following holds true for P1.
[Math. 566]



[2780] The following holds true for P2.
[Math. 567]



[2781] Further, (6) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-1-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-1-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2782] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2783] The following holds true for X1. In the following, y is an integer no smaller than three and no greater than r#(2d+1),1.
[Math. 568]



[2784] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than three, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 569]



[2785] Further, the following holds true for X4.
[Math. 570]





[2786] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than four and no greater than seven.
[Math. 571]



[2787] The following holds true for P1.
[Math. 572]



[2788] The following holds true for P2.
[Math. 573]



[2789] Further, (7) when g=2×f (where f is an integer no smaller than one), when a vector for row 2x(2xf) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-2-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-2-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2790] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2791] The following holds true for X1.
[Math. 574]



[2792] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than three.
[Math. 575]





[2793] Further, the following holds true for X4. In the following, y is an integer no smaller than three and no greater than r#(2d+1),4.
[Math. 576]



[2794] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than four and no greater than seven, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 577]



[2795] The following holds true for P1.
[Math. 578]





[2796] The following holds true for P2.
[Math. 579]



[2797] Further, (8) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-2-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-2-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2798] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2799] The following holds true for X1.
[Math. 580]





[2800] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than three.
[Math. 581]



[2801] Further, the following holds true for X4. In the following, y is an integer no smaller than three and no greater than r#(2d+1),4.
[Math. 582]



[2802] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than four and no greater than seven, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 583]



[2803] The following holds true for P1.
[Math. 584]



[2804] The following holds true for P2.
[Math. 585]



[2805] As such, an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial can be generated by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, and the code so generated achieves high error correction capability.

(Embodiment F2)



[2806] In the present embodiment, description is provided of a method of code configuration that is a generalization of the method described in embodiment F1 of configuring an LDPC-CC of coding rate 7/9 that is based on a parity check polynomial.

[2807] Bits of information bits X1, X2, X3, X4, X5, X6, X7 and parity bits P1, P2, at time point j, are expressed X1,j, X2,j, X3,j, X4,j, X5.j, X6,j, X7,j and P1,j, P2,j, respectively.

[2808] A vector uj, at time point j, is expressed uj = (X1,j, X2,j, X3,j, X4,j, X5.j, X6,j, X7,j, P1,j, P2,j).

[2809] Given a delay operator D, polynomial expressions of the information bits X1, X2, X3, X4, X5, X6, X7 are X1(D), X2(D), X3(D), X4(D), X5(D), X6(D), X7(D), and polynomial expressions of the parity bits P1, P2 are P1(D), P2(D).

[2810] Further, consideration is given to an LDPC-CC of coding rate 7/9 and time-varying period 2m that is based on a parity check polynomial.

[2811] The following mathematical expressions are provided as parity check polynomials satisfying zero for an LDPC-CC of coding rate 7/9 and time-varying period 2m that is based on a parity check polynomial.

[2812] First, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1×P2(D).
[Math. 586-1]





[Math. 586-2]







[2813] In expressions (147-1-1), (147-1-2), (147-2-1), (147-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[2814] In expressions (147-1-1), (147-1-2), (147-2-1), (147-2-2), α#(2i),p,q (where p is an integer no smaller than one and no greater than seven, q is an integer no smaller than one and no greater than r#(2i),p (where r#(2i),p is a natural number)) and β#(2i),0 is a natural number, β#(2i),1 is a natural number, β#(2i),2 is an integer no smaller than zero, and β#(2i),3 is a natural number.

[2815] Further, R#(2i),p is a natural number satisfying 1≤R#(2i),p<r#(2i),p.

[2816] Further, y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and (α#(2i),p,y≠α#(2i),p,z holds true for all y and all z satisfying y≠z.)

[2817] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (147-1-1) or expression (147-1-2) is referred to as "#(2i); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (147-2-1) or expression (147-2-2) is referred to as "#(2i); second expression" for realizing a time-varying period 2m.

[2818] Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (147-1-1) or expression (147-1-2) is prepared.

[2819] That is, for i=0, a parity check polynomial satisfying zero provided by expression (147-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (147-1-2) where i=0 is prepared.

[2820] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (147-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (147-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (147-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (147-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (147-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (147-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (147-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (147-1-2) where i=m-1 is prepared.



[2821] Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (147-2-1) or expression (147-2-2) is prepared.

[2822] That is, for i=0, a parity check polynomial satisfying zero provided by expression (147-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (147-2-2) where i=0 is prepared.

[2823] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (147-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (147-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (147-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (147-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (147-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (147-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (147-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (147-2-2) where i=m-1 is prepared.



[2824] Similarly, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1×P2(D).
[Math. 587-1]





[Math. 587-2]







[2825] In expressions (148-1-1), (148-1-2), (148-2-1), (148-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[2826] In expressions (148-1-1), (148-1-2), (148-2-1), (148-2-2), α#(2i+1),p,q (where p is an integer no smaller than one and no greater than seven, q is an integer no smaller than one and no greater than r#(2i+i),p (where r#(2i+1),p is a natural number)) and β#(2i+1),0 is a natural number, β#(2i+1),1 is a natural number, β#(2i+1),2 is an integer no smaller than zero, and β#(2i+1),3 is a natural number.

[2827] Further, R#(2i),p is a natural number satisfying 1≤R#(2i+1),p<r#(2i+1),p.

[2828] Further, y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for all y and all z satisfying y≠z.)

[2829] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (148-1-1) or expression (148-1-2) is referred to as "#(2i+1); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (148-2-1) or expression (148-2-2) is referred to as "#(2i+1); second expression" for realizing a time-varying period 2m.

[2830] Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (148-1-1) or expression (148-1-2) is prepared.

[2831] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (148-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (148-1-2) where i=0 is prepared.

[2832] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (148-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (148-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (148-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (148-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (148-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (148-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (148-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (148-1-2) where i=m-1 is prepared.



[2833] Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (148-2-1) or expression (148-2-2) is prepared.

[2834] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (148-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (148-2-2) where i=0 is prepared.

[2835] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (148-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (148-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (148-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (148-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (148-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (148-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (148-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (148-2-2) where i=m-1 is prepared.



[2836] As such, an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2837] Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (147-1-1) or expression (147-1-2), parity check polynomials satisfying zero provided by expression (147-2-1) or expression (147-2-2), parity check polynomials satisfying zero provided by expression (148-1-1) or expression (148-1-2), and parity check polynomials satisfying zero provided by expression (148-2-1) or expression (148-2-2).

[2838] For example, the time varying period 2×m can be formed by preparing a 4×m number of different parity check polynomials satisfying zero.

[2839] Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

[2840] The following describes the relationship between time point j and expressions (147-1-1), (147-1-2), (147-2-1), (147-2-2), (148-1-1), (148-1-2), (148-2-1), and (148-2-2) (where j is an integer no smaller than zero).

[2841] The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m-1).

[2842] Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i = k in #(2i); first expression and #(2i); second expression, hold true.

[2843] Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m-1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

[2844] The following describes a method of configuring a parity check matrix for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2845] As already described above, a vector uj at time point j is expressed as uj=(X1,j, X2,j, X3,j, X4,j, X5,j, X6,j, X7,j, P1,j, P2,j) (where j is an integer no smaller than zero). In the following, a case where u is a transmission vector is considered. Note that in the following, j is an integer no smaller than one, and thus j differs between the description having been provided above and the description provided in the following. (j is set as such to facilitate understanding of the correspondence between the column numbers and the row numbers of the parity check matrix.)

[2846] Accordingly, u=(u1, u2, u3, ..., Uy-1, uy, Uy+1, ...)T=(X1,1, X2,1, X3,1, X4,1, X5,1, X6,1, X7,1, P1,1, P2,1, X1,2, X2,2, X3,2, X4,2, X5,2, X6,2, X7,2, P1,2, P2,2, X1,3, X2,3, X3,3, X4,3, X5,3, X6,3, X7,3, P1,3, P2,3, ..., X1,y-1, X2,y-1, X3,y-1, X4,y-1, X5,y-1, X6,y-1, X7,y-1, P1,y-1, P2,y-1, X1,y, X2,y, X3,y, X4,y, X5,y, X6,y, X7,y, P1,y, P2,y, X1,y+1, X2,y+1, X3,y+1, X4,y+1, X5,y+1, X6,y+1, X7,y+1, P1,y+1,P2,y+1, ...)T. Further, when using H to denote a parity check matrix for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, Hu=0 holds true (here, Hu=0 indicates that all elements of the vector Hu are zeroes).

[2847] FIG. 84 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the topmost row of the parity check matrix is considered as the first row. Further, row number is incremented by one each time moving to a lower row. Accordingly, the topmost row is considered as the first row, the row immediately below the first row is considered as the second row, and the subsequent rows are considered as the third row, the fourth row, and so on.

[2848] As illustrated in FIG. 84:

"a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of#0; first expression";

"a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of#0; second expression";

"a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of#1; first expression";
"a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of#1; second expression";

"a vector for the 2×(2m-1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression";

"a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression";

"a vector for the 2×(2m+1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of#0; first expression";

"a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of#0; second expression";

"a vector for the 2×(2m+2)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of#1; first expression";

"a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of#1; second expression";

"a vector for the 2×i-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); first expression"; and

"a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); second expression", and so on (where i is an integer no smaller than one).



[2849] FIG. 85 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the leftmost column of the parity check matrix Hpro_m is considered as the first column. Further, column number is incremented by one each time moving to a rightward column. Accordingly, the leftmost column is considered as the first column, the column immediately to the right of the first column is considered as the second column, and the subsequent columns are considered as the third column, the fourth column, and so on.

[2850] As illustrated in FIG. 85:

"a vector for the first column of the parity check matrix H is related to X1 at time point 1";

"a vector for the second column of the parity check matrix H is related to X2 at time point 1";

"a vector for the third column of the parity check matrix H is related to X3 at time point 1";

"a vector for the fourth column of the parity check matrix H is related to X4 at time point 1";

"a vector for the fifth column of the parity check matrix H is related to X5 at time point 1";

"a vector for the sixth column of the parity check matrix H is related to X6 at time point 1";

"a vector for the seventh column of the parity check matrix H is related to X7 at time point 1";

"a vector for the eighth column of the parity check matrix H is related to P1 at time point 1";

"a vector for the ninth column of the parity check matrix H is related to P2 at time point 1";

"a vector for the 9×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 9×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 9×(j-1)+3th column of the parity check matrix H is related to X3 at time point j";

"a vector for the 9×(j-1)+4th column of the parity check matrix H is related to X4 at time point j";

"a vector for the 9×(j-1)+5th column of the parity check matrix H is related to X5 at time point j";

"a vector for the 9×(j-1)+6th column of the parity check matrix H is related to X6 at time point j";

"a vector for the 9×(j-1)+7th column of the parity check matrix H is related to X7 at time point j";

"a vector for the 9×(j-1)+8th column of the parity check matrix H is related to P1 at time point j";

"a vector for the 9×(j-1)+9th column of the parity check matrix H is related to P1 at time point j" and so on (where j is an integer no smaller than one).



[2851] FIG. 86 indicates a parity check matrix for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2852] The following focuses on 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D), 1×P1(D), 1×P2(D) in the parity check matrix for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2853] The parity check polynomials at time point j=1 are parity check polynomials when i=0 in expressions (147-1-1), (147-1-2), (147-2-1), (147-2-2).

[2854] A vector for the first row in FIG. 86 can be generated from a parity check polynomial when i=0 in expression (147-1-1) or expression (147-1-2) (refer to FIG. 84).

[2855] In expressions (147-1-1) and (147-1-2):
  • terms for 1×X1(D), 1×X2(D), 1×X3(D) exist;
  • terms for 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D) do not exist; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[2856] Further, the relationship between column numbers and X1, X2, X3, X4, X5, X6, X7, P1, P2 is as indicated in FIG. 85. Based on the relationship indicated in FIG. 85 and the fact that terms for 1×X1(D), 1×X2(D), 1×X3(D) exist, columns related to X1, X2, X3 in the vector for the first row in FIG. 86 are "1". Further, based on the relationship indicated in FIG. 85 and the fact that terms for 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D) do not exist, columns related to X4, X5, X6, X7 in the vector for the first row in FIG. 86 are "0". In addition, based on the relationship indicated in FIG. 85 and the fact that a term for 1×P1(D) exists but a term for 1×P2(D) does not exist, a column related to P1 in the vector for the first row in FIG. 86 is "1", and a column related to P2 in the vector for the first row in FIG. 86 is "0".

[2857] As such, the vector for the first row in FIG. 86 is "111000010", as indicated by 3900-1 in FIG. 86.

[2858] A vector for the second row in FIG. 86 can be generated from a parity check polynomial when i=0 in expression (147-2-1) or expression (147-2-2) (refer to FIG. 84).

[2859] In expressions (147-2-1) and (147-2-2):
  • terms for 1×X1(D), 1×X2(D), 1×X3(D) do not exist;
  • terms for 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D) exist; and
  • a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists.


[2860] Further, the relationship between column numbers and X1, X2, X3, X4, X5, X6, X7, P1, P2 is as indicated in FIG. 85. Based on the relationship indicated in FIG. 85 and the fact that terms for 1×X1(D), 1×X2(D), 1×X3(D) do not exist, columns related to X1, X2, X3 in the vector for the second row in FIG. 86 are "0". Further, based on the relationship indicated in FIG. 85 and the fact that terms for 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D) exist, columns related to X4, X5, X6, X7 in the vector for the second row in FIG. 86 are "1". In addition, based on the relationship indicated in FIG. 85 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the second row in FIG. 86 is "Y", and a column related to P2 in the vector for the second row in FIG. 86 is "1", where Y is either "0" or "1".

[2861] As such, the vector for the second row in FIG. 86 is "0001111Y1", as indicated by 3900-2 in FIG. 86.

[2862] The parity check polynomials at time point j=2 are parity check polynomials when i=0 in expressions (148-1-1), (148-1-2), (148-2-1), (148-2-2).

[2863] A vector for the third row in FIG. 86 can be generated from a parity check polynomial when i=0 in expression (148-1-1) or expression (148-1-2) (refer to FIG. 84).

[2864] In expressions (148-1-1) and (148-1-2):
  • terms for 1×X1(D), 1×X2(D), 1×X3(D) do not exist;
  • terms for 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D) exist; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[2865] Further, the relationship between column numbers and X1, X2, X3, X4, X5, X6, X7, P1, P2 is as indicated in FIG. 85. Based on the relationship indicated in FIG. 85 and the fact that terms for 1×X1(D), 1×X2(D), 1×X3(D) do not exist, columns related to X1, X2, X3 in the vector for the third row in FIG. 86 are "0". Further, based on the relationship indicated in FIG. 85 and the fact that terms for 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D) exist, columns related to X4, X5, X6, X7 in the vector for the third row in FIG. 86 are "1". In addition, based on the relationship indicated in FIG. 85 and the fact that a term for 1×P1(D) exists but a term for 1×P2(D) does not exist, a column related to P1 in the vector for the third row in FIG. 86 is "1", and a column related to P2 in the vector for the third row in FIG. 86 is "0".

[2866] As such, the vector for the third row in FIG. 86 is "000111110", as indicated by 3901-1 in FIG. 86.

[2867] A vector for the fourth row in FIG. 86 can be generated from a parity check polynomial when i=0 in expression (148-2-1) or expression (148-2-2) (refer to FIG. 84).

[2868] In expressions (148-2-1) and (148-2-2):
  • terms for 1×X1(D), 1×X2(D), 1×X3(D) exist;
  • terms for 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D) do not exist; and
  • a term for 1 ×P1(D) may or may not exist but a term for 1×P2(D) exists.


[2869] Further, the relationship between column numbers and X1, X2, X3, X4, X5, X6, X7, P1, P2 is as indicated in FIG. 85. Based on the relationship indicated in FIG. 85 and the fact that terms for 1×X1(D), 1×X2(D), 1×X3(D) exist, columns related to X1, X2, X3 in the vector for the fourth row in FIG. 86 are "1". Further, based on the relationship indicated in FIG. 85 and the fact that terms for 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D) do not exist, columns related to X4, X5, X6, X7 in the vector for the fourth row in FIG. 86 are "0". In addition, based on the relationship indicated in FIG. 85 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the fourth row in FIG. 86 is "Y", and a column related to P2 in the vector for the fourth row in FIG. 86 is "1".

[2870] As such, the vector for the fourth row in FIG. 86 is "1110000Y1", as indicated by 3901-2 in FIG. 86.

[2871] Because it can be considered that the above similarly applies to cases where time point j=3, 4, 5, the parity check matrix H has the configuration indicated in FIG. 86.

[2872] That is, due to the parity check polynomials of expressions (147-1-1), (147-1-2), (147-2-1), (147-2-2) being used at time point j=2k+1 (where k is an integer no smaller than zero), "111000010" exists in the 2×(2k+1)-1th row of the parity check matrix H, and "0001111Y1" exists in the 2×(2k+1)th row of the parity check matrix H, as illustrated in FIG. 86.

[2873] Further, due to the parity check polynomials of expressions (148-1-1), (148-1-2), (148-2-1), (148-2-2) being used at time point j=2k+2 (where k is an integer no smaller than zero), "000111110" exists in the 2×(2k+2)-1th row of the parity check matrix H, and "1110000Y1" exists in the 2x(2k+2)th row of the parity check matrix H, as illustrated in FIG. 86.

[2874] Accordingly, as illustrated in FIG. 86, when denoting a column number of a leftmost column corresponding to "1" in "111000010" in a row where "111000010" exists (e.g., 3900-1 in FIG. 86) as "a", "000111110" (e.g., 3901-1 in FIG. 86) exists in a row that is two rows below the row where "111000010" exists, starting from column "a+9".

[2875] Similarly, as illustrated in FIG. 86, when denoting a column number of a leftmost column corresponding to "1" in "0001111Y1" in a row where "0001111Y1" exists (e.g., 3900-2 in FIG. 86) as "b", "1110000Y1" (e.g., 3901-2 in FIG. 86) exists in a row that is two rows below the row where "0001111Y1" exists, starting from column "b+9".

[2876] Similarly, as illustrated in FIG. 86, when denoting a column number of a leftmost column corresponding to "1" in "000111110" in a row where "000111110" exists (e.g., 3901-1 in FIG. 86) as "c", "111000010" (e.g., 3902-1 in FIG. 86) exists in a row that is two rows below the row where "000111110" exists, starting from column "c+9".

[2877] Similarly, as illustrated in FIG. 86, when denoting a column number of a leftmost column corresponding to "1" in "1110000Y1" in a row where "1110000Y1" exists (e.g., 3901-2 in FIG. 86) as "d", "0001111Y1" (e.g., 3902-2 in FIG. 86) exists in a row that is two rows below the row where "1110000Y1" exists, starting from column "d+9".

[2878] The following describes a parity check matrix for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial when tail-biting is not performed, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2879] In the following, Hcom[u][v] (where u and v are integers no smaller than one) denotes an element at row "u" column "v" of a parity check matrix for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2880] Based on description above provided with reference to FIG. 84:

"a vector for the 2×g-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); first expression"; and

"a vector for the (2×g)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); second expression" (where g is an integer no smaller than one).



[2881] Based on description above provided with reference to FIG. 85:

"a vector for the 9×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 9×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 9×(j-1)+3th column of the parity check matrix H is related to X3 at time point j";

"a vector for the 9×(j-1)+4th column of the parity check matrix H is related to X4 at time point j";

"a vector for the 9×(j-1)+5th column of the parity check matrix H is related to X5 at time point j";

"a vector for the 9×(j-1)+6th column of the parity check matrix H is related to X6 at time point j";

"a vector for the 9×(j-1)+7th column of the parity check matrix H is related to X7 at time point j";

"a vector for the 9×(j-1)+8th column of the parity check matrix H is related to P1 at time point j";

"a vector for the 9×(j-1)+9th column of the parity check matrix H is related to P2 at time point j"; (where j is an integer no smaller than one).



[2882] Based on the above, the following describes component Hcom[2×g-1][v] in row 2×g-1 (where g is an integer no smaller than one) and component Hcom[2×g][v] in row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2883] As already described above, a parity check polynomial satisfying zero of #((g-1)%2m); first expression can be used to generate a vector for row 2×g-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2884] Further, a parity check polynomial satisfying zero of #((g-1)%2m); second expression can be used to generate a vector for row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2885] Accordingly, when g=2×f-1 (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (147-1-1) or expression (147-1-2), can be used to generate a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2886] Further, a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (147-2-1) or expression (147-2-2), can be used to generate a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2887]  Further, when g=2×f (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (148-1-1) or expression (148-1-2), can be used to generate a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2888] Further, a parity check polynomial satisfying zero of #(((2×f)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (148-2-1) or expression (148-2-2), can be used to generate a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[2889] Accordingly, (1) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (147-1-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (147-1-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2890] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2891] The following holds true for X1.
[Math. 588]



[2892] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than three.
[Math. 589]



[2893] Further, the following holds true for X4. In the following, y is an integer no smaller than R#(2c),4+1 and no greater than r#(2c),4.
[Math. 590]





[2894] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than four and no greater than seven, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 591]



[2895] The following holds true for P1.
[Math. 592]



[2896] The following holds true for P2.
[Math. 593]



[2897] Further, (2) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (147-1-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (147-1-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2898] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2899] The following holds true for X1.
[Math. 594]



[2900] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than three.
[Math. 595]



[2901] Further, the following holds true for X4. In the following, y is an integer no smaller than R#(2c),4+1 and no greater than r#(2c),4.
[Math. 596]



[2902] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than four and no greater than seven, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 597]



[2903] The following holds true for P1.
[Math. 598]



[2904] The following holds true for P2.
[Math. 599]





[2905] Further, (3) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (147-2-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (147-2-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2906] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2907] The following holds true for X1. In the following, and y is an integer no smaller than R#(2c),1+1 and no greater than r#(2c),1.
[Math. 600]



[2908] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than three, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 601]





[2909] Further, the following holds true for X4.
[Math. 602]



[2910] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than four and no greater than seven.
[Math. 603]



[2911] The following holds true for P1.
[Math. 604]





[2912] The following holds true for P2.
[Math. 605]



[2913] Further, (4) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (147-2-2), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (147-2-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[2914] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2915] The following holds true for X1. In the following, y is an integer no smaller than R#(2c),1+1 and no greater than r#(2c),1.
[Math. 606]





[2916] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than three, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 607]



[2917] Further, the following holds true for X4.
[Math. 608]



[2918] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than four and no greater than seven.
[Math. 609]





[2919] The following holds true for P1.
[Math. 610]



[2920] The following holds true for P2.
[Math. 611]



[2921] Further, (5) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (148-1-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (148-1-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2922] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2923] The following holds true for X1. In the following, y is an integer no smaller than R#(2d+1),1+1 and no greater than r#(2d+1),1.
[Math. 612]



[2924] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than three, and y is an integer no smaller than R#(2d+1),z+1 and no greater than r#(2d+1),z.
[Math. 613]



[2925] Further, the following holds true for X4.
[Math. 614]



[2926] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than four and no greater than seven.
[Math. 615]



[2927] The following holds true for P1.
[Math. 616]



[2928] The following holds true for P2.
[Math. 617]



[2929] Further, (6) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (148-1-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (148-1-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2930] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2931] The following holds true for X1. In the following, y is an integer no smaller than R#(2d+1),1+1 and no greater than r#(2d+1),1.
[Math. 618]



[2932] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than three, and y is an integer no smaller than R#(2d+1),z+1 and no greater than r#(2d+1),z.
[Math. 619]



[2933] Further, the following holds true for X4.
[Math. 620]





[2934] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than four and no greater than seven.
[Math. 621]



[2935] The following holds true for P1.
[Math. 622]



[2936] The following holds true for P2.
[Math. 623]



[2937] Further, (7) when g=2×f (where f is an integer no smaller than one), when a vector for row 2x(2xf) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (148-2-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (148-2-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2938] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2x(2xf) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2939] The following holds true for X1.
[Math. 624]



[2940] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than three.
[Math. 625]





[2941] Further, the following holds true for X4. In the following, y is an integer no smaller than R#(2d+1),4+1 and no greater than r#(2d+1),4.
[Math. 626]



[2942] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than four and no greater than seven, and y is an integer no smaller than R#(2d+1),z+1 and no greater than r#(2d+1),z.
[Math. 627]



[2943] The following holds true for P1.
[Math. 628]



[2944] The following holds true for P2.
[Math. 629]



[2945] Further, (8) when g=2×f (where f is an integer no smaller than one), when a vector for row 2x(2xf) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (148-2-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (148-2-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[2946] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2x(2xf) of the parity check matrix H, which is for an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[2947] The following holds true for X1.
[Math. 630]





[2948] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than three.
[Math. 631]



[2949] Further, the following holds true for X4. In the following, y is an integer no smaller than R#(2d+1),4+1 and no greater than r#(2d+1),4.
[Math. 632]



[2950] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than four and no greater than seven, and y is an integer no smaller than R#(2d+1),z+1 and no greater than r#(2d+1),z.
[Math. 633]



[2951] The following holds true for P1.
[Math. 634]



[2952] The following holds true for P2.
[Math. 635]



[2953] As such, an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial can be generated by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, and the code so generated achieves high error correction capability.

(Embodiment F3)



[2954] In the present embodiment, description is provided of a device that uses the LDPC-CC of coding rate 7/9 that is based on a parity check polynomial, description of which has been provided in embodiments F1 and F2.

[2955] As one example, description is provided of a case where the LDPC-CC of coding rate 7/9 that is based on a parity check polynomial, description of which has been provided in embodiments F1 and F2, is applied to a communication device.

[2956] FIG. 22 illustrates the structures of a transmitting device 2200 and a receiving device 2210 in the communication device pertaining to the present embodiment.

[2957] An encoder 2201 receives information to be transmitted as input, and is capable of performing various types of encoding. In particular, when receiving a specification to perform encoding by using the LDPC-CC of coding rate 7/9 that is based on a parity check polynomial, description of which has been provided in embodiments F1 and F2, the encoder 2201 performs encoding by using the LDPC-CC of coding rate 7/9 that is based on a parity check polynomial, description of which has been provided in embodiments F1 and F2, to calculate parities P1 and P2. Further, the encoder 2201 outputs the information to be transmitted and the parities P1 and P2 as a transmission sequence.

[2958] A modulator 2202 receives the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, performs mapping based on a predetermined modulation scheme (e.g., BPSK, QPSK, 16QAM, 64QAM), and outputs a baseband signal. Further, the modulator 2202 may also receive information other than the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, as input, perform mapping, and output a baseband signal. For example, the modulator 2202 may receive control information as input.

[2959] The transmitting device outputs a transmission signal after performing predetermined signal processing (e.g., signal processing for generation of an OFDM signal, frequency conversion, amplification) with respect to such signals (e.g., baseband signals, pilot signals). The transmitting device may transmit the transmission signal over a wireless transmission path utilizing electromagnetic waves, or over a wired transmission path utilizing a coaxial cable, a power line, an optical cable, or the like.

[2960] The transmission signal is received by the receiving device 2210 after travelling over the transmission path. A receiver 2211 receives a reception signal as input, performs predetermined signal processing (e.g., bandwidth limitation, frequency conversion, signal processing for OFDM, frequency offset estimation, signal detection, channel estimation), and outputs a baseband signal and a channel estimation signal.

[2961] A log-likelihood ratio generation section 2212 receives the baseband signal and the channel estimation signal as input (may receive other signals as input), and for example, calculates and outputs a log-likelihood ratio for each bit (may calculate and output a hard value (hard decision value)).

[2962] A decoder 2213 receives the log-likelihood ratio for each bit as input, performs belief propagation decoding (e.g., sum-product decoding, scheduled sum-product decoding (Layered BP (belief propagation) decoding), min-sum decoding, Normalized BP decoding, offset BP decoding), and outputs an estimation sequence. The decoder 2213 performs the belief propagation decoding based on the parity check matrix for the LDPC-CC of coding rate 7/9 that is based on a parity check polynomial, description of which has been provided in embodiments F1 and F2.

[2963]  FIG. 87 illustrates one example of the structure of an encoder for the LDPC-CC of coding rate 7/9 that is based on a parity check polynomial, description of which has been provided in embodiments F1 and F2. Description on such an encoder has been provided with reference to the encoder 2201 in FIG. 22.

[2964] In FIG. 87, an Xz computation section 4001-z (where z is an integer no smaller than one and no greater than seven) includes a plurality of shift registers that are connected in series and a calculator that performs XOR calculation on bits collected from some of the shift registers (refer to FIGs. 2 and 22).

[2965] The Xz computation section 4001-z receives an information bit Xz,j at time point j as input, performs the XOR calculation, and outputs bits 4002-z-1 and 4002-z-2, which are acquired through the Xz calculation.

[2966] A P1 computation section 4004-1 includes a plurality of shift registers that are connected in series and a calculator that that performs XOR calculation on bits collected from some of the shift registers (refer to FIGs. 2 and 22).

[2967] The P1 computation section 4004-1 receives a bit P1,j of parity P1 at time point j as input, performs the XOR calculation, and outputs bits 4005-1-1 and 4005-1-2, which are acquired through the P1 calculation.

[2968] A P2 computation section 4004-2 includes a plurality of shift registers that are connected in series and a calculator that that performs XOR calculation on bits collected from some of the shift registers (refer to FIGs. 2 and 22).

[2969] The P2 computation section 4004-2 receives a bit P2,j of parity P2 at time point j as input, performs the XOR calculation, and outputs bits 4005-2-1 and 4005-2-2, which are acquired through the P2 calculation.

[2970] An XOR (calculator) 4005-1 receives the bits 4002-1-1 through 4002-7-1 acquired by X1 calculation through X7 calculation, respectively, the bit 4005-1-1 acquired by P1 calculation, and the bit 4005-2-1 acquired by the P2 calculation as input, performs XOR calculation, and outputs a bit P1,j of parity P1 at time point j.

[2971] An XOR (calculator) 4005-2 receives the bits 4002-1-2 through 4002-7-2 acquired by X1 calculation through X7 calculation, respectively, the bit 4005-1-2 acquired by P1 calculation, and the bit 4005-2-2 acquired by the P2 calculation as input, performs XOR calculation, and outputs a bit P2,j of parity P2 at time point j.

[2972] It is preferable that initial values of the shift registers of the Xz computation section 4001-z, the P1 computation section 4004-1, and the P2 computation section 4004-2 illustrated in FIG. 87 be set to "0" (zero). By making such a configuration, it becomes unnecessary to transmit to the receiving device parities P1 and P2 before the setting of initial values.

[2973] The following describes a method of information-zero termination.

[2974] Suppose that in FIG. 88, information X1 through X7 exist from time point 0, and information X7 at time point s (where s is an integer no smaller than zero) is the last information bit. That is, suppose that the information to be transmitted from the transmitting device to the receiving device is information X1,j through X7,j, being information X1 through X7 at time point j, respectively, where j is an integer no smaller than zero and no greater than s.

[2975] In such a case, the transmitting device transmits information X1 through X7, parity P1, and parity P2 from time point 0 to time point s, or that is, transmits X1,j, X2,j, X3,j, X4,j, X5,j, X6,j, X7,j, P1,j, P2,j, where j is an integer no smaller than zero and no greater than s. (Note that P1,j and P2,j denote parity P1 and parity P2 at time point j, respectively.)

[2976] Further, suppose that information X1 through X7 from time point s+1 to time point s+g (where g is an integer no smaller than one) is "0", or that is, when denoting information X1 through X7 at time point t as X1,t, X2,t, X3,t, X4,t, X5,t, X6,t, X7,t, respectively, X1,t=0, X2,t=0, X3,t=0, X4,t=0, X5,t=0, X6,t=0, X7,t=0 hold true for t being an integer no smaller than s+1 and no greater than s+g. The transmitting device, by performing encoding, acquires parities P1,t and P2,t for t being an integer no smaller than s+1 and no greater than s+g. The transmitting device, in addition to the information and parities described above, transmits parities P1,t and P2,t for t being an integer no smaller than s+1 and no greater than s+g.

[2977] Meanwhile, the receiving device performs decoding by using log-likelihood ratios for the information and the parities transmitted by the transmitting device, and log-likelihood ratios corresponding to X1,t=0, X2,t=0, X3,t=0, X4,t=0, X5,t=0, X6,t=0, X7,t=0 for t being an integer no smaller than s+1 and no greater than s+g, and thereby acquires an estimation sequence of information.

[2978] FIG. 89 illustrates an example differing from that illustrated in FIG. 88. Suppose that information X1 through X7 exist from time point 0, and information Xf for time point s (where s is an integer no smaller than zero) is the last information bit. Here, f is an integer no smaller than one and no greater than six. In FIG. 88, f equals 5, for example. That is, suppose that the information to be transmitted from the transmitting device to the receiving device is information Xi,s, where i is an integer no smaller than one and no greater than f, and information X1,j, information X2,j, information X3,j, information X4,j, information X5,j, information X6,j, information X7,j, being information X1 through X7 at time point j, respectively, where j is an integer no smaller than zero and no greater than s-1.

[2979] In such a case, the transmitting device transmits information X1 through X7, parity P1, and parity P2 from time point 0 to time point s-1, or that is, transmits X1,j, X2,j, X3,j, X4,j, X5,j, X6,j, X7,j, P1,j, P2,j, where j is an integer no smaller than zero and no greater than s-1. (Note that P1,j and P2,j denote parity P1 and parity P2 at time point j, respectively.)

[2980] Further, suppose that at time point s, information Xi,s, when i is an integer no smaller than one and no greater than f, is information that the transmitting device is to transmit, and suppose that Xk,s, when k is an integer so smaller than f+1 and no greater than seven, equals "0" (zero).

[2981] Further, suppose that information X1 through X7 from time point s+1 to time point s+g-1 (where g is an integer no smaller than two) is "0", or that is, when denoting information X1 through X7 at time point t as X1,t, X2,t, X3,t, X4,t, X5,t, X6,t, X7,t, respectively, X1,t=0, X2,t=0, X3,t=0, X4,t=0, X5,t=0, X6,t=0, X7,t=0 hold true when t is an integer no smaller than s+1 and no greater than s+g-1. The transmitting device, by performing encoding from time point s to time point s+g-1, acquires parities P1,u and P2,u for u being an integer no smaller than s and no greater than s+g-1. The transmitting device, in addition to the information and parities described above, transmits Xi,s for i being an integer no smaller than one and no greater than f, and parities P1,u and P2,u for u being an integer no smaller than s and no greater than s+g-1.

[2982] Meanwhile, the receiving device performs decoding by using log-likelihood ratios for the information and the parities transmitted by the transmitting device, log-likelihood ratios corresponding to Xk,s=0 (where k is an integer no smaller than f+1 and no greater than seven) and log-likelihood ratios corresponding to X1,t=0, X2,t=0, X3,t=0, X4,t=0, X5,t=0, X6,t=0, X7,t=0 for t being an integer no smaller than s+1 and no greater than s+g-1, and thereby acquires an estimation sequence of information.

[2983] Although description is provided above taking an example where error correction coding is introduced to a communication device, the error correction coding described above is not limited to being introduced to a communication device, and for example, may be introduced to a storage medium (storage). When making such a modification, information that is to be stored to a storage medium (storage) is encoded by using the LDPC-CC of coding rate 7/9 that is based on a parity check polynomial, description of which has been provided in embodiments F1 and F2, and resultant information and parities are stored to the storage medium (storage). When making such a modification, it is preferable that information-zero termination be introduced as described above and that a data sequence as described above corresponding to a data sequence (information and parities) transmitted by the transmitting device when information-zero termination is applied be stored to the storage medium (storage).

[2984] Further, the LDPC-CC of coding rate 7/9 that is based on a parity check polynomial, description of which has been provided in embodiments F1 and F2, is applicable to any device that requires error correction coding (e.g., a memory, a hard disk).

(Embodiment F4)



[2985] In the present embodiment, description is provided of a method of configuring an LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). The LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme described in the present embodiment is based on the LDPC-CC of coding rate 7/9 that is based on a parity check polynomial, description of which has been provided in embodiments F1 and F2.

[2986] Patent Literature 2 includes explanation regarding an LDPC-CC of coding rate (n-1)/n (where n is an integer no smaller than two) that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). However, Patent Literature 2 poses a problem for not disclosing an LDPC-CC of a coding rate not satisfying (n-1)/n that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[2987] In the present embodiment, as one example of an LDPC-CC of a coding rate not satisfying (n-1)/n that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), description is provided of a method of configuring an LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[Periodic Time-varying LDPC-CC of Coding rate 7/9 Using Improved Tail-biting Scheme and Based on Parity Check Polynomial]



[2988] The following describes a periodic time-varying LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme and is based on a parity check polynomial, based on the configuration of the LDPC-CC of coding rate 7/9 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments F1 and F2.

[2989] The following describes a method of configuring an LDPC-CC of coding rate 7/9 and time-varying period 2m that is based on a parity check polynomial. Such method has already been described in embodiment F2.

[2990] First, the following parity check polynomials satisfying zero are prepared.
[Math. 636-1]





[Math. 636-2]







[2991] In expressions (197-1-1), (197-1-2), (197-2-1), (197-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[2992] In expressions (197-1-1), (197-1-2), (197-2-1), (197-2-2), α#(2i),p,q (where p is an integer no smaller than one and no greater than seven, q is an integer no smaller than one and no greater than r#(2i),p (where r#(2i),p is a natural number)) and β#(2i),0 is a natural number, β#(2i),1 is a natural number, β#(2i),2 is an integer no smaller than zero, and β#(2i),3 is a natural number.

[2993] Further, R#(2i),p is a natural number satisfying 1≤R#(2i),p<r#(2i),p.

[2994] Further, y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for all y and all z satisfying y≠z.)

[2995] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (197-1-1) or expression (197-1-2) is referred to as "#(2i); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (197-2-1) or expression (197-2-2) is referred to as "#(2i); second expression" for realizing a time-varying period 2m.

[2996] Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (197-1-1) or expression (197-1-2) is prepared.

[2997] That is, for i=0, a parity check polynomial satisfying zero provided by expression (197-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (197-1-2) where i=0 is prepared.

[2998] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (197-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (197-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (197-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (197-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (197-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (197-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (197-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (197-1-2) where i=m-1 is prepared.



[2999] Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (197-2-1) or expression (197-2-2) is prepared.

[3000] That is, for i=0, a parity check polynomial satisfying zero provided by expression (197-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (197-2-2) where i=0 is prepared.

[3001] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (197-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (197-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (197-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (197-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (197-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (197-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (197-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (197-2-2) where i=m-1 is prepared.



[3002] Similarly, the following parity check polynomials satisfying zero are provided.
[Math. 637-1]





[Math. 637-2]







[3003] In expressions (198-1-1), (198-1-2), (198-2-1), (198-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[3004] In expressions (198-1-1), (198-1-2), (198-2-1), (198-2-2), α#(2i+1),p,q (where p is an integer no smaller than one and no greater than seven, q is an integer no smaller than one and no greater than r#(2i+1),p (where r#(2i+1),p is a natural number)) and β#(2i+1),0 is a natural number, β#(2i+1),1 is a natural number, β#(2i+1),2 is an integer no smaller than zero, and β#(2i+1),3 is a natural number.

[3005] Further, R#(2i+1),p is a natural number satisfying 1≤R#(2i+1),p<r#(2i+1),p.

[3006]  Further, y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for all y and all z satisfying y≠z.)

[3007] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (198-1-1) or expression (198-1-2) is referred to as "#(2i+1); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (198-2-1) or expression (198-2-2) is referred to as "#(2i+1); second expression" for realizing a time-varying period 2m.

[3008] Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (198-1-1) or expression (198-1-2) is prepared.

[3009] That is, for i=0, a parity check polynomial satisfying zero provided by expression (198-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (198-1-2) where i=0 is prepared.

[3010] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (198-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (198-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (198-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (198-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (198-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (198-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (198-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (198-1-2) where i=m-1 is prepared.



[3011] Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (198-2-1) or expression (198-2-2) is prepared.

[3012] That is, for i=0, a parity check polynomial satisfying zero provided by expression (198-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (198-2-2) where i=0 is prepared.

[3013] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (198-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (198-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (198-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (198-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (198-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (198-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (198-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (198-2-2) where i=m-1 is prepared.



[3014] As such, an LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3015] Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (197-1-1) or expression (197-1-2), parity check polynomials satisfying zero provided by expression (197-2-1) or expression (197-2-2), parity check polynomials satisfying zero provided by expression (198-1-1) or expression (198-1-2), and parity check polynomials satisfying zero provided by expression (198-2-1) or expression (198-2-2).

[3016] For example, the time varying period 2×m is formed by preparing a 4×m number of different parity check polynomials satisfying zero.

[3017] Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

[3018] The following describes the relationship between time point j and expressions (197-1-1), (197-1-2), (197-2-1), (197-2-2), (198-1-1), (198-1-2), (198-2-1), and (198-2-2) (where j is an integer no smaller than zero).

[3019] The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m-1).

[3020] Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i = k in #(2i); first expression and #(2i); second expression, hold true.

[3021] Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m-1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

[3022] Note that in the parity check polynomials satisfying zero of expressions (197-1-1), (197-1-2), (197-2-1), (197-2-2), (198-1-1), (198-1-2), (198-2-1), and (198-2-2), a sum of the number of terms of P1(D) and the number of terms of P2(D) equals two. This realizes sequentially finding parities P1 and P2 when applying an improved tail-biting scheme, and thus, is a significant factor realizing a reduction in computation amount (circuit scale).

[3023] The following describes the relationship between the time-varying period of the parity check polynomials satisfying zero for the LDPC-CC of coding rate 7/9 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments F1 and F2 and on which the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, and block size in the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) proposed in the present embodiment.

[3024] Regarding this point, in order to achieve error correction capability of even higher level, a configuration is preferable where a Tanner graph formed by the LDPC-CC of coding rate 7/9 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments F1 and F2 and on which the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, resembles a Tanner graph of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). Thus, the following conditions are significant.

<Condition #N1>



[3025] 
  • The number of rows in a parity check matrix for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is a multiple of 4×m.
    • Accordingly, the number of columns in the parity check matrix for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is a multiple of 9×2×m. According to this condition, (for example) a log-likelihood ratio that is necessary in decoding is a log-likelihood ratio of the number of columns in the parity check matrix for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).


[3026] Note that the relationship between the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and the LDPC-CC of coding rate 7/9 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments F1 and F2 and on which the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, is described in detail later in the present disclosure.

[3027] Thus, when denoting the parity check matrix for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as Hpro, the number of columns of Hpro can be expressed as 9×2×m×z (where z is a natural number).

[3028] Accordingly, a transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as vs=(Xs,1,1, Xs,2,1, ..., Xs,7,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,7,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,7,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,7,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T (where k=1, 2, ..., 2×m×z-1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×z)), and Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes).

[3029] Xs,j,k (where j is an integer no smaller than one and no greater than seven) is a bit of information Xj, Ppros,1,k is a bit of parity P1 of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and Ppros,2,k is a bit of parity P2 of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[3030] Further, λpro,s,k=(Xs,1,k, Xs,2,k, Xs,3,k, Xs,4,k, Xs,5,k, Xs,6,k, Xs,7,k, Ppros,1,k, Ppros,2,k) holds true.

[3031] In addition, the number of rows in the parity check matrix Hpro for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is 4×m×z.

[3032] It has been indicated above that the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based on the LDPC-CC of coding rate 7/9 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments F1 and F2. This is explained in the following.

[3033] First, consideration is made of a parity check matrix when configuring a periodic time-varying LDPC-CC using tail-biting by using only parity check polynomials satisfying zero for the LDPC-CC of coding rate 7/9 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments F1 and F2.

[3034] FIG. 90 illustrates a configuration of a parity check matrix H when configuring a periodic time-varying LDPC-CC using tail-biting by performing tail-biting by using only parity check polynomials satisfying zero for an LDPC-CC of coding rate 7/9 and time-varying period 2m.

[3035] Since Condition #N1 is satisfied in FIG. 90, the number of rows of the parity check matrix is m×z and the number of columns of the parity check matrix is 9×2×m×z.

[3036] As illustrated in FIG. 90:

"a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×(2m-1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression";

"a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression";

"a vector for the 2×(2m+1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the 2×(2m+2)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×i-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); first expression";

"a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); second expression" (where i is an integer no smaller than one and no greater than 2×m×z);

"a vector for the 2×(2m-1)×z-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)×zth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)×z-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression"; and

"a vector for the 2×(2m)×zth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression".



[3037] To prepare for the explanation to be provided in the following, a mathematical expression is provided of the parity check matrix H in FIG. 90, which is a parity check matrix when configuring a periodic time-varying LDPC-CC by performing tail-biting by using only parity check polynomials satisfying zero for the LDPC-CC of coding rate 7/9 and time-varying period 2m that is based on a parity check polynomial, description of which is provided in embodiments F1 and F2. When denoting a vector having one row and 9×2×m×z columns in row k of the parity check matrix H as hk, the parity check matrix H in FIG. 90 is expressed as follows.
[Math. 638]



[3038] The following describes a parity check matrix for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[3039] FIG. 91 illustrates one example of a configuration of a parity check matrix Hpro for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[3040] The parity check matrix Hpro for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) satisfies Condition #N1.

[3041] When denoting a vector having one row and 9×2×m×z columns in row k of the parity check matrix Hpro in FIG. 91, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), as gk, the parity check matrix Hpro in FIG. 91 is expressed as follows.
[Math. 639]



[3042] A transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as Vs=(Xs,1,1, Xs,2,1, ..., Xs,7,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,7,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,7,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,7,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λprο,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T (where k=1, 2, ..., 2×m×z-1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×z)), and Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes).

[3043] Xs,j,k (where j is an integer no smaller than one and no greater than seven) is a bit of information Xj, Ppros,1,k is a bit of parity P1 of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and Ppros,2,k is a bit of parity P2 of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[3044] In the parity check matrix Hpro in FIG. 91, which illustrates one example of a configuration of a parity check matrix Hpro for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), rows other than row one, or that is, rows between row two to row 2×(2×m)×z in the parity check matrix Hpro in FIG. 91, have the same configuration as rows between row two and row 2×(2×m)×z in the parity check matrix H in FIG. 90 (refer to FIGs. 90 and 91). Accordingly, FIG. 91 includes an indication of #0'; first expression at 4401 in the first row. (This point is explained later in the present disclosure.) Accordingly, the following relational expression holds true based on expressions 199 and 200.

[Math. 640]



[3045] Further, the following holds true when i=1.
[Math. 641]



[3046] Accordingly, the parity check matrix Hpro for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as follows.
[Math. 642]



[3047] In expression 203, expression 202 holds true.

[3048] Next, explanation is provided of a method of configuring g1 in expression 203 so that parities can be found sequentially and high error correction capability can be achieved.

[3049] One example of a method of configuring g1 in expression 203, so that parities can be found sequentially and high error correction capability can be achieved, is using a parity check polynomial satisfying zero of #0; first expression of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), which serves as the basis.

[3050] Since g1 is row one of the parity check matrix Hpro for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), g1 is generated from a parity check polynomial satisfying zero that is obtained by transforming a parity check polynomial satisfying zero of #0; first expression. As described above, a parity check polynomial satisfying zero of #0; first expression is expressed by either expression (204-1-1) or expression (204-1-2).
[Math. 643]







[3051] As one example of a parity check polynomial satisfying zero for generating vector g1 in row one of the parity check matrix Hpro for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), a parity check polynomial satisfying zero of #0; first expression is expressed as follows, for either expression (204-1-1) or expression (204-1-2).
[Math. 644]



[3052] Accordingly, vector g1 is a vector having one row and 9×2×m×z columns that is obtained by performing tail-biting with respect to expression 205.

[3053] Note that in the following, a parity check polynomial that satisfies zero provided by expression 205 is referred to as #0'; first expression.

[3054] Accordingly, row one of the parity check matrix Hpro for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be obtained by transforming #0'; first expression of expression 205 (that is, a vector g1 corresponding to one row and 9×2×m×z columns can be obtained).

[3055] A transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is vs=(Xs,1,1, Xs,2,1, ..., Xs,7,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,7,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,7,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,7,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T, and the number of parity check polynomials satisfying zero necessary for obtaining this transmission sequence is 2×(2×m)×z.

[3056] Here, when arranging such 2×(2×m)×z number of parity check polynomials satisfying zero in order, a parity check polynomial satisfying zero appearing eth is referred to in the following as an "eth parity check polynomial satisfying zero" (where e is an integer no smaller than zero and no greater than 2×(2×m)×z-1).

[3057] As such, the parity check polynomials satisfying zero are arranged in the following order:

zeroth: zeroth parity check polynomial satisfying zero;

first: first parity check polynomial satisfying zero;

second: second parity check polynomial satisfying zero;

eth: eth parity check polynomial satisfying zero;

2×(2×m)×z-2th: 2×(2×m)×z-2th parity check polynomial satisfying zero; and

2×(2×m)×z-1th: 2×(2×m)×z-1th parity check polynomial satisfying zero.



[3058] Accordingly, the transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is obtained. (As can be seen from description provided above, when expressing the parity check matrix Hpro for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as provided in expression 200, a vector composed of row e+1 of the parity check matrix Hpro corresponds to the eth parity check polynomial satisfying zero.)

[3059] Accordingly, in the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the second parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the third parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression;

the 2×(2m)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression;

the 2×(2m+1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; first expression;

the 2×(2m+1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×(2m+2)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the 2×(2m+2)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression; and

the 2×(2m)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression.



[3060] That is,
the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;
the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;
the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression; and
the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).

[3061] As description has been provided above, the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), at the same time as achieving high error correction capability, enables finding multiple parities sequentially, and therefore, achieves an advantageous effect of reducing circuit scale of an encoder.

[3062] In the following, explanation is provided of what is meant by "finding parities sequentially".

[3063] In the example described above, since bits of information X1 through X7 are pre-acquired, Ppros,1,1 can be calculated by using the 0th parity check polynomial satisfying zero of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), or that is, by using the parity check polynomial satisfying zero of #0'; first expression provided by expression 205.

[3064] Then, from the bits of information X1 through X7 and Ppros,1,1, another parity (denoted as Pc=1) can be calculated by using another parity check polynomial satisfying zero.

[3065] Further, from the bits of information X1 through X7 and Pc=1, another parity (denoted as Pc=2) can be calculated by using another parity check polynomial satisfying zero.

[3066] By repeating such operation, from the bits of information X1 through X7 and Pc=h, another parity (denoted as Pc=h+1) can be calculated by using a given parity check polynomial satisfying zero.

[3067] This is referred to as "finding parities sequentially", and when parities can be found sequentially, multiple parities can be obtained without calculation of complex simultaneous equations, whereby an advantageous effect is achieved of reducing circuit scale (computation amount) of an encoder.

[3068] Next, explanation is provided of configurations and operations of an encoder and a decoder for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[3069] In the following, one example case is considered where the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is used in a communication system. When applying the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) to a communication system, the encoder and the decoder for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) are characterized for each being configured and each operating based on the parity check matrix Hpro for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and based on the relationship Hprovs=0.

[3070] The following provides explanation while referring to FIG. 25, which is an overall diagram of a communication system. An encoder 2511 of a transmitting device 2501 receives an information sequence of block s (Xs,1,1, Xs,2,1, ..., Xs,7,1, Xs,1,2, Xs,2,2, ..., Xs,7,2, ..., Xs,1,k, Xs,2,k, ..., Xs,7,k, ..., Xs,1,2×m×z, Xs2,2×m×z, ..., Xs,7,2×m×z) as input. The encoder 2511 performs encoding based on the parity check matrix Hpro for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and based on the relationship Hprovs=0. The encoder 2511 generates a transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), denoted as vs=(Xs,1,1, Xs,2,1, ..., Xs,7,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,7,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,7,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,7,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T, and outputs the transmission sequence vs. As already described above, the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is characterized for enabling parities to be found sequentially.

[3071] A decoder 2523 of a receiving device 2520 in FIG. 25 receives, as input, a log-likelihood ratio of each bit of, for example, the transmission sequence vs=(Xs,1,1, Xs,2,1, ..., Xs,7,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,7,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,7,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,7,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T. The log-likelihood ratios are output from a log-likelihood ratio generator 2522. The decoder 2523 performs decoding for an LDPC code according to the parity check matrix Hpro for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). For example, the decoding may be decoding disclosed in Non-Patent Literature 4, Non-Patent Literature 6, Non-Patent Literature 7, Non-Patent Literature 8, etc., i.e., simple BP decoding such as min-sum decoding, offset BP decoding, or Normalized BP decoding, or Belief Propagation (BP) decoding in which scheduling is performed with respect to the row operations (Horizontal operations) and the column operations (Vertical operations) such as Shuffled BP decoding or Layered BP decoding. The decoding may also be decoding such as bit-flipping decoding disclosed in Non-Patent Literature 17, for example. The decoder 2523 obtains an estimation transmission sequence (estimation encoded sequence) (reception sequence) of block s through the decoding, and outputs the estimation transmission sequence.

[3072] In the above, explanation is provided on operations of the encoder and the decoder in a communication system as one example. Alternatively, the encoder and the decoder may be used in technical fields related to storages, memories, etc.

[3073] The following describes a specific example of a configuration of a parity check matrix for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[3074] When denoting the parity check matrix for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as Hpro as described above, the number of columns of Hpro can be expressed as 9×2×m×z (where z is a natural number). (Note that m denotes a time-varying period of the LDPC-CC of coding rate 7/9 that is based on a parity check polynomial, which serves as the basis.)

[3075] Accordingly, as already described above, a transmission sequence (encoded sequence (codeword)) vs composed of a 7×2×m×z number of bits in block s of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as vs=(Xs,1,1, Xs,2,1, ..., Xs,7,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,7,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,7,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,7,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λprο,s,2×m×z-1, λpro,s,2×m×z)T (where k=1, 2, ..., 2×m×z-1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×z)), and Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes).

[3076] Xs,j,k (where j is an integer no smaller than one and no greater than seven) is a bit of information Xj, Ppros,1,k is a bit of parity P1 of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and Ppros,2,k is a bit of parity P2 of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[3077] Further, λpro,s,k=(Xs,1,k, Xs,2,k, Xs,3,k, Xs,4,k, Xs,5,k, Xs,6,k, Xs,7,k, Ppros,1,k, Ppros,2,k) holds true.

[3078] In addition, the number of rows in the parity check matrix Hpro for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is 4×m×z.

[3079] Note that the method of configuring parity check polynomials satisfying zero for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) has already been described above.

[3080] In the above, description has been provided of a parity check matrix Hpro for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), whose transmission sequence (encoded sequence (codeword)) vs of block s is vs=(Xs,1,1, Xs,2,1, ..., Xs,7,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,7,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,7,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,7,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T and for which Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes). The following provides description of a configuration of a parity check matrix Hpro_m for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), for which Hpro_mus=0 holds true (here, Hpro_mus=0 indicates that all elements of the vector Hpro_mus are zeroes) when expressing a transmission sequence (encoded sequence (codeword)) us of block s as us=(Xs,1,1, Xs,1,2, ..., Xs,1,2×m×z-1, Xs,1,2×m×z, Xs,2,1, Xs,2,2, ..., Xs,2,2×m×z-1, Xs,2,2×m×z, Xs,3,1, Xs,3,2, ..., Xs,3,2×m×z-1, Xs,3,2×m×z, Xs,4,1, Xs,4,2, ..., Xs,4,2×m×z-1, Xs,4,2×m×z, Xs,5,1, Xs,5,2, ..., Xs,5,2×m×z-1, Xs,5,2×m×z, Xs,6,1, Xs,6,2, ..., Xs,6,2×m×z-1, Xs,6,2×m×z, Xs,7,1, Xs,7,2, ..., Xs,7,2×m×z-1, Xs,7,2×m×z, Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z, Ppros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, Ppros,2,2×m×z)T=(ΛX1,s, ΛX2,s, ΛX3,s, ΛX4,s, ΛX5,s, ΛX6,s, ΛX7,s, Λpro1,s, Λpro2,s)T.

[3081] Note that ΛXf,s (where f is an integer no smaller than one and no greater than seven) satisfies ΛXf,s=(Xs,f,1, Xs,f,2, Xs,f,3, ..., Xs,f,2×m×z-2, Xs,f,2×m×z-1, Xs,f,2×m×z) (ΛXf,s is a vector having one row and 2×m×z columns), and Λpro1,s and Λpro2,s satisfy Λpro1,s=(Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z) and Λpro2,s=(Ppros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, Ppros,2,2×m×z), respectively (Λpro1,s and Λpro2,s are both vectors having one row and 2×m×z columns).

[3082] Here, the number of bits of information X1 included in one block is 2×m×z, the number of bits of information X2 included in one block is 2×m×z, the number of bits of information X3 included in one block is 2×m×z, the number of bits of information X4 included in one block is 2×m×z, the number of bits of information X5 included in one block is 2×m×z, the number of bits of information X6 included in one block is 2×m×z, the number of bits of information X7 included in one block is 2×m×z, the number of bits of parity bits P1 included in one block is 2×m×z, and the number of bits of parity bits P2 included in one block is 2×m×z. Accordingly, the parity check matrix Hpro_m for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as Hpro_m=[Hx,1, Hx,2, Hx,3, Hx,4, Hx,5, Hx,6, Hx,7, Hp1, Hp2], as illustrated in FIG. 92. Since a transmission sequence (encoded sequence (codeword)) us of block s is us=(Xs,1,1, Xs,1,2, ..., Xs,1,2×m×z-1, Xs,1,2×m×z, Xs,2,1, Xs,2,2, ..., Xs,2,2×m×z-1, Xs,2,2×m×z, Xs,3,1, Xs,3,2, ..., Xs,3,2×m×z-1, Xs,3,2×m×z, Xs,4,1, Xs,4,2, ..., Xs,4,2×m×z-1, Xs,4,2×m×z, Xs,5,1, Xs,5,2, ..., Xs,5,2×m×z-1, Xs,5,2×m×z, Xs,6,1, Xs,6,2, ..., Xs,6,2×m×z-1, Xs,6,2×m×z, Xs,7,1, Xs,7,2, ..., Xs,7,2×m×z-1, Xs,7,2×m×z, Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z, Ppros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, Ppros,2,2×m×z)T=(ΛX1,s, ΛX2,s, ΛX3,s, ΛX4,s, ΛX5,s, ΛX6,s, ΛX7,s, Λpro1,s, Λpro2,s)T, Hx,1 is a partial matrix related to information X1, Hx,2 is a partial matrix related to information X2, Hx,3 is a partial matrix related to information X3, Hx,4 is a partial matrix related to information X4, Hx,5 is a partial matrix related to information X5, Hx,6 is a partial matrix related to information X6, Hx,7 is a partial matrix related to information X7, Hp1 is a partial matrix related to parity P1, and Hp2 is a partial matrix related to parity P2. As illustrated in FIG. 92, the parity check matrix Hpro_m has 4×m×z rows and 9×2×m×z columns, the partial matrix Hx,1 related to information X1 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,2 related to information X2 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,3 related to information X3 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,4 related to information X4 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,5 related to information X5 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,6 related to information X6 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,7 related to information X7 has 4×m×z rows and 2×m×z columns, the partial matrix Hp1 related to parity P1 has 4×m×z rows and 2×m×z columns, and the partial matrix Hp2 related to parity P2 has 4×m×z rows and 2×m×z columns.

[3083] The transmission sequence (encoded sequence (codeword)) us composed of a 9×2×m×z number of bits in block s of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is us=(Xs,1,1, Xs,1,2, ..., Xs,1,2×m×z-1, Xs,1,2×m×z, Xs,2,1, Xs,2,2, ..., Xs,2,2×m×z-1, Xs,2,2×m×z, Xs,3,1, Xs,3,2, ..., Xs,3,2×m×z-1, Xs,3,2×m×z, Xs,4,1, Xs,4,2, ..., Xs,4,2×m×z-1, Xs,4,2×m×z, Xs,5,1, Xs,5,2, ..., Xs,5,2×m×z-1, Xs,5,2×m×z, Xs,6,1, Xs,6,2, ..., Xs,6,2×m×z-1, Xs,6,2×m×z, Xs,7,1, Xs,7,2, ..., Xs,7,2×m×z-1, Xs,7,2×m×z, Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z, Ppros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, PPros,2,2×m×z)TX1,s, ΛX2,s, ΛX3,s, ΛX4,s, ΛX5,s, ΛX6,s, ΛX7,s, Λpro1,s, Λpro2,s)T, and the number of parity check polynomials satisfying zero necessary for obtaining this transmission sequence is 4×m×z.

[3084] Here, when arranging such 2×(2×m)×z number of parity check polynomials satisfying zero in order, a parity check polynomial satisfying zero appearing eth is referred to in the following as an "eth parity check polynomial satisfying zero" (where e is an integer no smaller than zero and no greater than 2×(2×m)×z-1).

[3085] As such, the parity check polynomials satisfying zero are arranged in the following order:

zeroth: zeroth parity check polynomial satisfying zero;

first: first parity check polynomial satisfying zero;

second: second parity check polynomial satisfying zero;

eth: eth parity check polynomial satisfying zero;

2×(2×m)×z-2th: 2×(2×m)×z-2th parity check polynomial satisfying zero; and

2×(2×m)×z-1th: 2×(2×m)×z-1th parity check polynomial satisfying zero.



[3086] Accordingly, the transmission sequence (encoded sequence (codeword)) us of block s of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is obtained.

[3087] Accordingly, in the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the second parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the third parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression;

the 2×(2m)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression;

the 2×(2m+1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; first expression;

the 2×(2m+1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×(2m+2)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the 2×(2m+2)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression; and

the 2×(2m)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression.



[3088] That is,
the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;
the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;
the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression; and
the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).

[3089] In the present embodiment (in fact, commonly applying to the entirety of the present disclosure), % means a modulo, and for example, α%q represents a remainder after dividing α by q (where α is an integer no smaller than zero, and q is a natural number).

[3090] The following describes details of the configuration of the parity check matrix Hpro_m for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) based on what has been described above.

[3091] The parity check matrix Hpro_m for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) has 4×m×z rows and 9×2×m×z columns.

[3092] Accordingly, the parity check matrix Hpro_m for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) has rows one through 4×m×z, and columns one through 9×2×m×z.

[3093] Here, the topmost row of the parity check matrix Hpro_m is considered as the first row. Further, row number is incremented by one each time moving to a lower row. Accordingly, the topmost row is considered as the first row, the row immediately below the first row is considered as the second row, and the subsequent rows are considered as the third row, the fourth row, and so on.

[3094] Further, the leftmost column of the parity check matrix Hpro_m is considered as the first column. Further, column number is incremented by one each time moving to a rightward column. Accordingly, the leftmost column is considered as the first column, the column immediately to the right of the first column is considered as the second column, and the subsequent columns are considered as the third column, the fourth column, and so on.

[3095] In the parity check matrix Hpro_m, the partial matrix Hx,1 related to information X1 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,1 related to information X1 is denoted as Hx,1,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3096] Similarly, in the parity check matrix Hpro_m, the partial matrix Hx,2 related to information X2 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,2 related to information X2 is denoted as Hx,2,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3097] Further, in the parity check matrix Hpro_m, the partial matrix Hx,3 related to information X3 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,3 related to information X3 is denoted as Hx,3,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3098] Further, in the parity check matrix Hpro_m, the partial matrix Hx,4 related to information X4 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,4 related to information X4 is denoted as Hx,4,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3099] Further, in the parity check matrix Hpro_m, the partial matrix Hx,5 related to information X5 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,5 related to information X5 is denoted as Hx,5,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3100] Further, in the parity check matrix Hpro_m, the partial matrix Hx,6 related to information X6 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,6 related to information X6 is denoted as Hx,6,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3101] Further, in the parity check matrix Hpro_m, the partial matrix Hx,7 related to information X7 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,7 related to information X7 is denoted as Hx,7,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3102] Further, in the parity check matrix Hpro_m, the partial matrix Hp,1 related to parity P1 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hp,1 related to parity P1 is denoted as Hp1,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3103] Similarly, in the parity check matrix Hpro_m, the partial matrix Hp,2 related to parity P2 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hp,2 related to parity P2 is denoted as Hp2,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3104] The following provides detailed description of the configuration of Hx,1,comp[u][v], Hx,2,comp[u][v], Hx,3,comp[u][v], Hx,4,comp[u][v], Hx,5,comp[u][v], Hx,6,comp[u][v], Hx,7,comp[u][v], Hp1,comp[u][v], and Hp2,comp[u][v].

[3105] As already described above, in the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the second parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the third parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression;

the 2×(2m)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression;

the 2×(2m+1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; first expression;

the 2×(2m+1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×(2m+2)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the 2×(2m+2)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression; and

the 2×(2m)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression.



[3106] That is,
the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;
the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;
the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression; and
the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).

[3107] Further, a vector composed of row e+1 of the parity check matrix Hpro_m corresponds to the eth parity check polynomial satisfying zero.

[3108] Accordingly,
a vector composed of row one of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;
a vector composed of row two of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0; second expression;
a vector composed of row 2×g-1 of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); first expression; and
a vector composed of row 2×g of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); second expression (where g is an integer no smaller than two and no greater than 2×m×z).

[3109] Hx,1,comp[u][v], Hx,2,comp[u][v], Hx,3,comp[u][v], Hx,4,comp[u][v], Hx,5,comp[u][v], Hx,6,comp[u][v], Hx,7,comp[u][v], Hp1,comp[u][v], and Hp2,comp[u][v] can be expressed according to the relationship described above.

[3110] First, description is provided of the configuration of Hx,1,comp[u][v], Hx,2,comp[u][v], Hx,3,comp[u][v], Hx,4,comp[u][v], Hx,5,comp[u][v], Hx,6,comp[u][v], Hx,7,comp[u][v], Hp1,comp[u][v], and Hp2,comp[u][v] for row one of the parity check matrix Hpro_m, or that is, for u=1 .

[3111] The vector composed of row one of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0'; first expression provided by expression 205. Accordingly, Hx,1,comp[1][v] can be expressed as follows.
[Math. 645]





[3112] Considered in a similar manner, the following holds true for Hx,w,comp[1][v], where w is an integer no smaller than one and no greater than three.
[Math. 646]



[3113] Further, Hx,4,comp[1] [v] can be expressed as follows.
[Math. 647]



[3114] Considered in a similar manner, the following holds true for HxΩ,comp[1][v]. In the following, Ω is an integer no smaller than four and no greater than seven.
[Math. 648]





[3115] Further, Hp1,comp[1][v] can be expressed as follows.
[Math. 649]



[3116] Further, Hp2,comp[1][v] can be expressed as follows.
[Math. 650]



[3117] The vector composed of row two of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0; second expression. As described above, a parity check polynomial satisfying zero of #0; second expression is expressed by either expression (197-2-1) or expression (197-2-2).

[3118] Accordingly, Hx,1,comp[2][v] can be expressed as follows.
  1. <1> When a parity check polynomial satisfying zero of #0; second expression is expressed as provided in expression (197-2-1):
    Hx,1,comp[2][v] is expressed as follows.
    [Math. 651]




    Considered in a similar manner, the following holds true for Hx,Ω,comp[2][v], where Ω is an integer no smaller than one and no greater than three.
    [Math. 652]


    Further, Hx,4,comp[2][v] is expressed as follows.
    [Math. 653]


    Considered in a similar manner, the following holds true for Hx,w,comp[2][v], where w is an integer no smaller than four and no greater than seven.
    [Math. 654]




    Further, Hp1,comp[2][v] can be expressed as follows.
    [Math. 655]


    Further, Hp2,comp[2][v] can be expressed as follows.
    [Math. 656]

  2. <2> When a parity check polynomial satisfying zero of #0; second expression is expressed as provided in expression (197-2-2):
    Hx,1,comp[2][v] is expressed as follows.
    [Math. 657]



[3119] Considered in a similar manner, the following holds true for Hx,Ω,comp[2][v], where Ω is an integer no smaller than one and no greater than three.
[Math. 658]





[3120] Further, Hx,4,comp[2][v] is expressed as follows.
[Math. 659]



[3121] Considered in a similar manner, the following holds true for Hx,w,comp[2][v], where w is an integer no smaller than four and no greater than seven.
[Math. 660]



[3122] Further, Hp1,comp[2][v] can be expressed as follows.
[Math. 661]





[3123] Further, Hp2,comp[2][v] can be expressed as follows.
[Math. 662]



[3124] As already described above,
the vector composed of row 2×g-1 of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); first expression; and
the vector composed of row 2×g of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); second expression (where g is an integer no smaller than two and no greater than 2×m×z).

[3125] Accordingly, when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), a vector of row 2×(2×f-1)-1 of the parity check matrix Hpro_m for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); first expression, or that is, by using a parity check polynomial satisfying zero provided by expression (197-1-1) or expression (197-1-2).

[3126] Further, a vector of row 2×(2×f-1) of the parity check matrix Hpro_m for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); second expression, or that is, by using a parity check polynomial satisfying zero provided by expression (197-2-1) or expression (197-2-2).

[3127] Further, when g=2×f (where f is an integer no smaller than one and no greater than m×z), a vector of row 2×(2×f)-1 of the parity check matrix Hpro_m for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f)-1)%2m); first expression, or that is, by using a parity check polynomial satisfying zero provided by expression (198-1-1) or expression (198-1-2).

[3128] Further, a vector of row 2×(2×f) of the parity check matrix Hpro_m for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f)-1)%2m); second expression, or that is, by using a parity check polynomial satisfying zero provided by expression (198-2-1) or expression (198-2-2).

[3129] Accordingly, (1) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (197-1-1), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (197-1-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[3130] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f-1)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f-1)-1][v], Hx,3,comp[2×g-1][v]=Hx,3,comp[2×(2×f-1)-1][v], Hx,4,comp[2×g-1][v]=Hx,4,comp[2×(2×f-1)-1][v], Hx,5,comp[2×g-1][v]=Hx,5,comp[2×(2×f-1)-1][v], Hx,6,comp[2×g-1][v]=Hx,6,comp[2×(2×f-1)-1][v], Hx,7,comp[2×g-1][v]=Hx,7,comp[2×(2×f-1)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f-1)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[3131] First, the following holds true for Hx,1,comp[2×(2×f-1)-1][v].
[Math. 663]



[3132] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f-1)-1][v]. In the following, w is an integer no smaller than one and no greater than three.
[Math. 664]



[3133] Further, the following holds true for Hx,4,comp[2×(2×f-1)-1][v]. In the following, y is an integer no smaller than R#(2c),4+1 and no greater than r#(2c),4.
[Math. 665]



[3134] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f-1)-1][v]. In the following, Ω is an integer no smaller than four and no greater than seven, and y is an integer no smaller than R#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 666]





[3135] Further, the following holds true for Hp1,comp[2×(2×f-1)-1][v].
[Math. 667]



[3136] Further, the following holds true for Hp2,comp[2×(2×f-1)-1][v].
[Math. 668]



[3137] Further, (2) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (197-1-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (197-1-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[3138] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f-1)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f-1)-1][v], Hx,3,comp[2×g-1][v]=Hx,3,comp[2×(2×f-1)-1][v], Hx,4,comp[2×g-1][v]=Hx,4,comp[2×(2×f-1)-1][v], Hx,5,comp[2×g-1][v]=Hx,5,comp[2×(2×f-1)-1][v], Hx,6,comp[2×g-1][v]=Hx,6,comp[2×(2×f-1)-1][v], Hx,7,comp[2×g-1][v]=Hx,7,comp[2×(2×f-1)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f-1)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[3139] First, the following holds true for Hx,1,comp[2×(2×f-1)-1][v]
[Math. 669]



[3140] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f-1)-1][v]. In the following, w is an integer no smaller than one and no greater than three.
[Math. 670]





[3141] Further, the following holds true for Hx,4,comp[2×(2×f-1)-1][v]. In the following, y is an integer no smaller than R#(2c),4+1 and no greater than r#(2c),4.
[Math. 671]



[3142] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f-1)-1][v]. In the following, Ω is an integer no smaller than four and no greater than seven, and y is an integer no smaller than R#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 672]



[3143] Further, the following holds true for Hp1,comp[2×(2×f-1)-1][v].
[Math. 673]





[3144] Further, the following holds true for Hp2,comp[2×(2×f-1)-1][v].
[Math. 674]



[3145] Further, (3) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (197-2-1), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (197-2-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[3146] Accordingly, components Hx,1,comp[2×g][v]=Hx,1,comp[2×(2×f-1)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2×f-1)][v], Hx,3,comp[2×g][v]=Hx,3,comp[2×(2×f-1[v], Hx,4,comp[2×g][v]=Hx,4,comp[2×(2×f-1)][v], Hx,5,comp[2×g][v]=Hx,5,comp[2×(2×f-1)][v], Hx,6,comp[2×g][v]=Hx,6,comp[2×(2×f-1)][v], Hx,7,comp[2×g][v]=Hx,7,comp[2×(2×f-1)][v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f-1)][v], and Hp2,comp[2×g][v]=Hp2,comp[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[3147] First, the following holds true for Hx,1,comp[2×(2×f-1)][v]. In the following, y is an integer no smaller than R#(2c),1+1 and no greater than r#(2c),1.
[Math. 675]





[3148] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f-1)][v]. In the following, Ω is an integer no smaller than one and no greater than three, and y is an integer no smaller than K#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 676]



[3149] Further, the following holds true for Hx,4,comp[2×(2×f-1)][v].
[Math. 677]





[3150] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f-1)][v]. In the following, w is an integer no smaller than four and no greater than seven.
[Math. 678]



[3151] Further, the following holds true for Hp1,comp[2×(2×f-1)][v].
[Math.679]



[3152] Further, the following holds true for Hp2,comp[2×(2×f-1)][v].
[Math. 680]





[3153] Further, (4) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (197-2-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (197-2-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[3154] Accordingly, components Hx,1,comp[2×g][v]=Hx,1,comp[2×(2×f-1)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2×f-1)][v], Hx,3,comp[2×g][v]=Hx,3,comp[2×(2×f-1[v], Hx,4,comp[2×g][v]=Hx,4,comp[2×(2×f-1)][v], Hx,5,comp[2×g][v]=Hx,5,comp[2×(2×f-1)][v], Hx,6,comp[2×g][v]=Hx,6,comp[2×(2×f-1)][v], Hx,7,comp[2×g][v]=Hx,7,comp[2×(2×f-1)][v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f-1)][v], and Hp2,comp[2×g][v]=Hp2,comp[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[3155] First, the following holds true for Hx,1,comp[2×(2×f-1)][v]. In the following, y is an integer no smaller than R#(2c),1+1 and no greater than r#(2c),1.
[Math. 681]



[3156] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f-1)][v]. In the following, Ω is an integer no smaller than one and no greater than three, and y is an integer no smaller than K#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 682]



[3157] Further, the following holds true for Hx,4,comp[2×(2×f-1)][v].
[Math. 683]



[3158] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f-1)][v]. In the following, w is an integer no smaller than four and no greater than seven.
[Math. 684]





[3159] Further, the following holds true for Hp1,comp[2×(2×f-1)][v].
[Math.685]



[3160] Further, the following holds true for Hp2,comp[2×(2×f-1)][v].
[Math. 686]



[3161] Further, (5) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (198-1-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (198-1-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[3162] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f)-1][v], Hx,3,comp[2×g-1][v]=Hx,3,comp[2×(2×f)-1][v], Hx,4,comp[2×g-1][v]=Hx,4,comp[2×(2×f)-1][v], Hx,5,comp[2×g-1][v]=Hx,5,comp[2×(2×f)-1][v], Hx,6,comp[2×g-1][v]=Hx,6,comp[2×(2×f)-1][v], Hx,7,comp[2×g-1][v]=Hx,7,comp[2×(2 ×f)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[3163] First, the following holds true for Hx,1,comp[2×(2×f)-1][v]. In the following, y is an integer no smaller than R#(2d+1),1+1 and no greater than r#(2d+1),1.
[Math. 687]



[3164] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f)-1)][v]. In the following, Ω is an integer no smaller than one and no greater than three, and y is an integer no smaller than R#(2d+1),Ω+1 and no greater than r#(2d+1),Ω.
[Math. 688]



[3165] Further, the following holds true for Hx,4,comp[2×(2×f)-1][v].
[Math. 689]



[3166] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f)-1][v]. In the following, w is an integer no smaller than four and no greater than seven.
[Math. 690]



[3167] Further, the following holds true for Hp1,comp[2×(2×f)-1][v].
[Math. 691]





[3168] Further, the following holds true for Hp2,comp[2×(2×f)-1][v].
[Math. 692]



[3169] Further, (6) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (198-1-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (198-1-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[3170] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f)-1][v], Hx,3,comp[2×g-1][v]=Hx,3,comp[2×(2×f)-1][v], Hx,4,comp[2×g-1][v]=Hx,4,comp[2×(2×f)-1][v], Hx,5,comp[2×g-1][v]=Hx,5,comp[2×(2×f)-1][v], Hx,6,comp[2×g-1][v]=Hx,6,comp[2×(2×f)-1][v], Hx,7,comp[2×g-1][v]=Hx,7,comp[2×(2×f)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[3171] First, the following holds true for Hx,1,comp[2×(2×f)-1][v]. In the following, y is an integer no smaller than R#(2d+1),1+1 and no greater than r#(2d+1),1.
[Math. 693]





[3172] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f)-1)][v]. In the following, Ω is an integer no smaller than one and no greater than three, and y is an integer no smaller than R#(2d+1),Ω+1 and no greater than r#(2d+1),Ω.
[Math. 694]



[3173] Further, the following holds true for Hx,4,comp[2×(2×f)-1][v].
[Math. 695]





[3174] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f)-1][v]. In the following, w is an integer no smaller than four and no greater than seven.
[Math. 696]



[3175] Further, the following holds true for Hp1,comp[2×(2×f)-1][v].
[Math. 697]



[3176] Further, the following holds true for Hp2,comp[2×(2×f)-1][v].
[Math. 698]



[3177] Further, (7) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (198-2-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (198-2-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[3178] Accordingly, components Hx,1,comp[2×g][v]=Hx,1,comp[2×(2×f)][v], Hx,2,comp[2×g] [v]=Hx,2,comp[2×(2×f)][v], Hx,3,comp[2×g][v]=Hx,3,comp[2×(2×f)] [v], Hx,4,comp[2×g][v]=Hx,4,comp[2×(2×f)][v], Hx,5,comp[2×g][v]=Hx,5,comp[2×(2×f)][v], Hx,6,comp[2×g][v]=Hx,6,comp[2×(2×f)][v], Hx,7,comp[2×g][v]=Hx,2,comp[2×(2×f)] [v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f)][v], and Hp2,comp[2×g][v]=Hp2,comp[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[3179] The following holds true for Hx,1,comp[2×(2×f)][v].



[3180] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f)][v]. In the following, w is an integer no smaller than one and no greater than three.
[Math. 700]



[3181] Further, the following holds true for Hx,4,comp[2×(2×f)][v]. In the following, y is an integer no smaller than R#(2d+1),4+1 and no greater than r#(2d+1),4.
[Math. 701]



[3182] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f)][v]. In the following, Ω is an integer no smaller than four and no greater than seven, and y is an integer no smaller than R#(2d+1),Ω+1 and no greater than r#(2d+1),Ω.
[Math. 702]





[3183] Further, the following holds true for Hp1,comp[2×(2×f)][v].
[Math. 703]



[3184] Further, the following holds true for Hp2,comp[2×(2×f)][v].
[Math. 704]



[3185] Further, (8) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (198-2-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (198-2-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[3186] Accordingly, components Hx,1,comp[2×g][v]=Hx,1,comp[2×(2×f)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2 ×f)] [v], Hx,3,comp[2×g][v]=Hx,2,comp[2×(2 ×f)] [v], Hx,4,comp[2×g][v ]=Hx,4,comp[2×(2×f)][v], Hx,5,comp[2×g][v]=Hx,5,comp[2×(2×f)][v], Hx,6,comp[2×g][v]=Hx,6,comp[2×(2×f)][v], Hx,7,comp[2×g][v]=Hx,7,comp[2×(2×f)][v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f)][v], and Hp2,comp[2×g][v]=Hp2,comp[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[3187] The following holds true for Hx,1,comp[2×(2×f)][v].
[Math. 705]



[3188] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f)][v]. In the following, w is an integer no smaller than one and no greater than three.
[Math. 706]





[3189] Further, the following holds true for Hx,4,comp[2×(2×f)][v]. In the following, y is an integer no smaller than R#(2d+1),4+1 and no greater than r#(2d+1),4.
[Math. 707]



[3190] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f)][v]. In the following, Ω is an integer no smaller than four and no greater than seven, and y is an integer no smaller than R#(2d+1),Ω+1 and no greater than r#(2d+1),Ω.
[Math. 708]



[3191] Further, the following holds true for Hp1,comp[2×(2×f)][v].
[Math. 709]



[3192] Further, the following holds true for Hp2,comp[2×(2×f)][v].
[Math. 710]



[3193] An LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated as described above, and the code so generated achieves high error correction capability.

[3194] In the above, parity check polynomials satisfying zero for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) are set as follows:

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression; and

the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).



[3195] Based on this, the following method is conceivable as a configuration where usage of parity check polynomials satisfying zero is limited.

[3196] In this configuration, parity check polynomials satisfying zero for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) are set as follows:

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression provided by expression (197-2-1);

the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression provided by expression (197-1-1) or expression (198-1-1); and

the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression provided by expression (197-2-1) or expression (198-2-1) (where i is an integer no smaller than two and no greater than 2×m×z).



[3197] Accordingly, in the parity check matrix Hpro_m for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the vector composed of row one of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the vector composed of row two of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0; second expression provided by expression (197-2-1);

the vector composed of row 2×g-1 of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); first expression provided by expression (197-1-1) or expression (198-1-1); and

the vector composed of row 2×g of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); second expression provided by expression (197-2-1) or expression (198-2-1) (where g is an integer no smaller than two and no greater than 2×m×z).

Note that when making such a configuration, the above-described method of configuring the parity check matrix Hpro for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is applicable.



[3198] Such a method also enables generating a code with high error correction capability.

(Embodiment F5)



[3199] In embodiment F4, description is provided of an LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and a method of configuring a parity check matrix for the code.

[3200] With regards to parity check matrices for low density parity check (block) codes, one example of which is the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), a parity check matrix equivalent to a parity check matrix defined for a given LDPC code can be generated by using the parity check matrix defined for the given LDPC code.

[3201]  For example, a parity check matrix equivalent to the parity check matrix Hpro_m described in embodiment F4, which is for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using the parity check matrix Hpro_m.

[3202] The following describes a method of generating a parity check matrix equivalent to a parity check matrix defined for a given LDPC by using the parity check matrix defined for the given LDPC code.

[3203] Note that the method of generating an equivalent parity check matrix described in the present embodiment is not only applicable to the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) described in embodiment F4, but also is widely applicable to LDPC codes in general.

[3204] FIG. 31 illustrates the configuration of a parity check matrix H for an LDPC (block) code of coding rate (N-M)/N (N>M>0). For example, the parity check matrix of FIG. 31 has M rows and N columns. Here, to provide a general description, the parity check matrix H in FIG. 31 is considered to be a parity check matrix for defining an LDPC (block) code #A of coding rate (N-M)/N (N>M>0).

[3205] In FIG. 31, a transmission sequence (codeword) for block j is vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) (for systematic codes, Yj,k (where k is an integer no smaller than one and no greater than N) is information X or parity P (parity Ppro)).

[3206] Here, Hvj=0 holds true (where the zero in Hvj=0 indicates that all elements of the vector Hvj are zeroes. That is, row k of the vector Hvj has a value of zero for all k (where k is an integer no smaller than one and no greater than M)).

[3207] Then, an element of row k (where k is an integer no smaller than one and no greater than N) of the transmission sequence vj of block j (in FIG. 31, an element of column k in the transpose matrix vjT of the transmission sequence vj) is Yj,k, and a vector obtained by extracting column k of the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) can be expressed as ck, as illustrated in FIG. 31. Here, the parity check matrix H is expressed as follows.
[Math. 711]



[3208] FIG. 32 illustrates a configuration when interleaving is applied to the transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j. In FIG. 32, an encoding section 3202 receives information 3201 as input, performs encoding thereon, and outputs encoded data 3203. For example, when encoding the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), the encoder 3202 receives information in block j as input, performs encoding thereon based on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), and outputs the transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j.

[3209] Then, an accumulation and reordering section (interleaving section) 3204 receives the encoded data 3203 as input, accumulates the encoded data 3203, performs reordering thereon, and outputs interleaved data 3205. Accordingly, the accumulation and reordering section (interleaving section) 3204 receives the transmission sequence vj=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N)T of block j as input, and outputs a transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T, which is illustrated in FIG. 32, as a result of reordering being performed on the elements of the transmission sequence vj (v'j being an example). Here, as discussed above, the transmission sequence v'j is obtained by reordering the elements of the transmission sequence vj of block j. Accordingly, v'j is a vector having one row and n columns, and the N elements of v'j are such that one each of the terms Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N is present.

[3210] Here, an encoding section 3207 as shown in FIG. 32 having the functions of the encoding section 3202 and the accumulation and reordering section (interleaving section) 3204 is considered. Accordingly, the encoding section 3207 receives the information 3201 as input, performs encoding thereon, and outputs the encoded data 3203. For example, the encoding section 3207 receives information in block j as input, and as shown in FIG. 32, outputs the transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T. In the following, explanation is provided of a parity check matrix H' for the LDPC (block) code of coding rate (N-M)/N (N>M>0) corresponding to the encoding section 3207 (i.e., a parity check matrix H' that is equivalent to the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0)), while referring to Fig. 33. (Needless to say, the parity check matrix H' is a parity check matrix for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0).)

[3211] FIG. 33 shows a configuration of the parity check matrix H', which is a parity check matrix equivalent to the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), when the transmission sequence (codeword) is v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T. Here, an element of row one of the transmission sequence v'j of block j (an element of column one in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) is Yj,32. Accordingly, a vector obtained by extracting column one of the parity check matrix H', when using the above-described vector ck (k=1, 2, 3, ..., N-2, N-1, N), is c32. Similarly, an element of row two of the transmission sequence v'j of block j (an element of column two in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) is Yj,99. Accordingly, a vector obtained by extracting column two of the parity check matrix H' is c99. Further, as shown in FIG. 33, a vector obtained by extracting column three of the parity check matrix H' is c23, a vector obtained by extracting column N-2 of the parity check matrix H' is c234, a vector obtained by extracting column N-1 of the parity check matrix H' is c3, and a vector obtained by extracting column N of the parity check matrix H' is c43.

[3212] That is, when denoting an element of row i of the transmission sequence v'j of block j (an element of column i in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) as Yj,g (where g=1, 2, 3, ..., N-1, N-1, N), then a vector obtained by extracting column i of the parity check matrix H' is cg, when using the vector ck described above.

[3213] Accordingly, the parity check matrix H' for transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T is expressed as follows.
[Math. 712]



[3214] When denoting an element of row i of the transmission sequence v'j of block j (an element of column i in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) as Yj,g (where g=1, 2, 3, ..., N-1, N-1, N), a vector obtained by extracting column i of the parity check matrix H' is cg, when using the vector ck described above. When the above is followed to create a parity check matrix, then a parity check matrix for the transmission sequence v'j of block j can be obtained with no limitation to the above-given example.

[3215] Accordingly, when interleaving is applied to the transmission sequence (codeword) of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), a matrix for the interleaved transmission sequence is obtained by performing reordering of columns (column permutation) as described above on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0).

[3216] As such, it naturally follows that the transmission sequence (codeword) (vj) obtained by reverting the interleaved transmission sequence (codeword) (v'j) to its original order is the transmission sequence (codeword) of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Accordingly, by reverting the interleaved transmission sequence (codeword) (v'j) and a parity check matrix H' corresponding to the interleaved transmission sequence (codeword) (v'j) to their respective orders, the transmission sequence vj and a parity check matrix corresponding to the transmission sequence vj can be obtained, respectively. Further, the parity check matrix obtained by performing the reordering as described above is the parity check matrix H in FIG. 31, description of which has been provided above.

[3217] FIG. 34 illustrates an example of a decoding-related configuration of a receiving device, when encoding of FIG. 32 has been performed. The transmission sequence obtained when the encoding of FIG. 32 is performed undergoes processing such as mapping in accordance with a modulation scheme, frequency conversion, and modulated signal amplification, whereby a modulated signal is obtained. A transmitting device transmits the modulated signal. The receiving device then receives the modulated signal transmitted by the transmitting device to obtain a received signal. A log-likelihood ratio calculation section 3400 illustrated in FIG. 34 takes the received signal as input, calculates a log-likelihood ratio for each bit of the codeword, and outputs a log-likelihood ratio signal 3401.

[3218] For example, assume that the transmitting device transmits a transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T of block j. Then, the log-likelihood ratio calculation section 3400 calculates, from the received signal, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, and outputs the log-likelihood ratios.

[3219] An accumulation and reordering section (deinterleaving section) 3402 receives the log-likelihood ratio signal 3401 as input, performs accumulation and reordering thereon, and outputs a deinterleaved log-likelihood ratio signal 3403.

[3220] For example, the accumulation and reordering section (deinterleaving section) 3402 receives, as input, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, performs reordering, and outputs the log-likelihood ratios in the order of: the log-likelihood ratio for Yj,1, the log-likelihood ratio for Yj,2, the log-likelihood ratio for Yj,3, ..., the log-likelihood ratio for Yj,N-2, the log-likelihood ratio for Yj,N-1, and the log-likelihood ratio for Yj,N in the stated order.

[3221] A decoder 3404 receives the deinterleaved log-likelihood ratio signal 3403 as input, performs belief propagation (BP) decoding as disclosed in Non-Patent Literature 6 to 8, such as sum-product decoding, min-sum decoding, offset BP decoding, normalized BP decoding, shuffled BP decoding, and layered BP decoding in which scheduling is performed, based on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 31, and thereby obtains an estimation sequence 3405 (note that decoding schemes other than belief propagation decoding may be used).

[3222] For example, the decoder 3404 receives, as input, the log-likelihood ratio for Yj,1, the log-likelihood ratio for Yj,2, the log-likelihood ratio for Yj,3, ..., the log-likelihood ratio for Yj,N-2, the log-likelihood ratio for Yj,N-1, and the log-likelihood ratio for Yj,N in the stated order, performs belief propagation decoding based on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 31, and obtains the estimation sequence (note that decoding schemes other than belief propagation decoding may be used).

[3223] The following describes a decoding-related configuration that differs from that described above. The decoding-related configuration described in the following differs from the decoding-related configuration described above in that the accumulation and reordering section (deinterleaving section) 3402 is not included. The operations of the log-likelihood ratio calculation section 3400 are similar to those described above, and thus, explanation thereof is omitted in the following.

[3224] For example, assume that the transmitting device transmits a transmission sequence (codeword) v'j =(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T of block j. Then, the log-likelihood ratio calculation section 3400 calculates, from the received signal, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, and outputs the log-likelihood ratios (corresponding to 3406 in FIG. 34).

[3225] A decoder 3407 receives the log-likelihood ratio signal 3406 for each bit as input, performs belief propagation (BP) decoding as disclosed in Non-Patent Literature 6 to 8, such as sum-product decoding, min-sum decoding, offset BP decoding, normalized BP decoding, shuffled BP decoding, and layered BP decoding in which scheduling is performed, based on the parity check matrix H' for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 33, and thereby obtains an estimation sequence 3409 (note that decoding schemes other than belief propagation decoding may be used).

[3226] For example, the decoder 3407 receives, as input, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43 in the stated order, performs belief propagation decoding based on the parity check matrix H' for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 33, and obtains the estimation sequence (note that decoding schemes other than belief propagation decoding may be used).

[3227] As explained above, even when the transmitted data is reordered due to the transmitting device interleaving the transmission sequence vj=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N)T of block j, the receiving device is able to obtain the estimation sequence by using a parity check matrix corresponding to the reordered transmitted data.

[3228] Accordingly, when interleaving is applied to the transmission sequence (codeword) of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), a parity check matrix for the interleaved transmission sequence (codeword) is obtained by performing reordering of columns (i.e., column permutation) as described above on the parity check matrix for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). As such, the receiving device is able to perform belief propagation decoding and thereby obtain an estimation sequence without performing interleaving on the log-likelihood ratio for each acquired bit.

[3229] Note that in the above, explanation is provided of the relation between interleaving applied to a transmission sequence and a parity check matrix. In the following, explanation is provided of reordering of rows (row permutation) performed on a parity check matrix.

[3230] FIG. 35 illustrates a configuration of a parity check matrix H corresponding to a transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). For example, the parity check matrix H of FIG. 35 is a matrix having M rows and N columns. (for systematic codes, Yj,k (where k is an integer no smaller than one and no greater than N) is information X or parity P (parity Ppro), and is composed of (N-M) information bits and M parity bits). Here, Hvj = 0 holds true. (Here, the zero in Hvj = 0 indicates that all elements of the vector Hvj are zeroes. That is, row k of the vector Hvj has a value of zero for all k (where k is an integer no smaller than one and no greater than M.)

[3231] Further, a vector obtained by extracting column k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 35 is denoted as zk. Then, the parity check matrix H for the LDPC (block) code is expressed as follows.
[Math. 713]



[3232] Next, a parity check matrix obtained by performing reordering of rows (row permutation) on the parity check matrix H of FIG. 35 is considered.

[3233] FIG. 36 shows an example of a parity check matrix H' obtained by performing reordering of rows (row permutation) on the parity check matrix H of FIG. 35. The parity check matrix H', similar to the parity check matrix shown in FIG. 35, is a parity check matrix corresponding to the transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0).

[3234] The parity check matrix H' of FIG. 36 is composed of vectors zk obtained by extracting row k (where k is an integer no smaller one and no greater than M) of the parity check matrix H of FIG. 35. For example, in the parity check matrix H', the first row is composed of vector z130, the second row is composed of vector z24, the third row is composed of vector z45, ..., the (M-2)th row is composed of vector z33, the (M-1)th row is composed of vector z9, and the Mth row is composed of vector z3. Note that each of the M row-vectors obtained by extracting row k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H' is such that one each of z1, z2, z3, ... zM-2, zM-1, and zM is present.

[3235] Here, the parity check matrix H' for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) is expressed as follows.
[Math. 714]



[3236] Further, H'vj = 0 holds true. (Here, the zero in H'vj = 0 indicates that all elements of the vector H'vj are zeroes. That is, row k of the vector H'vj has a value of zero for all k (where k is an integer no smaller than one and no greater than M.)

[3237] That is, for the transmission sequence vjT of block j, a vector obtained by extracting row i of the parity check matrix H' in FIG. 36 is expressed as ck (where k is an integer no smaller than one and no greater than M), and each of the M row vectors obtained by extracting row k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H' in FIG. 36 is such that one each of z1, z2, z3, ... zM-2, zM-1, and zM is present.

[3238] As described above, for the transmission sequence vjT of block j, a vector obtained by extracting row i of the parity check matrix H' in FIG. 36 is expressed as ck (where k is an integer no smaller than one and no greater than M), and each of the M row vectors obtained by extracting row k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H' in FIG. 36 is such that one each of z1, z2, z3, ... zM-2, zM-1, and zM is present. Note that, when the above is followed to create a parity check matrix, then a parity check matrix for the transmission sequence parity vj of block j can be obtained with no limitation to the above-given example.

[3239] Accordingly, even when the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) is being used, it does not necessarily follow that a transmitting device and a receiving device are using the parity check matrix H. As such, a transmitting device and a receiving device may use as a parity check matrix, for example, a matrix obtained by performing reordering of columns (column permutation) as described above on the parity check matrix H or a matrix obtained by performing reordering of rows (row permutation) on the parity check matrix H.

[3240] In addition, a matrix obtained by performing both reordering of columns (column permutation) and reordering of rows (row permutation) as described above on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) may be used as a parity check matrix.

[3241] In such a case, a parity check matrix H1 is obtained by performing reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H2 is obtained by performing reordering of rows (row permutation) on the parity check matrix H1 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). A transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H2 so obtained.

[3242] Also, a parity check matrix H1,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H2,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix H1,1 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36).

[3243] Further, a parity check matrix H1,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H2,1. Finally, a parity check matrix H2,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H1,2.

[3244] As described above, a parity check matrix H2,s may be obtained by repetitively performing reordering of columns (column permutation) and reordering of rows (row permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H1,k is obtained by performing a kth (where k is an integer no smaller than two and no greater than s) reordering of columns (column permutation) on a parity check matrix H2,k-1. Then, a parity check matrix H2,k is obtained by performing a kth reordering of rows (row permutation) on the parity check matrix H1,k. Note that in the first instance, a parity check matrix H1,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H2,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H1,1.

[3245] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H2,s.

[3246]  In an alternative method, a parity check matrix H3 is obtained by performing reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H4 is obtained by performing reordering of columns (column permutation) on the parity check matrix H3 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H4 so obtained.

[3247] Also, a parity check matrix H3,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H4,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix H3,1 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33).

[3248] Then, a parity check matrix H3,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H4,1. Finally, a parity check matrix H4,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H3,2.

[3249] As described above, a parity check matrix H4,s may be obtained by repetitively performing reordering of rows (row permutation) and reordering of columns (column permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H3,k is obtained by performing a kth (where k is an integer no smaller two and no greater than s) reordering of rows (row permutation) on a parity check matrix H4,k-1. Then, a parity check matrix H4,k is obtained by performing a kth reordering of columns (column permutation) on the parity check matrix H3,k. Note that in the first instance, a parity check matrix H3,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H4,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H3,1.

[3250] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H4,s.

[3251] Here, note that by performing reordering of rows (row permutation) and reordering of columns (column permutation), the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) can be obtained from each of the parity check matrix H2, the parity check matrix H2,s, the parity check matrix H4, and the parity check matrix H4,s,.

[3252]  Similarly, a matrix obtained by performing both reordering of columns (column permutation) as described above and reordering of rows (row permutation) as described above on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) may be used as a parity check matrix.

[3253] In such a case, a parity check matrix H5 is obtained by performing reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H6 is obtained by performing reordering of rows (row permutation) on the parity check matrix H5 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). A transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H6 so obtained.

[3254] Also, a parity check matrix H5,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H6,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix H5,1 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36).

[3255] Further, a parity check matrix H5,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H6,1. Finally, a parity check matrix H6,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H5,2.

[3256] As described above, a parity check matrix H6,s may be obtained by repetitively performing reordering of columns (column permutation) and reordering of rows (row permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H5,k is obtained by performing a kth (where k is an integer no smaller than two and no greater than s) reordering of columns (column permutation) on a parity check matrix H6,k-1. Then, a parity check matrix H6,k is obtained by performing a kth reordering of rows (row permutation) on the parity check matrix H5,k. Note that in the first instance, a parity check matrix H5,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H6,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H5,1

[3257] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H6,s.

[3258] In an alternative method, a parity check matrix H7 is obtained by performing reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H8 is obtained by performing reordering of columns (column permutation) on the parity check matrix H7 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H8 so obtained.

[3259] Also, a parity check matrix H7,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H8,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix H7,1 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33).

[3260] Then, a parity check matrix H7,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H8,1. Finally, a parity check matrix H8,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H7,2.

[3261] As described above, a parity check matrix H8,s may be obtained by repetitively performing reordering of rows (row permutation) and reordering of columns (column permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H7,k is obtained by performing a kth (where k is an integer no smaller two and no greater than s) reordering of rows (row permutation) on a parity check matrix H8,k-1. Then, a parity check matrix H8,k is obtained by performing a kth reordering of columns (column permutation) on the parity check matrix H7,k. Note that in the first instance, a parity check matrix H7,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H8,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H7,1.

[3262] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H8,s.

[3263] Here, note that by performing reordering of rows (row permutation) and reordering of columns (column permutation), the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) can be obtained from each of the parity check matrix H6, the parity check matrix H6,s, the parity check matrix H8, and the parity check matrix H8,s,.

[3264] In the present embodiment, description is provided of a method of generating a parity check matrix equivalent to a parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) by performing reordering of rows (row permutation) and/or reordering of columns (column permutation) with respect to the parity check matrix H. Further, description is provided of a method of applying the equivalent parity check matrix in, for example, a communication/broadcast system using an encoder and a decoder using the equivalent parity check matrix. Note that the error correction code described herein may be applied to various fields, including but not limited to communication/broadcast systems.

(Embodiment F6)



[3265] In the present embodiment, description is provided of a device that uses the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), description of which is provided in embodiment F4.

[3266] As one example, description is provided of a case where the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is applied to a communication device.

[3267] Fig. 22 illustrates the structures of a transmitting device 2200 and a receiving device 2210 in the communication device pertaining to the present embodiment.

[3268] An encoder 2201 receives information to be transmitted as input, and is capable of performing various types of encoding (e.g., various coding rates and various block lengths of block codes (for example, in systematic codes, the sum of the number of information bits and the number of parity bits)). In particular, when receiving a specification to perform encoding by using the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), the encoder 2201 performs encoding by using the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) to calculate parities P1 and P2. Further, the encoder 2201 outputs the information to be transmitted and the parities P1 and P2 as a transmission sequence.

[3269] A modulator 2202 receives the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, performs mapping based on a predetermined modulation scheme (for example, BPSK, QPSK, 16QAM, or 64QAM), and outputs a baseband signal. Further, the modulator 2202 may also receive information other than the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, as input, perform mapping, and output a baseband signal. For example, the modulator 2202 may receive control information as input.

[3270] The transmitting device outputs a transmission signal after performing predetermined signal processing (e.g., signal processing for generation of an OFDM signal, frequency conversion, amplification) with respect to such signals (e.g., baseband signals, pilot signals). The transmitting device may transmit the transmission signal over a wireless transmission path utilizing electromagnetic waves, or over a wired transmission path utilizing a coaxial cable, a power line, an optical cable, or the like.

[3271] The transmission signal is received by the receiving device 2210 after travelling over the transmission path. A receiver 2211 receives a reception signal as input, performs predetermined signal processing (e.g., bandwidth limitation, frequency conversion, signal processing for OFDM, frequency offset estimation, signal detection, channel estimation), and outputs a baseband signal and a channel estimation signal.

[3272] A log-likelihood ratio generation section 2212 receives the baseband signal and the channel estimation signal as input (may receive other signals as input), and for example, calculates and outputs a log-likelihood ratio for each bit (may calculate and output a hard value (hard decision value)).

[3273] A decoder 2213 receives the log-likelihood ratio for each bit as input, performs belief propagation decoding (e.g., sum-product decoding, scheduled sum-product decoding (Layered BP (belief propagation) decoding), min-sum decoding, Normalized BP decoding, offset BP decoding), and outputs an estimation sequence. The decoder 2213 performs the belief propagation decoding based on the parity check matrix for the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[3274] Although description is provided above taking an example where error correction coding is introduced to a communication device, the error correction coding described above is not limited to being introduced to a communication device, and for example, may be introduced to a storage medium (storage). When making such a modification, information that is to be stored to a storage medium (storage) is encoded by using the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and resultant information and parities are stored to the storage medium (storage).

[3275] Further, the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is applicable to any device that requires error correction coding (e.g., a memory, a hard disk).

[3276] Note that when using a block code such as the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) in a device, there as cases where special processing needs to be executed.

[3277] Assume that a block length of the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) used in a device is 18000 bits (14000 information bits, and 4000 parity bits).

[3278] In such a case, the number of information bits necessary for encoding one block is 14000. Meanwhile, there are cases where the number of bits of information input to an encoding section of the device does not reach 14000. For example, assume a case where only 12000 information bits are input to the encoding section.

[3279] Here, it is assumed that the encoding section, in the above-described case, adds 2000 padding bits of information to the 12000 information bits having been input, and performs encoding by using a total of 14000 bits, composed of the 12000 information bits having been input and the 2000 padding bits, to generate 4000 parity bits. Here, assume that all of the 2000 padding bits are known bits. For example, assume that each of the 2000 padding bits is "0".

[3280] A transmitting device may output the 12000 information bits having been input, the 2000 padding bits, and the 4000 parity bits. Alternatively, a transmitting device may output the 12000 information bits having been input and the 4000 parity bits.

[3281] In addition, a transmitting device may perform puncturing with respect to the 5000 information bits having been input and the 4000 parity bits, and thereby output a number of bits smaller than 10000 in total.

[3282] Note that when performing transmission in such a manner, the transmitting device is required to transmit, to a receiving device, information notifying the receiving device that transmission has been performed in such a manner.

[3283] As described above, the LDPC-CC of coding rate 7/9 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), description of which is provided in embodiment F4, is applicable to various devices.

(Embodiment G1)



[3284] The present embodiment describes a method of configuring an LDPC-CC of coding rate 13/15 that is based on a parity check polynomial, as one example of an LDPC-CC not satisfying coding rate (n-1)/n.

[3285]  Bits of information bits X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13 and parity bits P1, P2, at time point j, are expressed X1,j, X2,j, X3,j, X4,j, X5,j, X6,j, X7,j, X8,j, X9,j, X10,j, X11,j, X12,j, X13,j and P1,j, P2,j, respectively.

[3286] A vector uj, at time point j, is expressed uj = (X1,j, X2,j, X3,j, X4,j, X5,j, X6,j, X7,j, X8,j, X9,j, X10,j ,X11,j, X12,j, X13,j, P1,j, P2,j).

[3287] Given a delay operator D, polynomial expressions of the information bits X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13 are X1(D), X2(D), X3(D), X4(D), X5(D), X6(D), X7(D), X8(D), X9(D), X10(D), X11(D), X12(D), X13(D), and polynomial expressions of the parity bits P1, P2 are P1(D), P2(D).

[3288] Further, consideration is given to an LDPC-CC of coding rate 13/15 and time-varying period 2m that is based on a parity check polynomial.

[3289] The following mathematical expressions are provided as parity check polynomials satisfying zero for an LDPC-CC of coding rate 13/15 and time-varying period 2m that is based on a parity check polynomial.

[3290] First, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1×P2(D).
[Math. 715-1]



[Math. 715-2]

[Math. 715-3]



[Math. 715-4]





[3291] In expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[3292] In expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2), a#(2i),p,q (where p is an integer no smaller than one and no greater than thirteen, q is an integer no smaller than one and no greater than r#(2i),p (where r#(2i),p is a natural number)) and β#(2i),0 is a natural number, β#(2i),1 is a natural number, β#(2i),2 is an integer no smaller than zero, and β#(2i),3 is a natural number.

[3293] Further, y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for all y and all z satisfying y≠z.)

[3294] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (97-1-1) or expression (97-1-2) is referred to as "#(2i); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (97-2-1) or expression (97-2-2) is referred to as "#(2i); second expression" for realizing a time-varying period 2m.

[3295] Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (97-1-1) or expression (97-1-2) is prepared.

[3296] That is, for i=0, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=0 is prepared.

[3297] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=m-1 is prepared.



[3298] Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (97-2-1) or expression (97-2-2) is prepared.

[3299] That is, for i=0, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=0 is prepared.

[3300] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=m-1 is prepared.



[3301] Similarly, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1×P2(D).
[Math. 716-1]



[Math. 716-2]

[Math. 716-3]



[Math. 716-4]



[3302] In expressions (98-1-1), (98-1-2), (98-2-1), (98-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[3303] In expressions (98-1-1), (98-1-2), (98-2-1), (98-2-2), α#(2i+1),p,q (where p is an integer no smaller than one and no greater than thirteen, q is an integer no smaller than one and no greater than r#(2i+i),P (where r#(2i+1),p is a natural number)) and β#(2i+1),0 is a natural number, β#(2i+1),1 is a natural number, β#(2i+1),2 is an integer no smaller than zero, and β#(2i+1),3 is a natural number.

[3304] Further, y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier, (y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+i),p,y≠α#(2i+i),p,z holds true for all y and all z satisfying y≠z.)

[3305] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (98-1-1) or expression (98-1-2) is referred to as "#(2i+1); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (98-2-1) or expression (98-2-2) is referred to as "#(2i+1); second expression" for realizing a time-varying period 2m.

[3306] Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (98-1-1) or expression (98-1-2) is prepared.

[3307] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=0 is prepared.

[3308] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=m-1 is prepared.



[3309] Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (98-2-1) or expression (98-2-2) is prepared.

[3310] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=0 is prepared.

[3311] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=m-1 is prepared.



[3312] As such, an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3313] Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (97-1-1) or expression (97-1-2), parity check polynomials satisfying zero provided by expression (97-2-1) or expression (97-2-2), parity check polynomials satisfying zero provided by expression (98-1-1) or expression (98-1-2), and parity check polynomials satisfying zero provided by expression (98-2-1) or expression (98-2-2).

[3314] For example, the time varying period 2×m can be formed by preparing a 4×m number of different parity check polynomials satisfying zero.

[3315] Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

[3316] The following describes the relationship between time point j and expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2), (98-1-1), (98-1-2), (98-2-1), and (98-2-2) (where j is an integer no smaller than zero).

[3317] The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m-1).

[3318] Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i = k in #(2i); first expression and #(2i); second expression, hold true.

[3319] Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m-1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

[3320] The following describes a method of configuring a parity check matrix for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3321] As already described above, a vector uj at time point j is expressed as uj=(X1,j, X2,j, X3,j, X4,j, X5,j, X6,j, X7,j, X8,j, X9,j, X10,j, X11,j, X12,j, X13,j, P1,j, P2,j) (where j is an integer no smaller than zero). In the following, a case where u is a transmission vector is considered. Note that in the following, j is an integer no smaller than one, and thus j differs between the description having been provided above and the description provided in the following. (j is set as such to facilitate understanding of the correspondence between the column numbers and the row numbers of the parity check matrix.)

[3322] Accordingly, u=(u1, u2, u3, ..., uy-1, uy, uy+1, ...)T=(X1,1, X2,1, X3,1, X4,1, X5,1, X6,1, X7,1, X8,1, X9,1, X10,1 X11,1, X12,1, X13,1, P1,1, P2,1, X1,2, X2,2, X3,2, X4,2, X5,2, X6,2, X7,2, X8,2, X9,2, X10,2, X11,2, X12,2, X13,2, P1,2, P2,2, X1,3, X2,3, X3,3, X4,3, X5,3, X6,3, X7,3, X8,3, X9,3, X10,3, X11,3, X12,3, X13,3, P1,3, P2,3, .., X 1,y-1, X2,y-1, X3,y-1, X4,y-1, X5,y-1, X6,y-1, X7,y-1, X8,y-1, X9,y-1, X10,y-1, X11,y-1, X12,y-1, X13,y-1, P1,y-1, P2,y-1, X1,y, X2,y, X3,y, X4,y, X5,y, X6,y, X7,y, X8,y, X9,y, X10,y, X11,y, X12,y, X13,y, P1,y, P2,y, X1,y+1, X2,y+1, X3,y+1, X4,y+1, X5,y+1, X6,y+1, X7,y+1, X8,y+1, X9,y+1, X10,y+1, X11,y+1, X12,y+1, X13,y+1, P1,y+1, P2,y+1, ...)T. Further, when using H to denote a parity check matrix for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, Hu=0 holds true (here, Hu=0 indicates that all elements of the vector Hu are zeroes).

[3323] FIG. 93 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the topmost row of the parity check matrix is considered as the first row. Further, row number is incremented by one each time moving to a lower row. Accordingly, the topmost row is considered as the first row, the row immediately below the first row is considered as the second row, and the subsequent rows are considered as the third row, the fourth row, and so on.

[3324] As illustrated in FIG. 93:

"a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";
"a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×(2m-1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression";

"a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression";

"a vector for the 2×(2m+1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the 2×(2m+2)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×i-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); first expression"; and

"a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); second expression", and so on (where i is an integer no smaller than one).



[3325] FIG. 94 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the leftmost column of the parity check matrix is considered as the first column. Further, column number is incremented by one each time moving to a rightward column. Accordingly, the leftmost column is considered as the first column, the column immediately to the right of the first column is considered as the second column, and the subsequent columns are considered as the third column, the fourth column, and so on.

[3326] As illustrated in FIG. 94:

"a vector for the first column of the parity check matrix H is related to X1 at time point 1";

"a vector for the second column of the parity check matrix H is related to X2 at time point 1";

"a vector for the third column of the parity check matrix H is related to X3 at time point 1";

"a vector for the fourth column of the parity check matrix H is related to X4 at time point 1";

"a vector for the fifth column of the parity check matrix H is related to X5 at time point 1";

"a vector for the sixth column of the parity check matrix H is related to X6 at time point 1";

"a vector for the seventh column of the parity check matrix H is related to X7 at time point 1";

"a vector for the eighth column of the parity check matrix H is related to X8 at time point 1";

"a vector for the ninth column of the parity check matrix H is related to X9 at time point 1";

"a vector for the tenth column of the parity check matrix H is related to X10 at time point 1";

"a vector for the eleventh column of the parity check matrix H is related to X11 at time point 1";

"a vector for the twelfth column of the parity check matrix H is related to X12 at time point 1";

"a vector for the thirteenth column of the parity check matrix H is related to X13 at time point 1";

"a vector for the fourteenth column of the parity check matrix H is related to P1 at time point 1";

"a vector for the fifteenth column of the parity check matrix H is related to P2 at time point 1";

"a vector for the 15×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 15×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 15×(j-1)+3th column of the parity check matrix H is related to X3 at time point j";

"a vector for the 15×(j-1)+4th column of the parity check matrix H is related to X4 at time point j";

"a vector for the 15×(j-1)+5th column of the parity check matrix H is related to X5 at time point j";

"a vector for the 15×(j-1)+6th column of the parity check matrix H is related to X6 at time point j";

"a vector for the 15×(j-1)+7th column of the parity check matrix H is related to X7 at time point j";

"a vector for the 15×(j-1)+8th column of the parity check matrix H is related to X8 at time point j";

"a vector for the 15×(j-1)+9th column of the parity check matrix H is related to X9 at time point j";

"a vector for the 15×(j-1)+10th column of the parity check matrix H is related to X10 at time point j";

"a vector for the 15×(j-1)+11h column of the parity check matrix H is related to X11 at time point j";

"a vector for the 15×(j-1)+12th column of the parity check matrix H is related to X12 at time point j";

"a vector for the 15×(j-1)+13th column of the parity check matrix H is related to X13 at time point j";

"a vector for the 15×(j-1)+14th column of the parity check matrix H is related to P1 at time point j";

"a vector for the 15×(j-1)+15th column of the parity check matrix H is related to P2 at time point j"; and so on (where j is an integer no smaller than one).



[3327] FIG. 95 indicates a parity check matrix for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3328] The following focuses on 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D), 1×X8(D), 1×X9(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D), 1×P1(D), 1×P2(D) in the parity check matrix for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3329] The parity check polynomials at time point j=1 are parity check polynomials when i=0 in expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2).

[3330] A vector for the first row in FIG. 95 can be generated from a parity check polynomial when i=0 in expression (97-1-1) or expression (97-1-2) (refer to FIG. 93).

[3331] In expressions (97-1-1) and (97-1-2):
  • terms for 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D) exist;
  • terms for 1×X7(D), 1×X8(D), 1×X9(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D) do not exist; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[3332] Further, the relationship between column numbers and X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, P1, P2 is as indicated in FIG. 94. Based on the relationship indicated in FIG. 94 and the fact that terms for 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D) exist, columns related to X1, X2, X3, X4, X5, X6 in the vector for the first row in FIG. 95 are "1". Further, based on the relationship indicated in FIG. 94 and the fact that terms for 1×X7(D), 1×X8(D), 1×X9(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D) do not exist, columns related to X7, X8, X9, X10, X11, X12, X13 in the vector for the first row in FIG. 95 are "0". In addition, based on the relationship indicated in FIG. 94 and the fact that a term for 1×P1(D) exists but a term for 1×P2(D) does not exist, a column related to P1 in the vector for the first row in FIG. 95 is "1", and a column related to P2 in the vector for the first row in FIG. 95 is "0".

[3333] As such, the vector for the first row in FIG. 95 is "111111000000010", as indicated by 3900-1 in FIG. 95.

[3334] A vector for the second row in FIG. 95 can be generated from a parity check polynomial when i=0 in expression (97-2-1) or expression (97-2-2) (refer to FIG. 93).

[3335] In expressions (97-2-1) and (97-2-2):
  • terms for 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D) do not exist;
  • terms for 1×X7(D), 1×X8(D), 1×X9(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D) exist; and
  • a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists.


[3336] Further, the relationship between column numbers and X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, P1, P2 is as indicated in FIG. 94. Based on the relationship indicated in FIG. 94 and the fact that terms for 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D) do not exist, columns related to X1, X2, X3, X4, X5, X6 in the vector for the second row in FIG. 95 are "0". Further, based on the relationship indicated in FIG. 94 and the fact that terms for 1×X7(D), 1×X8(D), 1×X9(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D) exist, columns related to X7, X8, X9, X10, X11, X12, X13 in the vector for the second row in FIG. 95 are "1". In addition, based on the relationship indicated in FIG. 94 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the second row in FIG. 95 is "Y", and a column related to P2 in the vector for the second row in FIG. 95 is "1", where Y is either "0" or "1".

[3337] As such, the vector for the second row in FIG. 95 is "0000001111111Y1", as indicated by 3900-2 in FIG. 95.

[3338] The parity check polynomials at time point j=2 are parity check polynomials when i=0 in expressions (98-1-1), (98-1-2), (98-2-1), (98-2-2).

[3339] A vector for the third row in FIG. 95 can be generated from a parity check polynomial when i=0 in expression (98-1-1) or expression (98-1-2) (refer to FIG. 93).

[3340] In expressions (98-1-1) and (98-1-2):
  • terms for 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D) do not exist;
  • terms for 1×X7(D), 1×X8(D), 1×X9(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D) exist; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[3341] Further, the relationship between column numbers and X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, P1, P2 is as indicated in FIG. 94. Based on the relationship indicated in FIG. 94 and the fact that terms for 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D) do not exist, columns related to X1, X2, X3, X4, X5, X6 in the vector for the third row in FIG. 95 are "0". Further, based on the relationship indicated in FIG. 94 and the fact that terms for 1×X7(D), 1×X8(D), 1×X9(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D) exist, columns related to X7, X8, X9, X10, X11, X12, X13 in the vector for the third row in FIG. 95 are "1". In addition, based on the relationship indicated in FIG. 94 and the fact that a term for 1×P1(D) exists but a term for 1×P2(D) does not exist, a column related to P1 in the vector for the third row in FIG. 95 is "1", and a column related to P2 in the vector for the third row in FIG. 95 is "0".

[3342] As such, the vector for the third row in FIG. 95 is "000000111111110", as indicated by 3901-1 in FIG. 95.

[3343] A vector for the fourth row in FIG. 95 can be generated from a parity check polynomial when i=0 in expression (98-2-1) or expression (98-2-2) (refer to FIG. 93).

[3344] In expressions (98-2-1) and (98-2-2):
  • terms for 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D) exist;
  • terms for 1×X7(D), 1×X8(D), 1×X9(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D) do not exist; and
  • a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists.


[3345] Further, the relationship between column numbers and X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, P1, P2 is as indicated in FIG. 94. Based on the relationship indicated in FIG. 94 and the fact that terms for 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D) exist, columns related to X1, X2, X3, X4, X5, X6 in the vector for the fourth row in FIG. 95 are "1". Further, based on the relationship indicated in FIG. 94 and the fact that terms for 1×X7(D), 1×X8(D), 1×X9(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D) do not exist, columns related to X7, X8, X9, X10, X11, X12, X13 in the vector for the fourth row in FIG. 95 are "0". In addition, based on the relationship indicated in FIG. 94 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the fourth row in FIG. 95 is "Y", and a column related to P2 in the vector for the fourth row in FIG. 95 is "1".

[3346] As such, the vector for the fourth row in FIG. 95 is "1111110000000Y1", as indicated by 3901-2 in FIG. 95.

[3347] Because it can be considered that the above similarly applies to cases where time point j=3, 4, 5, the parity check matrix H has the configuration indicated in FIG. 95.

[3348] That is, due to the parity check polynomials of expressions (97-1-1), (97-1-2), (97-2-1), (97-2-2) being used at time point j=2k+1 (where k is an integer no smaller than zero), "111111000000010" exists in the 2×(2k+1)-1th row of the parity check matrix H, and "0000001111111Y1" exists in the 2×(2k+1)th row of the parity check matrix H, as illustrated in FIG. 95.

[3349] Further, due to the parity check polynomials of expressions (98-1-1), (98-1-2), (98-2-1), (98-2-2) being used at time point j=2k+2 (where k is an integer no smaller than zero), "000000111111110" exists in the 2×(2k+2)-1th row of the parity check matrix H, and "1111110000000Y1" exists in the 2×(2k+2)th row of the parity check matrix H, as illustrated in FIG. 95.

[3350] Accordingly, as illustrated in FIG. 95, when denoting a column number of a leftmost column corresponding to "1" in "111111000000010" in a row where "111111000000010" exists (e.g., 3900-1 in FIG. 95) as "a", "000000111111110" (e.g., 3901-1 in FIG. 95) exists in a row that is two rows below the row where "111111000000010" exists, starting from column "a+9".

[3351] Similarly, as illustrated in FIG. 95, when denoting a column number of a leftmost column corresponding to "1" in "0000001111111Y1" in a row where "0000001111111Y1" exists (e.g., 3900-2 in FIG. 95) as "b", "1111110000000Y1" (e.g., 3901-2 in FIG. 95) exists in a row that is two rows below the row where "0000001111111Y1" exists, starting from column "b+9".

[3352] Similarly, as illustrated in FIG. 95, when denoting a column number of a leftmost column corresponding to "1" in "000000111111110" in a row where "000000111111110" exists (e.g., 3901-1 in FIG. 95) as "c", "111111000000010" (e.g., 3902-1 in FIG. 95) exists in a row that is two rows below the row where "000000111111110" exists, starting from column "c+9".

[3353] Similarly, as illustrated in FIG. 95, when denoting a column number of a leftmost column corresponding to "1" in "1111110000000Y1" in a row where "1111110000000Y1" exists (e.g., 3901-2 in FIG. 95) as "d", "0000001111111Y1" (e.g., 3902-2 in FIG. 95) exists in a row that is two rows below the row where "1111110000000Y1" exists, starting from column "d+9".

[3354] The following describes a parity check matrix for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial when tail-biting is not performed, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3355] In the following, Hcom[u][v] (where u and v are integers no smaller than one) denotes an element at row "u" column "v" of a parity check matrix for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3356] Based on description above provided with reference to FIG. 93:

"a vector for the 2×g-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); first expression"; and

"a vector for the (2×g)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); second expression" (where g is an integer no smaller than one).



[3357] Based on description above provided with reference to FIG. 94:

"a vector for the 15×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 15×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 15×(j-1)+3th column of the parity check matrix H is related to X3 at time point j";

"a vector for the 15×(j-1)+4th column of the parity check matrix H is related to X4 at time point j";

"a vector for the 15×(j-1)+5th column of the parity check matrix H is related to X5 at time point j";

"a vector for the 15×(j-1)+6th column of the parity check matrix H is related to X6 at time point j";

"a vector for the 15×(j-1)+7th column of the parity check matrix H is related to X7 at time point j";

"a vector for the 15×(j-1)+8th column of the parity check matrix H is related to X8 at time point j";

"a vector for the 15×(j-1)+9th column of the parity check matrix H is related to X9 at time point j";

"a vector for the 15×(j-1)+10th column of the parity check matrix H is related to X10 at time point j";

"a vector for the 15×(j-1)+11h column of the parity check matrix H is related to X11 at time point j";

"a vector for the 15×(j-1)+12th column of the parity check matrix H is related to X12 at time point j";

"a vector for the 15×(j-1)+13th column of the parity check matrix H is related to X13 at time point j";

"a vector for the 15×(j-1)+14th column of the parity check matrix H is related to P1 at time point j"; and

"a vector for the 15×(j-1)+15th column of the parity check matrix H is related to P2 at time point j"; (where j is an integer no smaller than one).



[3358] Based on the above, the following describes component Hcom[2×g-1][v] in row 2×g-1 (where g is an integer no smaller than one) and component Hcom[2×g][v] in row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3359] As already described above, a parity check polynomial satisfying zero of #((g-1)%2m); first expression can be used to generate a vector for row 2×g-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3360] Further, a parity check polynomial satisfying zero of #((g-1)%2m); second expression can be used to generate a vector for row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3361] Accordingly, when g=2×f-1 (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (97-1-1) or expression (97-1-2), can be used to generate a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3362] Further, a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (97-2-1) or expression (97-2-2), can be used to generate a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3363] Further, when g=2×f (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (98-1-1) or expression (98-1-2), can be used to generate a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3364] Further, a parity check polynomial satisfying zero of #(((2×f)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (98-2-1) or expression (98-2-2), can be used to generate a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3365] Accordingly, (1) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-1-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-1-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[3366] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[3367] The following holds true for X1.
[Math. 717]



[3368] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than six.
[Math. 718]





[3369] Further, the following holds true for X7. In the following, y is an integer no smaller than three and no greater than r#(2c),7.
[Math. 719]



[3370] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than seven and no greater than thirteen, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 720]



[3371] The following holds true for P1.
[Math. 721]



[3372] The following holds true for P2.
[Math. 722]



[3373] Further, (2) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-1-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-1-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[3374] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[3375] The following holds true for X1.
[Math. 723]





[3376] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than six.
[Math. 724]



[3377] Further, the following holds true for X7. In the following, y is an integer no smaller than three and no greater than r#(2c),7.
[Math. 725]



[3378] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than seven and no greater than thirteen, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 726]



[3379] The following holds true for P1.
[Math. 727]



[3380] The following holds true for P2.
[Math. 728]



[3381] Further, (3) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-2-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-2-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[3382] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[3383] The following holds true for X1. In the following, and y is an integer no smaller than three and no greater than r#(2c),1.
[Math. 729]



[3384] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than six, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 730]



[3385] Further, the following holds true for X7.
[Math. 731]





[3386] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than seven and no greater than thirteen.
[Math. 732]



[3387] The following holds true for P1.
[Math. 733]



[3388] The following holds true for P2.
[Math. 734]





[3389] Further, (4) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-2-2), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-2-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[3390] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[3391] The following holds true for X1. In the following, y is an integer no smaller than three and no greater than r#(2c),1.
[Math. 735]



[3392] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than six, and y is an integer no smaller than three and no greater than r#(2c),z.
[Math. 736]





[3393] Further, the following holds true for X7.
[Math. 737]



[3394] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than seven and no greater than thirteen.
[Math. 738]



[3395] The following holds true for P1.
[Math. 739]



[3396] The following holds true for P2.
[Math. 740]



[3397] Further, (5) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-1-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-1-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[3398] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[3399] The following holds true for X1. In the following, y is an integer no smaller than three and no greater than r#(2d+i),1.
[Math. 741]



[3400] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than six, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 742]



[3401] Further, the following holds true for X7.
[Math. 743]



[3402] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than seven and no greater than thirteen.
[Math. 744]



[3403] The following holds true for P1.
[Math. 745]



[3404] The following holds true for P2.
[Math. 746]



[3405] Further, (6) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-1-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-1-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[3406] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[3407] The following holds true for X1. In the following, y is an integer no smaller than three and no greater than r#(2d+1),1.
[Math. 747]



[3408] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than six, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 748]



[3409] Further, the following holds true for X7.
[Math. 749]



[3410] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than seven and no greater than thirteen.
[Math. 750]



[3411] The following holds true for P1.
[Math. 751]





[3412] The following holds true for P2.
[Math. 752]



[3413] Further, (7) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-2-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-2-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[3414] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[3415] The following holds true for X1.
[Math. 753]





[3416] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than six.
[Math. 754]



[3417] Further, the following holds true for X7. In the following, y is an integer no smaller than three and no greater than r#(2d+1),7.
[Math. 755]



[3418] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than seven and no greater than thirteen, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 756]





[3419] The following holds true for P1.
[Math. 757]



[3420] The following holds true for P2.
[Math. 758]



[3421] Further, (8) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-2-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-2-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[3422] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[3423] The following holds true for X1.
[Math. 759]



[3424] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than six.
[Math. 760]



[3425] Further, the following holds true for X7. In the following, y is an integer no smaller than three and no greater than r#(2d+1),7.
[Math. 761]



[3426] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than seven and no greater than thirteen, and y is an integer no smaller than three and no greater than r#(2d+1),z.
[Math. 762]



[3427] The following holds true for P1.
[Math. 763]



[3428] The following holds true for P2.
[Math. 764]



[3429] As such, an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial can be generated by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, and the code so generated achieves high error correction capability.

(Embodiment G2)



[3430] In the present embodiment, description is provided of a method of code configuration that is a generalization of the method described in embodiment F1 of configuring an LDPC-CC of coding rate 13/15 that is based on a parity check polynomial.

[3431] Bits of information bits X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13 and parity bits P1, P2, at time point j, are expressed X1,j, X2,j, X3,j, X4,j, X5,j, X6,j, X7,j, X8,j, X9,j, X10,j, X11,j, X12,j, X13,j and P1,j, P2,j, respectively.

[3432] A vector uj, at time point j, is expressed uj = (X1,j, X2,j, X3,j, X4,j, X5,j, X6,j, X7,j, X8,j, X9,j, X10,j, X11,j, X12,j, X13,j, P1,j, P2,j).

[3433] Given a delay operator D, polynomial expressions of the information bits X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13 are X1(D), X2(D), X3(D), X4(D), X5(D), X6(D), X7(D), X8(D), X9(D), X10(D), X11(D), X12(D), X13(D), and polynomial expressions of the parity bits P1, P2 are P1(D), P2(D).

[3434] Further, consideration is given to an LDPC-CC of coding rate 13/15 and time-varying period 2m that is based on a parity check polynomial.

[3435] The following mathematical expressions are provided as parity check polynomials satisfying zero for an LDPC-CC of coding rate 13/15 and time-varying period 2m that is based on a parity check polynomial.

[3436] First, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1×P2(D).
[Math. 765-1]



[Math. 765-2]



[Math. 765-3]

[Math. 765-4]



[3437] In expressions (147-1-1), (147-1-2), (147-2-1), (147-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[3438] In expressions (147-1-1), (147-1-2), (147-2-1), (147-2-2), α#(2i),p,q (where p is an integer no smaller than one and no greater than thirteen, q is an integer no smaller than one and no greater than r#(2i),p (where r#(2i),p is a natural number)) and β#(2i),0 is a natural number, β#(2i),1 is a natural number, β#(2i),2 is an integer no smaller than zero, and β#(2i),3 is a natural number.

[3439] Further, R#(2i),p is a natural number satisfying 1≤R#(2i),p<r#(2i),p.

[3440] Further, y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for all y and all z satisfying y≠z.)

[3441] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (147-1-1) or expression (147-1-2) is referred to as "#(2i); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (147-2-1) or expression (147-2-2) is referred to as "#(2i); second expression" for realizing a time-varying period 2m.

[3442] Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (147-1-1) or expression (147-1-2) is prepared.

[3443] That is, for i=0, a parity check polynomial satisfying zero provided by expression (147-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (147-1-2) where i=0 is prepared.

[3444] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (147-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (147-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (147-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (147-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (147-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (147-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (147-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (147-1-2) where i=m-1 is prepared.



[3445] Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (147-2-1) or expression (147-2-2) is prepared.

[3446] That is, for i=0, a parity check polynomial satisfying zero provided by expression (147-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (147-2-2) where i=0 is prepared.

[3447] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (147-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (147-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (147-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (147-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (147-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (147-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (147-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (147-2-2) where i=m-1 is prepared.



[3448] Similarly, because two parities P1 and P2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P1(D) and two for 1×P2(D).
[Math. 766-1]



[Math. 766-2]

[Math. 766-3]



[Math. 766-4]



[3449] In expressions (148-1-1), (148-1-2), (148-2-1), (148-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[3450] In expressions (148-1-1), (148-1-2), (148-2-1), (148-2-2), α#(2i+1),p,q (where p is an integer no smaller than one and no greater than thirteen, q is an integer no smaller than one and no greater than r#(2i+1),p (where r#(2i+1),p is a natural number)) and β#(2i+1),0 is a natural number, β#(2i+1),1 is a natural number, β#(2i+1),2 is an integer no smaller than zero, and β#(2i+1),3 is a natural number.

[3451] Further, R#(2i),p is a natural number satisfying 1≤R#(2i+1),p<r#(2i+1),p.

[3452] Further, y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier, (y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for all y and all z satisfying y≠z.)

[3453] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (148-1-1) or expression (148-1-2) is referred to as "#(2i+1); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (148-2-1) or expression (148-2-2) is referred to as "#(2i+1); second expression" for realizing a time-varying period 2m.

[3454] Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (148-1-1) or expression (148-1-2) is prepared.

[3455] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (148-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (148-1-2) where i=0 is prepared.

[3456] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (148-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (148-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (148-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (148-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (148-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (148-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (148-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (148-1-2) where i=m-1 is prepared.



[3457] Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (148-2-1) or expression (148-2-2) is prepared.

[3458] That is,
for i=0, a parity check polynomial satisfying zero provided by expression (148-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (148-2-2) where i=0 is prepared.

[3459] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (148-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (148-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (148-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (148-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (148-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (148-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (148-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (148-2-2) where i=m-1 is prepared.



[3460] As such, an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3461] Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (147-1-1) or expression (147-1-2), parity check polynomials satisfying zero provided by expression (147-2-1) or expression (147-2-2), parity check polynomials satisfying zero provided by expression (148-1-1) or expression (148-1-2), and parity check polynomials satisfying zero provided by expression (148-2-1) or expression (148-2-2).

[3462]  For example, the time varying period 2×m can be formed by preparing a 4×m number of different parity check polynomials satisfying zero.

[3463] Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

[3464] The following describes the relationship between time point j and expressions (147-1-1), (147-1-2), (147-2-1), (147-2-2), (148-1-1), (148-1-2), (148-2-1), and (148-2-2) (where j is an integer no smaller than zero).

[3465] The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m-1).

[3466] Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i = k in #(2i); first expression and #(2i); second expression, hold true.

[3467] Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m-1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

[3468] The following describes a method of configuring a parity check matrix for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3469] As already described above, a vector uj at time point j is expressed as uj=(X1,j, X2,j, X3,j, X4,j, X5,j, X6,j, X7,j, X8,j, X9,j, X10,j ,X11,j, X12,j, X13,j, P1,j, P2,j) (where j is an integer no smaller than zero). In the following, a case where u is a transmission vector is considered. Note that in the following, j is an integer no smaller than one, and thus j differs between the description having been provided above and the description provided in the following. (j is set as such to facilitate understanding of the correspondence between the column numbers and the row numbers of the parity check matrix.)

[3470] Accordingly, u=(u1, u2, u3, ..., uy-1, uy, Uy+1, ...)T=(X1,1, X2,1, X3,1, X4,1, X5,1, X6,1, X7,1, X8,1, X9,1, X10,1, X11,1, X12,1, X13,1, P1,1, P2,1, X1,2, X2,2, X3,2, X4,2, X5,2, X6,2, X7,2, X8,2, X9,2, X10,2, X11,2, X12,2, X13,2, P1,2, P2,2, X1,3, X2,3, X3,3, X4,3, X5,3, X6,3, X7,3, X8,3, X9,3, X10,3, X11,3, X12,3, X13,3, P1,3, P2,3, .., X1,y-1, X2,y-1, X3,y-1, X4,y-1, X5,y-1, X6,y-1, X7,y-1, X8,y-1, X9,y-1, X10,y-1, X11,y-1, X12,y-1, X13,y-1, P1,y-1, P2,y-1, X1,y, X2,y, X3,y, X4,y, X5,y, X6,y, X7,y, X8,y, X9,y, X10,y, X11,y, X12,y, X13,y, P1,y, P2,y, X1,y+1, X2,y+1, X3,y+1, X4,y+1, X5,y+1, X6,y+1, X7,y+1, X8,y+1, X9,y+1, X10,y+1, X11,y+1, X12,y+1, X13,y+1, P1,y+1, P2,y+1, ...)T. Further, when using H to denote a parity check matrix for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, Hu=0 holds true (here, Hu=0 indicates that all elements of the vector Hu are zeroes).

[3471] FIG. 93 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the topmost row of the parity check matrix is considered as the first row. Further, row number is incremented by one each time moving to a lower row. Accordingly, the topmost row is considered as the first row, the row immediately below the first row is considered as the second row, and the subsequent rows are considered as the third row, the fourth row, and so on.

[3472] As illustrated in FIG. 93:

"a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";
"a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×(2m-1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression";

"a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression";

"a vector for the 2×(2m+1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the 2×(2m+2)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×i-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); first expression"; and

"a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); second expression", and so on (where i is an integer no smaller than one).



[3473] FIG. 94 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the leftmost column of the parity check matrix Hpro_m is considered as the first column. Further, column number is incremented by one each time moving to a rightward column. Accordingly, the leftmost column is considered as the first column, the column immediately to the right of the first column is considered as the second column, and the subsequent columns are considered as the third column, the fourth column, and so on.

[3474] As illustrated in FIG. 94:

"a vector for the first column of the parity check matrix H is related to X1 at time point 1";

"a vector for the second column of the parity check matrix H is related to X2 at time point 1";

"a vector for the third column of the parity check matrix H is related to X3 at time point 1";

"a vector for the fourth column of the parity check matrix H is related to X4 at time point 1";

"a vector for the fifth column of the parity check matrix H is related to X5 at time point 1";

"a vector for the sixth column of the parity check matrix H is related to X6 at time point 1";

"a vector for the seventh column of the parity check matrix H is related to X7 at time point 1";

"a vector for the eighth column of the parity check matrix H is related to X8 at time point 1";

"a vector for the ninth column of the parity check matrix H is related to X9 at time point 1";

"a vector for the tenth column of the parity check matrix H is related to X10 at time point 1";

"a vector for the eleventh column of the parity check matrix H is related to X11 at time point 1";

"a vector for the twelfth column of the parity check matrix H is related to X12 at time point 1";

"a vector for the thirteenth column of the parity check matrix H is related to X13 at time point 1";

"a vector for the fourteenth column of the parity check matrix H is related to P1 at time point 1";

"a vector for the fifteenth column of the parity check matrix H is related to P2 at time point 1";

"a vector for the 15×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 15×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 15×(j-1)+3th column of the parity check matrix H is related to X3 at time point j";

"a vector for the 15×(j-1)+4th column of the parity check matrix H is related to X4 at time point j";

"a vector for the 15×(j-1)+5th column of the parity check matrix H is related to X5 at time point j";

"a vector for the 15×(j-1)+6th column of the parity check matrix H is related to X6 at time point j";

"a vector for the 15×(j-1)+7th column of the parity check matrix H is related to X7 at time point j";

"a vector for the 15×(j-1)+8th column of the parity check matrix H is related to X8 at time point j";

"a vector for the 15×(j-1)+9th column of the parity check matrix H is related to X9 at time point j";

"a vector for the 15×(j-1)+10th column of the parity check matrix H is related to X10 at time point j";

"a vector for the 15×(j-1)+11h column of the parity check matrix H is related to X11 at time point j";

"a vector for the 15×(j-1)+12th column of the parity check matrix H is related to X12 at time point j";

"a vector for the 15×(j-1)+13th column of the parity check matrix H is related to X13 at time point j";

"a vector for the 15×(j-1)+14th column of the parity check matrix H is related to P1 at time point j";

"a vector for the 15×(j-1)+15th column of the parity check matrix H is related to P2 at time point j"; and so on (where j is an integer no smaller than one).



[3475] FIG. 95 indicates a parity check matrix for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3476] The following focuses on 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D), 1×X7(D), 1×X8(D), 1×X9(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D), 1×P1,(D), 1×P2(D) in the parity check matrix for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3477] The parity check polynomials at time point j=1 are parity check polynomials when i=0 in expressions (147-1-1), (147-1-2), (147-2-1), (147-2-2).

[3478] A vector for the first row in FIG. 95 can be generated from a parity check polynomial when i=0 in expression (147-1-1) or expression (147-1-2) (refer to FIG. 93).

[3479] In expressions (147-1-1) and (147-1-2):
  • terms for 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D) exist;
  • terms for 1×X7(D), 1×X8(D), 1×X9(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D) do not exist; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[3480] Further, the relationship between column numbers and X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, P1, P2 is as indicated in FIG. 94. Based on the relationship indicated in FIG. 94 and the fact that terms for 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D) exist, columns related to X1, X2, X3, X4, X5, X6 in the vector for the first row in FIG. 95 are "1". Further, based on the relationship indicated in FIG. 94 and the fact that terms for 1×X7(D), 1×X8(D), 1×X9(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D) do not exist, columns related to X7, X8, X9, X10, X11, X12, X13 in the vector for the first row in FIG. 95 are "0". In addition, based on the relationship indicated in FIG. 94 and the fact that a term for 1×P1(D) exists but a term for 1×P2(D) does not exist, a column related to P1 in the vector for the first row in FIG. 95 is "1", and a column related to P2 in the vector for the first row in FIG. 95 is "0".

[3481] As such, the vector for the first row in FIG. 95 is "111111000000010", as indicated by 3900-1 in FIG. 95.

[3482] A vector for the second row in FIG. 95 can be generated from a parity check polynomial when i=0 in expression (147-2-1) or expression (147-2-2) (refer to FIG. 93).

[3483] In expressions (147-2-1) and (147-2-2):
  • terms for 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D) do not exist;
  • terms for 1×X7(D), 1×X8(D), 1×X9(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D) exist; and
  • a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists.


[3484] Further, the relationship between column numbers and X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, P1, P2 is as indicated in FIG. 94. Based on the relationship indicated in FIG. 94 and the fact that terms for 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D) do not exist, columns related to X1, X2, X3, X4, X5, X6 in the vector for the second row in FIG. 95 are "0". Further, based on the relationship indicated in FIG. 94 and the fact that terms for 1×X7(D), 1×X8(D), 1×X9(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D) exist, columns related to X7, X8, X9, X10, X11, X12, X13 in the vector for the second row in FIG. 95 are "1". In addition, based on the relationship indicated in FIG. 94 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the second row in FIG. 95 is "Y", and a column related to P2 in the vector for the second row in FIG. 95 is "1", where Y is either "0" or "1".

[3485] As such, the vector for the second row in FIG. 95 is "0000001111111Y1", as indicated by 3900-2 in FIG. 95.

[3486] The parity check polynomials at time point j=2 are parity check polynomials when i=0 in expressions (148-1-1), (148-1-2), (148-2-1), (148-2-2).

[3487] A vector for the third row in FIG. 95 can be generated from a parity check polynomial when i=0 in expression (148-1-1) or expression (148-1-2) (refer to FIG. 93).

[3488] In expressions (148-1-1) and (148-1-2):
  • terms for 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D) do not exist;
  • terms for 1×X7(D), 1×X8(D), 1×X9(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D) exist; and
  • a term for 1×P1(D) exists but a term for 1×P2(D) does not exist.


[3489] Further, the relationship between column numbers and X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, P1, P2 is as indicated in FIG. 94. Based on the relationship indicated in FIG. 94 and the fact that terms for 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6)(D) do not exist, columns related to X1, X2, X3, X4, X5, X6 in the vector for the third row in FIG. 95 are "0". Further, based on the relationship indicated in FIG. 94 and the fact that terms for 1×X7(D), 1×X8(D), 1×X8(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D) exist, columns related to X7, X8, X9, X10, X11, X12, X13 in the vector for the third row in FIG. 95 are "1". In addition, based on the relationship indicated in FIG. 94 and the fact that a term for 1×P1(D) exists but a term for 1×P2(D) does not exist, a column related to P1 in the vector for the third row in FIG. 95 is "1", and a column related to P2 in the vector for the third row in FIG. 95 is "0".

[3490] As such, the vector for the third row in FIG. 95 is "000000111111110", as indicated by 3901-1 in FIG. 95.

[3491] A vector for the fourth row in FIG. 95 can be generated from a parity check polynomial when i=0 in expression (148-2-1) or expression (148-2-2) (refer to FIG. 93).

[3492] In expressions (148-2-1) and (148-2-2):
  • terms for 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D) exist;
  • terms for 1×X7(D), 1×X8(D), 1×X9(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D) do not exist; and
  • a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists.


[3493] Further, the relationship between column numbers and X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, P1, P2 is as indicated in FIG. 94. Based on the relationship indicated in FIG. 94 and the fact that terms for 1×X1(D), 1×X2(D), 1×X3(D), 1×X4(D), 1×X5(D), 1×X6(D) exist, columns related to X1, X2, X3, X4, X5, X6 in the vector for the fourth row in FIG. 95 are "1". Further, based on the relationship indicated in FIG. 94 and the fact that terms for 1×X7(D), 1×X8(D), 1×X9(D), 1×X10(D), 1×X11(D), 1×X12(D), 1×X13(D) do not exist, columns related to X7, X8, X9, X10, X11, X12, X13 in the vector for the fourth row in FIG. 95 are "0". In addition, based on the relationship indicated in FIG. 94 and the fact that a term for 1×P1(D) may or may not exist but a term for 1×P2(D) exists, a column related to P1 in the vector for the fourth row in FIG. 95 is "Y", and a column related to P2 in the vector for the fourth row in FIG. 95 is "1".

[3494] As such, the vector for the fourth row in FIG. 95 is "1111110000000Y1", as indicated by 3901-2 in FIG. 95.

[3495] Because it can be considered that the above similarly applies to cases where time point j=3, 4, 5, the parity check matrix H has the configuration indicated in FIG. 95.

[3496] That is, due to the parity check polynomials of expressions (147-1-1), (147-1-2), (147-2-1), (147-2-2) being used at time point j=2k+1 (where k is an integer no smaller than zero), "111111000000010" exists in the 2×(2k+1)-1th row of the parity check matrix H, and "0000001111111Y1" exists in the 2×(2k+1)th row of the parity check matrix H, as illustrated in FIG. 95.

[3497] Further, due to the parity check polynomials of expressions (148-1-1), (148-1-2), (148-2-1), (148-2-2) being used at time point j=2k+2 (where k is an integer no smaller than zero), "000000111111110" exists in the 2×(2k+2)-1th row of the parity check matrix H, and "1111110000000Y1" exists in the 2×(2k+2)th row of the parity check matrix H, as illustrated in FIG. 95.

[3498] Accordingly, as illustrated in FIG. 95, when denoting a column number of a leftmost column corresponding to "1" in "111111000000010" in a row where "111111000000010" exists (e.g., 3900-1 in FIG. 95) as "a", "000000111111110" (e.g., 3901-1 in FIG. 95) exists in a row that is two rows below the row where "111111000000010" exists, starting from column "a+15".

[3499] Similarly, as illustrated in FIG. 95, when denoting a column number of a leftmost column corresponding to "1" in "0000001111111Y1" in a row where "0000001111111Y1" exists (e.g., 3900-2 in FIG. 95) as "b", "1111110000000Y1" (e.g., 3901-2 in FIG. 95) exists in a row that is two rows below the row where "0000001111111Y1" exists, starting from column "b+15".

[3500] Similarly, as illustrated in FIG. 95, when denoting a column number of a leftmost column corresponding to "1" in "000000111111110" in a row where "000000111111110" exists (e.g., 3901-1 in FIG. 95) as "c", "111111000000010" (e.g., 3902-1 in FIG. 95) exists in a row that is two rows below the row where "000000111111110" exists, starting from column "c+15".

[3501] Similarly, as illustrated in FIG. 95, when denoting a column number of a leftmost column corresponding to "1" in "1111110000000Y1" in a row where "1111110000000Y1" exists (e.g., 3901-2 in FIG. 95) as "d", "0000001111111Y1" (e.g., 3902-2 in FIG. 95) exists in a row that is two rows below the row where "1111110000000Y1" exists, starting from column "d+15".

[3502] The following describes a parity check matrix for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial when tail-biting is not performed, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3503] In the following, Hcom[u][v] (where u and v are integers no smaller than one) denotes an element at row "u" column "v" of a parity check matrix for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3504] Based on description above provided with reference to FIG. 93:

"a vector for the 2×g-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); first expression"; and

"a vector for the (2×g)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g-1)%2m); second expression" (where g is an integer no smaller than one).



[3505] Based on description above provided with reference to FIG. 94:

"a vector for the 15×(j-1)+1th column of the parity check matrix H is related to X1 at time point j";

"a vector for the 15×(j-1)+2th column of the parity check matrix H is related to X2 at time point j";

"a vector for the 15×(j-1)+3th column of the parity check matrix H is related to X3 at time point j";

"a vector for the 15×(j-1)+4th column of the parity check matrix H is related to X4 at time point j";

"a vector for the 15×(j-1)+5th column of the parity check matrix H is related to X5 at time point j";

"a vector for the 15×(j-1)+6th column of the parity check matrix H is related to X6 at time point j";

"a vector for the 15×(j-1)+7th column of the parity check matrix H is related to X7 at time point j";

"a vector for the 15×(j-1)+8th column of the parity check matrix H is related to X8 at time point j";

"a vector for the 15×(j-1)+9th column of the parity check matrix H is related to X9 at time point j";

"a vector for the 15×(j-1)+10th column of the parity check matrix H is related to X10 at time point j";

"a vector for the 15×(j-1)+11h column of the parity check matrix H is related to X11 at time point j";

"a vector for the 15×(j-1)+12th column of the parity check matrix H is related to X12 at time point j";

"a vector for the 15×(j-1)+13th column of the parity check matrix H is related to X13 at time point j";

"a vector for the 15×(j-1)+14th column of the parity check matrix H is related to P1 at time point j"; and

"a vector for the 15×(j-1)+15th column of the parity check matrix H is related to P2 at time point j"; (where j is an integer no smaller than one).



[3506] Based on the above, the following describes component Hcom[2×g-1][v] in row 2×g-1 (where g is an integer no smaller than one) and component Hcom[2×g][v] in row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3507] As already described above, a parity check polynomial satisfying zero of #((g-1)%2m); first expression can be used to generate a vector for row 2×g-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3508] Further, a parity check polynomial satisfying zero of #((g-1)%2m); second expression can be used to generate a vector for row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3509] Accordingly, when g=2×f-1 (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (147-1-1) or expression (147-1-2), can be used to generate a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3510] Further, a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (147-2-1) or expression (147-2-2), can be used to generate a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3511] Further, when g=2×f (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f)-1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (148-1-1) or expression (148-1-2), can be used to generate a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3512] Further, a parity check polynomial satisfying zero of #(((2×f)-1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (148-2-1) or expression (148-2-2), can be used to generate a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3513] Accordingly, (1) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (147-1-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (147-1-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[3514] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[3515] The following holds true for X1.
[Math. 767]



[3516] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than six.
[Math. 768]



[3517] Further, the following holds true for X7. In the following, y is an integer no smaller than R#(2c),7+1 and no greater than r#(2c),7.
[Math. 769]



[3518] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than seven and no greater than thirteen, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 770]



[3519] The following holds true for P1.
[Math. 771]





[3520] The following holds true for P2.
[Math. 772]



[3521] Further, (2) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (147-1-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (147-1-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[3522] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[3523] The following holds true for X1.
[Math. 773]





[3524] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than six.
[Math. 774]



[3525] Further, the following holds true for X7. In the following, y is an integer no smaller than R#(2c),7+1 and no greater than r#(2c),7.
[Math. 775]



[3526] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than seven and no greater than thirteen, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 776]





[3527] The following holds true for P1.
[Math. 777]



[3528] The following holds true for P2.
[Math. 778]



[3529] Further, (3) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (147-2-1), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (147-2-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[3530] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[3531] The following holds true for X1. In the following, and y is an integer no smaller than R#(2c),1+1 and no greater than r#(2c),1.
[Math. 779]



[3532] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than six, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 780]



[3533] Further, the following holds true for X7.
[Math. 781]



[3534] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than seven and no greater than thirteen.
[Math. 782]



[3535] The following holds true for P1.
[Math. 783]



[3536] The following holds true for P2.
[Math. 784]



[3537] Further, (4) when g=2×f-1 (where f is an integer no smaller than one), when a vector for row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (147-2-2), (2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (147-2-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[3538] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[3539] The following holds true for X1. In the following, y is an integer no smaller than R#(2c),1+1 and no greater than r#(2c),1.
[Math. 785]



[3540] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than six, and y is an integer no smaller than R#(2c),z+1 and no greater than r#(2c),z.
[Math. 786]



[3541] Further, the following holds true for X7.
[Math. 787]





[3542] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than seven and no greater than thirteen.
[Math. 788]



[3543] The following holds true for P1.
[Math. 789]



[3544] The following holds true for P2.
[Math. 790]



[3545] Further, (5) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (148-1-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (148-1-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[3546] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-I][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[3547] The following holds true for X1. In the following, y is an integer no smaller than R#(2d+1),1+1 and no greater than r#(2d+1),1.
[Math. 791]



[3548] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than six, and y is an integer no smaller than R#(2d+1),z+1 and no greater than r#(2d+1),z.
[Math. 792]





[3549] Further, the following holds true for X7.
[Math. 793]



[3550] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than seven and no greater than thirteen.
[Math. 794]



[3551] The following holds true for P1.
[Math. 795]



[3552] The following holds true for P2.
[Math. 796]



[3553] Further, (6) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (148-1-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (148-1-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[3554] Accordingly, component Hcom[2×g-1][v]=Hcom[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

[3555] The following holds true for X1. In the following, y is an integer no smaller than R#(2d+1),1+1 and no greater than r#(2d+1),1.
[Math. 797]





[3556] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than one and no greater than six, and y is an integer no smaller than R#(2d+1),z+1 and no greater than r#(2d+1),z.
[Math. 798]



[3557] Further, the following holds true for X7.
[Math. 799]



[3558] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than seven and no greater than thirteen.
[Math. 800]





[3559] The following holds true for P1.
[Math. 801]



[3560] The following holds true for P2.
[Math. 802]



[3561] Further, (7) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (148-2-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (148-2-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[3562] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+); second expression, is expressed as follows.

[3563]  The following holds true for X1.
[Math. 803]



[3564] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than six.
[Math. 804]



[3565] Further, the following holds true for X7. In the following, y is an integer no smaller than R#(2d+1),7+1 and no greater than r#(2d+1),7.
[Math. 805]



[3566] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than seven and no greater than thirteen, and y is an integer no smaller than R#(2d+1),z+1 and no greater than r#(2d+1),z.
[Math. 806]



[3567] The following holds true for P1.
[Math. 807]



[3568] The following holds true for P2.
[Math. 808]



[3569] Further, (8) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (148-2-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (148-2-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[3570] Accordingly, component Hcom[2×g][v]=Hcom[2×(2×f)][v] in row 2×g, or that is, row 2x(2xf) of the parity check matrix H, which is for an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+); second expression, is expressed as follows.

[3571] The following holds true for X1.
[Math. 809]



[3572] Considered in a similar manner, the following holds true for Xw. In the following, w is an integer no smaller than one and no greater than six.
[Math. 810]



[3573] Further, the following holds true for X7. In the following, y is an integer no smaller than R#(2d+1),7+1 and no greater than r#(2d+1),7.
[Math. 811]



[3574] Considered in a similar manner, the following holds true for Xz. In the following, z is an integer no smaller than seven and no greater than thirteen, and y is an integer no smaller than R#(2d+1),z+1 and no greater than r#(2d+1),z.
[Math. 812]



[3575] The following holds true for P1.
[Math. 813]



[3576] The following holds true for P2.
[Math. 814]



[3577] As such, an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial can be generated by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, and the code so generated achieves high error correction capability.

(Embodiment G3)



[3578] In the present embodiment, description is provided of a device that uses the LDPC-CC of coding rate 13/15 that is based on a parity check polynomial, description of which has been provided in embodiments G1 and G2.

[3579] As one example, description is provided of a case where the LDPC-CC of coding rate 13/15 that is based on a parity check polynomial, description of which has been provided in embodiments G1 and G2, is applied to a communication device.

[3580] FIG. 22 illustrates the structures of a transmitting device 2200 and a receiving device 2210 in the communication device pertaining to the present embodiment.

[3581] An encoder 2201 receives information to be transmitted as input, and is capable of performing various types of encoding. In particular, when receiving a specification to perform encoding by using the LDPC-CC of coding rate 13/15 that is based on a parity check polynomial, description of which has been provided in embodiments G1 and G2, the encoder 2201 performs encoding by using the LDPC-CC of coding rate 13/15 that is based on a parity check polynomial, description of which has been provided in embodiments G1 and G2, to calculate parities P1 and P2. Further, the encoder 2201 outputs the information to be transmitted and the parities P1 and P2 as a transmission sequence.

[3582] A modulator 2202 receives the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, performs mapping based on a predetermined modulation scheme (e.g., BPSK, QPSK, 16QAM, 64QAM), and outputs a baseband signal. Further, the modulator 2202 may also receive information other than the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, as input, perform mapping, and output a baseband signal. For example, the modulator 2202 may receive control information as input.

[3583] The transmitting device outputs a transmission signal after performing predetermined signal processing (e.g., signal processing for generation of an OFDM signal, frequency conversion, amplification) with respect to such signals (e.g., baseband signals, pilot signals). The transmitting device may transmit the transmission signal over a wireless transmission path utilizing electromagnetic waves, or over a wired transmission path utilizing a coaxial cable, a power line, an optical cable, or the like.

[3584] The transmission signal is received by the receiving device 2210 after travelling over the transmission path. A receiver 2211 receives a reception signal as input, performs predetermined signal processing (e.g., bandwidth limitation, frequency conversion, signal processing for OFDM, frequency offset estimation, signal detection, channel estimation), and outputs a baseband signal and a channel estimation signal.

[3585] A log-likelihood ratio generation section 2212 receives the baseband signal and the channel estimation signal as input (may receive other signals as input), and for example, calculates and outputs a log-likelihood ratio for each bit (may calculate and output a hard value (hard decision value)).

[3586] A decoder 2213 receives the log-likelihood ratio for each bit as input, performs belief propagation decoding (e.g., sum-product decoding, scheduled sum-product decoding (Layered BP (belief propagation) decoding), min-sum decoding, Normalized BP decoding, offset BP decoding), and outputs an estimation sequence. The decoder 2213 performs the belief propagation decoding based on the parity check matrix for the LDPC-CC of coding rate 13/15 that is based on a parity check polynomial, description of which has been provided in embodiments G1 and G2.

[3587] FIG. 96 illustrates one example of the structure of an encoder for the LDPC-CC of coding rate 13/15 that is based on a parity check polynomial, description of which has been provided in embodiments G1 and G2. Description on such an encoder has been provided with reference to the encoder 2201 in FIG. 22.

[3588] In FIG. 96, an Xz computation section 4001-z (where z is an integer no smaller than one and no greater than thirteen) includes a plurality of shift registers that are connected in series and a calculator that performs XOR calculation on bits collected from some of the shift registers (refer to FIGs. 2 and 22).

[3589] The Xz computation section 4001-z receives an information bit Xz,j at time point j as input, performs the XOR calculation, and outputs bits 4002-z-1 and 4002-z-2, which are acquired through the Xz calculation.

[3590] A P1 computation section 4004-1 includes a plurality of shift registers that are connected in series and a calculator that that performs XOR calculation on bits collected from some of the shift registers (refer to FIGs. 2 and 22).

[3591] The P1 computation section 4004-1 receives a bit P1,j of parity P1 at time point j as input, performs the XOR calculation, and outputs bits 4005-1-1 and 4005-1-2, which are acquired through the P1 calculation.

[3592] A P2 computation section 4004-2 includes a plurality of shift registers that are connected in series and a calculator that that performs XOR calculation on bits collected from some of the shift registers (refer to FIGs. 2 and 22).

[3593] The P2 computation section 4004-2 receives a bit P2,j of parity P2 at time point j as input, performs the XOR calculation, and outputs bits 4005-2-1 and 4005-2-2, which are acquired through the P2 calculation.

[3594] An XOR (calculator) 4005-1 receives the bits 4002-1-1 through 4002-13-1 acquired by X1 calculation through X13 calculation, respectively, the bit 4005-1-1 acquired by P1 calculation, and the bit 4005-2-1 acquired by the P2 calculation as input, performs XOR calculation, and outputs a bit P1,j of parity P1 at time point j.

[3595] An XOR (calculator) 4005-2 receives the bits 4002-1-2 through 4002-13-2 acquired by X1 calculation through X13 calculation, respectively, the bit 4005-1-2 acquired by P1 calculation, and the bit 4005-2-2 acquired by the P2 calculation as input, performs XOR calculation, and outputs a bit P2,j of parity P2 at time point j.

[3596] It is preferable that initial values of the shift registers of the Xz computation section 4001-z, the P1 computation section 4004-1, and the P2 computation section 4004-2 illustrated in FIG. 96 be set to "0" (zero). By making such a configuration, it becomes unnecessary to transmit to the receiving device parities P1 and P2 before the setting of initial values.

[3597] The following describes a method of information-zero termination.

[3598] Suppose that in FIG. 97, information X1 through X13 exist from time point 0, and information X13 at time point s (where s is an integer no smaller than zero) is the last information bit. That is, suppose that the information to be transmitted from the transmitting device to the receiving device is information X1,j through X13,j, being information X1 through X13 at time point j, respectively, where j is an integer no smaller than zero and no greater than s.

[3599] In such a case, the transmitting device transmits information X1 through X13, parity P1, and parity P2 from time point 0 to time point s, or that is, transmits X1,j, X2,j, X3,j, X4,j, X5,j, X6,j, X7,j, X8,j, X9,j, X10,j, X11,j, X12,j, X13,j, P1,j, P2,j, where j is an integer no smaller than zero and no greater than s. (Note that P1,j and P2,j denote parity P1 and parity P2 at time point j, respectively.)

[3600] Further, suppose that information X1 through X13 from time point s+1 to time point s+g (where g is an integer no smaller than one) is "0", or that is, when denoting information X1 through X13 at time point t as X1,t, X2,t, X3,t, X4,t, X5,t, X6,t, X7,t, X8,t, X9,t, X10,t, X11,t, X12,t, X13,t, respectively, X1,t=0, X2,t=0, X3,t=0, X4,t=0, X5,t=0, X6,t=0, X7,t=0, X8,t=0, X9,t=0, X10,t=0, X11,t=0, X12,t=0, X13,t=0 hold true for t being an integer no smaller than s+1 and no greater than s+g. The transmitting device, by performing encoding, acquires parities P1,t and P2,t for t being an integer no smaller than s+1 and no greater than s+g. The transmitting device, in addition to the information and parities described above, transmits parities P1,t and P2,t for t being an integer no smaller than s+1 and no greater than s+g.

[3601] Meanwhile, the receiving device performs decoding by using log-likelihood ratios for the information and the parities transmitted by the transmitting device, and log-likelihood ratios corresponding to X1,t=0, X2,t=0, X3,t=0, X4,t=0, X5,t=0, X6,t=0, X7,t=0, X8,t=0, X9,t=0, X10,t=0, X11,t=0, X12,t=0, X13,t=0 for t being an integer no smaller than s+1 and no greater than s+g, and thereby acquires an estimation sequence of information.

[3602] FIG. 98 illustrates an example differing from that illustrated in FIG. 97. Suppose that information X1 through X13 exist from time point 0, and information Xf for time point s (where s is an integer no smaller than zero) is the last information bit. Here, f is an integer no smaller than one and no greater than twelve. In FIG. 97, f equals 10, for example. That is, suppose that the information to be transmitted from the transmitting device to the receiving device is information Xi,s, where i is an integer no smaller than one and no greater than f, and information X1,j, information X2,j, information X3,j, information X4,j, information X5,j, information X6,j, information X7,j, information X8,j, information X9,j, information X10,j, information X11,j, information X12,j, information X13,j, being information X1 through X13 at time point j, respectively, where j is an integer no smaller than zero and no greater than s-1.

[3603] In such a case, the transmitting device transmits information X1 through X13, parity P1, and parity P2 from time point 0 to time point s-1, or that is, transmits X1,j, X2,j, X3,j, X4,j, X5,j, X6,j, X7,j, X8,j, X9,j, X10,j, X11,j, X12,j, X13,j, P1,j, P2,j, where j is an integer no smaller than zero and no greater than s-1. (Note that P1,j and P2,j denote parity P1 and parity P2 at time point j, respectively.)

[3604] Further, suppose that at time point s, information Xi,s, when i is an integer no smaller than one and no greater than f, is information that the transmitting device is to transmit, and suppose that Xk,s, when k is an integer so smaller than f+1 and no greater than thirteen, equals "0" (zero).

[3605] Further, suppose that information X1 through X13 from time point s+1 to time point s+g-1 (where g is an integer no smaller than two) is "0", or that is, when denoting information X1 through X13 at time point t as X1,t, X2,t, X3,t, X4,t, X5,t, X6,t, X7,t, X8,t=0, X9,t=0, X10,t=0, X11,t=0, X12,t=0, X13,t=0 respectively, X1,t=0, X2,t=0, X3,t=0, X4,t=0, X5,t=0, X6,t=0, X7,t=0, X8,t=0, X9,t=0, X10,t=0, X11,t=0, X12,t=0, X13,t=0 hold true when t is an integer no smaller than s+1 and no greater than s+g-1. The transmitting device, by performing encoding from time point s to time point s+g-1, acquires parities P1,u and P2,u for u being an integer no smaller than s and no greater than s+g-1. The transmitting device, in addition to the information and parities described above, transmits Xi,s for i being an integer no smaller than one and no greater than f, and parities P1,u and P2,u for u being an integer no smaller than s and no greater than s+g-1.

[3606] Meanwhile, the receiving device performs decoding by using log-likelihood ratios for the information and the parities transmitted by the transmitting device, log-likelihood ratios corresponding to Xk,s=0 (where k is an integer no smaller than f+1 and no greater than thirteen) and log-likelihood ratios corresponding to X1,t=0, X2,t=0, X3,t=0, X4,t=0, X5,t=0, X6,t=0, X7,t=0, X8,t=0, X9,t=0, X10,t=0, X11,t=0, X12,t=0, X13,t=0 for t being an integer no smaller than s+1 and no greater than s+g-1, and thereby acquires an estimation sequence of information.

[3607] Although description is provided above taking an example where error correction coding is introduced to a communication device, the error correction coding described above is not limited to being introduced to a communication device, and for example, may be introduced to a storage medium (storage). When making such a modification, information that is to be stored to a storage medium (storage) is encoded by using the LDPC-CC of coding rate 13/15 that is based on a parity check polynomial, description of which has been provided in embodiments G1 and G2, and resultant information and parities are stored to the storage medium (storage). When making such a modification, it is preferable that information-zero termination be introduced as described above and that a data sequence as described above corresponding to a data sequence (information and parities) transmitted by the transmitting device when information-zero termination is applied be stored to the storage medium (storage).

[3608] Further, the LDPC-CC of coding rate 13/15 that is based on a parity check polynomial, description of which has been provided in embodiments G1 and G2, is applicable to any device that requires error correction coding (e.g., a memory, a hard disk).

(Embodiment G4)



[3609] In the present embodiment, description is provided of a method of configuring an LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). The LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme described in the present embodiment is based on the LDPC-CC of coding rate 13/15 that is based on a parity check polynomial, description of which has been provided in embodiments G1 and G2.

[3610] Patent Literature 2 includes explanation regarding an LDPC-CC of coding rate (n-1)/n (where n is an integer no smaller than two) that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). However, Patent Literature 2 poses a problem for not disclosing an LDPC-CC of a coding rate not satisfying (n-1)/n that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[3611] In the present embodiment, as one example of an LDPC-CC of a coding rate not satisfying (n-1)/n that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), description is provided of a method of configuring an LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[Periodic Time-varying LDPC-CC of Coding rate 13/15 Using Improved Tail-biting Scheme and Based on Parity Check Polynomial]



[3612] The following describes a periodic time-varying LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme and is based on a parity check polynomial, based on the configuration of the LDPC-CC of coding rate 13/15 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments G1 and G2.

[3613] The following describes a method of configuring an LDPC-CC of coding rate 13/15 and time-varying period 2m that is based on a parity check polynomial. Such method has already been described in embodiment G2.

[3614] First, the following parity check polynomials satisfying zero are prepared.
[Math. 815-1]



[Math. 815-2]

[Math. 815-3]



[Math. 815-4]





[3615] In expressions (197-1-1), (197-1-2), (197-2-1), (197-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[3616] In expressions (197-1-1), (197-1-2), (197-2-1), (197-2-2), α#(2i),p,q (where p is an integer no smaller than one and no greater than thirteen, q is an integer no smaller than one and no greater than r#(2i),p (where r#(2i),p is a natural number)) and β#(2i),0 is a natural number, β#(2i),1 is a natural number, β#(2i),2 is an integer no smaller than zero, and β#(2i),3 is a natural number.

[3617] Further, R#(2i),p is a natural number satisfying 1≤R#(2i),p<r#(2i),p.

[3618] Further, y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and α#(2i),p,y≠α#(2i),p,z holds true for all y and all z satisfying y≠z.)

[3619] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (197-1-1) or expression (197-1-2) is referred to as "#(2i); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (197-2-1) or expression (197-2-2) is referred to as "#(2i); second expression" for realizing a time-varying period 2m.

[3620] Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (197-1-1) or expression (197-1-2) is prepared.

[3621] That is, for i=0, a parity check polynomial satisfying zero provided by expression (197-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (197-1-2) where i=0 is prepared.

[3622] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (197-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (197-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (197-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (197-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (197-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (197-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (197-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (197-1-2) where i=m-1 is prepared.



[3623] Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (197-2-1) or expression (197-2-2) is prepared.

[3624] That is, for i=0, a parity check polynomial satisfying zero provided by expression (197-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (197-2-2) where i=0 is prepared.

[3625] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (197-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (197-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (197-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (197-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (197-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (197-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (197-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (197-2-2) where i=m-1 is prepared.



[3626] Similarly, the following parity check polynomials satisfying zero are provided.
[Math. 816-1]



[Math. 816-2]



[Math. 816-3]

[Math. 816-4]





[3627] In expressions (198-1-1), (198-1-2), (198-2-1), (198-2-2), i is an integer no smaller than zero and no greater than m-1 (i=0, 1, ..., m-2, m-1).

[3628] In expressions (198-1-1), (198-1-2), (198-2-1), (198-2-2), α#(2i+1),p,q (where p is an integer no smaller than one and no greater than thirteen, q is an integer no smaller than one and no greater than r#(2i+1),p (where r#(2i+1),p is a natural number)) and β#(2i+1),0 is a natural number, β#(2i+1),1 is a natural number, β#(2i+1),2 is an integer no smaller than zero, and β#(2i+1),3 is a natural number.

[3629] Further, R#(2i+1),p is a natural number satisfying 1≤R#(2i+1),p<r#(2i+1),p.

[3630] Further, y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r#(2i+1),p, and α#(2i+1),p,y≠α#(2i+1),p,z holds true for all y and all z satisfying y≠z.)

[3631] Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (198-1-1) or expression (198-1-2) is referred to as "#(2i+1); first expression" for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (198-2-1) or expression (198-2-2) is referred to as "#(2i+1); second expression" for realizing a time-varying period 2m.

[3632] Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (198-1-1) or expression (198-1-2) is prepared.

[3633] That is, for i=0, a parity check polynomial satisfying zero provided by expression (198-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (198-1-2) where i=0 is prepared.

[3634] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (198-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (198-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (198-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (198-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (198-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (198-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (198-1-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (198-1-2) where i=m-1 is prepared.



[3635] Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (198-2-1) or expression (198-2-2) is prepared.

[3636] That is, for i=0, a parity check polynomial satisfying zero provided by expression (198-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (198-2-2) where i=0 is prepared.

[3637] Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (198-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (198-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (198-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (198-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (198-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (198-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m-1); and

for i=m-1, a parity check polynomial satisfying zero provided by expression (198-2-1) where i=m-1, or a parity check polynomial satisfying zero provided by expression (198-2-2) where i=m-1 is prepared.



[3638] As such, an LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

[3639] Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (197-1-1) or expression (197-1-2), parity check polynomials satisfying zero provided by expression (197-2-1) or expression (197-2-2), parity check polynomials satisfying zero provided by expression (198-1-1) or expression (198-1-2), and parity check polynomials satisfying zero provided by expression (198-2-1) or expression (198-2-2).

[3640] For example, the time varying period 2×m is formed by preparing a 4×m number of different parity check polynomials satisfying zero.

[3641] Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

[3642] The following describes the relationship between time point j and expressions (197-1-1), (197-1-2), (197-2-1), (197-2-2), (198-1-1), (198-1-2), (198-2-1), and (198-2-2) (where j is an integer no smaller than zero).

[3643] The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m-1).

[3644] Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i = k in #(2i); first expression and #(2i); second expression, hold true.

[3645] Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m-1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

[3646] Note that in the parity check polynomials satisfying zero of expressions (197-1-1), (197-1-2), (197-2-1), (197-2-2), (198-1-1), (198-1-2), (198-2-1), and (198-2-2), a sum of the number of terms of P1(D) and the number of terms of P2(D) equals two. This realizes sequentially finding parities P1 and P2 when applying an improved tail-biting scheme, and thus, is a significant factor realizing a reduction in computation amount (circuit scale).

[3647] The following describes the relationship between the time-varying period of the parity check polynomials satisfying zero for the LDPC-CC of coding rate 13/15 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments G1 and G2 and on which the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, and block size in the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) proposed in the present embodiment.

[3648] Regarding this point, in order to achieve error correction capability of even higher level, a configuration is preferable where a Tanner graph formed by the LDPC-CC of coding rate 13/15 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments G1 and G2 and on which the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, resembles a Tanner graph of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). Thus, the following conditions are significant.

<Condition #N1>



[3649] 
  • The number of rows in a parity check matrix for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is a multiple of 4×m.
    • Accordingly, the number of columns in the parity check matrix for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is a multiple of 15×2×m. According to this condition, (for example) a log-likelihood ratio that is necessary in decoding is a log-likelihood ratio of the number of columns in the parity check matrix for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).


[3650] Note that the relationship between the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and the LDPC-CC of coding rate 13/15 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments G1 and G2 and on which the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, is described in detail later in the present disclosure.

[3651] Thus, when denoting the parity check matrix for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as Hpro, the number of columns of Hpro can be expressed as 15×2×m×z (where z is a natural number).

[3652] Accordingly, a transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as vs=(Xs,1,1, Xs,2,1,...,Xs,13,1,Ppros,1,1,Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,13,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,13,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,13,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z) (where k=1, 2, ..., 2×m×z-1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×z)), and Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes).

[3653] Xs,j,k (where j is an integer no smaller than one and no greater than thirteen) is a bit of information Xj, Ppros,1,k is a bit of parity P1 of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and Ppros,2,k is a bit of parity P2 of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[3654] Further, λpro,s,k=(Xs,1,k, Xs,2,k, Xs,3,k, Xs,4,k, Xs,5,k, Xs,6,k, Xs,7,k, Xs,8,k, Xs,9,k, Xs,10,k, Xs,11,k, Xs,12,k, Xs,13,k, Ppros,1,k, Ppros,2,k) holds true.

[3655] In addition, the number of rows in the parity check matrix Hpro for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is 4×m×z.

[3656] It has been indicated above that the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based on the LDPC-CC of coding rate 13/15 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments G1 and G2. This is explained in the following.

[3657] First, consideration is made of a parity check matrix when configuring a periodic time-varying LDPC-CC using tail-biting by using only parity check polynomials satisfying zero for the LDPC-CC of coding rate 13/15 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments G1 and G2.

[3658] FIG. 99 illustrates a configuration of a parity check matrix H when configuring a periodic time-varying LDPC-CC using tail-biting by performing tail-biting by using only parity check polynomials satisfying zero for an LDPC-CC of coding rate 13/15 and time-varying period 2m.

[3659] Since Condition #N1 is satisfied in FIG. 99, the number of rows of the parity check matrix is m×z and the number of columns of the parity check matrix is 15×2×m×z.

[3660] As illustrated in FIG. 99:

"a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×(2m-1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression";

"a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression";

"a vector for the 2×(2m+1)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression";

"a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression";

"a vector for the 2×(2m+2)-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression";

"a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression";

"a vector for the 2×i-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); first expression";

"a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i-1)%2m); second expression" (where i is an integer no smaller than one and no greater than 2×m×z);

"a vector for the 2×(2m-1)×z-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); first expression";

"a vector for the 2×(2m-1)×zth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-2); second expression";

"a vector for the 2×(2m)×z-1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); first expression"; and

"a vector for the 2×(2m)×zth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m-1); second expression".



[3661] To prepare for the explanation to be provided in the following, a mathematical expression is provided of the parity check matrix H in FIG. 99, which is a parity check matrix when configuring a periodic time-varying LDPC-CC by performing tail-biting by using only parity check polynomials satisfying zero for the LDPC-CC of coding rate 13/15 and time-varying period 2m that is based on a parity check polynomial, description of which is provided in embodiments G1 and G2. When denoting a vector having one row and 15×2×m×z columns in row k of the parity check matrix H as hk, the parity check matrix H in FIG. 99 is expressed as follows.
[Math. 817]



[3662] The following describes a parity check matrix for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[3663] FIG. 100 illustrates one example of a configuration of a parity check matrix Hpro for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[3664] The parity check matrix Hpro for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) satisfies Condition #N1.

[3665] When denoting a vector having one row and 15×2×m×z columns in row k of the parity check matrix Hpro in FIG. 100, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), as gk, the parity check matrix Hpro in FIG. 100 is expressed as follows.
[Math. 818]



[3666] A transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as vs=(Xs,1,1, Xs,2,1, ..., Xs,13,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,13,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,13,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,13,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T (where k=1, 2, ..., 2×m×z-1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×z)), and Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes).

[3667] Xs,j,k (where j is an integer no smaller than one and no greater than thirteen) is a bit of information Xj, Ppros,1,k is a bit of parity P1 of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and Ppros,2,k is a bit of parity P2 of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[3668] In the parity check matrix Hpro in FIG. 100, which illustrates one example of a configuration of a parity check matrix Hpro for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), rows other than row one, or that is, rows between row two to row 2×(2×m)×z in the parity check matrix Hpro in FIG. 100, have the same configuration as rows between row two and row 2×(2×m)×z in the parity check matrix H in FIG. 99 (refer to FIGs. 99 and 100). Accordingly, FIG. 100 includes an indication of #0'; first expression at 4401 in the first row. (This point is explained later in the present disclosure.) Accordingly, the following relational expression holds true based on expressions 199 and 200.
[Math. 819]



[3669] Further, the following holds true when i=1.
[Math. 820]



[3670] Accordingly, the parity check matrix Hpro for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as follows.
[Math. 821]



[3671] In expression 203, expression 202 holds true.

[3672] Next, explanation is provided of a method of configuring g1 in expression 203 so that parities can be found sequentially and high error correction capability can be achieved.

[3673] One example of a method of configuring g1 in expression 203, so that parities can be found sequentially and high error correction capability can be achieved, is using a parity check polynomial satisfying zero of #0; first expression of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), which serves as the basis.

[3674] Since g1 is row one of the parity check matrix Hpro for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), g1 is generated from a parity check polynomial satisfying zero that is obtained by transforming a parity check polynomial satisfying zero of #0; first expression. As described above, a parity check polynomial satisfying zero of #0; first expression is expressed by either expression (204-1-1) or expression (204-1-2).
[Math. 822-1]



[Math. 822-2]





[3675] As one example of a parity check polynomial satisfying zero for generating vector g1 in row one of the parity check matrix Hpro for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), a parity check polynomial satisfying zero of #0; first expression is expressed as follows, for either expression (204-1-1) or expression (204-1-2).
[Math. 823]





[3676] Accordingly, vector g1 is a vector having one row and 15×2×m×z columns that is obtained by performing tail-biting with respect to expression 205.

[3677] Note that in the following, a parity check polynomial that satisfies zero provided by expression 205 is referred to as #0'; first expression.

[3678] Accordingly, row one of the parity check matrix Hpro for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be obtained by transforming #0'; first expression of expression 205 (that is, a vector g1 corresponding to one row and 15×2×m×z columns can be obtained).

[3679] A transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is vs=(Xs,2,1, ..., Xs,13,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,13,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,13,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,13,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T, and the number of parity check polynomials satisfying zero necessary for obtaining this transmission sequence is 2×(2×m)×z.

[3680] Here, when arranging such 2×(2×m)×z number of parity check polynomials satisfying zero in order, a parity check polynomial satisfying zero appearing eth is referred to in the following as an "eth parity check polynomial satisfying zero" (where e is an integer no smaller than zero and no greater than 2×(2×m)×z-1).

[3681] As such, the parity check polynomials satisfying zero are arranged in the following order:

zeroth: zeroth parity check polynomial satisfying zero;

first: first parity check polynomial satisfying zero;

second: second parity check polynomial satisfying zero;

eth: eth parity check polynomial satisfying zero;

2×(2×m)×z-2th: 2×(2×m)×z-2th parity check polynomial satisfying zero; and

2×(2×m)×z-1th: 2×(2×m)×z-1th parity check polynomial satisfying zero.



[3682] Accordingly, the transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is obtained. (As can be seen from description provided above, when expressing the parity check matrix Hpro for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as provided in expression 200, a vector composed of row e+1 of the parity check matrix Hpro corresponds to the eth parity check polynomial satisfying zero.)

[3683] Accordingly, in the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the second parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the third parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression;

the 2×(2m)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression;

the 2×(2m+1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; first expression;

the 2×(2m+1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×(2m+2)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the 2×(2m+2)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression; and

the 2×(2m)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression.



[3684] That is,
the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;
the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;
the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression; and
the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).

[3685] As description has been provided above, the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), at the same time as achieving high error correction capability, enables finding multiple parities sequentially, and therefore, achieves an advantageous effect of reducing circuit scale of an encoder.

[3686] In the following, explanation is provided of what is meant by "finding parities sequentially".

[3687] In the example described above, since bits of information X1 through X13 are pre-acquired, Ppros,1,1 can be calculated by using the 0th parity check polynomial satisfying zero of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), or that is, by using the parity check polynomial satisfying zero of #0'; first expression provided by expression 205.

[3688] Then, from the bits of information X1 through X13 and Ppros,1,1, another parity (denoted as Pc=1) can be calculated by using another parity check polynomial satisfying zero.

[3689] Further, from the bits of information X1 through X13 and Pc=1, another parity (denoted as Pc=2) can be calculated by using another parity check polynomial satisfying zero.

[3690] By repeating such operation, from the bits of information X1 through X13 and Pc=h, another parity (denoted as Pc=h+1) can be calculated by using a given parity check polynomial satisfying zero.

[3691] This is referred to as "finding parities sequentially", and when parities can be found sequentially, multiple parities can be obtained without calculation of complex simultaneous equations, whereby an advantageous effect is achieved of reducing circuit scale (computation amount) of an encoder.

[3692] Next, explanation is provided of configurations and operations of an encoder and a decoder for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[3693] In the following, one example case is considered where the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is used in a communication system. When applying the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) to a communication system, the encoder and the decoder for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) are characterized for each being configured and each operating based on the parity check matrix Hpro for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and based on the relationship Hprovs=0.

[3694] The following provides explanation while referring to FIG. 25, which is an overall diagram of a communication system. An encoder 2511 of a transmitting device 2501 receives an information sequence of block s (Xs,1,1, Xs,2,1, ..., Xs,13,1, Xs,1,2, Xs,2,2, ..., Xs,13,2, ..., Xs,1,k, Xs,2,k, ..., Xs,13,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,13,2×m×z) as input. The encoder 2511 performs encoding based on the parity check matrix Hpro for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and based on the relationship Hprovs=0. The encoder 2511 generates a transmission sequence (encoded sequence (codeword)) vs of block s of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), denoted as vs=(Xs,1,1, Xs,2,1, ..., Xs,13,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,13,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,13,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,13,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T , and outputs the transmission sequence vs. As already described above, the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is characterized for enabling parities to be found sequentially.

[3695] A decoder 2523 of a receiving device 2520 in FIG. 25 receives, as input, a log-likelihood ratio of each bit of, for example, the transmission sequence vs=(Xs,1,1, Xs,2,1, ..., Xs,7,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,7,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,7,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,7,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T. The log-likelihood ratios are output from a log-likelihood ratio generator 2522. The decoder 2523 performs decoding for an LDPC code according to the parity check matrix Hpro for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). For example, the decoding may be decoding disclosed in Non-Patent Literature 4, Non-Patent Literature 6, Non-Patent Literature 7, Non-Patent Literature 8, etc., i.e., simple BP decoding such as min-sum decoding, offset BP decoding, or Normalized BP decoding, or Belief Propagation (BP) decoding in which scheduling is performed with respect to the row operations (Horizontal operations) and the column operations (Vertical operations) such as Shuffled BP decoding or Layered BP decoding. The decoding may also be decoding such as bit-flipping decoding disclosed in Non-Patent Literature 17, for example. The decoder 2523 obtains an estimation transmission sequence (estimation encoded sequence) (reception sequence) of block s through the decoding, and outputs the estimation transmission sequence.

[3696] In the above, explanation is provided on operations of the encoder and the decoder in a communication system as one example. Alternatively, the encoder and the decoder may be used in technical fields related to storages, memories, etc.

[3697]  The following describes a specific example of a configuration of a parity check matrix for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[3698] When denoting the parity check matrix for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as Hpro as described above, the number of columns of Hpro can be expressed as 15×2×m×z (where z is a natural number). (Note that m denotes a time-varying period of the LDPC-CC of coding rate 13/15 that is based on a parity check polynomial, which serves as the basis.)

[3699] Accordingly, as already described above, a transmission sequence (encoded sequence (codeword)) vs composed of a 15×2×m×z number of bits in block s of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as vs=(Xs,1,1, Xs,2,1, ..., Xs,13,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,13,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,13,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,13,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T=(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T (where k=1, 2, ..., 2×m×z-1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×z)), and Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes).

[3700] Xs,j,k (where j is an integer no smaller than one and no greater than thirteen) is a bit of information Xj, Ppros,1,k is a bit of parity P1 of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and Ppros,2,k is a bit of parity P2 of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[3701] Further, λpro,s,k=(Xs,1,k, Xs,2,k, Xs,3,k, Xs,4,k, Xs,5,k, Xs,6,k, Xs,7,k, Xs,8,k, Xs,9,k, Xs,10,k, Xs,11,k, Xs,12,k, Xs,13,k, Ppros,1,k, Ppros,2,k) holds true.

[3702] In addition, the number of rows in the parity check matrix Hpro for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is 4×m×z.

[3703] Note that the method of configuring parity check polynomials satisfying zero for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) has already been described above.

[3704] In the above, description has been provided of a parity check matrix Hpro for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), whose transmission sequence (encoded sequence (codeword)) vs of block s is vs=(Xs,1,1, Xs,2,1,...,Xs,13,1, Ppros,1,1, Ppros,2,1, Xs,1,2, Xs,2,2, ..., Xs,13,2, Ppros,1,2, Ppros,2,2, ..., Xs,1,k, Xs,2,k, ..., Xs,13,k, Ppros,1,k, Ppros,2,k, ..., Xs,1,2×m×z, Xs,2,2×m×z, ..., Xs,13,2×m×z, Ppros,1,2×m×z, Ppros,2,2×m×z)T =(λpro,s,1, λpro,s,2, ..., λpro,s,2×m×z-1, λpro,s,2×m×z)T and for which Hprovs=0 holds true (here, Hprovs=0 indicates that all elements of the vector Hprovs are zeroes). The following provides description of a configuration of a parity check matrix Hpro_m for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), for which Hpro_mus=0 holds true (here, Hpro mus=0 indicates that all elements of the vector Hpro_mus are zeroes) when expressing a transmission sequence (encoded sequence (codeword)) us of block s as us=(Xs,1,1, Xs,1,2, ..., Xs,1,2×m×z-1, Xs,1,2×m×z, Xs,2,1, Xs,2,2, ..., Xs,2,2×m×z-1, Xs,2,2×m×z, Xs,3,1, Xs,3,2, ..., Xs,3,2×m×z-1, Xs,3,2×m×z, Xs,4,1, Xs,4,2, ..., Xs,4,2×m×z-1, Xs,4,2×m×z, Xs,5,1, Xs,5,2, ..., Xs,5,2×m×z-1, Xs,5,2×m×z, Xs,6,1, Xs,6,2, ..., Xs,6,2×m×z-1, Xs,6,2×m×z, Xs,7,1, Xs,7,2, ..., Xs,7,2×m×z-1, Xs,7,2×m×z, Xs,8,1, Xs,8,2, ..., Xs,8,2×m×z-1, Xs,8,2×m×z, Xs,9,1, Xs,9,2, ..., Xs,9,2×m×z-1, Xs,9,2×m×z, Xs,10,1, Xs,10,2, ..., Xs,10,2×m×z-1, Xs,10,2×m×z, Xs,11,1, Xs,11,2, ..., Xs,11,2×m×z-1, Xs,11,2×m×z, Xs,12,1, Xs,12,2, ..., Xs,12,2×m×z-1, Xs,12,2×m×z, Xs,13,1, Xs,13,2, ..., Xs,13,2×m×z-1, Xs,13,2×m×z, Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z, Ppros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, Ppros,2,2×m×z)T=(Λx1,s, Λx2,s, ΛX3,s ΛX4,s, ΛX5,s, ΛX6,s, ΛX7,s, ΛX8,s, ΛX9,s, ΛX10,s, ΛX11,s, ΛX12,s, ΛX13,spro1,s, Λpro2,s)T.

[3705] Note that ΛXf,s (where f is an integer no smaller than one and no greater than thirteen) satisfies ΛXf,s=(Xs,f,1, Xs,f,2, Xs,f,3, ..., Xs,f,2×m×z-2, Xs,f,2×m×z-1, Xs,f,2×m×z) (ΛXf,s is a vector having one row and 2×m×z columns), and Λpro1,s and Λpro2,s satisfy Λpro1,s=(Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppr°s,i,2xmxz) and Λpro2,s=(Ppros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, PPros,2,2×m×z), respectively (Λpro1,s and Λpro2,s are both vectors having one row and 2×m×z columns).

[3706] Here, the number of bits of information X1 included in one block is 2×m×z, the number of bits of information X2 included in one block is 2×m×z, the number of bits of information X3 included in one block is 2×m×z, the number of bits of information X4 included in one block is 2×m×z, the number of bits of information X5 included in one block is 2×m×z, the number of bits of information X6 included in one block is 2×m×z, the number of bits of information X7 included in one block is 2×m×z, the number of bits of information X8 included in one block is 2×m×z, the number of bits of information X9 included in one block is 2×m×z, the number of bits of information X10 included in one block is 2×m×z, the number of bits of information X11 included in one block is 2×m×z, the number of bits of information X12 included in one block is 2×m×z, the number of bits of information X13 included in one block is 2×m×z, the number of bits of parity bits P1 included in one block is 2×m×z, and the number of bits of parity bits P2 included in one block is 2×m×z. Accordingly, the parity check matrix Hpro_m for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as Hpro m=[Hx,1, Hx,2, Hx,3, Hx,4, Hx,5, Hx,6, Hx,7, Hx,8, Hx,9, Hx,10, Hx,11, Hx,12, Hx,13, Hp1, Hp2], as illustrated in FIG. 101. Since a transmission sequence (encoded sequence (codeword)) us of block s is us=(Xs,1,1, Xs,1,2, ..., Xs,1,2×m×z-1, Xs,1,2×m×z, Xs,2,1, Xs,2,2, ..., Xs,2,2×m×z-1, Xs,2,2×m×z, Xs,3,1, Xs,3,2, ..., Xs,3,2×m×z-1, Xs,3,2×m×z, Xs,4,1, Xs,4,2, ..., Xs,4,2×m×z-1, Xs,4,2×m×z, Xs,5,1, Xs,5,2, ..., Xs,5,2×m×z-1, Xs,5,2×m×z, Xs,6,1, Xs,6,2, ..., Xs62×m×z-1, Xs,6,2×m×z, Xs,7,1, Xs,7,2, ..., Xs,7,2×m×z-1, Xs,7,2×m×z, Xs,8,1, Xs,8,2, ..., Xs,8,2×m×z-1, Xs,8,2×m×z, Xs,9,1, Xs,9,2, ..., Xs,9,2×m×z-1, Xs,9,2×m×z, Xs,10,1, Xs,10,2, ..., Xs,10,2×m×z-1, Xs,10,2×m×z, Xs,11,1, Xs,11,2, ..., Xs,11,2×m×z-1, Xs,11,2×m×z, Xs,12,1, Xs,12,2, ..., Xs,12,2×m×z-1, Xs,12,2×m×z, Xs,13,1, Xs,13,2, ..., Xs,13,2×m×z-1, Xs,13,2×m×z, Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z, Ppros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, Ppros,2,2×m×z)T=(ΛX1,s, ΛX2,s, ΛX3,s, ΛX4,s, ΛX5,s, ΛX,6s, ΛX7,s, ΛX8,s, ΛX9,s, ΛX10,s, ΛX11,s, ΛX12,s, ΛX13,spro1,s, Λpro2,s)T, Hx,1 is a partial matrix related to information X1, Hx,2 is a partial matrix related to information X2, Hx,3 is a partial matrix related to information X3, Hx,4 is a partial matrix related to information X4, Hx,5 is a partial matrix related to information X5, Hx,6 is a partial matrix related to information X6, Hx,7 is a partial matrix related to information X7, Hx,8 is a partial matrix related to information X8, Hx,9 is a partial matrix related to information X9, Hx,10 is a partial matrix related to information X10, Hx,11 is a partial matrix related to information X11, Hx,12 is a partial matrix related to information X12, Hx,13 is a partial matrix related to information X13, Hp1 is a partial matrix related to parity P1, and Hp2 is a partial matrix related to parity P2. As illustrated in FIG. 101, the parity check matrix Hpro_m has 4×m×z rows and 15×2×m×z columns, the partial matrix Hx,1 related to information X1 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,2 related to information X2 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,3 related to information X3 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,4 related to information X4 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,5 related to information X5 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,6 related to information X6 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,7 related to information X7 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,8 related to information X8 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,9 related to information X9 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,10 related to information X10 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,11 related to information X11 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,12 related to information X12 has 4×m×z rows and 2×m×z columns, the partial matrix Hx,13 related to information X13 has 4×m×z rows and 2×m×z columns, the partial matrix Hp1 related to parity P1 has 4×m×z rows and 2×m×z columns, and the partial matrix Hp2 related to parity P2 has 4×m×z rows and 2×m×z columns.

[3707] The transmission sequence (encoded sequence (codeword)) us composed of a 15×2×m×z number of bits in block s of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is us=(Xs,1,1, Xs,1,2, ..., Xs,1,2×m×z-1, Xs,1,2×m×z, Xs,2,1, Xs,2,2, ..., Xs,2,2×m×z-1, Xs,2,2×m×z, Xs,3,1, Xs,3,2, ..., Xs,3,2×m×z-1, Xs,3,2×m×z, Xs,4,1, Xs,4,2, ..., Xs,4,2×m×z-1, Xs,4,2×m×z, Xs,5,1, Xs,5,2, ..., Xs,5,2×m×z-1, Xs,5,2×m×z, Xs,6,1, Xs,6,2, ..., Xs,6,2×m×z-1, Xs,6,2×m×z, Xs,7,1, Xs,7,2, ..., Xs,7,2×m×z-1, Xs,7,2×m×z, Xs,8,1, Xs,8,2, ..., Xs,8,2×m×z-1, Xs,8,2×m×z, Xs,9,1, Xs,9,2, ..., Xs,9,2×m×z-1, Xs,9,2×m×z, Xs,10,1, Xs,10,2, ..., Xs,10,2×m×z-1, Xs,10,2×m×z, Xs,11,1, Xs,11,2, ..., Xs,11,2×m×z-1, Xs,11,2×m×z, Xs,12,1, Xs,12,2, ..., Xs,12,2×m×z-1, Xs,12,2×m×z, Xs,13,1, Xs,13,2, ..., Xs,13,2×mx×z-1, Xs,13,2×m×z, Ppros,1,1, Ppros,1,2, ..., Ppros,1,2×m×z-1, Ppros,1,2×m×z, PPros,2,1, Ppros,2,2, ..., Ppros,2,2×m×z-1, Ppros,2,2×m×z)T=(ΛX1,s, ΛX2,s, ΛX3,s, ΛX4,s, ΛX5,s, ΛX6,s, ΛX7,s, ΛX8,s, ΛX9,s, ΛX10,s, ΛX11,s, ΛX12,s, ΛX13,spro1,s, Λpro2,s)T, and the number of parity check polynomials satisfying zero necessary for obtaining this transmission sequence is 4×m×z.

[3708] Here, when arranging such 2×(2×m)×z number of parity check polynomials satisfying zero in order, a parity check polynomial satisfying zero appearing eth is referred to in the following as an "eth parity check polynomial satisfying zero" (where e is an integer no smaller than zero and no greater than 2×(2×m)×z-1).

[3709] As such, the parity check polynomials satisfying zero are arranged in the following order:

zeroth: zeroth parity check polynomial satisfying zero;

first: first parity check polynomial satisfying zero;

second: second parity check polynomial satisfying zero;

eth: eth parity check polynomial satisfying zero;

2×(2×m)×z-2th: 2×(2×m)×z-2th parity check polynomial satisfying zero; and

2×(2×m)×z-1th: 2×(2×m)×z-1th parity check polynomial satisfying zero.



[3710] Accordingly, the transmission sequence (encoded sequence (codeword)) us of block s of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is obtained.

[3711] Accordingly, in the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the second parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the third parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression;

the 2×(2m)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression;

the 2×(2m+1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; first expression;

the 2×(2m+1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×(2m+2)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the 2×(2m+2)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression; and

the 2×(2m)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression.



[3712] That is,
the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;
the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;
the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression; and
the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).

[3713] In the present embodiment (in fact, commonly applying to the entirety of the present disclosure), % means a modulo, and for example, α%q represents a remainder after dividing α by q (where α is an integer no smaller than zero, and q is a natural number).

[3714] The following describes details of the configuration of the parity check matrix Hpro_m for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) based on what has been described above.

[3715] The parity check matrix Hpro_m for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) has 4×m×z rows and 15×2×m×z columns.

[3716] Accordingly, the parity check matrix Hpro_m for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) has rows one through 4×m×z, and columns one through 15×2×m×z.

[3717] Here, the topmost row of the parity check matrix Hpro_m is considered as the first row. Further, row number is incremented by one each time moving to a lower row. Accordingly, the topmost row is considered as the first row, the row immediately below the first row is considered as the second row, and the subsequent rows are considered as the third row, the fourth row, and so on.

[3718] Further, the leftmost column of the parity check matrix Hpro_m is considered as the first column. Further, column number is incremented by one each time moving to a rightward column. Accordingly, the leftmost column is considered as the first column, the column immediately to the right of the first column is considered as the second column, and the subsequent columns are considered as the third column, the fourth column, and so on.

[3719] In the parity check matrix Hpro_m, the partial matrix Hx,1 related to information X1 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,1 related to information X1 is denoted as Hx,1,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3720] Similarly, in the parity check matrix Hpro_m, the partial matrix Hx,2 related to information X2 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,2 related to information X2 is denoted as Hx,2,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3721] Further, in the parity check matrix Hpro_m, the partial matrix Hx,3 related to information X3 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,3 related to information X3 is denoted as Hx,3,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3722] Further, in the parity check matrix Hpro_m, the partial matrix Hx,4 related to information X4 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,4 related to information X4 is denoted as Hx,4,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3723] Further, in the parity check matrix Hpro_m, the partial matrix Hx,5 related to information X5 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,5 related to information X5 is denoted as Hx,5,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3724] Further, in the parity check matrix Hpro_m, the partial matrix Hx,6 related to information X6 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,6 related to information X6 is denoted as Hx,6,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3725] Further, in the parity check matrix Hpro_m, the partial matrix Hx,7 related to information X7 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,7 related to information X7 is denoted as Hx,7,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3726] Further, in the parity check matrix Hpro_m, the partial matrix Hx,8 related to information X8 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,8 related to information X8 is denoted as Hx,8,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3727] Further, in the parity check matrix Hpro_m, the partial matrix Hx,9 related to information X9 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,9 related to information X9 is denoted as Hx,9,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3728] Further, in the parity check matrix Hpro_m, the partial matrix Hx,10 related to information X10 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,10 related to information X10 is denoted as Hx,10,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3729] Further, in the parity check matrix Hpro_m, the partial matrix Hx,11 related to information X11 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,11 related to information X11 is denoted as Hx,11,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3730] Further, in the parity check matrix Hpro_m, the partial matrix Hx,12 related to information X12 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,12 related to information X12 is denoted as Hx,12,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3731] Further, in the parity check matrix Hpro_m, the partial matrix Hx,13 related to information X13 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hx,13 related to information X13 is denoted as Hx,13,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3732] Further, in the parity check matrix Hpro_m, the partial matrix Hp,1 related to parity P1 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hp,1 related to parity P1 is denoted as Hp1,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3733] Similarly, in the parity check matrix Hpro_m, the partial matrix Hp,2 related to parity P2 has 4×m×z rows and 2×m×z columns. In the following, an element at row u, column v of the partial matrix Hp,2 related to parity P2 is denoted as Hp2,comp[u][v] (where u is an integer no smaller than one and no greater than 4×m×z, and v is an integer no smaller than one and no greater than 2×m×z).

[3734] The following provides detailed description of the configuration of Hx,1,comp[u][v], Hx,2,comp[u][v], Hx,3,comp[u][v], Hx,4,comp[u][v], Hx,5,comp[u][v], Hx,6,comp[u][v], Hx,7,comp[u][v], Hx,8,comp[u][v], Hx,9,comp[u][v], Hx,10,comp[u][v], Hx,11,comp[u][v], Hx,12,comp[u][v], Hx,13,comp[u][v], Hp1,comp[u][v], and Hp2,comp[u][v].

[3735] As already described above, in the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the second parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the third parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression;

the 2×(2m)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression;

the 2×(2m+1)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; first expression;

the 2×(2m+1)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×(2m+2)-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the 2×(2m+2)-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m-1)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); first expression;

the 2×(2m-1)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-2); second expression;

the 2×(2m)×z-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); first expression; and

the 2×(2m)×z-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m-1); second expression.



[3736] That is,
the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;
the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;
the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression; and
the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).

[3737] Further, a vector composed of row e+1 of the parity check matrix Hpro_m corresponds to the eth parity check polynomial satisfying zero.

[3738] Accordingly,
a vector composed of row one of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;
a vector composed of row two of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0; second expression;
a vector composed of row 2×g-1 of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); first expression; and
a vector composed of row 2×g of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); second expression (where g is an integer no smaller than two and no greater than 2×m×z).

[3739] Hx,1,comp[u][v], Hx,2,comp[u][v], Hx,3,comp[u][v], Hx,4,comp[u][v], Hx,5,comp[u][v], Hx,6,comp[u][v], Hx,7,comp[u][v], Hx,8,comp[u][v], Hx,9,comp[u][v], Hx,10,comp[u][v], Hx,11,comp[u][v], Hx,12,comp[u][v], Hx,13,comp[u][v], Hp1,comp[u][v], and Hp2,comp[u][v] can be expressed according to the relationship described above.

[3740] First, description is provided of the configuration of Hx,1,comp[u][v], Hx,2,comp[u][v], Hx,3,comp[u][v], Hx,4,comp[u][v], Hx,5,comp[u][v], Hx,6,comp[u][v], Hx,7,comp[u][v], Hx,8,comp[u][v], Hx,9,comp[u][v], Hx,10,comp[u][v], Hx,11,comp[u][v], Hx,12,comp[u][v], Hx,13,comp[u][v], Hp1,comp[u][v], and Hp2,comp[u][v] for row one of the parity check matrix Hpro_m, or that is, for u=1.

[3741] The vector composed of row one of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0'; first expression provided by expression 205. Accordingly, Hx,1,comp[u][v] can be expressed as follows.
[Math. 824]



[3742] Considered in a similar manner, the following holds true for Hx,w,comp[1][v], where w is an integer no smaller than one and no greater than six.
[Math. 825]



[3743] Further, Hx,7,comp[1][v] can be expressed as follows.
[Math. 826]





[3744] Considered in a similar manner, the following holds true for HxΩ,comp[1][v]. In the following, Ω is an integer no smaller than seven and no greater than thirteen.
[Math. 827]



[3745] Further, Hp1,comp[1][v] can be expressed as follows.
[Math. 828]



[3746] Further, Hp2,comp[1][v] can be expressed as follows.
[Math. 829]



[3747] The vector composed of row two of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0; second expression. As described above, a parity check polynomial satisfying zero of #0; second expression is expressed by either expression (197-2-1) or expression (197-2-2).

[3748]  Accordingly, Hx,1,comp[2][v] can be expressed as follows.
  1. <1> When a parity check polynomial satisfying zero of #0; second expression is expressed as provided in expression (197-2-1):
    Hx,1,comp[2][v] is expressed as follows.
    [Math. 830]


    Considered in a similar manner, the following holds true for Hx,Ω,comp[2][v], where Ω is an integer no smaller than one and no greater than six.
    [Math. 831]


    Further, Hx,7,comp[2][v] is expressed as follows.
    [Math. 832]




    Considered in a similar manner, the following holds true for Hx,w,comp[2][v], where w is an integer no smaller than seven and no greater than thirteen.
    [Math. 833]


    Further, Hp1,comp[2][v] can be expressed as follows.
    [Math. 834]


    Further, Hp2,comp[2][v] can be expressed as follows.
    [Math. 835]

  2. <2> When a parity check polynomial satisfying zero of #0; second expression is expressed as provided in expression (197-2-2):
    Hx,1,comp[2][v] is expressed as follows.
    [Math. 836]



[3749] Considered in a similar manner, the following holds true for Hx,Ω,comp[2][v], where Ω is an integer no smaller than one and no greater than six.
[Math. 837]



[3750] Further, Hx,7,comp[2][v] is expressed as follows.
[Math. 838]



[3751] Considered in a similar manner, the following holds true for Hx,w,comp[2][v], where w is an integer no smaller than seven and no greater than thirteen.
[Math. 839]





[3752] Further, Hp1,comp[2][v] can be expressed as follows.
[Math. 840]



[3753] Further, Hp2,comp[2][v] can be expressed as follows.
[Math. 841]



[3754] As already described above,
the vector composed of row 2×g-1 of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); first expression; and
the vector composed of row 2×g of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); second expression (where g is an integer no smaller than two and no greater than 2×m×z).

[3755] Accordingly, when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), a vector of row 2×(2×f-1)-1 of the parity check matrix Hpro_m for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); first expression, or that is, by using a parity check polynomial satisfying zero provided by expression (197-1-1) or expression (197-1-2).

[3756] Further, a vector of row 2×(2×f-1) of the parity check matrix Hpro_m for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f-1)-1)%2m); second expression, or that is, by using a parity check polynomial satisfying zero provided by expression (197-2-1) or expression (197-2-2).

[3757] Further, when g=2×f (where f is an integer no smaller than one and no greater than m×z), a vector of row 2×(2×f)-1 of the parity check matrix Hpro_m for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f)-1)%2m); first expression, or that is, by using a parity check polynomial satisfying zero provided by expression (198-1-1) or expression (198-1-2).

[3758] Further, a vector of row 2×(2×f) of the parity check matrix Hpro_m for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated by using a parity check polynomial satisfying zero of #(((2×f)-1)%2m); second expression, or that is, by using a parity check polynomial satisfying zero provided by expression (198-2-1) or expression (198-2-2).

[3759] Accordingly, (1) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (197-1-1), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (197-1-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[3760] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f-1)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f-1)-1][v], Hx,3,comp[2×g-1][v]=Hx,3,comp[2×(2×f-1)-1][v], Hx,4,comp[2×g-1][v]=Hx,4,comp[2×(2×f-1)-1][v], Hx,5,comp[2×g-1][v]=Hx,5,comp[2×(2×f-1)-1][v], Hx,6,comp[2×g-1][v]=Hx,6,comp[2×(2×f-1)-1][v], Hx,7,comp[2×g-1][v]=Hx,7,comp[2×(2×f-1)-1][v], Hx,8,comp[2×g-1][v]=Hx,8,comp[2×(2×f-1)-1][v], Hx,9,comp[2×g-1][v]=Hx,9,comp[2×(2×f-1)-1][v], Hx,10,comp[2×g-1][v]=Hx,10,comp[2×(2×f-1)-1][v], Hx,11,comp[2×g-1][v]=Hx,11,comp[2×(2×f-1)-1][v], Hx,12,comp[2×g-1][v]=Hx,12,comp[2×(2×f-1)-1][v], Hx,13,comp[2×g-1][v]=Hx,13,comp[2×(2×f-1)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f-1)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[3761] First, the following holds true for Hx,1,comp[2×(2×f-1)-1][v].
[Math. 842]



[3762] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f-1)-1][v]. In the following, w is an integer no smaller than one and no greater than six.
[Math. 843]



[3763] Further, the following holds true for Hx,7,comp[2×(2×f-1)-1][v]. In the following, y is an integer no smaller than R#(2c),7+1 and no greater than r#(2c),7.
[Math. 844]



[3764] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f-1)-1][v]. In the following, Ω is an integer no smaller than seven and no greater than thirteen, and y is an integer no smaller than K#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 845]



[3765] Further, the following holds true for Hp1,comp[2×(2×f-1)-1][v].
[Math. 846]



[3766] Further, the following holds true for Hp2,comp[2×(2×f-1)-1][v].
[Math. 847]



[3767] Further, (2) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (197-1-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (197-1-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[3768] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f-1)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f-1)-1][v], Hx,3,comp[2×g-1][v]=Hx,3,comp[2×(2×f-1)-1][v], Hx,4,comp[2×g-1][v]=Hx,4,comp[2×(2×f-1)-1][v], Hx,5,comp[2×g-1][v]=Hx,5,comp[2×(2×f-1)-1][v], Hx,6,comp[2×g-1][v]=Hx,6,comp[2×(2×f-1)-1][v], Hx,7,comp[2×g-1][v]=Hx,7,comp[2×(2×f-1)-1][v], Hx,8,comp[2×g-1][v]=Hx,8,comp[2×(2×f-1)-1][v], Hx,9,comp[2×g-1][v]=Hx,9,comp[2×(2×f-1)-1][v], Hx,10,comp[2×g-1][v]=Hx,10,comp[2×(2×f-1)-1][v], Hx,11,comp[2×g-1][v]=Hx,11,comp[2×(2×f-1)-1][v], Hx,12,comp[2×g-1][v]=Hx,12,comp[2×(2×f-1)-1][v], Hx,13,comp[2×g-1][v]=Hx,13,comp[2×(2×f-1)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f-1)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f-1)-1][v] in row 2×g-1, or that is, row 2×(2×f-1)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[3769] First, the following holds true for Hx,1,comp[2×(2×f-1)-1][v]
[Math. 848]





[3770] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f-1)-1][v]. In the following, w is an integer no smaller than one and no greater than six.
[Math. 849]



[3771] Further, the following holds true for Hx,7,comp[2×(2×f-1)-1][v]. In the following, y is an integer no smaller than R#(2c),7+1 and no greater than r#(2c),7.
[Math. 850]





[3772] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f-1)-1][v]. In the following, Ω is an integer no smaller than seven and no greater than thirteen, and y is an integer no smaller than R#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 851]



[3773] Further, the following holds true for Hp1,comp[2×(2×f-1)-1][v].
[Math. 852]



[3774] Further, the following holds true for Hp2,comp[2×(2×f-1)-1][v].

[Math. 853]

Further, (3) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (197-2-1), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (197-2-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[3775] Accordingly, components Hx,1,comp[2×g][v]=Hx,1,comp[2×(2×f-1)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2×f-1)][v], Hx,3,comp[2×g][v]=Hx,3,comp[2×(2×f-1)][v], Hx,4,comp[2×g][v]=Hx,4,comp[2×(2×f-1)][v], Hx,5,comp[2×g][v]=Hx,5,comp[2×(2×f-1)][v], Hx,6,comp[2×g][v]=Hx,6,comp[2×(2×f-1)][v], Hx,7,comp[2×g][v]=Hx,7,comp[2×(2×f-1)][v], Hx,8,comp[2×g][v]=Hx,8,comp[2×(2×f-1)][v], Hx,9,comp[2×g][v]=Hx,9,comp[2×(2×f-1)][v], Hx,10,comp[2×g][v]=Hx,10,comp[2×(2×f-1)][v], Hx,11,comp[2×g][v]=Hx,11,comp[2×(2×f-1)][v], Hx,12,comp[2×g][v]=Hx,12,comp[2×(2×f-1)][v], Hx,13,comp[2×g][v]=Hx,13,comp[2×(2×f-1)][v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f-1)][v], and Hp2,comp[2×g][v]=Hp2,comp[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[3776] First, the following holds true for Hx,1,comp[2×(2×f-1)][v]. In the following, y is an integer no smaller than R#(2c),1+1 and no greater than r#(2c),1.
[Math. 854]



[3777] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f-1)][v]. In the following, Ω is an integer no smaller than one and no greater than six, and y is an integer no smaller than R#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 855]



[3778] Further, the following holds true for Hx,7,comp[2×(2×f-1)][v].
[Math. 856]



[3779] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f-1)][v]. In the following, w is an integer no smaller than seven and no greater than thirteen.
[Math. 857]





[3780] Further, the following holds true for Hp1,comp[2×(2×f-1)][v].
[Math.858]



[3781] Further, the following holds true for Hp2,comp[2×(2×f-1)][v].
[Math. 859]



[3782] Further, (4) when g=2×f-1 (where f is an integer no smaller than two and no greater than m×z), when a vector for row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (197-2-2), ((2×f-1)-1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (197-2-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m-1).

[3783] Accordingly, components Hx,1,comp[2×g][v]=Hx,1,comp[2×(2×f-1)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2×f-1)][v], Hx,3,comp[2×g][v]=Hx,3,comp[2×(2×f-1[v], Hx,4,comp[2×g][v]=Hx,4,comp[2×(2×f-1)][v], Hx,5,comp[2×g][v]=Hx,5,comp[2×(2×f-1[v], Hx,6,comp[2×g][v]=Hx,6,comp[2×(2×f-1)][v], Hx,7,comp[2×g][v]=Hx,7,comp[2×(2×f-1)][v], Hx,8,comp[2×g][v]=Hx,8,comp[2×(2×f-1)][v], Hx,9,comp[2×g][v]=Hx,9,comp[2×(2×f-1)][v], Hx,10,comp[2×g][v]=Hx,10,comp[2×(2×f-1)][v], Hx,11,comp[2×g][v]=Hx,11,comp[2×(2×f-1)][v], Hx,12,comp[2×g][v]=Hx,12,comp[2×(2×f-1[v], Hx,13,comp[2×g][v]=Hx,13,comp[2×(2×f-1)][v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f-1)][v], and Hp2,comp[2×g][v]=Hp2,comp[2×(2×f-1)][v] in row 2×g, or that is, row 2×(2×f-1) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[3784] First, the following holds true for Hx,1,comp[2×(2×f-1)][v]. In the following, y is an integer no smaller than R#(2c),1+1 and no greater than r#(2c),1.
[Math. 860]



[3785] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f-1)][v]. In the following, Ω is an integer no smaller than one and no greater than six, and y is an integer no smaller than R#(2c),Ω+1 and no greater than r#(2c),Ω.
[Math. 861]





[3786] Further, the following holds true for Hx,7,comp[2×(2×f-1)][v].
[Math. 862]



[3787] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f-1)][v]. In the following, w is an integer no smaller than seven and no greater than thirteen.
[Math. 863]



[3788] Further, the following holds true for Hp1,comp[2×(2×f-1)][v].
[Math.864]



[3789] Further, the following holds true for Hp2,comp[2×(2×f-×)][v].
[Math. 865]



[3790] Further, (5) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (198-1-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (198-1-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[3791] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f)-1][v], Hx,3,comp[2×g-1][v]=Hx,3,comp[2×(2×f)-1][v], Hx,4,comp[2×g-1][v]=Hx,4,comp[2×(2×f)-1][v], Hx,5,comp[2×g-1][v]=Hx,5,comp[2×(2×f)-1][v], Hx,6,comp[2×g-1][v]=Hx,6,comp[2×(2×f)-1][v], Hx,7,comp[2×g-1][v]=Hx,7,comp[2×(2×f)-1][v], Hx,8,comp[2×g-1][v]=Hx,8,comp[2×(2×f)-1][v], Hx,9,comp[2×g-1][v]=Hx,9,comp[2×(2×f)-1][v], Hx,10,comp[2×g-1][v]=Hx,10,comp[2×(2×f)-1][v], Hx,11,comp[2×g-1][v]=Hx,11,comp[2×(2×f)-1][v], Hx,12,comp[2×g-1][v]=Hx,12,comp[2×(2×f)-1][v], Hx,13,comp[2×g-1][v]=Hx,13,comp[2×(2×f)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[3792] First, the following holds true for Hx,1,comp[2×(2×f)-1][v]. In the following, y is an integer no smaller than R#(2d+1),1+1 and no greater than r#(2d+1),1.
[Math. 866]



[3793] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f)-1)][v]. In the following, Ω is an integer no smaller than one and no greater than six, and y is an integer no smaller than R#(2d+1),Ω+1 and no greater than r#(2d+1),Ω.
[Math. 867]



[3794] Further, the following holds true for Hx,7,comp[2×(2×f)-1][v].
[Math. 868]





[3795] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f)-1][v]. In the following, w is an integer no smaller than seven and no greater than thirteen.
[Math. 869]



[3796] Further, the following holds true for Hp1,comp[2×(2×f)-1][v].
[Math. 870]



[3797] Further, the following holds true for Hp2,comp[2×(2×f)-1][v].
[Math. 871]



[3798] Further, (6) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (198-1-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (198-1-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[3799] Accordingly, components Hx,1,comp[2×g-1][v]=Hx,1,comp[2×(2×f)-1][v], Hx,2,comp[2×g-1][v]=Hx,2,comp[2×(2×f)-1][v], Hx,3,comp[2×g-1][v]=Hx,3,comp[2×(2×f)-1][v], Hx,4,comp[2×g-1][v]=Hx,4,comp[2×(2×f)-1][v], Hx,5,comp[2×g-1][v]=Hx,5,comp[2×(2×f)-1][v], Hx,6,comp[2×g-1][v]=Hx,6,comp[2×(2×f)-1][v], Hx,7,comp[2×g-1][v]=Hx,7,comp[2×(2×f)-1][v], Hx,8,comp[2×g-1][v]=Hx,8,comp[2×(2×f)-1][v], Hx,9,comp[2×g-1][v]=Hx,9,comp[2×(2×f)-1][v], Hx,10,comp[2×g-1][v]=Hx,10,comp[2×(2×f)-1][v], Hx,11,comp[2×g-1][v]=Hx,11,comp[2×(2×f)-1][v], Hx,12,comp[2×g-1][v]=Hx,12,comp[2×(2×f)-1][v], Hx,13,comp[2×g-1][v]=Hx,13,comp[2×(2×f)-1][v], Hp1,comp[2×g-1][v]=Hp1,comp[2×(2×f)-1][v], and Hp2,comp[2×g-1][v]=Hp2,comp[2×(2×f)-1][v] in row 2×g-1, or that is, row 2×(2×f)-1 of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[3800] First, the following holds true for Hx,1,comp[2×(2×f)-1][v]. In the following, y is an integer no smaller than R#(2d+1),1+1 and no greater than r#(2d+1),1.
[Math. 872]





[3801] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f)-1)][v]. In the following, Ω is an integer no smaller than one and no greater than six, and y is an integer no smaller than R#(2d+1),Ω+1 and no greater than r#(2d+1),Ω.
[Math. 873]



[3802] Further, the following holds true for Hx,7,comp[2×(2×f)-1][v].
[Math. 874]





[3803] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f)-1][v]. In the following, w is an integer no smaller than seven and no greater than thirteen.
[Math. 875]



[3804] Further, the following holds true for Hp1,comp[2×(2×f)-1][v].
[Math. 876]



[3805] Further, the following holds true for Hp2,comp[2×(2×f)-1][v].
[Math. 877]



[3806] Further, (7) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (198-2-1), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (198-2-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[3807] Accordingly, components Hx,1,comp[2×g][v]=Hx,1,comp[2×(2×f)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2×f)][v], Hx,3,comp[2×g][v]=Hx,3,comp[2×(2×f)][v], Hx,4,comp[2×g][v]=Hx,4,comp[2×(2×f)][v], Hx,5,comp[2×g][v]=Hx,5,comp[2×(2×f)][v], Hx,6,comp[2×g][v]=Hx,6,comp[2×(2×f)][v], Hx,7,comp[2×g][v]=Hx,7,comp[2×(2×f)][v], Hx,8,comp[2×g][v]=Hx,8,comp[2×(2×f)][v], Hx,9,comp[2×g][v]=Hx,9comp[2×(2×f)][v], Hx,10,comp[2×g][v]=Hx,10,comp[2×(2×f)][v], Hx,11,comp[2×g][v]=Hx,11,comp[2×(2×f)][v], Hx,12,comp[2×g][v]=Hx,12,comp[2×(2×f)][v], Hx,13,comp[2×g][v]=Hx,13,comp[2×(2×f)][v], Hp1,comp[2×g][v]=Hp1,comp[2×(2×f)][v], and Hp2,comp[2×g][v]=Hp2,comp[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[3808] The following holds true for Hx,1,comp[2×(2×f)][v].
[Math. 878]



[3809] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f)][v]. In the following, w is an integer no smaller than one and no greater than six.
[Math. 879]



[3810] Further, the following holds true for Hx,7,comp[2×(2×f)][v]. In the following, y is an integer no smaller than R#(2d+i),7+1 and no greater than r#(2d+i),7.
[Math. 880]



[3811] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f)][v]. In the following, Ω is an integer no smaller than seven and no greater than thirteen, and y is an integer no smaller than R#(2d+1),Ω+1 and no greater than r#(2d+1),Ω.
[Math. 881]





[3812] Further, the following holds true for Hp1,comp[2×(2×f)][v].
[Math. 882]



[3813] Further, the following holds true for Hp2,comp[2×(2×f)][v].
[Math. 883]



[3814] Further, (8) when g=2×f (where f is an integer no smaller than one and no greater than m×z), when a vector for row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using a parity check polynomial satisfying zero provided by expression (198-2-2), ((2×f)-1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (198-2-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m-1).

[3815] Accordingly, components Hx,1,comp[2×g][v]=Hx,1,comp[2×(2×f)][v], Hx,2,comp[2×g][v]=Hx,2,comp[2×(2×f)][v], Hx,3,comp[2×g][v]=Hx,3,comp[2×(2×f)][v], Hx,4,comp[2×g][v]=Hx,4,comp[2×(2×f)][v], Hx,5,comp[2×g][v]=Hx,5,comp[2×(2×f)][v], Hx,6,comp[2×g][v]=Hx,6,comp[2×(2×f)][v], Hx,7,comp[2×g][v]=Hx,7,comp[2×(2×f)][v], Hx,8,comp[2×g][v]=Hx,8,comp[2×(2×f)][v], Hx,9,comp[2×g][v]=Hx,9,comp[2×(2×f)][v], Hx,10,comp[2×g][v]=Hx,10,comp[2×(2×f)][v], Hx,22,comp[2×g][v]=Hx,11,comp[2×(2×f)][v], Hx,12,comp[2×g][v]=Hx,12,comp[2×(2×f)][v], Hx,13,comp[2×g][v]=Hx,13,comp[2×(2×f)][v], Hp1,comp[2×g][V]=Hp1,comp[2×(2×f)][v], and Hp2,comp[2×g][v]=Hp2,comp[2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix Hpro_m, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), is expressed as follows.

[3816] The following holds true for Hx,1,comp[2×(2×f)][v].
[Math. 884]



[3817] Considered in a similar manner, the following holds true for Hx,w,comp[2×(2×f)][v]. In the following, w is an integer no smaller than one and no greater than six.
[Math. 885]





[3818] Further, the following holds true for Hx,7,comp[2×(2×f)][v]. In the following, y is an integer no smaller than R#(2d+i),7+1 and no greater than r#(2d+i),7.
[Math. 886]



[3819] Considered in a similar manner, the following holds true for Hx,Ω,comp[2×(2×f)][v]. In the following, Ω is an integer no smaller than seven and no greater than thirteen, and y is an integer no smaller than R#(2d+1)+1 and no greater than r#(2d+1),Ω.
[Math. 887]



[3820] Further, the following holds true for Hp1,comp[2×(2×f)][v].
[Math. 888]



[3821] Further, the following holds true for Hp2,comp[2×(2×f)][v].
[Math. 889]



[3822] An LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be generated as described above, and the code so generated achieves high error correction capability.

[3823] In the above, parity check polynomials satisfying zero for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) are set as follows:

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression; and

the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).



[3824] Based on this, the following method is conceivable as a configuration where usage of parity check polynomials satisfying zero is limited.

[3825] In this configuration, parity check polynomials satisfying zero for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) are set as follows:

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression provided by expression (197-2-1);

the 2×i-2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); first expression provided by expression (197-1-1) or expression (198-1-1); and

the 2×i-1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i-1)%2m); second expression provided by expression (197-2-1) or expression (198-2-1) (where i is an integer no smaller than two and no greater than 2×m×z).



[3826] Accordingly, in the parity check matrix Hpro_m for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the vector composed of row one of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0'; first expression provided by expression 205;

the vector composed of row two of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #0; second expression provided by expression (197-2-1);

the vector composed of row 2×g-1 of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); first expression provided by expression (197-1-1) or expression (198-1-1); and

the vector composed of row 2×g of the parity check matrix Hpro_m is generated by using a parity check polynomial satisfying zero of #((g-1)%2m); second expression provided by expression (197-2-1) or expression (198-2-1) (where g is an integer no smaller than two and no greater than 2×m×z).



[3827] Note that when making such a configuration, the above-described method of configuring the parity check matrix Hpro for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is applicable.

[3828] Such a method also enables generating a code with high error correction capability.

(Embodiment G5)



[3829] In embodiment G4, description is provided of an LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and a method of configuring a parity check matrix for the code.

[3830] With regards to parity check matrices for low density parity check (block) codes, one example of which is the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), a parity check matrix equivalent to a parity check matrix defined for a given LDPC code can be generated by using the parity check matrix defined for the given LDPC code.

[3831] For example, a parity check matrix equivalent to the parity check matrix Hpro_m described in embodiment G4, which is for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), can be generated by using the parity check matrix Hpro_m.

[3832] The following describes a method of generating a parity check matrix equivalent to a parity check matrix defined for a given LDPC by using the parity check matrix defined for the given LDPC code.

[3833] Note that the method of generating an equivalent parity check matrix described in the present embodiment is not only applicable to the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) described in embodiment G4, but also is widely applicable to LDPC codes in general.

[3834] FIG. 31 illustrates the configuration of a parity check matrix H for an LDPC (block) code of coding rate (N-M)/N (N>M>0). For example, the parity check matrix of FIG. 31 has M rows and N columns. Here, to provide a general description, the parity check matrix H in FIG. 31 is considered to be a parity check matrix for defining an LDPC (block) code #A of coding rate (N-M)/N (N>M>0).

[3835] In FIG. 31, a transmission sequence (codeword) for block j is vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) (for systematic codes, Yj,k (where k is an integer no smaller than one and no greater than N) is information X or parity P (parity Ppro)).

[3836] Here, Hvj=0 holds true (where the zero in Hvj=0 indicates that all elements of the vector Hvj are zeroes. That is, row k of the vector Hvj has a value of zero for all k (where k is an integer no smaller than one and no greater than M)).

[3837] Then, an element of row k (where k is an integer no smaller than one and no greater than N) of the transmission sequence vj of block j (in FIG. 31, an element of column k in the transpose matrix vjT of the transmission sequence vj) is Yj,k, and a vector obtained by extracting column k of the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) can be expressed as ck, as illustrated in FIG. 31. Here, the parity check matrix H is expressed as follows.
[Math. 890]



[3838] FIG. 32 illustrates a configuration when interleaving is applied to the transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j. In FIG. 32, an encoding section 3202 receives information 3201 as input, performs encoding thereon, and outputs encoded data 3203. For example, when encoding the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), the encoder 3202 receives information in block j as input, performs encoding thereon based on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), and outputs the transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j.

[3839] Then, an accumulation and reordering section (interleaving section) 3204 receives the encoded data 3203 as input, accumulates the encoded data 3203, performs reordering thereon, and outputs interleaved data 3205. Accordingly, the accumulation and reordering section (interleaving section) 3204 receives the transmission sequence vj=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) T of block j as input, and outputs a transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T, which is illustrated in FIG. 32, as a result of reordering being performed on the elements of the transmission sequence vj (v'j being an example). Here, as discussed above, the transmission sequence v'j is obtained by reordering the elements of the transmission sequence vj of block j. Accordingly, v'j is a vector having one row and n columns, and the N elements of v'j are such that one each of the terms Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N is present.

[3840] Here, an encoding section 3207 as shown in FIG. 32 having the functions of the encoding section 3202 and the accumulation and reordering section (interleaving section) 3204 is considered. Accordingly, the encoding section 3207 receives the information 3201 as input, performs encoding thereon, and outputs the encoded data 3203. For example, the encoding section 3207 receives information in block j as input, and as shown in FIG. 32, outputs the transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T. In the following, explanation is provided of a parity check matrix H' for the LDPC (block) code of coding rate (N-M)/N (N>M>0) corresponding to the encoding section 3207 (i.e., a parity check matrix H' that is equivalent to the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0)), while referring to Fig. 33. (Needless to say, the parity check matrix H' is a parity check matrix for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0).)

[3841] FIG. 33 shows a configuration of the parity check matrix H', which is a parity check matrix equivalent to the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), when the transmission sequence (codeword) is v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T. Here, an element of row one of the transmission sequence v'j of block j (an element of column one in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) is Yj,32. Accordingly, a vector obtained by extracting column one of the parity check matrix H', when using the above-described vector ck (k=1, 2, 3, ..., N-2, N-1, N), is c32. Similarly, an element of row two of the transmission sequence v'j of block j (an element of column two in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) is Yj,99. Accordingly, a vector obtained by extracting column two of the parity check matrix H' is c99. Further, as shown in FIG. 33, a vector obtained by extracting column three of the parity check matrix H' is c23, a vector obtained by extracting column N-2 of the parity check matrix H' is c234, a vector obtained by extracting column N-1 of the parity check matrix H' is c3, and a vector obtained by extracting column N of the parity check matrix H' is c43.

[3842] That is, when denoting an element of row i of the transmission sequence v'j of block j (an element of column i in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) as Yj,g (where g=1, 2, 3, ..., N-1, N-1, N), then a vector obtained by extracting column i of the parity check matrix H' is cg, when using the vector ck described above.

[3843] Accordingly, the parity check matrix H' for transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T is expressed as follows.
[Math. 891]



[3844] When denoting an element of row i of the transmission sequence v'j of block j (an element of column i in the transpose matrix v'jT of the transmission sequence v'j in FIG. 33) as Yj,g (where g=1, 2, 3, ..., N-1, N-1, N), a vector obtained by extracting column i of the parity check matrix H' is cg, when using the vector ck described above. When the above is followed to create a parity check matrix, then a parity check matrix for the transmission sequence v'j of block j can be obtained with no limitation to the above-given example.

[3845] Accordingly, when interleaving is applied to the transmission sequence (codeword) of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), a matrix for the interleaved transmission sequence is obtained by performing reordering of columns (column permutation) as described above on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0).

[3846] As such, it naturally follows that the transmission sequence (codeword) (vj) obtained by reverting the interleaved transmission sequence (codeword) (v'j) to its original order is the transmission sequence (codeword) of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Accordingly, by reverting the interleaved transmission sequence (codeword) (v'j) and a parity check matrix H' corresponding to the interleaved transmission sequence (codeword) (v'j) to their respective orders, the transmission sequence vj and a parity check matrix corresponding to the transmission sequence vj can be obtained, respectively. Further, the parity check matrix obtained by performing the reordering as described above is the parity check matrix H in FIG. 31, description of which has been provided above.

[3847]  FIG. 34 illustrates an example of a decoding-related configuration of a receiving device, when encoding of FIG. 32 has been performed. The transmission sequence obtained when the encoding of FIG. 32 is performed undergoes processing such as mapping in accordance with a modulation scheme, frequency conversion, and modulated signal amplification, whereby a modulated signal is obtained. A transmitting device transmits the modulated signal. The receiving device then receives the modulated signal transmitted by the transmitting device to obtain a received signal. A log-likelihood ratio calculation section 3400 illustrated in FIG. 34 takes the received signal as input, calculates a log-likelihood ratio for each bit of the codeword, and outputs a log-likelihood ratio signal 3401.

[3848] For example, assume that the transmitting device transmits a transmission sequence (codeword) v'j=(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T of block j. Then, the log-likelihood ratio calculation section 3400 calculates, from the received signal, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, and outputs the log-likelihood ratios.

[3849] An accumulation and reordering section (deinterleaving section) 3402 receives the log-likelihood ratio signal 3401 as input, performs accumulation and reordering thereon, and outputs a deinterleaved log-likelihood ratio signal 3403.

[3850] For example, the accumulation and reordering section (deinterleaving section) 3402 receives, as input, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, performs reordering, and outputs the log-likelihood ratios in the order of: the log-likelihood ratio for Yj,1, the log-likelihood ratio for Yj,2, the log-likelihood ratio for Yj,3, ..., the log-likelihood ratio for Yj,N-2, the log-likelihood ratio for Yj,N-1, and the log-likelihood ratio for Yj,N in the stated order.

[3851] A decoder 3404 receives the deinterleaved log-likelihood ratio signal 3403 as input, performs belief propagation (BP) decoding as disclosed in Non-Patent Literature 6 to 8, such as sum-product decoding, min-sum decoding, offset BP decoding, normalized BP decoding, shuffled BP decoding, and layered BP decoding in which scheduling is performed, based on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 31, and thereby obtains an estimation sequence 3405 (note that decoding schemes other than belief propagation decoding may be used).

[3852] For example, the decoder 3404 receives, as input, the log-likelihood ratio for Yj,1, the log-likelihood ratio for Yj,2, the log-likelihood ratio for Yj,3, ..., the log-likelihood ratio for Yj,N-2, the log-likelihood ratio for Yj,N-1, and the log-likelihood ratio for Yj,N in the stated order, performs belief propagation decoding based on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 31, and obtains the estimation sequence (note that decoding schemes other than belief propagation decoding may be used).

[3853] The following describes a decoding-related configuration that differs from that described above. The decoding-related configuration described in the following differs from the decoding-related configuration described above in that the accumulation and reordering section (deinterleaving section) 3402 is not included. The operations of the log-likelihood ratio calculation section 3400 are similar to those described above, and thus, explanation thereof is omitted in the following.

[3854] For example, assume that the transmitting device transmits a transmission sequence (codeword) v'j =(Yj,32, Yj,99, Yj,23, ..., Yj,234, Yj,3, Yj,43)T of block j. Then, the log-likelihood ratio calculation section 3400 calculates, from the received signal, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43, and outputs the log-likelihood ratios (corresponding to 3406 in FIG. 34).

[3855] A decoder 3407 receives the log-likelihood ratio signal 3406 for each bit as input, performs belief propagation (BP) decoding as disclosed in Non-Patent Literature 6 to 8, such as sum-product decoding, min-sum decoding, offset BP decoding, normalized BP decoding, shuffled BP decoding, and layered BP decoding in which scheduling is performed, based on the parity check matrix H' for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 33, and thereby obtains an estimation sequence 3409 (note that decoding schemes other than belief propagation decoding may be used).

[3856] For example, the decoder 3407 receives, as input, the log-likelihood ratio for Yj,32, the log-likelihood ratio for Yj,99, the log-likelihood ratio for Yj,23, ..., the log-likelihood ratio for Yj,234, the log-likelihood ratio for Yj,3, and the log-likelihood ratio for Yj,43 in the stated order, performs belief propagation decoding based on the parity check matrix H' for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 33, and obtains the estimation sequence (note that decoding schemes other than belief propagation decoding may be used).

[3857] As explained above, even when the transmitted data is reordered due to the transmitting device interleaving the transmission sequence vj=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N)T of block j, the receiving device is able to obtain the estimation sequence by using a parity check matrix corresponding to the reordered transmitted data.

[3858] Accordingly, when interleaving is applied to the transmission sequence (codeword) of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0), a parity check matrix for the interleaved transmission sequence (codeword) is obtained by performing reordering of columns (i.e., column permutation) as described above on the parity check matrix for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). As such, the receiving device is able to perform belief propagation decoding and thereby obtain an estimation sequence without performing interleaving on the log-likelihood ratio for each acquired bit.

[3859] Note that in the above, explanation is provided of the relation between interleaving applied to a transmission sequence and a parity check matrix. In the following, explanation is provided of reordering of rows (row permutation) performed on a parity check matrix.

[3860] FIG. 35 illustrates a configuration of a parity check matrix H corresponding to a transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). For example, the parity check matrix H of FIG. 35 is a matrix having M rows and N columns. (for systematic codes, Yj,k (where k is an integer no smaller than one and no greater than N) is information X or parity P (parity Ppro), and is composed of (N-M) information bits and M parity bits). Here, Hvj = 0 holds true. (Here, the zero in Hvj = 0 indicates that all elements of the vector Hvj are zeroes. That is, row k of the vector Hvj has a value of zero for all k (where k is an integer no smaller than one and no greater than M.)

[3861] Further, a vector obtained by extracting column k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) as illustrated in FIG. 35 is denoted as zk. Then, the parity check matrix H for the LDPC (block) code is expressed as follows.
[Math. 892]



[3862] Next, a parity check matrix obtained by performing reordering of rows (row permutation) on the parity check matrix H of FIG. 35 is considered.

[3863] FIG. 36 shows an example of a parity check matrix H' obtained by performing reordering of rows (row permutation) on the parity check matrix H of FIG. 35. The parity check matrix H', similar to the parity check matrix shown in FIG. 35, is a parity check matrix corresponding to the transmission sequence (codeword) vjT=(Yj,1, Yj,2, Yj,3, ..., Yj,N-2, Yj,N-1, Yj,N) of block j of the LDPC (block) code #A of coding rate (N-M)/N (N>M>0).

[3864] The parity check matrix H' of FIG. 36 is composed of vectors zk obtained by extracting row k (where k is an integer no smaller one and no greater than M) of the parity check matrix H of FIG. 35. For example, in the parity check matrix H', the first row is composed of vector z130, the second row is composed of vector z24, the third row is composed of vector z45, ..., the (M-2)th row is composed of vector z33, the (M-1)th row is composed of vector z9, and the Mth row is composed of vector z3. Note that each of the M row-vectors obtained by extracting row k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H' is such that one each of z1, z2, z3, ... zM-2, zM-1, and zM is present.

[3865] Here, the parity check matrix H' for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) is expressed as follows.
[Math. 893]



[3866] Further, H'vj = 0 holds true. (Here, the zero in H'vj = 0 indicates that all elements of the vector H'vj are zeroes. That is, row k of the vector H'vj has a value of zero for all k (where k is an integer no smaller than one and no greater than M.)

[3867] That is, for the transmission sequence vjT of block j, a vector obtained by extracting row i of the parity check matrix H' in FIG. 36 is expressed as ck (where k is an integer no smaller than one and no greater than M), and each of the M row vectors obtained by extracting row k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H' in FIG. 36 is such that one each of z1, z2, z3, ... zM-2, zM-1, and zM is present.

[3868] As described above, for the transmission sequence vjT of block j, a vector obtained by extracting row i of the parity check matrix H' in FIG. 36 is expressed as ck (where k is an integer no smaller than one and no greater than M), and each of the M row vectors obtained by extracting row k (where k is an integer no smaller than one and no greater than M) of the parity check matrix H' in FIG. 36 is such that one each of z1, z2, z3, ... zM-2, zM-1, and zM is present. Note that, when the above is followed to create a parity check matrix, then a parity check matrix for the transmission sequence parity vj of block j can be obtained with no limitation to the above-given example.

[3869] Accordingly, even when the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) is being used, it does not necessarily follow that a transmitting device and a receiving device are using the parity check matrix H. As such, a transmitting device and a receiving device may use as a parity check matrix, for example, a matrix obtained by performing reordering of columns (column permutation) as described above on the parity check matrix H or a matrix obtained by performing reordering of rows (row permutation) on the parity check matrix H.

[3870] In addition, a matrix obtained by performing both reordering of columns (column permutation) and reordering of rows (row permutation) as described above on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) may be used as a parity check matrix.

[3871] In such a case, a parity check matrix H1 is obtained by performing reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H2 is obtained by performing reordering of rows (row permutation) on the parity check matrix H1 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). A transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H2 so obtained.

[3872] Also, a parity check matrix H1,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H2,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix H1,1 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36).

[3873] Further, a parity check matrix H1,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H2,1. Finally, a parity check matrix H2,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H1,2.

[3874] As described above, a parity check matrix H2,s may be obtained by repetitively performing reordering of columns (column permutation) and reordering of rows (row permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H1,k is obtained by performing a kth (where k is an integer no smaller than two and no greater than s) reordering of columns (column permutation) on a parity check matrix H2,k-1. Then, a parity check matrix H2,k is obtained by performing a kth reordering of rows (row permutation) on the parity check matrix H1,k. Note that in the first instance, a parity check matrix H1,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H2,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H1,1.

[3875] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H2,s.

[3876] In an alternative method, a parity check matrix H3 is obtained by performing reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H4 is obtained by performing reordering of columns (column permutation) on the parity check matrix H3 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H4 so obtained.

[3877] Also, a parity check matrix H3,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H4,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix H3,1 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33).

[3878] Then, a parity check matrix H3,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H4,1. Finally, a parity check matrix H4,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H3,2.

[3879] As described above, a parity check matrix H4,s may be obtained by repetitively performing reordering of rows (row permutation) and reordering of columns (column permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H3,k is obtained by performing a kth (where k is an integer no smaller two and no greater than s) reordering of rows (row permutation) on a parity check matrix H4,k-1. Then, a parity check matrix H4,k is obtained by performing a kth reordering of columns (column permutation) on the parity check matrix H3,k. Note that in the first instance, a parity check matrix H3,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H4,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H3,1.

[3880]  In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H4,s.

[3881] Here, note that by performing reordering of rows (row permutation) and reordering of columns (column permutation), the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) can be obtained from each of the parity check matrix H2, the parity check matrix H2,s, the parity check matrix H4, and the parity check matrix H4,s,.

[3882] Similarly, a matrix obtained by performing both reordering of columns (column permutation) as described above and reordering of rows (row permutation) as described above on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) may be used as a parity check matrix.

[3883] In such a case, a parity check matrix H5 is obtained by performing reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H6 is obtained by performing reordering of rows (row permutation) on the parity check matrix H5 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). A transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H6 so obtained.

[3884] Also, a parity check matrix H5,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). Subsequently, a parity check matrix H6,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix H5,1 (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36).

[3885] Further, a parity check matrix H5,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H6,1. Finally, a parity check matrix H6,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H5,2.

[3886] As described above, a parity check matrix H6,s may be obtained by repetitively performing reordering of columns (column permutation) and reordering of rows (row permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H5,k is obtained by performing a kth (where k is an integer no smaller than two and no greater than s) reordering of columns (column permutation) on a parity check matrix H6,k-1. Then, a parity check matrix H6,k is obtained by performing a kth reordering of rows (row permutation) on the parity check matrix H5,k. Note that in the first instance, a parity check matrix H5,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H6,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H5,1.

[3887] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H6,s.

[3888] In an alternative method, a parity check matrix H7 is obtained by performing reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H8 is obtained by performing reordering of columns (column permutation) on the parity check matrix H7 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33). In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H8 so obtained.

[3889] Also, a parity check matrix H7,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) (i.e., through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36). Subsequently, a parity check matrix H8,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix H7,1 (i.e., through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33).

[3890] Then, a parity check matrix H7,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H8,1. Finally, a parity check matrix H8,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H7,2.

[3891] As described above, a parity check matrix H8,s may be obtained by repetitively performing reordering of rows (row permutation) and reordering of columns (column permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H7,k is obtained by performing a kth (where k is an integer no smaller two and no greater than s) reordering of rows (row permutation) on a parity check matrix H8,k-1. Then, a parity check matrix H8,k is obtained by performing a kth reordering of columns (column permutation) on the parity check matrix H7,k. Note that in the first instance, a parity check matrix H7,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0). Then, a parity check matrix H8,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H7,1.

[3892] In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H8,s.

[3893] Here, note that by performing reordering of rows (row permutation) and reordering of columns (column permutation), the parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) can be obtained from each of the parity check matrix H6, the parity check matrix H6,s, the parity check matrix H8, and the parity check matrix H8,s,.

[3894] In the present embodiment, description is provided of a method of generating a parity check matrix equivalent to a parity check matrix H for the LDPC (block) code #A of coding rate (N-M)/N (N>M>0) by performing reordering of rows (row permutation) and/or reordering of columns (column permutation) with respect to the parity check matrix H. Further, description is provided of a method of applying the equivalent parity check matrix in, for example, a communication/broadcast system using an encoder and a decoder using the equivalent parity check matrix. Note that the error correction code described herein may be applied to various fields, including but not limited to communication/broadcast systems.

(Embodiment G6)



[3895] In the present embodiment, description is provided of a device that uses the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), description of which is provided in embodiment G4.

[3896] As one example, description is provided of a case where the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is applied to a communication device.

[3897] Fig. 22 illustrates the structures of a transmitting device 2200 and a receiving device 2210 in the communication device pertaining to the present embodiment.

[3898] An encoder 2201 receives information to be transmitted as input, and is capable of performing various types of encoding (e.g., various coding rates and various block lengths of block codes (for example, in systematic codes, the sum of the number of information bits and the number of parity bits)). In particular, when receiving a specification to perform encoding by using the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), the encoder 2201 performs encoding by using the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) to calculate parities P1 and P2. Further, the encoder 2201 outputs the information to be transmitted and the parities P1 and P2 as a transmission sequence.

[3899]  A modulator 2202 receives the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, performs mapping based on a predetermined modulation scheme (for example, BPSK, QPSK, 16QAM, or 64QAM), and outputs a baseband signal. Further, the modulator 2202 may also receive information other than the transmission sequence, which includes the information to be transmitted and the parities P1 and P2, as input, perform mapping, and output a baseband signal. For example, the modulator 2202 may receive control information as input.

[3900] The transmitting device outputs a transmission signal after performing predetermined signal processing (e.g., signal processing for generation of an OFDM signal, frequency conversion, amplification) with respect to such signals (e.g., baseband signals, pilot signals). The transmitting device may transmit the transmission signal over a wireless transmission path utilizing electromagnetic waves, or over a wired transmission path utilizing a coaxial cable, a power line, an optical cable, or the like.

[3901] The transmission signal is received by the receiving device 2210 after travelling over the transmission path. A receiver 2211 receives a reception signal as input, performs predetermined signal processing (e.g., bandwidth limitation, frequency conversion, signal processing for OFDM, frequency offset estimation, signal detection, channel estimation), and outputs a baseband signal and a channel estimation signal.

[3902] A log-likelihood ratio generation section 2212 receives the baseband signal and the channel estimation signal as input (may receive other signals as input), and for example, calculates and outputs a log-likelihood ratio for each bit (may calculate and output a hard value (hard decision value)).

[3903] A decoder 2213 receives the log-likelihood ratio for each bit as input, performs belief propagation decoding (e.g., sum-product decoding, scheduled sum-product decoding (Layered BP (belief propagation) decoding), min-sum decoding, Normalized BP decoding, offset BP decoding), and outputs an estimation sequence. The decoder 2213 performs the belief propagation decoding based on the parity check matrix for the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[3904] Although description is provided above taking an example where error correction coding is introduced to a communication device, the error correction coding described above is not limited to being introduced to a communication device, and for example, may be introduced to a storage medium (storage). When making such a modification, information that is to be stored to a storage medium (storage) is encoded by using the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and resultant information and parities are stored to the storage medium (storage).

[3905]  Further, the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is applicable to any device that requires error correction coding (e.g., a memory, a hard disk).

[3906] Note that when using a block code such as the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) in a device, there as cases where special processing needs to be executed.

[3907] Assume that a block length of the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) used in a device is 15000 bits (13000 information bits, and 2000 parity bits).

[3908] In such a case, the number of information bits necessary for encoding one block is 13000. Meanwhile, there are cases where the number of bits of information input to an encoding section of the device does not reach 13000. For example, assume a case where only 12000 information bits are input to the encoding section.

[3909] Here, it is assumed that the encoding section, in the above-described case, adds 1000 padding bits of information to the 12000 information bits having been input, and performs encoding by using a total of 13000 bits, composed of the 12000 information bits having been input and the 1000 padding bits, to generate 2000 parity bits. Here, assume that all of the 1000 padding bits are known bits. For example, assume that each of the 1000 padding bits is "0".

[3910] A transmitting device may output the 12000 information bits having been input, the 1000 padding bits, and the 2000 parity bits. Alternatively, a transmitting device may output the 12000 information bits having been input and the 2000 parity bits.

[3911] In addition, a transmitting device may perform puncturing with respect to the 12000 information bits having been input and the 2000 parity bits, and thereby output a number of bits smaller than 14000 in total.

[3912] Note that when performing transmission in such a manner, the transmitting device is required to transmit, to a receiving device, information notifying the receiving device that transmission has been performed in such a manner.

[3913] As described above, the LDPC-CC of coding rate 13/15 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), description of which is provided in embodiment G4, is applicable to various devices.

(Other Matters)



[3914] Needless to say, two or more of the embodiments described in the present disclosure may be combined for implementation.

[Industrial Applicability]



[3915] The encoding method, encoder, and the like pertaining to the present invention achieve high error correction capability, and can thereby secure high data reception quality.

[Reference Signs List]



[3916] 
2200
transmitting device



Claims

1. An encoding method comprising:

generating, by performing encoding of coding rate 2/4 on an information sequence X1 and an information sequence X2, an encoded sequence composed of the information sequence X1, the information sequence X2, a parity sequence P1 and a parity sequence P2, the encoding based on a predetermined parity check matrix of a low density parity check convolutional code, LDPC-CC, using tail-biting,

wherein the predetermined parity check matrix has 4xmxz rows and 4×2×m×z columns with a time-varying period of 2xm formed by 4xm parity check polynomials including

one parity check polynomial satisfying zero provided by expression (165-1-1) or (165-1-2) with i=0 referred to as "#0; first expression", or by expression (173) with i=0 referred to as "#0', first expression"

m-1 parity check polynomials satisfying zero provided by expression (165-1-1) or (165-1-2) referred to as "#(2i); first expression", i= 1, ..., m-1,

m parity check polynomials satisfying zero provided by expression (165-2-1) or (165-2-2) referred to as "#(2i); second expression", i= 0, 1, ..., m-1,

m parity check polynomials satisfying zero provided by expression (166-1-1) or (166-1-2) referred to as "#(2i+1); first expression", i= 0, 1, ..., m-1,

m parity check polynomials satisfying zero provided by expression (166-2-1) or (166-2-2) referred to as "#(2i+1); second expression", i= 0, 1, ..., m-1,

where m is an even number no smaller than two and z is a natural number, wherein

the predetermined parity check matrix is one of a first parity check matrix and a second parity check matrix, the second parity check matrix being generated by performing at least one of row permutation and column permutation on the first parity check matrix,

where the expressions (165-1-1), (165-1-2), (165-2-1), (165-2-2), (166-1-1), (166-1-2), (166-2-1), (166-2-2) and (173) are as follows:







where

p is an integer no smaller than one and no greater than two,

q is an integer no smaller than one and no greater than r#(2i),p,

r#(2i),p is a natural number, Xp(D) is a polynomial expression of the information sequence Xp and Pp(D) is a polynomial expression of the parity sequence Pp, D being a delay operator,

α#(2i),p,q and β#(2i),0 are natural numbers,

β#(2i),1 is a natural number,

β#(2i),2 is an integer no smaller than zero,

β#(2i),3 is a natural number,

R#(2i),p is a natural number,

1≤R#(2i),p<r#(2i),p holds true, and
where

α#(2i),p,y≠α#(2i),p,z holds true for (y, z) where y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and y and z satisfy y≠z;









where

p is an integer no smaller than one and no greater than two,

q is an integer no smaller than one and no greater than r#(2i+1),p,

r#(2i+1),p is a natural number, Xp(D) is a polynomial expression of the information sequence Xp and Pp(D) is a polynomial expression of the parity sequence Pp, D being a delay operator,

α#(2i+1),p,q and β#(2i+1),0 are natural numbers,

β#(2i-1),1 is a natural number,

β#(2i+1),2 is an integer no smaller than zero,

β#(2i+1),3 is a natural number,

R#(2i+1),p is a natural number,

1≤R#(2i+1),p<r#(2i+1),p holds true, and
where

α#(2i+1),p,y≠α#(2i+1),p,z holds true for (y, z) where y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r(#2i+1),p, and y and z satisfy y≠z,



where

the parameters have the same properties as in the formulas above for i = 0,
where

a vector for the first row of the first parity check matrix is generated from the parity check polynomial satisfying zero referred to as #0; first expression or from the parity check polynomial satisfying zero referred to as #0'; first expression; and

a vector for the (2×g-1)th row of the first parity check matrix is generated from the parity check polynomial satisfying zero referred to as #((g-1)%2m); first expression, g = 2, ..., 2×m×z; and

a vector for the (2×g)th row of the first parity check matrix is generated from the parity check polynomial satisfying zero referred to as #((g-1)%2m); second expression, g = 1, 2, ..., 2×m×z.


 
2. A decoding method of decoding an encoded sequence composed of an information sequence X1, an information sequence X2, a parity sequence P1 and a parity sequence P2, comprising:

receiving log-likelihood ratios for each bit of the encoded sequence as input,

performing belief propagation decoding based on a predetermined parity check matrix of a low density parity check convolutional code, LDPC-CC, using tail-biting and having a coding rate 2/4,

outputting an estimation sequence,

wherein the predetermined parity check matrix has 4xmxz rows and 4×2×m×z columns with a time-varying period of 2×m formed by 4×m parity check polynomials including

one parity check polynomial satisfying zero provided by expression (165-1-1) or (165-1-2) with i=0 referred to as "#0; first expression", or by expression (173) with i=0 referred to as "#0', first expression"

m-1 parity check polynomials satisfying zero provided by expression (165-1-1) or (165-1-2) referred to as "#(2i); first expression", i= 1, ..., m-1,

m parity check polynomials satisfying zero provided by expression (165-2-1) or (165-2-2) referred to as "#(2i); second expression", i= 0, 1, ..., m-1,

m parity check polynomials satisfying zero provided by expression (166-1-1) or (166-1-2) referred to as "#(2i+1); first expression", i= 0, 1, ..., m-1,

m parity check polynomials satisfying zero provided by expression (166-2-1) or (166-2-2) referred to as "#(2i+1); second expression", i= 0, 1, ..., m-1,

where m is an even number no smaller than two and z is a natural number,







where

p is an integer no smaller than one and no greater than two,

q is an integer no smaller than one and no greater than r#(2i),p,

r#(2i),p is a natural number, Xp(D) is a polynomial expression of the information sequence Xp and Pp(D) is a polynomial expression of the parity sequence Pp, D being a delay operator,

α#(2i),p,q and β#(2i),0 are natural numbers,

β#(2i),1 is a natural number,

β#(2i),2 is an integer no smaller than zero,

β#(2i),3 is a natural number,

R#(2i),p is a natural number,

1≤R#(2i),p<r#(2i),p holds true, and
where

α#(2i),p,y≠α#(2i),p,z holds true for (y, z) where y is an integer no smaller than one and no greater than r#(2i),p, z is an integer no smaller than one and no greater than r#2i,p, and y and z satisfy y≠z;













where

p is an integer no smaller than one and no greater than two,

q is an integer no smaller than one and no greater than r#(2i+1),p,

r#(2i+1),p is a natural number, Xp(D) is a polynomial expression of the information sequence Xp and Pp(D) is a polynomial expression of the parity sequence Pp, D being a delay operator,

α#(2i+1),p,q and β#(2i+1),0 are natural numbers,

β#(2i+1),1 is a natural number,

β#(2i+1),2 is an integer no smaller than zero,

β#(2i+1),3 is a natural number,

R#(2i+1),p is a natural number,

1≤R#(2i+1),p<r#(2i+1),p holds true, and

where
α#(2i+1),p,y≠α#(2i+1),p,z holds true for (y, z) where y is an integer no smaller than one and no greater than r#(2i+1),p, z is an integer no smaller than one and no greater than r(#2i+1),p, and y and z satisfy y≠z,

where

the parameters have the same properties as in the formulas above for i = 0, where

a vector for the first row of the first parity check matrix is generated from the parity check polynomial satisfying zero referred to as #0; first expression or from the parity check polynomial satisfying zero referred to as #0'; first expression; and

a vector for the (2×g-1)th row of the first parity check matrix is generated from the parity check polynomial satisfying zero referred to as #((g-1)%2m); first expression, g = 2, ..., 2×m×z; and

a vector for the (2×g)th row of the first parity check matrix is generated from the parity check polynomial satisfying zero referred to as #((g-1)%2m); second expression, g = 1, 2, ..., 2×m×z.


 


Ansprüche

1. Ein Codierungsverfahren, umfassend:

erzeugen einer codierten Folge, welche aus der Informationssequenz X1, der Informationssequenz X2, einer Paritätssequenz P1 und einer Paritätssequenz P2 besteht, durch Durchführen von Codieren einer Informationssequenz X1 und einer Informationssequenz X2 bei einer Informationsrate (coding rate) von 2/4, wobei das Codieren auf einer vorbestimmten Paritätskontrollmatrix eines Low Density Parity Check Faltungscode, LDPC-CC, unter Verwendung von tail-biting basiert,

wobei die vorbestimmte Paritätskontrollmatrix 4xmxz Zeilen und 4×2×m×z Spalten mit einer zeitabhängigen Periode von 2xm hat, welche aus 4xm Paritätskontrollpolynomen aufgebaut ist, wobei

ein Paritätskontrollpolynom null genügt gemäß Ausdruck (165-1-1) oder (165-1-2), bezeichnet für i=0 als "#0; erster Ausdruck", oder gemäß Ausdruck (173), bezeichnet für i=0 als "#0', erster Ausdruck",

m-1 Paritätskontrollpolynome null genügen gemäß Ausdruck (165-1-1) oder (165-1-2), bezeichnet als "#(2i); erster Ausdruck", i= 1, ..., m-1

m Paritätskontrollpolynome null genügen gemäß Ausdruck (165-2-1) oder (165-2-2), bezeichnet als "#(2i); zweiter Ausdruck", i= 0, 1, ..., m-1,

m Paritätskontrollpolynome null genügen gemäß Ausdruck (166-1-1) oder (166-1-2), bezeichnet als "#(2i+1); erster Ausdruck ", i= 0, 1, ..., m-1,

m Paritätskontrollpolynome null genügen gemäß Ausdruck (166-2-1) oder (166-2-2), bezeichnet als "#(2i+1); zweiter Ausdruck ", i= 0, 1, ..., m-1,

wobei m eine gerade Zahl nicht kleiner als zwei ist und z eine natürliche Zahl ist, wobei

die vorbestimmte Paritätskontrollmatrix eine einer ersten Paritätskontrollmatrix oder einer zweiten Paritätskontrollmatrix ist, wobei die zweite Paritätskontrollmatrix durch Durchführen mindestens einer Zeilenvertauschung und/oder einer Spaltenvertauschung an der ersten Paritätskontrollmatrix erzeugt wird,

wobei die Ausdrücke (165-1-1), (165-1-2), (165-2-1), (165-2-2), (166-1-1), (166-1-2), (166-2-1), (166-2-2) und (173) wie folgt lauten:







wobei

p ein Integer nicht kleiner als eins und nicht größer als zwei ist,

q ein Integer nicht kleiner als eins und nicht größer als r#(2i),p ist,

r#(2i),p eine natürlich Zahl ist, Xp(D) ein polynomialer Ausdruck der Informationssequenz Xp und Pp(D) eine polynomialer Ausdruck der Paritätssequenz Pp ist, wobei D ein Verzögerungsoperator ist,

α#(2i),p,q und β#(2i),0 natürliche Zahlen sind,

β#(2i),1 eine natürliche Zahl ist,

β#(2i),2 ein Integer nicht kleiner als null ist,

β#(2i),3 eine natürliche Zahl ist,

R#(2i),p eine natürliche Zahl ist,

1≤R#(2i),p<r#(2i),p wahr ist, und
wobei

α#(2i),p,y≠α#(2i),p,z für (y, z) wahr ist, wobei y ein Integer nicht kleiner als eins und nicht größer als r#(2i),p ist, z ein Integer nicht kleiner als eins und nicht größer als r#2i,p ist, und y und z y≠z genügen;









wobei

p ein Integer nicht kleiner als eins und nicht größer als zwei ist,

q ein Integer nicht kleiner als eins und nicht größer als r#(2i+1),p ist,

r#(2i+1),p eine natürlich Zahl ist, Xp(D) ein polynomialer Ausdruck der Informationssequenz Xp und Pp(D) eine polynomialer Ausdruck der Paritätssequenz Pp ist, wobei D ein Verzögerungsoperator ist,

α#(2i+1),p,q und β#(2i+1),0 natürliche Zahlen sind,

β#(2i+1),1 eine natürliche Zahl ist,

β#(2i+1),2 ein Integer nicht kleiner als null ist,

β#(2i+1),3 eine natürliche Zahl ist,

R#(2i+1),p eine natürliche Zahl ist,

1≤R#(2i+1),p<r#(2i+1),p wahr ist, und
wobei

α#(2i+1),p,y≠α#(2i+1),p,z für (y, z) wahr ist, wobei y ein Integer nicht kleiner als eins und nicht größer als r#(2i+1),p ist, z ein Integer nicht kleiner als eins und nicht größer als r(#2i+1),p ist, und y und z y≠z genügen,



wobei

die Parameter die selben Eigenschaften wie in den obigen Formeln für i = 0 haben,
wobei

ein Vektor für die erste Zeile der Paritätskontrollmatrix aus dem Paritätskontrollpolynom erzeugt wird, das null genügt, bezeichnet als #0; erster Ausdruck, oder aus dem Paritätskontrollpolynom, das null genügt, bezeichnet als #0'; erster Ausdruck; und

ein Vektor für die (2×g-1)te Zeile der Paritätskontrollmatrix aus dem Paritätskontrollpolynom erzeugt wird, das null genügt, bezeichnet als #((g-1)%2m); erster Ausdruck, g = 2, ..., 2×m×z; und

ein Vektor für die (2×g)te Zeile der Paritätskontrollmatrix aus dem Paritätskontrollpolynom erzeugt wird, das null genügt, bezeichnet als #((g-1)%2m); zweiter Ausdruck, g = 1, 2, ..., 2×m×z.


 
2. Ein Decodierungsverfahren zur Decodierung einer codierten Sequenz, welche aus einer Informationssequenz X1, der Informationssequenz X2, einer Paritätssequenz P1 und einer Paritätssequenz P2 besteht, umfassend:

empfangen von log-likelihood Verhältnissen für jedes Bit der codierten Sequenz als Eingabe,

durchführen von Belief-Propagation-Decodierung, die auf einer vorbestimmten Paritätskontrollmatrix eines Low Density Parity Check Faltungscode, LDPC-CC, basiert, welcher tail-biting verwendet und eine Informationsrate (coding rate) von 2/4 hat,

ausgeben einer Abschätzungssequenz,

wobei die vorbestimmte Paritätskontrollmatrix 4xmxz Zeilen und 4×2×m×z Spalten mit einer zeitabhängigen Periode von 2xm hat, welche aus 4xm Paritätskontrollpolynomen aufgebaut ist, wobei

ein Paritätskontrollpolynom null genügt gemäß Ausdruck (165-1-1) oder (165-1-2), bezeichnet für i=0 als "#0; erster Ausdruck", oder gemäß Ausdruck (173), bezeichnet für i=0 als "#0', erster Ausdruck",

m-1 Paritätskontrollpolynome null genügen gemäß Ausdruck (165-1-1) oder (165-1-2), bezeichnet als "#(2i); erster Ausdruck", i= 1, ..., m-1

m Paritätskontrollpolynome null genügen gemäß Ausdruck (165-2-1) oder (165-2-2), bezeichnet als "#(2i); zweiter Ausdruck", i= 0, 1, ..., m-1,

m Paritätskontrollpolynome null genügen gemäß Ausdruck (166-1-1) oder (166-1-2), bezeichnet als "#(2i+1); erster Ausdruck ", i= 0, 1, ..., m-1,

m Paritätskontrollpolynome null genügen gemäß Ausdruck (166-2-1) oder (166-2-2), bezeichnet als "#(2i+1); zweiter Ausdruck ", i= 0, 1, ..., m-1,

wobei m eine gerade Zahl nicht kleiner als zwei ist und z eine natürliche Zahl ist,







wobei

p ein Integer nicht kleiner als eins und nicht größer als zwei ist,

q ein Integer nicht kleiner als eins und nicht größer als r#(2i),p ist, r#(2i),p eine natürlich Zahl ist, Xp(D) ein polynomialer Ausdruck der Informationssequenz Xp und Pp(D) eine polynomialer Ausdruck der Paritätssequenz Pp ist, wobei D ein Verzögerungsoperator ist,

α#(2i),p,q und β#(2i),0 natürliche Zahlen sind,

β#(2i),1 eine natürliche Zahl ist,

β#(2i),2 ein Integer nicht kleiner als null ist,

β#(2i),3 eine natürliche Zahl ist,

R#(2i),p eine natürliche Zahl ist,

1≤R#(2i),p<r#(2i),p wahr ist, und
wobei

α#(2i),p,y≠α#(2i),p,z für (y, z) wahr ist, wobei y ein Integer nicht kleiner als eins und nicht größer als r#(2i),p ist, z ein Integer nicht kleiner als eins und nicht größer als r#2i,p ist, und y und z y≠z genügen;











wobei

p ein Integer nicht kleiner als eins und nicht größer als zwei ist,

q ein Integer nicht kleiner als eins und nicht größer als r#(2i+1),p ist,

r#(2i+1),p eine natürlich Zahl ist, Xp(D) ein polynomialer Ausdruck der Informationssequenz Xp und Pp(D) eine polynomialer Ausdruck der Paritätssequenz Pp ist, wobei D ein Verzögerungsoperator ist,

α#(2i+1),p,q und β#(2i+1),0 natürliche Zahlen sind,

β#(2i+1),1 eine natürliche Zahl ist,

β#(2i+1),2 ein Integer nicht kleiner als null ist,

β#(2i+1),3 eine natürliche Zahl ist,

R#(2i+1),p eine natürliche Zahl ist,

1≤R#(2i+1),p<r#(2i+1),p wahr ist, und
wobei

α#(2i+1),p,y≠α#(2i+1),p,z für (y, z) wahr ist, wobei y ein Integer nicht kleiner als eins und nicht größer als r#(2i+1),p ist, z ein Integer nicht kleiner als eins und nicht größer als r(#2i+1),p ist,

und y und z y≠z genügen;



wobei

die Parameter die selben Eigenschaften wie in den obigen Formeln für i = 0 haben,
wobei

ein Vektor für die erste Zeile der Paritätskontrollmatrix aus dem Paritätskontrollpolynom erzeugt wird, das null genügt, bezeichnet als #0; erster Ausdruck, oder aus dem Paritätskontrollpolynom, das null genügt, bezeichnet als #0'; erster Ausdruck; und

ein Vektor für die (2×g-1)te Zeile der Paritätskontrollmatrix aus dem Paritätskontrollpolynom erzeugt wird, das null genügt, bezeichnet als #((g-1)%2m); erster Ausdruck, g = 2, ..., 2×m×z; und

ein Vektor für die (2×g)te Zeile der Paritätskontrollmatrix aus dem Paritätskontrollpolynom erzeugt wird, das null genügt, bezeichnet als #((g-1)%2m); zweiter Ausdruck, g = 1, 2, ..., 2×m×z.


 


Revendications

1. Procédé de codage comprenant :

génération, par exécution d'un codage d'un débit de codage de 2/4 sur une séquence d'informations X1 et une séquence d'informations X2, d'une séquence codée composée de la séquence d'informations X1, la séquence d'informations X2, une séquence de parité P1, et une séquence de parité P2, le codage fondé sur une matrice de contrôle de parité prédéterminée d'un code convolutif à contrôle de parité à faible densité, LDPC-CC (Low-Density Parity-Check Convolutional Code), utilisant une gestion de bits de fin (tail-biting),

dans lequel la matrice de contrôle de parité prédéterminée affiche 4xmxz rangées et 4x2xmxz colonnes avec une période variant dans le temps de 2xm constituée par 4xm polynômes de contrôle de parité incluant

un polynôme de contrôle de parité satisfaisant zéro fourni par une expression (165-1-1) ou (165-1-2) avec i=0 désigné en tant que "#0 ; première expression", ou par une expression (173) avec i=0 désignée en tant que "#0' ; première expression"

m-1 polynômes de contrôle de parité satisfaisant zéro fournis par une expression (165-1-1) ou (165-1-2) désignés en tant que "#(2i) ; première expression", i=1, ..., m-1,

m polynômes de contrôle de parité satisfaisant zéro fournis par une expression (165-2-1) ou (165-2-2) désignés en tant que "#(2i) ; deuxième expression", i=0, 1, ..., 1 m-1,

m polynômes de contrôle de parité satisfaisant zéro fournis par une expression (166-1-1) ou (166-1-2) désignés en tant que "#(2i+1) ; première expression", i=0, 1, ..., m-1,

m polynômes de contrôle de parité satisfaisant zéro fournis par une expression (166-2-1) ou (166-2-2) désignés en tant que "#(2i+1) ; deuxième expression", i=0, 1, ..., m-1,

où m est un nombre pair plus grand que deux et z est un nombre entier naturel, dans lequel

la matrice de contrôle de parité prédéterminée est une d'une première matrice de contrôle de parité et une deuxième matrice de contrôle de parité, la deuxième matrice de contrôle de parité étant générée en effectuant au moins une d'une permutation de rangées et une permutation de colonnes sur la première matrice de contrôle de parité,

où les expressions (165-1-1), (165-1-2), (165-2-1), (165-2-2), (166-1-1), (166-1-2), (166-2-1), (166-2-2) et (173) sont comme suit :







p est un entier plus grand que un et plus petit que deux,

q est n entier plus grand que un et plus petit que Γ#(2i),p,

Γ#(2i),p est un nombre entier naturel, Xp(D) est une expression polynomiale de la séquence d'informations Xp et Pp(D) est une expression polynomiale de la séquence de parité Pp, D étant un opérateur de délai,

α#(2i),p,q et β#(2i),0 sont des nombres entiers naturels,

β#(2i),1 est un nombre entier naturel,

β#(2i),2 est un entier plus grand que zéro,

β#(2i),3 est un nombre entier naturel,

R#(2i),P est un nombre entier naturel,

1≤R#(2i),P#(2i),p se vérifie, et

α#(2i),p,y#(2i),p,z se vérifie pour (y, z) où y est un nombre entier plus grand que un et plus petit que Γ#(2i),p, z est un nombre entier plus grand que un et plus petit que Γ#(2i),p, et y et z satisfont à y≠z ;









p est un entier plus grand que un et plus petit que deux,

q est n entier plus grand que un et plus petit que Γ#(2i+1),p,

Γ#(2i+1),p est un nombre entier naturel, Xp(D) est une expression polynomiale de la séquence d'informations Xp et Pp(D) est une expression polynomiale de la séquence de parité Pp, D étant un opérateur de délai,

α#(2i+1),p,q et β#(2i+1),0 sont des nombres entiers naturels,

β#(2i+1),1 est un nombre entier naturel,

β#(2i+1),2 est un entier plus grand que zéro,

β#(2i+1),3 est un nombre entier naturel,

R#(2i+1),P est un nombre entier naturel,

1≤R(2i+1),P#(2i+1),p se vérifie, et

α#(2i+1),p,y≠α#(2i+1),p,z se vérifie pour (y, z) où y est un nombre entier plus grand que un et plus petit que Γ#(2i+1),p, z est un entier plus grand que un et plus petit que Γ#(2i+1),p, et y et z satisfont à y≠z,



les paramètres ont les mêmes propriétés que dans les formules ci-dessus pour i=0,

un vecteur pour la première rangée de la première matrice de contrôle de parité est généré à partir du polynôme de contrôle de parité satisfaisant zéro désigné comme #0 ; première expression ou à partir du polynôme de contrôle de parité satisfaisant zéro désigné comme #0' ; première expression ; et

un vecteur pour la (2xg-1)ème rangée de la première matrice de contrôle de parité est généré à partir du polynôme de contrôle de parité satisfaisant zéro désigné comme #((g-1)%2m) ; première expression, g=2, ..., 2xmxz ; et

un vecteur pour la (2xg)ème rangée de la première matrice de contrôle de parité est généré à partir du polynôme de contrôle de parité satisfaisant zéro désigné comme #((g-1)%2m) ; deuxième expression, g=1, 2, ..., 2xmxz.


 
2. Procédé de décodage de décodage d'une séquence codée composée d'une séquence d'informations X1, une séquence d'informations X2, une séquence de parité P1 et une séquence de parité P2, comprenant :

réception de rapports de vraisemblance logarithmique pour chaque bit de la séquence codée en tant qu'entrée,

exécution d'un décodage par propagation de croyance selon une matrice de contrôle de parité prédéterminée d'un code convolutif à contrôle de parité à faible densité, LDPC-CC (Low-Density Parity-Check Convolutional Code), utilisant la gestion de bits de fin et présentant un débit de codage de 2/4,

génération en sortie d'une séquence d'estimation,

dans lequel la matrice de contrôle de parité prédéterminée affiche 4xmxz rangées et 4x2xmxz colonnes avec une période variant dans le temps de 2xm constituée par 4xm polynômes de contrôle de parité incluant

un polynôme de contrôle de parité satisfaisant zéro fourni par une expression (165-1-1) ou (165-1-2) avec i=0 désigné en tant que "#0 ; première expression", ou par une expression (173) avec i=0 désignée en tant que "#0' ; première expression"

m-1 polynômes de contrôle de parité satisfaisant zéro fournis par une expression (165-1-1) ou (165-1-2) désignés en tant que "#(2i) ; première expression", i=1, ..., m-1,

m polynômes de contrôle de parité satisfaisant zéro fournis par une expression (165-2-1) ou (165-2-2) désignés en tant que "#(2i) ; deuxième expression", i=0, 1, ..., 1 m-1,

m polynômes de contrôle de parité satisfaisant zéro fournis par une expression (166-1-1) ou (166-1-2) désignés en tant que "#(2i+1) ; première expression", i=0, 1, ..., m-1,

m polynômes de contrôle de parité satisfaisant zéro fournis par une expression (166-2-1) ou (166-2-2) désignés en tant que "#(2i+1) ; deuxième expression", i=0, 1, ..., m-1,

où m est un nombre pair plus grand que deux et z est un nombre entier naturel,







p est un entier plus grand que un et plus petit que deux,

q est n entier plus grand que un et plus petit que Γ#(2i),p,

Γ#(2i),p est un nombre entier naturel, Xp(D) est une expression polynomiale de la séquence d'informations Xp et Pp(D) est une expression polynomiale de la séquence de parité Pp, D étant un opérateur de délai,

α#(2i),p,q et β#(2i),0 sont des nombres entiers naturels,

β#(2i),1 est un nombre entier naturel,

β#(2i),2 est un entier plus grand que zéro,

β#(c2i),3 est un nombre entier naturel,

R#(2i),P est un nombre entier naturel,

1≤R#(2i),P#(2i),p se vérifie, et

α#(2i),p,y≠α#(2i),p,z se vérifie pour (y, z) où y est un nombre entier plus grand que un et plus petit que Γ#(2i),p, z est un entier plus grand que un et plus petit que Γ#(2i),p, et y et z satisfont à y≠z ;











p est un entier plus grand que un et plus petit que deux,

q est n entier plus grand que un et plus petit que Γ#(2i+1),p,

Γ#(2i+1),p est un nombre entier naturel, Xp(D) est une expression polynomiale de la séquence d'informations Xp et Pp(D) est une expression polynomiale de la séquence de parité Pp, D étant un opérateur de délai,

α#(2i+1),p,q et β#(2i+1),0 sont des nombres entiers naturels,

β#(2i+1),0 est un nombre entier naturel,

β#(2i+1),2 est un entier plus grand que zéro,

β#(2i+1),0 est un nombre entier naturel,

R#(2i+1),P est un nombre entier naturel,

1≤R#(2i+1),P#(2i+1),p se vérifie, et

α#(2i+1),p,y≠α#(2i+1),p,z se vérifie pour v(y, z) où y est un nombre entier plus grand que un et plus petit que Γ#(2i+1),p, z est un entier plus grand que un et plus petit que Γ#(2i+1),p, et y et z satisfont à y≠z,



les paramètres ont les mêmes propriétés que dans la formule ci-dessus pour i=0,

un vecteur pour la première rangée de la première matrice de contrôle de parité est généré à partir du polynôme de contrôle de parité satisfaisant zéro désigné comme #0 ; première expression ou à partir du polynôme de contrôle de parité satisfaisant zéro désigné comme #0' ; première expression ; et

un vecteur pour la (2xg-1)ème rangée de la première matrice de contrôle de parité est généré à partir du polynôme de contrôle de parité satisfaisant zéro désigné comme #((g-1)%2m) ; première expression, g=2, ..., 2xmxz ; et

un vecteur pour la (2xg)ème rangée de la première matrice de contrôle de parité est généré à partir du polynôme de contrôle de parité satisfaisant zéro désigné comme #((g-1)%2m) ; deuxième expression, g=1, 2, ..., 2xmxz.


 




Drawing




















































































































































































































































































































Cited references

REFERENCES CITED IN THE DESCRIPTION



This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description




Non-patent literature cited in the description