(19)
(11)EP 2 907 136 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
27.05.2020 Bulletin 2020/22

(21)Application number: 13845261.0

(22)Date of filing:  03.10.2013
(51)Int. Cl.: 
G11C 13/00  (2006.01)
G11C 29/50  (2006.01)
G11C 11/56  (2006.01)
(86)International application number:
PCT/US2013/063194
(87)International publication number:
WO 2014/058695 (17.04.2014 Gazette  2014/16)

(54)

DRIFT ACCELERATION IN RESISTANCE VARIABLE MEMORY

DRIFTBESCHLEUNIGUNG BEI EINEM WIDERSTANDSVERÄNDERLICHEN SPEICHER

ACCÉLÉRATION DE DÉRIVATION DANS UNE MÉMOIRE VARIABLE DE RÉSISTANCE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 09.10.2012 US 201213647527

(43)Date of publication of application:
19.08.2015 Bulletin 2015/34

(73)Proprietor: Micron Technology, Inc.
Boise, ID 83716-9632 (US)

(72)Inventors:
  • CALDERONI, Alessandro
    Boise, Idaho 84706 (US)
  • FERRO, Massimo
    I-26010 Camisano CR (IT)
  • FANTINI, Paolo
    I-20871 Vimercate MB (IT)

(74)Representative: Gill Jennings & Every LLP 
The Broadgate Tower 20 Primrose Street
London EC2A 2ES
London EC2A 2ES (GB)


(56)References cited: : 
US-A1- 2005 231 999
US-A1- 2009 016 099
US-A1- 2010 188 885
US-A1- 2012 014 164
US-A1- 2008 175 035
US-A1- 2009 052 236
US-A1- 2012 014 164
  
  • LIN Y Y ET AL: "A simple new write scheme for low latency operation of phase change memory", VLSI TECHNOLOGY (VLSIT), 2012 SYMPOSIUM ON, IEEE, 12 June 2012 (2012-06-12), pages 51-52, XP032204489, DOI: 10.1109/VLSIT.2012.6242456 ISBN: 978-1-4673-0846-5
  • JING LI ET AL: "Resistance drift in phase change memory", RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2012 IEEE INTERNATIONAL, IEEE, 15 April 2012 (2012-04-15), pages 6C.1.1-6C.1.6, XP032204957, DOI: 10.1109/IRPS.2012.6241871 ISBN: 978-1-4577-1678-2
  • AHN CHIYUI ET AL: "Crystallization properties and their drift dependence in phase-change memory studied with a micro-thermal stage", JOURNAL OF APPLIED PHYSICS, AMERICAN INSTITUTE OF PHYSICS, US, vol. 110, no. 11, 12 December 2011 (2011-12-12), pages 114520-1-114520-6, XP012151747, ISSN: 0021-8979, DOI: 10.1063/1.3667295 [retrieved on 2011-12-12]
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

Technical Field



[0001] The present disclosure relates generally to semiconductor memory apparatuses and methods, and more particularly, to drift acceleration in resistance variable memory.

Background



[0002] Memory devices are typically provided as internal, semiconductor, integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), flash memory, and resistance variable memory, among others. Types of resistance variable memory include programmable conductor memory, phase change random access memory (PCRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM; also referred to as magnetic random access memory), and conductive-bridging random access memory (CBRAM), among others.

[0003] Memory devices can be utilized as volatile and non-volatile memory for a wide range of electronic applications in need of high memory densities, high reliability, and low power consumption. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, solid state drives (SSDs), personal digital assistants (PDAs), digital cameras, cellular telephones, portable music players, e.g., MP3 players, and movie players, among other electronic devices. Data, such as program code, user data, and/or system data, such as a basic input/output system (BIOS), are typically stored in non-volatile memory devices.

[0004] Resistance variable memory such as PCRAM includes resistance variable memory cells that can store data based on the resistance of a storage element, e.g., a storage element having a variable resistance. As such, resistance variable memory cells can be programmed to store data corresponding to a target state by varying the resistance level of the resistance variable storage element. Resistance variable memory cells can be programmed to a target state, e.g., corresponding to a particular resistance, by applying sources of an electrical field or energy, such as positive or negative electrical signals, e.g., positive or negative voltage or current signals, to the cells, e.g., to the storage element of the cells, for a particular time interval.

[0005] One of a number of states, e.g., resistance states, can be set for a resistance variable memory cell. For example, a single level cell (SLC) may be programmed to one of two states, e.g., logic 1 or 0, which can depend on whether the cell is programmed to a resistance above or below a particular level. As an additional example, various resistance variable memory cells can be programmed to one of multiple different states corresponding to multiple data states, e.g., 10, 01, 00, 11, 111, 101, 100, 1010, 1111, 0101, 0001, etc. Such cells may be referred to as multi state cells, multi-digit cells, and/or multilevel cells (MLCs).

[0006] The state of a resistance variable memory cell can be determined, e.g., read, by sensing current through the cell responsive to an applied interrogation voltage. The sensed current, which varies based on the resistance of the cell, can indicate the state of the cell, e.g., the binary data stored by the cell. However, the resistance of a programmed resistance variable memory cell can drift, e.g., shift, over time. Resistance drift can result in erroneous sensing of a resistance variable memory cell, e.g., a determination that the cell is in a state other than that to which it was programmed, among other issues.

[0007] By way of background, reference is made to the following publications:
An article entitled: "A Simple New Write Scheme for Low Latency Operation of Phase Change Memory" by Lin Y et al., VLSI TECHNOLOGY (VLSIT), 2012 SYMPOSIUM ON, IEEE, 12 June 2012 (2012-06-12), pages 51-52, XP032204489, describes the results of an investigation into the behavior of resistance drift after RESET operation for phase change memory (PCRAM). Disclosed is an effective way to accelerate the drift so that the program/read latency may better match that for DRAM for SCM (storage class memory) application by simply applying an extra annealing pulse after RESET. This can quickly anneal out many defects (that are responsible for the drift) and provide a drift-free period that enlarges the read window.

[0008] Another article entitled: "Resistance Drift in Phase Change Memory" by Jing Li et al., RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2012 IEEE INTERNATIONAL, IEEE, 15 April 2012 (2012-04-15), pages 6C. 1.1-6C.1.6, XP032204957, discusses the major reliability issue in MLC PCM, namely time dependent resistance drift in amorphous chalcogenide materials. Starting from experimental observations, this paper presents a complete physical picture for structural relaxation (SR), which is considered to be the underlying mechanism for resistance drift. In particular, various physics models and quantum molecular dynamics simulation are presented to reveal the interrelationship between atomic structure and electrical properties of amorphous chalcogenide materials. The paper provides insights to develop mitigation techniques including material engineering and various design techniques, etc. to ensure reliable MLC operations.

[0009] US 2009/016099 A1 (JEONG CHANG-WOOK ET AL) describes multiple level cell phase-change memory devices having post-programming operation resistance drift saturation.

[0010] US 2012/014164 A1 (KAMOSHIDA MASAHIRO ET AL) describes a resistance-change memory and a method of operating a resistance-change memory.

Summary of the Invention



[0011] The present invention is defined in the appended independent claims 1 and 9. to which reference should be made. Advantageous features are set out in the appended dependent claims 2-8, 10-12.

Brief Description of the Drawings



[0012] 

Figure 1 is a schematic of a portion of an array of resistance variable memory cells that can be operated in accordance with a number of embodiments of the present disclosure.

Figure 2A is a graph illustrating signals associated with operating resistance variable memory cells in accordance with prior approaches.

Figure 2B is a graph illustrating signals associated with operating resistance variable memory cells in accordance with a number of embodiments of the present disclosure.

Figure 3 illustrates example pre-read signals associated with operating resistance variable memory cells in accordance with a number of embodiments of the present disclosure.

Figure 4 is a graph illustrating acceleration of resistance drift in accordance with a number of embodiments of the present disclosure.

Figure 5 illustrates a circuit associated with accelerating drift in accordance with a number of embodiments of the present disclosure.

Figure 6 is an apparatus in the form of a memory device in accordance with a number of embodiments of the present disclosure.


Detailed Description



[0013] The present disclosure includes apparatuses and methods associated drift acceleration in resistance variable memory. A number of embodiments include applying a programming signal to the resistance variable memory cell to program the cell to a target state, subsequently applying a pre-read signal to the resistance variable memory cell to accelerate a drift of a resistance of the programmed cell, and subsequently applying a read signal to the resistance variable memory cell.

[0014] A number of embodiments of the present disclosure can accelerate resistance drift associated with the programmed states of resistance variable memory cells, e.g., phase change memory cells, which can provide improved stabilization of resistance states as compared to previous approaches. For example, a number of embodiments of the present disclosure can accelerate resistance drift via application of a pre-read signal, e.g., a voltage signal, to the programmed cell before readout. The pre-read signal can be a more viable way to accelerate drift as compared to prior approaches such as drift acceleration through temperature, e.g., via an anneal process. As such, embodiments of the present disclosure can provide benefits such as increased accuracy and/or reliability, e.g., decreased error rate, and/or increased memory life, among other benefits.

[0015] In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how a number of embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure.

[0016] As used herein, "a number of' something can refer to one or more such things. For example, a number of memory cells can refer to one or more memory cells. Additionally, the designators "M" and "N" as used herein, particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included with a number of embodiments of the present disclosure.

[0017] The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate the embodiments of the present disclosure, and should not be taken in a limiting sense.

[0018] Figure 1 is a schematic of a portion of an array 100 of resistance variable memory cells that can be operated in accordance with a number of embodiments of the present disclosure. In the embodiment illustrated in Figure 1, the memory array 100 includes a number of memory cells, e.g., phase change memory cells, each having an associated access device 102 and resistance variable element 104, e.g., a phase change material 104. The access devices 102 can be operated, e.g., turned on/off, to select the memory cells in order to perform operations such as data programming and/or data reading operations on the resistance variable elements 104.

[0019] In the embodiment illustrated in Figure 1, the access devices 102 are metal oxide semiconductor field effect transistors (MOSFETs). As shown in Figure 1, a gate of each MOSFET 102 associated with each memory cell is coupled to one of a number of access lines 105-0 (WL0), 105-1 (WL1), ..., 105-N (WLN), i.e., each access line 105-0, 105-1, ..., 105-N is coupled to a row of memory cells, e.g., phase change memory cells. The access lines 105-0, 105-1, . . ., 105-N may be referred to herein as "word lines." The designator "N" is used to indicate that a memory array can include a number of access lines.

[0020] The resistance variable elements 104 can be, for example, a phase change chalcogenide alloy such as an indium(In)-antimony(Sb)-tellurium(Te) (1ST) material, e.g., In2Sb2Te5, In1Sb2Te4, In1Sb4Te7, etc., or a germanium-antimony-tellurium (GST) material, e.g., a Ge-Sb-Te material such as Ge2Sb2Te5, Ge1Sb2Te4, Ge1Sb4Te7, etc. The hyphenated chemical composition notation, as used herein, indicates the elements included in a particular mixture or compound, and is intended to represent all stoichiometries involving the indicated elements. Other phase change materials can include GeTe, In-Se, Sb2Te3, GaSb, InSb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, and Ge-Te-Sn-Pt, among various other phase change materials.

[0021] In the embodiment illustrated in Figure 1, each resistance variable element 104 is coupled to one of a number of sense lines 107-0 (BL0), 107-1 (BL1), ..., 107-M (BLM), i.e., each sense line 107-0, 107-1, ..., 107-M is coupled to a column of memory cells, e.g., phase change memory cells. The sense lines 107-0,107-1, ..., 107-M may be referred to herein as "bit lines." The designator "M" is used to indicate that a memory array can include a number of sense lines. For ease of addressing in the digital environment, the number of access lines 105-1, ..., 105-N and the number of sense lines 107-1, .. ., 107-M can each be some power of two, e.g., 256 access lines by 4,096 sense lines. However, embodiments are not limited to particular numbers of access lines and/or sense lines.

[0022] In operation, appropriate voltage and/or current signals, e.g., pulses, can be applied to the sense lines 107-0, 107-1, ..., 107-M and access lines 105-0, 105-1, ..., 105-N in order to program data to and/or read data from the memory cells of the array 100. As an example, the data stored by a memory cell of array 100 can be determined by turning on an access device 102 and sensing a current passing through the phase change element 104. The current sensed on the bit line associated with the memory cell being read, e.g., bit line 107-0, 107-1, ..., 107-M, corresponds to a resistance level of the resistance variable element, e.g., phase change element, 104, which in turn corresponds to a particular data value, e.g., a binary value such as 1, 0, 001, 111, 101 1, etc.

[0023] Embodiments of the present disclosure are not limited to the example array 100 illustrated in Figure 1. For example, as one of ordinary skill in the art will appreciate, the access device 102 associated with a particular memory cell can be a device other than a MOSFET. In some embodiments, the access device 102 can be a two-terminal access device, e.g., a diode, a three-terminal access device, e.g., a bipolar junction transistor (BJT), among other types of access devices. Also, a memory array can have an architecture other than that illustrated in Figure 1, as will be understood by one of ordinary skill in the art.

[0024] In operation, a phase change memory cell can be programmed to one of a number of states. For example, a single level cell (SLC) may be programmed to a reset state (amorphous state) or a set state (crystalline state). A reset pulse, e.g., a pulse used to program a cell to a reset state, can include a relatively high current pulse applied to the cell for a relatively short period of time such that the phase change material of the cell melts and rapidly cools, resulting in a relatively small amount of crystallization. Conversely, a set pulse, e.g., a pulse used to program a cell to a set state, can include a relatively lower current pulse applied to the cell for a relatively longer time interval and with a slower quenching speed, which results in an increased crystallization of the phase change material. As an example, the reset state may correspond to a stored binary data value of "0" and the set state may correspond to a stored binary data value of "1," for instance. In a number of embodiments, a phase change memory cell can be programmed to one of more than two states. For instance, a multilevel cell (MLC) can be programmed to one of a set state, a reset state, and a number of intermediate states, e.g., a number of states corresponding to a resistance levels between a resistance level corresponding to the set state and the resistance level corresponding to the reset state. As such, an MLC can store multiple binary digits. For instance, a phase change cell programmable to one of four states, e.g., a set state, a reset state, and two intermediate states, can store two binary digits, e.g., 11, 10, 01, and 00.

[0025] Figure 2A is a graph 210 illustrating signals associated with operating resistance variable memory cells in accordance with prior approaches. Graph 210 includes a programming signal, e.g., pulse, 214 and a read signal, e.g., pulse, 216. Programming signal 214 can be applied to a selected cell to program the cell to a target state. Read signal 216 can be applied to a selected cell to read the cell, to determine the state of the cell. The programming signal 214 and the read signal 216 can be current and/or voltage pulses, for instance.

[0026] A memory cell, e.g., a phase change memory cell, operated in accordance with graph 210 can experience resistance drift during the time between application of programming pulse 214 and read pulse 216. That is, the resistance of the programmed cell can shift over time. Such resistance drift can be due to a spontaneous increase of the resistance of the cell after programming, e.g., due to structural relaxation of an amorphous portion of the phase change element, for instance.

[0027] Figure 2B is a graph 218 illustrating signals associated with operating resistance variable memory cells in accordance with a number of embodiments of the present disclosure. Graph 218 includes a programming signal, e.g., pulse, 214, a pre-read signal, e.g., pulse, 222, and a read signal, e.g., pulse 220. Programming signal 214 can be applied to a selected cell to program the cell to a selected state. Read signal 220 can be applied to a selected cell to read the cell, e.g., to determine the state of the cell.

[0028] Pre-read signal 222 can be applied to a selected cell to accelerate a drift of a resistance of a programmed selected cell in accordance with embodiments described herein. A particular pre-read signal 222 can be determined, for instance, based on a target state. The programming signal 214, the pre-read signal 222, and the read signal 216 can be current and/or voltage pulses, for instance. In a number of embodiments, an application of pre-read signal 222 can increase stability of a state of the memory cell, increase a rate of stabilization of a state of the memory cell, and increase accuracy, reliability, and/or memory cell life, among other benefits.

[0029] As described further in connection with Figure 3, application of a pre-read signal, e.g., signal 222, can include applying a current and/or voltage to a memory cell for a particular time interval. In a number of embodiments, a pre-read signal 222 can be applied after an application of a programming signal 216 and/or after each of a number of programming operations performed on a selected cell. A subsequent pre-read signal may be applied to the cell only after performing a subsequent programming operation on the cell, in a number of embodiments. The programming signal, e.g., signal 214, can include, for example, a set signal or a reset signal, among others. A pre-read signal can be applied for a particular time interval, and a read signal can be applied following the pre-read signal application. In a number of embodiments, the pre-read signal can be configured to accelerate drift of resistance through the cell and increase stability of a programmed state of the cell.

[0030] Figure 3 illustrates example pre-read signals associated with operating resistance variable memory cells in accordance with a number of embodiments of the present disclosure. A number of different pre-read signals, e.g., 322-1, 322-2, 322-3, and 322-4, can be utilized to accelerate resistance drift. In the example shown in Figure 3, pre-read signal 322-1 is applied to a selected cell for a time interval 323-1 and has an amplitude equal to that of a read signal 320-1, e.g., vpre-read = vread. In a number of embodiments, applying the pre-read signal for a longer time interval than the read signal may result in accelerated drift and/or increased stability of the programming state, for example. Increasing the pre-read signal time interval, e.g., 323-1, may increase drift acceleration and/or a stability increase regardless of the length of the read signal, in a number of embodiments.

[0031] In the example shown in Figure 3, pre-read signal 322-2 is applied to a selected cell for a time interval 323-2 and has an amplitude less than that of a read signal 320-2, e.g., vpre-read < vread. In this example, pre-read signal 322-3 is applied to a selected cell for a time interval 323-3 and has an amplitude greater than that of a read signal 320-3, e.g., vpre-read > vread. Pre-read signal 322-4 is applied to a selected cell in a number of pre-read pulses, e.g., at least two, at a number of intervals, e.g., time intervals, prior to applying a read signal 320-4. In a number of embodiments, a train of pre-read pulses 322-4 of different amplitudes and time intervals are applied to a selected cell.

[0032] Increasing a pre-read signal amplitude can result in increased drift acceleration and/or a stability increase; however, a pre-read amplitude that is above a threshold may result in increased disturbance, e.g., noise, in the memory cell and/or a programming reset. A decreased pre-read amplitude may result in a decreased drift acceleration. Application of a number of pre-read pulses can accelerate resistance drift, and the application can be stopped at a desired point of operation. For example, if it is desired to perform an action on the array, the application of the pre-read pulse can be stopped, the action can be performed, and the application can be restarted.

[0033] An amplitude of the pre-read signal applied can affect the rate of acceleration of drift in a number of embodiments. For example, a portion of a pre-read signal having a particular amplitude can be applied to the cell, and a different portion of the pre-read signal having a different amplitude can be applied to the cell. Each portion can be configured to accelerate the drift of the resistance of the cell at a different rate than one another. For example, a higher amplitude pre-read signal may result in an increased drift acceleration as compared to a lower amplitude pre-read signal. A time interval for which the pre-read signal is applied to the cell can be adjusted. Increasing a time interval of a pre-read signal application may result in an increased drift acceleration, for example.

[0034] The read signal can be applied to the cell after some period of time following application of the pre-read signal, for example. The read signal application can be shifted in time to allow for actions to be performed on the cell and/or the array, for example. A number of pre-read signals can be applied before the read signal in a number of embodiments.

[0035] In a number of examples, the method including drift acceleration in resistance variable memory can be performed during a wafer testing process. The method including drift acceleration in resistance variable memory can include testing the memory cell, in a number of embodiments. For example, a programming signal can be applied to the memory cell, and a pre-read signal can be applied to the memory cell. The memory cell can be tested, e.g., following the pre-read signal application, and a read signal can be applied to the memory cell.

[0036] Figure 4 is a graph 425 illustrating acceleration of resistance drift in accordance with a number of embodiments of the present disclosure. The graph 425 illustrates read current (nA) versus time (s) for a number of programmed phase change memory cells. As indicated by curves 424 and 426, the read current associated with a programmed memory cell drifts, e.g., decreases, over time. A log-log scale is used for graph 425 to highlight the empirical power law of the read current decrease, e.g., increased resistance, with time:

where I0 is the resistance at a reference time t0 and v is the drift exponent. As an example, v can be about 0.1 at room temperature for a cell programmed to a full reset, e.g., fully amorphous, state. The curve 424 represents an average current decrease associated with a number of cells that do not receive a pre-read signal in accordance with embodiments described herein. For instance, curve 424 represents programmed cells receiving an applied bias voltage pulse only when the cell is being read, e.g., only at read time as shown at 444.

[0037] The curve 426 represents an average current decrease associated with a number of cells that receive an applied pre-read signal in accordance with embodiments described herein. In this example, curve 426 represents programmed cells receiving a constant applied bias voltage over a particular time interval with the cells being read after application of the pre-read signal, e.g., as shown at 442.

[0038] As illustrated in Figure 4, curve 426 decreases more rapidly than curve 424. That is, the drift exponent (v) corresponding to curve 426, e.g., 0.105, is larger than the drift exponent corresponding to curve 424, e.g., 0.065. As such, curve 426 represents about a 40% increase in the drift exponent (v) as compared to curve 424, which corresponds to an accelerated read current drift, e.g., increased resistance drift, associated with curve 426. The increased v associated with curve 426 can be due to an electric field induced structural relaxation enhancement associated with the constant applied bias voltage applied subsequent to programming the cells and prior to reading the cells. The accelerated drift, e.g., increased v, associated with curve 426 can be similar to drift acceleration due to an annealing process performed on the cells. Therefore, a number of embodiments of the present disclosure can result in an increased drift acceleration without performing an anneal process to induce structural relaxation, for instance.

[0039] Figure 5 illustrates a circuit 530 associated with accelerating drift in accordance with a number of embodiments of the present disclosure. Memory cell 532 can be a resistance variable memory cell, e.g., phase change memory cell. The circuit 530 includes a switch 540 operable to selectively couple the memory cell to a program signal 534 (PGM), a pre-read signal 536 (PRE-READ), and a read signal 538 (READ). The pre-read signal 536 can be a pre-read signal such as those described in association with Figures 2B and 3, for instance.

[0040] Figure 6 is an apparatus in the form of a memory device 650 in accordance with a number of embodiments of the present disclosure. As used herein, an "apparatus" can refer to, but is not limited to, any of a variety of structures or combinations of structures, such as a circuit or circuitry, a die or dice, a module or modules, a device or devices, or a system or systems, for example.

[0041] As shown in Figure 6, memory device 650 includes a controller 652 coupled to a memory array 600. Memory array 600 can be, for example, memory array 100 previously described in connection with Figure 1 Although one memory array is shown in Figure 6, embodiments of the present disclosure are not so limited (e.g., memory device 650 can include more than one memory array coupled to controller 652).

[0042] Controller 652 can include, for example, control circuitry and/or firmware. For instance, controller 652 can include circuitry 630, as illustrated in Figure 6. Controller 652 can be included on the same physical device (e.g., the same die) as memory array 600, or can be included on a separate physical device that is communicatively coupled to the physical device that includes memory array 600. In a number of embodiments, components of controller 652 can be spread across multiple physical devices (e.g., some components on the same die as the array, and some components on a different die, module, or board).

[0043] Circuitry 630 can perform operations in accordance with a number of embodiments of the present disclosure to determine the state of the memory cells in memory array 600. For example, circuitry 630 can be, for example, circuit 530 previously described in connection with Figure 5.

[0044] The embodiment illustrated in Figure 6 can include additional circuitry that is not illustrated so as not to obscure embodiments of the present disclosure. For example, memory device 630 can include address circuitry to latch address signals provided over I/O connectors through I/O circuitry. Address signals can be received and decoded by a row decoder and a column decoder, to access memory array 600.

Conclusion



[0045] The present disclosure includes apparatuses and methods of operating a multilevel phase change memory cell of an array of multilevel phase change memory cells as set forth in the claims, .


Claims

1. A method of operating a multilevel phase change memory cell (532) of an array (100, 600) of phase change memory cells, each multilevel phase change memory cell being configured to be programmable to one of a set state, a reset state, and a number of intermediate states, the method further comprising:

a programming operation of applying a programming signal (214) to the multilevel phase change memory cell (532) to program the multilevel phase change memory cell (532) to a target state;

a subsequent intermediate operation of applying a pre-read signal (222; 322-1; 322-2; 322-3; 322-4) determined based on the target state to the programmed multilevel phase change memory cell (532) to accelerate a drift of a resistance of the programmed multilevel phase change memory cell (425) without performing an anneal process; and

a reading operation subsequent to the intermediate operation, of applying a read signal (220; 320-1; 320-2; 320-3; 320-4) to the multilevel phase change memory cell (532) after a time interval (323-1; 323-2; 323-3) following application of the pre-read signal (222; 322-1; 322-2; 322-3; 322-4).


 
2. The method of claim 1, wherein applying the pre-read signal (222; 322-1; 322-2; 322-3; 322-4) comprises applying a pre-read signal (322-1) having an amplitude that is equivalent to an amplitude of the read signal (320-1).
 
3. The method of claim 2, including applying the pre-read signal (222; 322-1; 322-2; 322-3; 322-4) to the programmed multilevel phase change memory cell (532) for a longer time interval than a time interval over which the read signal (220; 320-1; 320-2; 320-3; 320-4) is applied to the cell.
 
4. The method of claim 1, wherein applying the pre-read signal (222; 322-1; 322-2; 322-3; 322-4) comprises applying a pre-read signal (322-2) having an amplitude that is less than an amplitude of the read signal (320-2).
 
5. The method of claim 1, wherein applying the pre-read signal (222; 322-1; 322-2; 322-3; 322-4) comprises applying a pre-read signal (322-3) having an amplitude that is greater than an amplitude of the read signal (320-3).
 
6. The method of any one of claims 1 to 2, wherein applying the pre-read signal (222; 322-1; 322-2; 322-3; 322-4) includes applying at least two pre-read signal pulses (322-4).
 
7. The method of any one of claims 1 to 2, wherein applying the pre-read signal (222; 322-1; 322-2; 322-3; 322-4) includes:

applying a first portion of the pre-read signal to the programmed multilevel phase change memory cell, the first portion having a first amplitude (222; 322-1; 322-2; 322-3; 322-4); and

applying a second portion of the pre-read signal to the programmed multilevel phase change memory cell, the second portion having a second amplitude (222; 322-1; 322-2; 322-3; 322-4);

wherein the first portion is configured to accelerate the drift of the resistance at a different rate than a rate at which the second portion is configured to accelerate the drift of the resistance (222; 322-1; 322-2; 322-3; 322-4).


 
8. The method of any one of claims 1 to 2, wherein the method includes applying a subsequent pre-read signal (222) to the programmed multilevel phase change memory cell (532) only after performing a subsequent programming operation on the cell (532).
 
9. An apparatus (650), comprising:

an array (100; 600) of multilevel phase change memory cells, wherein each multilevel phase change memory cell is programmable to one of a set state, a reset state, and a number of intermediate states; and

a controller (652) coupled to the array (100; 600) and configured to control:

a programming operation of programming, by a programming signal (214), a multilevel phase change memory cell (532) of the array, to a target state (214);

a subsequent intermediate operation of applying a pre-read signal (222; 322-1; 322-2; 322-3; 322-4) to the programmed multilevel phase change memory cell, wherein the pre-read signal (222; 322-1; 322-2; 322-3; 322-4) is determined based on the target state, and configured to accelerate drift of a resistance (425) of the programmed multilevel phase change memory cell (532) without performing an anneal process; and

a reading operation, subsequent to the intermediate operation, of applying a read signal (220; 320-1; 320-2; 320-3; 320-4) to the programmed multilevel phase change memory cell (532)_after a time interval (323-1; 323-2; 323-3) following application of the pre-read signal (222; 322-1; 322-2; 322-3; 322-4).


 
10. The apparatus (650) of claim 9, wherein the controller (650) is configured to control applying the pre-read signal (222; 322-1; 322-2; 322-3; 322-4) to the programmed multilevel phase change memory cell (532) for a particular time interval (323-1; 323-2; 323-3).
 
11. The apparatus (650) of claim 9, wherein the apparatus includes a circuit (530; 630) coupled to the array (100; 600) and configured to:

selectively apply a programming signal (214; 534) to the multilevel phase change memory cell (532) during programming;

selectively apply the pre-read signal (222; 322-1; 322-2; 322-3; 322-4; 536) to the programmed multilevel phase change memory cell (532); and

selectively apply a read signal (220; 320-1; 320-2; 320-3; 320-4; 538) to the programmed multilevel phase change memory cell (532) during reading.


 
12. The apparatus (650) of claim 11, wherein the circuit (530; 630) comprises a switch (540) operable to selectively apply the programming signal (534), the pre-read signal (536), and the read signal (538) to the multilevel phase change memory cell (532).
 


Ansprüche

1. Verfahren zum Betreiben einer mehrstufigen Phasenänderungs-Speicherzelle (532) eines Arrays (100, 600) von Phasenänderungs-Speicherzellen, wobei jede mehrstufige Phasenänderungs-Speicherzelle so konfiguriert ist, dass sie entweder auf einen festgelegten Zustand, einen Rücksetzzustand oder eine Anzahl von Zwischenzuständen programmierbar ist, wobei das Verfahren ferner Folgendes umfasst:

eine Programmieroperation zum Anlegen eines Programmiersignals (214) an die mehrstufige Phasenänderungs-Speicherzelle (532), um die mehrstufige Phasenänderungs-Speicherzelle (532) auf einen Zielzustand zu programmieren;

eine anschließende Zwischenoperation zum Anlegen eines auf der Grundlage des Zielzustands bestimmten Vor-Lesesignals (222; 322-1; 322-2; 322-3; 322-4) an die programmierte mehrstufige Phasenänderungs-Speicherzelle (532), um eine Drift eines Widerstands der programmierten mehrstufigen Phasenänderungs-Speicherzelle (425) zu beschleunigen, ohne einen Glühvorgang durchzuführen; und

eine auf die Zwischenoperation folgende Leseoperation zum Anlegen eines Lesesignals (220; 320-1; 320-2; 320-3; 320-4) an die mehrstufige Phasenänderungs-Speicherzelle (532) nach einem Zeitintervall (323-1; 323-2; 323-3) nach dem Anlegen des Vor-Lesesignals (222; 322-1; 322-2; 322-3; 322-4).


 
2. Verfahren nach Anspruch 1, wobei das Anlegen des Vor-Lesesignals (222; 322-1; 322-2; 322-3; 322-4) das Anlegen eines Vor-Lesesignals (322-1) mit einer Amplitude umfasst, die einer Amplitude des Lesesignals (320-1) entspricht.
 
3. Verfahren nach Anspruch 2, einschließlich des Anlegens des Vor-Lesesignals (222; 322-1; 322-2; 322-3; 322-4) an die programmierte mehrstufige Phasenänderungs-Speicherzelle (532) für ein längeres Zeitintervall als ein Zeitintervall, über das das Lesesignal (220; 320-1; 320-2; 320-3; 320-4) an die Zelle angelegt wird.
 
4. Verfahren nach Anspruch 1, wobei das Anlegen des Vor-Lesesignals (222; 322-1; 322-2; 322-3; 322-4) das Anlegen eines Vor-Lesesignals (322-2) mit einer Amplitude umfasst, die kleiner als eine Amplitude des Lesesignals (320-2) ist.
 
5. Verfahren nach Anspruch 1, wobei das Anlegen des Vor-Lesesignals (222; 322-1; 322-2; 322-3; 322-4) das Anlegen eines Vor-Lesesignals (322-3) mit einer Amplitude umfasst, die größer als eine Amplitude des Lesesignals (320-3) ist.
 
6. Verfahren nach einem der Ansprüche 1 bis 2, wobei das Anlegen des Vor-Lesesignals (222; 322-1; 322-2; 322-3; 322-4) das Anlegen von mindestens zwei Vor-Lesesignalimpulsen (322-4) umfasst.
 
7. Verfahren nach einem der Ansprüche 1 bis 2, wobei das Anlegen des Vor-Lesesignals (222; 322-1; 322-2; 322-3; 322-4) Folgendes umfasst:

Anlegen eines ersten Teils des Vor-Lesesignals an die programmierte mehrstufige Phasenänderungs-Speicherzelle, wobei der erste Teil eine erste Amplitude (222; 322-1; 322-2; 322-3; 322-4) aufweist; und

Anlegen eines zweiten Teils des Vor-Lesesignals an die programmierte mehrstufige Phasenänderungs-Speicherzelle, wobei der zweite Teil eine zweite Amplitude (222; 322-1; 322-2; 322-3; 322-4) aufweist;

wobei der erste Teil konfiguriert ist, um die Drift des Widerstandes mit einer anderen Rate zu beschleunigen als eine Rate, bei der der zweite Teil konfiguriert ist, um die Drift des Widerstandes zu beschleunigen (222; 322-1; 322-2; 322-3; 322-4).


 
8. Verfahren nach einem der Ansprüche 1 bis 2, wobei das Verfahren das Anlegen eines nachfolgenden Vor-Lesesignals (222) an die programmierte mehrstufige Phasenänderungs-Speicherzelle (532) erst nach Durchführung einer nachfolgenden Programmieroperation an der Zelle (532) umfasst.
 
9. Vorrichtung (650), umfassend:

ein Array (100; 600) von mehrstufigen Phasenänderungs-Speicherzellen, wobei jede mehrstufige Phasenänderungs-Speicherzelle auf einen von einem festgelegten Zustand, einem Rücksetzzustand und einer Anzahl von Zwischenzuständen programmierbar ist; und

eine Steuerung (652), die mit dem Array (100; 600) gekoppelt und zur Steuerung von Folgendem konfiguriert ist:

eine Programmieroperation zum Programmieren, durch ein Programmiersignal (214), einer mehrstufigen Phasenänderungs-Speicherzelle (532) des Arrays auf einen Zielzustand (214);

eine anschließende Zwischenoperation zum Anlegen eines Vor-Lesesignals (222; 322-1; 322-2; 322-3; 322-4) an die programmierte mehrstufige Phasenänderungs-Speicherzelle, wobei das Vor-Lesesignal (222; 322-1; 322-2; 322-3; 322-4) auf der Grundlage des Zielzustandes bestimmt wird und konfiguriert ist, um die Drift eines Widerstandes (425) der programmierten mehrstufigen Phasenänderungs-Speicherzelle (532) zu beschleunigen, ohne einen Glühvorgang durchzuführen; und

eine auf die Zwischenoperation folgende Leseoperation zum Anlegen eines Lesesignals (220; 320-1; 320-2; 320-3; 320-4) an die programmierte mehrstufige Phasenänderungs-Speicherzelle (532) nach einem Zeitintervall (323-1; 323-2; 323-3) nach Anlegen des Vor-Lesesignals (222; 322-1; 322-2; 322-3; 322-4).


 
10. Vorrichtung (650) nach Anspruch 9, wobei die Steuerung (650) so konfiguriert ist, dass sie das Anlegen des Vor-Lesesignals (222; 322-1; 322-2; 322-3; 322-4) an die programmierte mehrstufige Phasenänderungs-Speicherzelle (532) für ein bestimmtes Zeitintervall (323-1; 323-2; 323-3) steuert.
 
11. Vorrichtung (650) nach Anspruch 9, wobei die Vorrichtung eine Schaltung (530; 630) umfasst, die mit dem Array (100; 600) gekoppelt und wie folgt konfiguriert ist:

Selektives Anlegen eines Programmiersignals (214; 534) an die mehrstufige Phasenänderungs-Speicherzelle (532) während des Programmiervorgangs;

Selektives Anlegen des Vor-Lesesignals (222; 322-1; 322-2; 322-3; 322-4; 536) an die programmierte mehrstufige Phasenänderungs-Speicherzelle (532); und

Selektives Anlegen eines Lesesignals (220; 320-1; 320-2; 320-3; 320-4; 538) an die programmierte mehrstufige Phasenänderungs-Speicherzelle (532) während des Lesevorgangs.


 
12. Vorrichtung (650) nach Anspruch 11, wobei die Schaltung (530; 630) einen Schalter (540) umfasst, der so betätigt werden kann, dass das Programmiersignal (534), das Vor-Lesesignal (536) und das Lesesignal (538) selektiv an die mehrstufige Phasenänderungs-Speicherzelle (532) angelegt werden.
 


Revendications

1. Procédé de fonctionnement d'une cellule de mémoire à changement de phase multiniveaux (532) d'un réseau (100, 600) de cellules de mémoire à changement de phase, chaque cellule de mémoire à changement de phase multiniveau étant configurée pour être programmable dans l'un d'un état défini, d'un état de réinitialisation, et d'un certain nombre d'états intermédiaires, le procédé comprenant en outre :

une opération de programmation destinée à appliquer un signal de programmation (214) à la cellule de mémoire à changement de phase multiniveaux (532) pour programmer la cellule de mémoire à changement de phase multiniveaux (532) à un état cible ;

une opération intermédiaire consécutive destinée à appliquer un signal de pré-lecture (222 ; 322-1 ; 322-2 ; 322-3 ; 322-4) déterminé en fonction de l'état cible à la cellule de mémoire de changement de phase multiniveaux (532) pour accélérer une dérive d'une résistance de la cellule de mémoire à changement de phase multiniveaux programmée (425) sans effectuer un processus de recuit ; et

une opération de lecture consécutive à l'opération intermédiaire, destinée à appliquer un signal de lecture (220 ; 320-1 ; 320-2 ; 320-3 ; 320-4) à la cellule de mémoire à changement de phase multiniveau (532) après un intervalle de temps (323-1 ; 323-2 ; 323-3) après application du signal de pré-lecture (222 ; 322-1 ; 322-2 ; 322-3 ; 322-4).


 
2. Procédé selon la revendication 1, dans lequel l'application du signal de pré-lecture (222 ; 322-1 ; 322-2 ; 322-3 ; 322-4) comprend l'application d'un signal de pré-lecture (322-1) ayant une amplitude équivalente à une amplitude du signal de lecture (320-1).
 
3. Procédé selon la revendication 2, comportant l'application du signal de pré-lecture (222 ; 322-1 ; 322-2 ; 322-3 ; 322-4) à la cellule de mémoire à changement de phase multiniveaux programmée (532) pendant un intervalle de temps plus long qu'un intervalle de temps pendant lequel le signal de lecture (220 ; 320-1 ; 320-2 ; 320-3 ; 320-4) est appliqué à la cellule.
 
4. Procédé selon la revendication 1, dans lequel l'application du signal de pré-lecture (222 ; 322-1 ; 322-2 ; 322-3 ; 322-4) comprend l'application d'un signal de pré-lecture (322-2) ayant une amplitude qui est inférieure à une amplitude du signal de lecture (320-2).
 
5. Procédé selon la revendication 1, dans lequel l'application du signal de pré-lecture (222 ; 322-1 ; 322-2 ; 322-3 ; 322-4) comprend l'application d'un signal de pré-lecture (322-3) ayant une amplitude supérieure à une amplitude du signal de lecture (320-3).
 
6. Procédé selon l'une quelconque des revendications 1 à 2, dans lequel l'application du signal de pré-lecture (222 ; 322-1 ; 322-2 ; 322-3 ; 322-4) comporte l'application d'au moins deux impulsions de signal de pré-lecture (322-4).
 
7. Procédé selon l'une quelconque des revendications 1 à 2, dans lequel l'application du signal de pré-lecture (222 ; 322-1 ; 322-2 ; 322-3 ; 322-4) comporte :

l'application d'une première partie du signal de pré-lecture à la cellule de mémoire à changement de phase multiniveaux programmée, la première partie ayant une première amplitude (222 ; 322-1 ; 322-2 ; 322-3 ; 322-4) ; et

l'application d'une seconde partie du signal de pré-lecture à la cellule de mémoire à changement de phase multiniveaux programmée, la seconde partie ayant une seconde amplitude (222 ; 322-1 ; 322-2 ; 322-3 ; 322-4) ;

dans lequel la première partie est configurée pour accélérer la dérive de la résistance à une vitesse différente de celle à laquelle la seconde partie est configurée pour accélérer la dérive de la résistance (222 ; 322-1 ; 322-2 ; 322-3 ; 322-4).


 
8. Procédé selon l'une quelconque des revendications 1 à 2, dans lequel le procédé comporte l'application d'un signal de pré-lecture ultérieur (222) à la cellule de mémoire à changement de phase multiniveaux programmée (532) uniquement après avoir effectué une opération de programmation consécutive sur la cellule (532).
 
9. Appareil (650) comprenant :

un réseau (100 ; 600) de cellules de mémoire à changement de phase multiniveaux, dans lequel chaque cellule de mémoire à changement de phase multiniveaux est programmable à l'un d'un état défini, d'un état de réinitialisation et d'un certain nombre d'états intermédiaires ; et

un dispositif de commande (652) couplé au réseau (100 ; 600) et configuré pour :

une opération de programmation destinée à programmer, par un signal de programmation (214), une cellule de mémoire à changement de phase multiniveaux (532) du réseau, à un état cible (214) ;

une opération intermédiaire consécutive destinée à appliquer un signal de pré-lecture (222 ; 322-1 ; 322-2 ; 322-3 ; 322-4) à la cellule de mémoire de changement de phase multiniveaux programmée, le signal de pré-lecture (222 ; 322-1 ; 322-2 ; 322-3 ; 322-4) étant déterminé en fonction de l'état cible, et configuré pour accélérer la dérive d'une résistance (425) de la cellule de mémoire de changement de phase multiniveaux programmée (532) sans effectuer un processus de recuit ; et

une opération de lecture, consécutive à l'opération intermédiaire, destinée à appliquer un signal de lecture (220 ; 320-1 ; 320-2 ; 320-3 ; 320-4) à la cellule de mémoire de changement de phase multiniveaux programmée (532) après un intervalle de temps (323-1 ; 323-2 ; 323-3) après application du signal de pré-lecture (222 ; 322-1 ; 322-2 ; 322-3 ; 322-4).


 
10. Appareil (650) selon la revendication 9, dans lequel le dispositif de commande (650) est configuré pour commander l'application du signal de pré-lecture (222 ; 322-1 ; 322-2 ; 322-3 ; 322-4) à la cellule de mémoire à changement de phase multiniveaux programmée (532) pour un intervalle de temps particulier (323-1 ; 323-2 ; 323-3).
 
11. Appareil (650) selon la revendication 9, dans lequel l'appareil comporte un circuit (530 ; 630) couplé au réseau (100 ; 600) et configuré pour :

appliquer sélectivement un signal de programmation (214 ; 534) à la cellule de mémoire à changement de phase multiniveaux (532) pendant la programmation ;

appliquer sélectivement le signal de pré-lecture (222 ; 322-1 ; 322-2 ; 322-3 ; 322-4 ; 536) à la cellule de mémoire à changement de phase multiniveaux programmée (532) ; et

appliquer sélectivement un signal de lecture (220 ; 320-1 ; 320-2 ; 320-3 ; 320-4 ; 538) à la cellule de mémoire à changement de phase multiniveaux programmée (532) pendant la lecture.


 
12. Appareil (650) selon la revendication 11, dans lequel le circuit (530 ; 630) comprend un interrupteur (540) actionnable pour appliquer sélectivement le signal de programmation (534), le signal de pré-lecture (536) et le signal de lecture (538) à la cellule de mémoire à changement de phase multiniveaux (532).
 




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REFERENCES CITED IN THE DESCRIPTION



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Patent documents cited in the description




Non-patent literature cited in the description