(19)
(11)EP 2 913 851 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
05.07.2017 Bulletin 2017/27

(21)Application number: 15156628.8

(22)Date of filing:  25.02.2015
(51)International Patent Classification (IPC): 
H01L 27/146(2006.01)

(54)

Imaging systems with through-oxide via connections

ABBILDUNGSSYSTEME MIT THROUGH-OXIDE-VIA-VERBINDUNGEN

SYSTÈMES D'IMAGERIE AYANT DES TROUS D'INTERCONNEXION TRANSVERSANT UN OXYDE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 27.02.2014 US 201414191965

(43)Date of publication of application:
02.09.2015 Bulletin 2015/36

(73)Proprietor: Semiconductor Components Industries, LLC
Phoenix, AZ 85008 (US)

(72)Inventors:
  • Borthakur, Swarnal
    Boise, ID Idaho ID 83706 (US)
  • Korobov, Vladimir
    San Mateo, CA California CA 94402 (US)
  • Sulfridge, Marc
    Boise, ID Idaho ID 83713 (US)

(74)Representative: Clarke, Geoffrey Howard et al
Avidity IP Broers Building Hauser Forum 21 JJ Thomson Ave
Cambridge CB3 0FA
Cambridge CB3 0FA (GB)


(56)References cited: : 
EP-A2- 2 230 691
US-A1- 2014 015 084
US-A1- 2012 256 319
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description


    [0001] This application claims priority to U.S. Patent Application No. 14/191,965 filed on February 27, 2014.

    Background



    [0002] This relates generally to imaging systems, and more particularly, to imaging systems with through-oxide vias in first and second integrated circuit dies.

    [0003] Modern electronic devices such as cellular telephones, cameras, and computers often use digital image sensors. Imaging systems (i.e., image sensors) often include a two-dimensional array of image sensing pixels. Each pixel typically includes a photosensor such as a photodiode that receives incident photons (light) and converts the photons into electrical signals. The imaging system contains an image sensor die with an image sensor integrated circuit and an array of photodiodes. The image sensor die is attached to a digital signal processing die with a digital signal processing integrated circuit.

    [0004] A bond pad on the image sensor die may be coupled to the image sensor integrated circuit and the digital signal processing integrated circuit using vias. However, the amount of time, space, efficiency, and cost for forming via connections between the metal routing paths in the integrated circuits may be limited. In conventional imaging systems, forming a through-silicon via to connect the image sensor die to the bond pad and forming connections from the bond pad to the digital signal processing die can limit the amount of time, space, efficiency, and cost for forming these connections.

    [0005] It would therefore be desirable to provide improved ways of forming via connections in imaging systems. Document US 2012/256319 shows an image sensor package comprising a digital circuit die bonded to an image sensor die. In accordance with an embodiment of the present invention there is provided an integrated circuit package as defined in claim 1. In accordance with another embodiment, the via has a first end that is connected to the bond pad and a second end that extends into the second integrated circuit die.

    [0006] In accordance with another embodiment, the first integrated circuit die has a first metal interconnect, the second integrated circuit die has a second metal interconnect, and the via couples the first metal interconnect to the second metal interconnect.

    [0007] In accordance with another embodiment, the first integrated circuit die includes a shallow trench isolation structure, and the via is formed through the shallow trench isolation structure.

    [0008] In accordance with the invention the first integrated circuit die includes an image sensor integrated circuit, and the second integrated circuit die includes a digital signal processing integrated circuit.

    [0009] In accordance with another embodiment, the integrated circuit package includes a via liner that surrounds the via.

    [0010] In accordance with another embodiment, the via includes a given via in a plurality of vias that is formed through the first integrated circuit die and that contacts the bond pad, and each via in the plurality of vias are circular.

    [0011] In accordance with another embodiment, the via includes a rectangular slot.

    [0012] In accordance with another embodiment, the first integrated circuit includes metal routing paths and an image sensor pixel that is coupled to the via through the metal routing paths.

    [0013] In accordance with another embodiment of the present invention there is provided a method of forming an image sensor package as defined in claim 8. In accordance with another embodiment, the method includes grinding the first die after attaching the first die to the second die, and depositing a buffer layer on the first die prior to performing selective etching.

    [0014] In accordance with another embodiment, the first die includes a silicon substrate, and wherein performing selective etching to form the hole comprises performing selective etching to form the hole through the silicon substrate.

    [0015] In accordance with another embodiment, the method includes depositing a passivation layer in the hole in the silicon substrate after performing selective etching to form the hole in the silicon substrate.

    [0016] In accordance with another embodiment, performing selective etching to form the hole includes performing selective etching to extend the hole from the silicon substrate into the second die, the via simultaneously provides a first connection between the first die and the second die and a second connection between the bond pad and the first die.

    [0017] In accordance with another embodiment, the first die includes a shallow trench isolation structure, and performing selective etching to form the hole further includes forming the hole through the shallow trench isolation structure.

    [0018] In accordance with an embodiment, a system is provided that includes a central processing unit, memory, input-output circuitry, and an imaging device, the imaging device includes a first die, a second die attached to the first die, a bond pad on the first die, and a through-oxide via that contacts the bond pad and extends through the first die into the second die.

    [0019] In accordance with another embodiment, the first die includes first metal routing paths, the second die includes second metal routing paths, the through-oxide via electrically couples the bond pad to the first and the second metal routing paths.

    [0020] In accordance with another embodiment, the through-oxide via connects the first and second metal routing paths.

    [0021] In accordance with another embodiment, the first die includes a shallow trench isolation structure, and the through-oxide via extends through the shallow trench isolation structure.

    [0022] In accordance with the invention, the first die includes an image sensor integrated circuit, and the second die includes a digital signal processing integrated circuit.

    Brief Description of the Drawings



    [0023] 

    FIG. 1 is a diagram of an illustrative imaging system that may include a camera module having an image sensor in accordance with an embodiment of the present invention.

    FIG. 2 is a cross-sectional side view of an image sensor package having through-oxide vias in accordance with an embodiment of the present invention.

    FIG. 3 is a flow chart showing illustrative steps that may be involved in forming an illustrative imaging system having through-oxide vias in accordance with an embodiment of the present invention.

    FIGS. 4A and 4B are cross-sectional side views of an image sensor package having through-oxide vias in accordance with an embodiment of the present invention.

    FIGS. 5A and 5B are top views of a bond pad with through-oxide vias in accordance with an embodiment of the present invention.

    FIG. 6 is a block diagram of a system employing the embodiments of FIGS. 2-5 in accordance with an embodiment of the present invention.



    [0024] Electronic devices such as digital cameras, computers, cellular telephones, and other electronic devices include image sensors that gather incoming image light to capture an image. The image sensors may include arrays of imaging pixels. The pixels in the image sensors may include photosensitive elements such as photodiodes that convert the incoming image light into image signals. Image sensors may have any number of pixels (e.g., hundreds or thousands or more). A typical image sensor may, for example, have hundreds of thousands or millions of pixels (e.g., megapixels). Image sensors may include control circuitry such as circuitry for operating the imaging pixels and readout circuitry for reading out image signals corresponding to the electric charge generated by the photosensitive elements.

    [0025] FIG. 1 is a diagram of an illustrative electronic device that uses an image sensor to capture images. Electronic device 10 of FIG. 1 may be a portable electronic device such as a camera, a cellular telephone, a video camera, or other imaging device that captures digital image data. Camera module 12 may be used to convert incoming light into digital image data. Camera module 12 may include one or more lenses 14 and one or more corresponding image sensors 16. During image capture operations, light from a scene may be focused onto image sensor 16 by lens 14. Image sensor 16 provides corresponding digital image data to processing circuitry 18. Image sensor 16 may, for example, be a backside illumination image sensor. If desired, camera module 12 may be provided with an array of lenses 14 and an array of corresponding image sensors 16. Image sensor 16 may include an array of image sensor pixels such as an array of image sensor pixels 15 and a corresponding array of color filter elements.

    [0026] Processing circuitry 18 may include one or more integrated circuits (e.g., image processing circuits, microprocessors, storage devices such as random-access memory and non-volatile memory, etc.) and may be implemented using components that are separate from camera module 12 and/or that form part of camera module 12 (e.g., circuits that form part of an integrated circuit that includes image sensors 16 or an integrated circuit within module 12 that is associated with image sensors 16). Image data that has been captured by camera module 12 may be processed and stored using processing circuitry 18. Processed image data may, if desired, be provided to external equipment (e.g., a computer or other device) using wired and/or wireless communications paths coupled to processing circuitry 18.

    [0027] FIG. 2 is a cross-sectional side view of an image sensor package such as image sensor package 20. Image sensor package 20 may have an image sensor integrated circuit die such as image sensor integrated circuit die 22 (also referred to as image sensor die 22) and a digital signal processing (DSP) integrated circuit die 24 (also referred to as DSP die 24). Image sensor die 22 may contain integrated circuits for an array of image sensor pixels 15 (see, e.g. FIG. 1) in a silicon substrate such as silicon substrate 26. Silicon substrate 26 may have shallow trench isolation (STI) structures such as STI structure 28 that separate the flow of current between adjacent transistors in the image sensor die. STI structure 28 may be formed from oxide materials.

    [0028] A buffer layer such as buffer layer 30 may be deposited over silicon substrate 26. Buffer layer 30 may be formed from multiple layers of buffer materials such as oxides. Image sensor die 22 may have interconnect layers such as interconnect layers 32. DSP die 24 may also have interconnect layers such as interconnect layers 34. Image sensor die 22 may be bonded or attached to DSP die 24 such that interconnect layers 32 and 34 are facing each other. Interconnect layers 32 may form the front side of image sensor die 22 and interconnect layers 32 may form the front side of DSP die 24. Image sensor package 20 may form part of a backside illumination imaging system, where light is received from the direction of the backside of the image sensor die 22 (e.g. from the side with buffer layer 30). The arrangement in FIG. 2 is merely exemplary; image sensor package 20 may also form part of a frontside illumination system. Image sensor die 22 and DSP die 24 may be attached in any suitable way to form the imaging system.

    [0029] Interconnect layer 32 may have metal interconnects (e.g. metal routing paths) such as metal interconnects 36. Interconnect layer 34 may have metal interconnects such as metal interconnects 38. Interconnect layers 32 and 34 may be formed from multiple layers of materials and contain multiple layers of metal interconnects. A bond pad such as bond pad 40 may be formed on a passivation layer over silicon substrate 26. Bond pad 40 may be formed from aluminum. There may be more than one bond pad such as bond pad 40 on the surface of silicon substrate 26. Bond pad 40 may have a rectangular or square-shaped surface with four sides. Bond pad 40 may have an area that is smaller than that of a bond pad that may be used in a conventional through-silicon via configuration. For example, bond pad 40 may have a length that ranges from 70-110 micrometers and a width that ranges from 70-110 micrometers, or any other suitable dimensions for the bond pad.

    [0030] Vias such as through-oxide vias 42 may be formed in image sensor die 22 and DSP die 24 to electrically connect bond pad 40 to the integrated circuits in the dies (e.g. image sensor integrated circuits and DSP integrated circuits). Through-oxide vias 42 may be formed from conductive material such as copper and any other suitable conductive material. Through-oxide vias 42 may be surrounded by via liners such as via liners 44 and may pass through STI structure 28. Via liners 44 may be formed from tantalum or any other suitable conductive materials. Via liners 44 may be surrounded by a passivation layer such as passivation layer 45. Passivation layer 45 may be formed from oxide material. Through-oxide via 42 may have one end that is connected to bond pad 40 and another end that extends through image sensor die 22 into DSP die 24. Through-oxide vias 42 may connect bond pad 40 to metal interconnects 36 and 38 while connecting the metal interconnects 36 and 38 to each other.

    [0031] In this way, the bond pad connections and the inter-die connections (e.g. the connections between the metal interconnects in the first and second dies, such as metal interconnects 36 and 38) may be formed using a single structure and process (e.g. through-oxide vias) rather than separate processes and structures for the bond pad connections and the inter-die connections. The electrical connection between bond pad 40 and the circuitry in the first and second dies using through-oxide vias 42 rather than conventional through-silicon via methods may result in reducing bond pad area for bond pad 40 and the number of masking layers used during processing, which improves the amount of space and cost for manufacturing image sensor packages. A single etching process to form the bond pad connection and the inter-die connections may be desirable as it may improve the process integration (e.g. reduce development cycle time), minimize topography (e.g. improve yield of light reaching the photodiodes in the image sensor), and reduce the cost of the process.

    [0032] FIG. 3 is a flow chart of illustrative steps that may be involved in forming an illustrative imaging system having through-oxide vias such as the image sensor package shown in FIG. 2.

    [0033] At step 46, a first die such as image sensor die 22 and a second die such as DSP die 24 may be attached to each other and the image sensor die 22 may be ground or polished to a desired thickness. Image sensor die 22 may be bonded or attached to DSP die 24 such that their front side interconnect layers such as interconnect layers 32 and interconnect layers 34 face each other. Image sensor die 22 may include a silicon substrate such as silicon substrate 26 with an image sensor integrated circuit for the array of photodiodes in silicon substrate 26. The silicon substrate such as silicon substrate 26 may be ground and thinned to a desired thickness, which may range from 2-3 microns for backside illuminated image sensors.

    [0034] At step 48, a buffer layer such as buffer layer 30 may be deposited on the first die such as image sensor die 22. The buffer layer may be formed from oxide materials and may be formed from multiple layers of materials. For example, an antireflective coating layer formed from oxide materials may be deposited on the first die and additional buffer layers also formed from oxide materials may be deposited over the first die and the antireflective coating layer.

    [0035] At step 50, selective etching may be performed to form a hole in a silicon substrate of the first die, such as silicon substrate 26 of image sensor die 22. The hole may reach an STI structure in the silicon substrate, such as STI structure 28. The STI structure may be positioned between adjacent transistors in the silicon substrate to block and isolate the current flow from the transistors from each other.

    [0036] At step 52, a passivation layer such as passivation layer 45 may be deposited in the hole such that the passivation layer covers the walls of the hole in the silicon substrate, such as silicon substrate 26. The passivation layer may be formed from oxide material.

    [0037] At step 54, selective etching may be performed to extend the hole through an STI structure such as STI structure 28 and interconnect layers such as interconnect layers 36 and 38. The hole may extend through layers of metal routing paths in the interconnect layers such as metal interconnects 36 and 38. The hole may be etched such that the hole extends through the first die and into the second die (i.e. from the first die to the second die). The etching may be done in a single etching process or multiple etching processes. A single etching process may be desirable as it may improve the process integration (e.g. reduce development cycle time), minimize topography (e.g. improve yield of light reaching the photodiodes in the image sensor), and reduce the cost of the process.

    [0038] At step 56, a via liner such as via liner 44 may be deposited in the hole. The via liner may be deposited such that the via liner lines the inner surfaces of the hole. Via liner 44 may be formed from tantalum or any other suitable materials.

    [0039] At step 58, a conductive material such as copper may be deposited in the hole to form through-oxide vias such as through-oxide vias 42. The rest of the hole may be filled by the conductive material. Through-oxide vias 42 may be electrically coupled to metal interconnects 36 and 38.

    [0040] At step 60, a bond pad such as bond pad 40 may be formed on the first die such as image sensor die 22 such that the bond pad contacts the through-oxide via. Bond pad 40 may be electrically coupled to both the first die and the second die with through-oxide via 42, since through-oxide via is connected to bond pad 40, the metal interconnects in the first die (e.g. metal interconnects 36), and the metal interconnects in the second die (e.g. metal interconnects 38). In this way, the bond pad connections and the inter-die connections (e.g. formed between metal interconnects 36 and 38) may be formed using a single structure and process (e.g. through-oxide vias) rather than separate processes and structures for the bond pad connections and the inter-die connections. The electrical connection between bond pad 40 and the metal routing paths in the first and second dies using through-oxide vias 42 rather than conventional through-silicon via methods may result in a smaller bond pad area for bond pad 40 and fewer buffer layers used, which improves the amount of space and cost for manufacturing image sensor packages.

    [0041] FIGS. 4A and 4B show cross-sectional views of various configurations of through-oxide vias that can be formed in an image sensor package. In FIG. 4A, an image sensor package such as image sensor package 20-A may have first and second dies such as image sensor die 22-A and DSP die 24-A. DSP die 24-A may include an application-specific integrated circuit (ASIC). Image sensor die 22-A may have metal interconnects 36-A and 37-A and DSP die 24-A may have metal interconnects 38-A. Metal interconnects 37-A may be coupled to one or more image sensor integrated circuits for an array of photodiodes (e.g. image sensor pixels 15 in FIG. 1) in image sensor die 22-A. Image sensor package 20-A may include vias 43-A which serve as inter-die connections that connect the metal interconnect 37-A in the first die to metal interconnect 38-A in the second die. Image sensor package 20-A may also include a through-oxide via such as through-oxide via 42-A and a bond pad such as bond pad 40-A that rests on a top surface of the image sensor die. Through-oxide via 42-A may be formed such that bond pad 40-A is simultaneously electrically coupled to metal interconnect 36-A and 38-A (e.g. through-oxide via 42-A may be both an inter-die connection between the first and second dies as well as a bond pad connection between bond pad 40-A and the metal interconnects 36-A and 38-A). However, since metal interconnect 36-A and metal interconnect 37-A are not electrically coupled, bond pad 40-A is not electrically coupled to metal interconnect 37-A and image sensor integrated circuits in image sensor die 22-A.

    [0042] In FIG. 4B, an image sensor package such as image sensor package 20-B may have first and second dies such as image sensor die 22-B and DSP die 24-B. DSP die 24-B may include an application-specific integrated circuit (ASIC). Image sensor die 22-B may have metal interconnects 36-B and DSP die 24-B may have metal interconnects 38-A. Metal interconnects 36-B may be coupled to one or more image sensor integrated circuits for an array of photodiodes (e.g. image sensor pixels 15 in FIG. 1) in image sensor die 22-B. Image sensor package 20-B may also include a through-oxide via such as through-oxide via 36-A and a bond pad such as bond pad 40-B that rests on a top surface of the image sensor die. Through-oxide via 42-B may be formed such that bond pad 40-B is simultaneously electrically coupled to metal interconnect 36-B and 38-B (e.g. through-oxide via 42-B may be both an inter-die connection between the first and second dies as well as a bond pad connection between bond pad 40-A and the metal interconnects 36-A and 38-A). Bond pad 40-B may be electrically coupled to both metal interconnect 38-B in DSP die 24-B as well as pixel circuitry in image sensor die 22-A (through metal interconnect 36-B).

    [0043] The configurations of through-oxide vias in FIGS. 4A and 4B are merely exemplary; there may be any suitable number of through-oxide vias that are formed in any suitable number of combinations to form any suitable connections between the bond pad and different layers of circuitry in the image sensor package.

    [0044] FIGS. 5A and 5B show various configurations of through-oxide vias that may be formed from a cut-away top view of a bond pad. As shown in FIG. 5A, bond pad 80-A may be formed from a conductive material such as aluminum. Bond pad 80-A may have top and bottom surfaces. The bottom surface of bond pad 80-A may be connected to and contact a number of through-oxide vias such as through-oxide vias 42 in FIGS. 2 and 4. The through-oxide vias 42 may be circular and there may be a plurality of through-oxide vias that contact bond pad 80-A along a side of the top surface. The arrangement in FIG. 5A is merely exemplary; any suitable number of and shape of through-oxide vias 42 may be formed in any suitable arrangement to connect to bond pad 80-A. Through-oxide vias 42 may be positioned adjacent to each other. The spacing between the vias 42 may be around 4.4 micrometers or any other suitable distance. Bond pad 80-A may have an area that is smaller than that of a bond pad that may be used in a conventional through-silicon via configuration. For example, bond pad 80-A may have a length that ranges from 70-110 micrometers and a width that ranges from 70-110 micrometers, or any other suitable dimensions for the bond pad.

    [0045] As shown in FIG. 5B, bond pad 80-B may be formed from a conductive material such as aluminum. Bond pad 80-B may have top and bottom surfaces. The bottom surface of bond pad 80-B may be connected to and contact a number of through-oxide vias such as through-oxide vias 42 in FIGS. 2 and 4. Through-oxide vias 42 may be formed from a rectangular slot shaped opening in the silicon substrate and may be formed from a rectangular block of conductive material. A slot-shaped through-oxide via 42 may be connected to bond pad 80-B at one of the via's rectangular sides (shown in FIG. 5B). The arrangement shown in FIG. 5B is merely exemplary; the via may contact the bond pad in any suitable location. The slot-shaped via 42 may be 52 micrometers by 3.8 micrometers or have any other suitable ranges of dimensions. Bond pad 80-B may have an area that is smaller than that of a bond pad that may be used in a conventional through-silicon via configuration. For example, bond pad 80-B may have a length that ranges from 70-110 micrometers and a width that ranges from 70-110 micrometers, or any other suitable dimensions for the bond pad.

    [0046] FIG. 6 shows in simplified form a typical processor system 300, such as a digital camera, which includes an imaging device 200. Imaging device 200 may include a pixel array 201. Imaging device 200 may include an image sensor package such as image sensor package 20 with through-oxide vias 42 as shown in FIG. 2. Processor system 300 is exemplary of a system having digital circuits that may include imaging device 200. Without being limiting, such a system may include a computer system, still or video camera system, scanner, machine vision, vehicle navigation, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system, and other systems employing an imaging device.

    [0047] Processor system 300, which may be a digital still or video camera system, may include a lens such as lens 396 for focusing an image onto a pixel array such as pixel array 201 when shutter release button 397 is pressed. Processor system 300 may include a central processing unit such as central processing unit (CPU) 395. CPU 395 may be a microprocessor that controls camera functions and one or more image flow functions and communicates with one or more input/output (I/O) devices 391 over a bus such as bus 393. Imaging device 200 may also communicate with CPU 395 over bus 393. System 300 may include random access memory (RAM) 392 and removable memory 394. Removable memory 394 may include flash memory that communicates with CPU 395 over bus 393. Imaging device 200 may be combined with CPU 395, with or without memory storage, on a single integrated circuit or on a different chip. Although bus 393 is illustrated as a single bus, it may be one or more buses or bridges or other communication paths used to interconnect the system components.

    [0048] Various embodiments have been described illustrating imaging systems having bond pads connected to various dies in the imaging system using through-oxide vias. A system with a central processing unit, memory, and input-output circuitry may include an imaging device. The imaging device, or integrated circuit package, may include a first integrated circuit die, a second integrated circuit die that is attached or bonded to the first integrated circuit die, a bond pad on the first integrated circuit die; and a via that couples the bond pad on the first integrated circuit die to the second integrated circuit die. The via may have a first end that is connected to the bond pad and a second end that extends into the second integrated circuit die. The first and second integrated circuit dies may have first and second metal interconnects (also referred to as metal routing paths). The via may couple the first metal interconnect to the second metal interconnect. The first integrated circuit die includes a shallow trench isolation structure. The via is formed through the shallow trench isolation structure. The first integrated circuit die includes an image sensor integrated circuit and the second integrated circuit die includes a digital signal processing integrated circuit. A via liner may surrounds the via. The via may be one of a plurality of vias that is formed through the first integrated circuit die and that contacts the bond pad. The vias may be circular or rectangular slots. The first integrated circuit may include an image sensor pixel that is coupled to the via through the metal routing paths in the first integrated circuit.

    [0049] The via may be formed by performing selective etching to form a hole that extends into the first and second dies, depositing conductive material in the hole to form a via in the hole, and forming the bond pad on the first die to contact the via. The via may simultaneously provide a first connection between the first die and the second die and a second connection between the bond pad and the first die. A buffer layer may be deposited on the first die prior to performing selective etching. The first die includes a silicon substrate. Selective etching to form the hole may include performing selective etching to form the hole through the silicon substrate. A passivation layer may be deposited in the hole in the silicon substrate after performing selective etching to form the hole in the silicon substrate. The hole in the silicon substrate is then formed through the shallow trench isolation structure in the first die and extended into the second die by selective etching.

    [0050] The foregoing is merely illustrative of the principles of this invention which can be practiced in other embodiments.


    Claims

    1. An integrated circuit package (20), comprising:

    a first integrated circuit die (22) comprising an image sensor integrated circuit;

    a second integrated circuit die (24) comprising a digital signal processing integrated circuit, wherein the second integrated circuit die (24) is bonded to the first integrated circuit die (22);

    a bond pad (40) on the first integrated circuit die (22); and

    a via (42) that extends through the first integrated circuit die (22) and into the second integrated circuit die (24) and that couples the bond pad (40) on the first integrated circuit die (22) to the second integrated circuit die (24), wherein the first integrated circuit die (22) includes a shallow trench isolation structure (28), and wherein the via (42) is formed through the shallow trench isolation structure (28).


     
    2. The integrated circuit package defined in claim 1, wherein the via (42) has a first end that is connected to the bond pad (40) and a second end that extends into the second integrated circuit die (24).
     
    3. The integrated circuit package defined in claim 1, wherein the first integrated circuit die (22) has a first metal interconnect (36), wherein the second integrated circuit die (24) has a second metal interconnect (38), and wherein the via (42) couples the first metal interconnect (36) to the second metal interconnect (38).
     
    4. The integrated circuit package defined in claim 1, further comprising:

    a via liner (44) that surrounds the via (42).


     
    5. The integrated circuit package defined in claim 1, wherein the via (42) comprises a given via in a plurality of vias that is formed through the first integrated circuit die (22) and that contacts the bond pad (40), and wherein each via in the plurality of vias are circular.
     
    6. The integrated circuit package defined in claim 1, wherein the via (42) comprises a rectangular slot.
     
    7. The integrated circuit package defined in claim 1, wherein the first integrated circuit die (22) includes metal routing paths (36) and an image sensor pixel (15) that is coupled to the via (42) through the metal routing paths (36).
     
    8. A method of forming an integrated circuit package (20) according to claim 1, comprising:

    attaching (46) the first integrated circuit die (22) to the second integrated circuit die (24);

    performing (50) selective etching to form a hole that extends into the first integrated circuit die (22) and the second integrated circuit die (24), wherein the first integrated circuit die (22) comprises the shallow trench isolation structure (28), and wherein performing selective etching to form the hole further comprises forming (54) the hole through the shallow trench isolation structure (28);

    depositing (58) conductive material in the hole to form the via (42) in the hole; and

    forming (60) the bond pad (40) on the first integrated circuit die (22) to contact the via (42).


     
    9. The method defined in claim 8, further comprising:

    grinding (46) the first integrated circuit die (22) after attaching the first integrated circuit die (22) to the second integrated circuit die (24); and

    depositing (48) a buffer layer (30) on the first integrated circuit die (22) prior to performing (50) selective etching.


     
    10. The method defined in claim 8, wherein the first integrated circuit die (22) comprises a silicon substrate (26), and wherein performing (54) selective etching to form the hole comprises performing selective etching to form the hole through the silicon substrate (26).
     
    11. The method defined in claim 10, further comprising:

    depositing (52) a passivation layer (45) in the hole in the silicon substrate (26) after performing selective etching to form the hole in the silicon substrate (26).


     
    12. The method defined in claim 10, wherein performing (50) selective etching to form the hole further comprises performing (54) selective etching to extend the hole from the silicon substrate (26) into the second integrated circuit die (24), wherein the via (40) simultaneously provides a first connection between the first integrated circuit die (22) and the second integrated circuit die (24) and a second connection between the bond pad (40) and the first integrated circuit die (22).
     


    Ansprüche

    1. Integriertes Schaltkreispaket (20), Folgendes umfassend:

    einen ersten integrierten Schaltkreis-Die (22), umfassend einen integrierten Bildsensorschaltkreis;

    einen zweiten integrierten Schaltkreis-Die (24), umfassend einen ein Digitalsignal verarbeitenden integrierten Schaltkreis, wobei der zweite integrierte Schaltkreis-Die (24) an den ersten integrierten Schaltkreis-Die (22) gebunden ist;

    ein Bindungs-Pad (40) auf dem ersten integrierten Schaltkreis-Die (22); und

    eine Durchkontaktierung (42), die sich durch den ersten integrierten Schaltkreis-Die (22) und in den zweiten integrierten Schaltkreis-Die (24) erstreckt, und die das Bindungs-Pad (40) auf dem ersten integrierten Schaltkreis-Die (22) an den zweiten integrierten Schaltkreis-Die (24) koppelt, wobei der erste integrierte Schaltkreis-Die (22) eine flache Grabenisolierungsanordnung (28) enthält, und wobei die Durchkontaktierung (42) durch die flache Grabenisolierungsanordnung (28) hindurch ausgebildet ist.


     
    2. Integriertes Schaltkreispaket nach Anspruch 1, wobei die Durchkontaktierung (42) ein erstes Ende, das mit dem Bindungs-Pad (40) verbunden ist, und ein zweites Ende, das sich in den zweiten integrierten Schaltkreis-Die (24) hinein erstreckt, aufweist.
     
    3. Integriertes Schaltkreispaket nach Anspruch 1, wobei der erste integrierte Schaltkreis-Die (22) eine erste Metallverbindung (36) aufweist, wobei der zweite integrierte Schaltkreis-Die (24) eine zweite Metallverbindung (38) aufweist und wobei die Durchkontaktierung (42) die erste Metallverbindung (36) mit der zweiten Metallverbindung (38) koppelt.
     
    4. Integriertes Schaltkreispaket nach Anspruch 1, ferner Folgendes umfassend:

    eine Durchkontaktierungsauskleidung (44), die die Durchkontaktierung (42) umgibt.


     
    5. Integriertes Schaltkreispaket nach Anspruch 1, wobei die Durchkontaktierung (42) eine bestimmte Durchkontaktierung unter mehreren Durchkontaktierungen umfasst, die durch den ersten integrierten Schaltkreis-Die (22) hindurch ausgebildet ist und die das Bindungs-Pad (40) berührt, und wobei jede Durchkontaktierung unter den mehreren Durchkontaktierungen kreisrund ist.
     
    6. Integriertes Schaltkreispaket nach Anspruch 1, wobei die Durchkontaktierung (42) einen rechteckigen Schlitz umfasst.
     
    7. Integriertes Schaltkreispaket nach Anspruch 1, wobei der erste integrierte Schaltkreis-Die (22) Metallführungspfade (36) und ein Bildsensorpixel (15), das über die Metallführungspfade (36) mit der Durchkontaktierung (42) gekoppelt ist, umfasst.
     
    8. Verfahren zum Ausbilden eines integrierten Schaltkreispakets (20) nach Anspruch 1, Folgendes umfassend:

    Verbinden (46) des ersten integrierten Schaltkreis-Dies (22) mit dem zweiten integrierten Schaltkreis-Die (24);

    Ausführen (50) von selektivem Ätzen zum Ausbilden eines Lochs, das sich in den ersten integrierten Schaltkreis-Die (22) und in den zweiten integrierten Schaltkreis-Die (24) hinein erstreckt, wobei der erste integrierte Schaltkreis-Die (22) die flache Grabenisolierungsanordnung (28) umfasst und wobei das Ausführen des selektiven Ätzens zum Ausbilden des Lochs ferner das Ausbilden (54) des Lochs durch die flache Grabenisolierungsanordnung (28) hindurch umfasst;

    Ablagern (58) von leitfähigem Material in dem Loch zum Ausbilden der Durchkontaktierung (42) in dem Loch; und

    Ausbilden (60) des Bindungs-Pads (40) auf dem ersten integrierten Schaltkreis-Die (22) zum Berühren der Durchkontaktierung (42).


     
    9. Verfahren nach Anspruch 8, ferner Folgendes umfassend:

    Abschleifen (46) des ersten integrierten Schaltkreis-Dies (22) nach dem Befestigen des ersten integrierten Schaltkreis-Dies (22) an dem zweiten integrierten Schaltkreis-Die (24); und

    Ablagern (48) einer Pufferschicht (30) auf dem ersten integrierten Schaltkreis-Die (22) vor dem Ausführen (50) des selektiven Ätzens.


     
    10. Verfahren nach Anspruch 8, wobei der erste integrierte Schaltkreis-Die (22) ein Siliciumsubstrat (26) umfasst und wobei das Ausführen (54) von selektivem Ätzen zum Ausbilden des Lochs das Ausführen von selektivem Ätzen zum Ausbilden des Lochs durch das Siliciumsubstrat (26) umfasst.
     
    11. Verfahren nach Anspruch 10, ferner Folgendes umfassend:

    Ablagern (52) einer Passivierungsschicht (45) in dem Loch in dem Siliciumsubstrat (26) nach dem Ausführen von selektivem Ätzen zum Ausbilden des Lochs in dem Siliciumsubstrat (26).


     
    12. Verfahren nach Anspruch 10, wobei das Ausführen (50) von selektivem Ätzen zum Ausbilden des Lochs ferner das Ausführen (54) von selektivem Ätzen umfasst, um das Loch von dem Siliciumsubstrat (26) in den zweiten integrierten Schaltkreis-Die (24) zu erweitern, wobei die Durchkontaktierung (40) gleichzeitig eine erste Verbindung zwischen dem ersten integrierten Schaltkreis-Die (22) und dem zweiten integrierten Schaltkreis-Die (24) und eine zweite Verbindung zwischen dem Bindungs-Pad (40) und dem ersten integrierten Schaltkreis-Die (22) bereitstellt.
     


    Revendications

    1. Boîtier de circuit intégré (20), comprenant :

    un premier dé de circuit intégré (22) comprenant un circuit intégré de capteur d'image ;

    un second dé de circuit intégré (24) comprenant un circuit intégré de traitement de signal numérique, dans lequel le second dé de circuit intégré (24) est lié au premier dé de circuit intégré (22) ;

    un plot de liaison (40) sur le premier dé de circuit intégré (22) ; et

    un via (42) qui s'étend à travers le premier dé de circuit intégré (22) et dans le second dé de circuit intégré (24) et qui couple le plot de liaison (40) sur le premier dé de circuit intégré (22) au second dé de circuit intégré (24), dans lequel le premier dé de circuit intégré (22) comporte une structure d'isolement à tranchée superficielle (28), et dans lequel le via (42) est formé à travers la structure d'isolement à tranchée superficielle (28).


     
    2. Boîtier de circuit intégré selon la revendication 1, dans lequel le via (42) a une première extrémité qui est connectée au plot de liaison (40) et une seconde extrémité qui s'étend dans le second dé de circuit intégré (24).
     
    3. Boîtier de circuit intégré selon la revendication 1, dans lequel le premier dé de circuit intégré (22) a une première interconnexion en métal (36), dans lequel le second dé de circuit intégré (24) a une seconde interconnexion en métal (38), et dans lequel le via (42) couple la première interconnexion en métal (36) à la seconde interconnexion en métal (38).
     
    4. Boîtier de circuit intégré selon la revendication 1, comprenant en outre :

    une garniture de via (44) qui entoure le via (42).


     
    5. Boîtier de circuit intégré selon la revendication 1, dans lequel le via (42) comprend un via donné dans une pluralité de vias qui est formé à travers le premier dé de circuit intégré (22) et qui vient en contact avec le plot de liaison (40), et dans lequel chaque via dans la pluralité de vias est circulaire.
     
    6. Boîtier de circuit intégré selon la revendication 1, dans lequel le via (42) comprend une fente rectangulaire.
     
    7. Boîtier de circuit intégré selon la revendication 1, dans lequel le premier dé de circuit intégré (22) comporte des chemins d'acheminement en métal (36) et un pixel de capteur d'image (15) qui est couplé au via (42) à travers les chemins d'acheminement en métal (36).
     
    8. Procédé de formation d'un boîtier de circuit intégré (20) selon la revendication 1, comprenant :

    la fixation (46) du premier dé de circuit intégré (22) au second dé de circuit intégré (24) ;

    la réalisation (50) d'un gravage sélectif pour former un trou qui s'étend dans le premier dé de circuit intégré (22) et le second dé de circuit intégré (24), dans lequel le premier dé de circuit intégré (22) comprend la structure d'isolement à tranchée superficielle (28), et dans lequel la réalisation d'un gravage sélectif pour former le trou comprend en outre la formation (54) du trou à travers la structure d'isolement à tranchée superficielle (28) ;

    le dépôt (58) d'un matériau conducteur dans le trou pour former le via (42) dans le trou ; et

    la formation (60) du plot de liaison (40) sur le premier dé de circuit intégré (22) pour venir en contact avec le via (42).


     
    9. Procédé selon la revendication 8, comprenant en outre :

    le meulage (46) du premier dé de circuit intégré (22) après fixation du premier dé de circuit intégré (22) au second dé de circuit intégré (24) ; et

    le dépôt (48) d'une couche tampon (30) sur le premier dé de circuit intégré (22) avant la réalisation (50) d'un gravage sélectif.


     
    10. Procédé selon la revendication 8, dans lequel le premier dé de circuit intégré (22) comprend un substrat en silicium (26), et dans lequel la réalisation (54) d'un gravage sélectif pour former le trou comprend la réalisation d'un gravage sélectif pour former le trou à travers le substrat en silicium (26).
     
    11. Procédé selon la revendication 10, comprenant en outre :

    le dépôt (52) d'une couche de passivation (45) dans le trou dans le substrat en silicium (26) après la réalisation d'un gravage sélectif pour former le trou dans le substrat en silicium (26).


     
    12. Procédé selon la revendication 10, dans lequel la réalisation (50) d'un gravage sélectif pour former le trou comprend en outre la réalisation (54) d'un gravage sélectif pour étendre le trou depuis le substrat en silicium (26) dans le second dé de circuit intégré (24), dans lequel le via (40) fournit simultanément une première connexion entre le premier dé de circuit intégré (22) et le second dé de circuit intégré (24) et une seconde connexion entre le plot de liaison (40) et le premier dé de circuit intégré (22).
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description