(19)
(11)EP 2 939 273 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
04.12.2019 Bulletin 2019/49

(21)Application number: 13868517.7

(22)Date of filing:  24.12.2013
(51)Int. Cl.: 
H01L 29/786  (2006.01)
H01L 29/417  (2006.01)
H01L 29/45  (2006.01)
H01L 27/32  (2006.01)
H01L 29/423  (2006.01)
H01L 29/49  (2006.01)
(86)International application number:
PCT/KR2013/012088
(87)International publication number:
WO 2014/104708 (03.07.2014 Gazette  2014/27)

(54)

THIN FILM TRANSISTOR

DÜNNFILMTRANSISTOR

TRANSISTOR À COUCHE MINCE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 27.12.2012 KR 20120155587
28.11.2013 KR 20130146139

(43)Date of publication of application:
04.11.2015 Bulletin 2015/45

(73)Proprietor: LG Display Co., Ltd.
Seoul 150-721 (KR)

(72)Inventors:
  • KWON, Se Yeoul
    Goyang-si, Gyeonggi-do 411-809 (KR)
  • CHO, Min Gu
    Goyang-si, Gyeonggi-do 411-809 (KR)
  • YOUN, Sang Cheon
    Seoul 150-866 (KR)

(74)Representative: Viering, Jentschura & Partner mbB Patent- und Rechtsanwälte 
Am Brauhaus 8
01099 Dresden
01099 Dresden (DE)


(56)References cited: : 
WO-A1-2011/104895
KR-A- 20040 093 792
US-A- 5 844 647
US-A1- 2010 224 872
US-A1- 2012 098 008
US-A1- 2012 175 615
WO-A1-2012/063436
KR-A- 20120 124 316
US-A1- 2005 275 038
US-A1- 2011 297 948
US-A1- 2012 168 756
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    Technical Field


    CROSS-REFERENCE TO RELATED APPLICATION



    [0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2012-0155587, filed on December 27, 2012. This application also claims priority to and the benefit of Korean Patent Application No. 10-2013-0146139, filed on November 28, 2013.

    BACKGROUND


    1. Field of the Invention



    [0002] The present invention relates to a thin film transistor (TFT), a method of manufacturing the same, and a display device including the thin film transistor, and more particularly, to a thin film transistor having a coplanar structure with improves optical reliability and characteristics thereof, a method of manufacturing the thin film transistor, and a display device including the thin film transistor.

    2. Discussion of Related Art



    [0003] As interest in information display has recently increased and demands for portable electronic devices have increased, lightweight thin flat panel display devices have been widely studied and commercialized. From among flat panel display devices, particularly, liquid crystal display (LCD) devices and organic light-emitting display (OLED) devices have been particularly widely studied. LCD devices and organic light-emitting display devices use a thin film transistor as a switching device and/or a driving device.

    [0004] Thin-film transistors using an oxide semiconductor are classified into thin film transistors having a coplanar structure and thin film transistors having an inverted-staggered structure according to positions of an active layer, a gate electrode, a source electrode, and a drain electrode. A parasitic capacitance between a gate electrode and an active layer in a thin film transistor having an inverted-staggered structure is very high. Because of such high parasitic capacitance, it is difficult to apply the thin film transistor having the inverted-staggered structure to a large-scaled display device. Therefore, coplanar type thin film transistors are employed in large-scaled display devices.

    [0005] The active layer of a thin film transistor can be formed of amorphous silicon, poly-silicon or an oxide semiconductor. When a thin film transistor using poly-silicon is manufactured, a process of implanting ions to adjust a resistance of an active layer is additionally performed. Accordingly, an ion implantation process using an additional mask for defining an ion implantation region is disadvantageously added.

    [0006] On the other hand, a thin film transistor using an oxide semiconductor has higher electron mobility than a thin film transistor using amorphous silicon, and exhibit lower leakage current than the thin film transistor using the amorphous silicon or the poly-silicon, and satisfies a high reliability test condition. Also, the thin film transistor using the oxide semiconductor advantageously has a uniform distribution of threshold voltages when compared to the thin film transistor using the poly silicon.

    [0007] Despite such excellent electric and optical characteristics, the oxide semiconductor based TFT has a few drawbacks. For instance, the oxide semiconductor based TFT, especially the inverted-staggered type, exhibits high parasitic capacitance between the gate electrode and the active layer, which makes it difficult to be employed in the TFT in large display panels. In addition, the oxide semiconductor based TFTs may exhibit hysteresis (i.e., threshold voltage shift) when the oxide semiconductor material is exposed to incident light during the operation.

    [0008] Thus, there remains a need for oxide semiconductor technologies that can enhance the performance and operation stability of TFTs.

    [0009] Oxide semiconductor TFTs using light shields are known from US 2012/0168756 and US 2010/0224872.

    SUMMARY OF THE INVENTION



    [0010] In the present invention an oxide semiconductor thin film transistor is provided according to the claims.

    [0011] Additional features of the invention will be set forth in the description, which follows, and in part will be apparent from the description, or may be learned by practice of the invention.

    [0012] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

    Brief Description of Drawings



    [0013] The above and other objects, features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the accompanying drawings.

    FIG. 1a is a cross-sectional view illustrating a thin film transistor (TFT).

    FIG. 1b is a cross-sectional view illustrating a thin film transistor 100B.

    FIGS. 2a through 2c are pictorial representations (through a cross sectional view) depicting an exemplary thin film transistors.

    FIGS. 3a and 3b are pictorial representations (through a cross sectional view) depicting an exemplary thin film transistors.

    FIGS. 4a and 4b are pictorial representations (through a cross sectional view) depicting an exemplary thin film transistors according to embodiments of the present invention.

    FIG. 5 is a cross-sectional view illustrating a thin film transistor.

    FIG. 6 is a graph for explaining the light reliability of a thin film transistor, according to an embodiment of the present invention;

    FIGS. 7a and 7b are cross-sectional views illustrating a thin film transistor.

    FIG. 8 illustrates manufacturing a device including a thin film transistor.


    DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS



    [0014] The following detailed description is made with reference to the figures. Exemplary embodiments are described to illustrate the claimed invention, not to limit its scope, which is defined by the appended claims. Throughout the present disclosure, it should be appreciated that references to an element formed "on" a layer are interpreted as an element formed directly on the referenced layer as well as the configuration in which an extra element is formed between the element and the referenced layer. Also, it should be appreciated that references to "one embodiment," "an embodiment," "some embodiments," are the likes are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the disclosed features.

    [0015] Dimensions of the embodiments depicted in the figures are scaled for clearer explanation, and it should be appreciated that the embodiments are not limited the disclosed dimensions.

    [0016] FIG. 1a is a cross-sectional view illustrating a thin film transistor (TFT) 1100A. Referring to FIG. 1a, the thin film transistor 100A includes a flexible substrate 110, a buffer layer 120, an active layer 130A, a gate insulating film 160, a gate electrode 140, an interlayer insulating film 170, a source electrode 151, and a drain electrode 152.

    [0017] The flexible substrate 110 is a substrate for supporting and protecting various elements that may be formed thereon. The flexible substrate 110 is a lower support plate located in a bottom of the thin film transistor 100A. The flexible substrate 110 may be formed of various materials according to various applications using the thin film transistor 100A. For example, when the thin film transistor 100A is used in a flexible application such as a flexible display device, the flexible substrate 110 may be formed of a flexible insulating material. Examples of the flexible insulating material may include polyimide (PI), polyetherimide (PEI), polyethylene terephthalate (PET), polycarbonate (PC), polystyrene (PS), styrene acrylonitrile copolymer, and silicon-acrylic resin. Also, when the thin film transistor 100A is used in an application having a high transmittance such as a transparent display device, the flexible substrate 110 may be formed of a flexible transparent insulating material.

    [0018] An active layer 130A, which is formed of an oxide semiconductor, is formed on the flexible substrate 110. In the present disclosure, the active layer 130A may be referred to as an oxide semiconductor layer. The active layer 130A may be formed by depositing an oxide semiconductor material on the flexible substrate 110 and then patterning the oxide semiconductor material to leave only an oxide semiconductor having a size enough to form the active layer 130A.

    [0019] The oxide semiconductor of the active layer 130A may be various metal oxides. For example, examples of a material for the oxide semiconductor may include a quaternary metal oxide such as an indium tin gallium zinc oxide (InSnGaZnO)-based material, a ternary metal oxide such as an indium gallium zinc oxide (InGaZnO)-based material, an indium tin zinc oxide (InSnZnO)-based material, an indium aluminum zinc oxide (InAlZnO)-based material, an indium hafnium zinc oxide (InHfZnO), a tin gallium zinc oxide (SnGaZnO)-based material, an aluminum gallium zinc oxide (AlGaZnO)-based material, or a tin aluminum zinc oxide (SnAlZnO)-based material, and a binary metal oxide such as an indium zinc oxide (InZnO)-based material, a tin zinc oxide (SnZnO)-based material, an aluminum zinc oxide (AlZnO)-based material, a zinc magnesium oxide (ZnMgO)-based material, a tin magnesium oxide (SnMgO)-based material, an indium magnesium oxide (InMgO)-based material, an indium gallium oxide (InGaO)-based material, an indium oxide (InO)-based material, a tin oxide (SnO)-based material, or a zinc oxide (ZnO)-based material. A composition ratio of elements included in each of the materials used to form the oxide semiconductor is not limited and may be variously adjusted.

    [0020] The thin film transistor 100A includes a gate electrode 140, which is formed to overlap at least a portion of the active layer 130A. The gate electrode 140 is formed of a conductive material. In some examples, the gate electrode 140 may be formed of a metal, and may reflect light. The gate electrode 140 may be formed of any one of, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and an alloy thereof. However, the present embodiment is not limited thereto, and the gate electrode 140 may be formed of any of various materials. Also, the gate electrode 140 may have a multi-layered structure including a material selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, and an alloy thereof.

    [0021] The thin film transistor 100A further includes a source electrode 151 and a drain electrode 152. Each of the source electrode 151 and the drain electrode 152 may be formed of a conductive material. Each of the source electrode 151 and the drain electrode 152 may be formed of a metal, and may reflect light. Each of the source electrode 151 and the drain electrode 152 may be formed of any one of, for example, Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, and an alloy thereof. However, the present example is not limited thereto, and each of the source electrode 151 and the drain electrode 152 may be formed of various materials. Also, each of the source electrode 151 and the drain electrode 152 may have a multi-layered structure including a material selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, and an alloy thereof.

    [0022] The source electrode 151 and the drain electrode 152 are electrically connected to the source region and the drain region of the active layer 130A, respectively, through the contact holes formed in the interlayer insulating film 170 and/or the gate insulating film 160. An upper channel region is formed between the source region and the drain region of the active layer 130A. The upper channel region is formed in an upper portion of the active layer 130A adjacent to the gate electrode 140.

    [0023] The source electrode 151, the drain electrode 152, and the gate electrode 140 cover a top surface of the active layer 130A including the oxide semiconductor. Since each of the source electrode 151, the drain electrode 152, and the gate electrode 140 may be formed of a metal and may reflect light as described above, the source electrode 151, the drain electrode 152, and the gate electrode 140 protect the active layer 130A from external light incident on the active layer 130A. In particular, since materials used for a substrate that supports the thin film transistor 100A are generally transparent materials, external light may be incident from the bottom of the active layer 130A. In addition, when the thin film transistor 100A employed in a bottom emission organic light-emitting display (OLED) device, the light emitted from an organic emission layer can reach the thin film transistor 100A, and thus the reliability of the thin film transistor 100A may be reduced. Also, when the thin film transistor 100A is applied to a liquid crystal display (LCD) device using a separate backlight unit, the reliability of the thin film transistor 100A may be reduced due to light incident on the active layer 130A from the backlight unit. For simpler explanation, the term "external light" is used in the present disclosure to refer any light incident on the active layer 130A, irrespective of the source or the direction of the light from the source.

    [0024] Various insulating materials and/or layers are used to electrically insulate the elements of the thin film transistor 100A. The gate insulating film 160 is formed on the active layer 130A, and insulates the active layer 130A and the gate electrode 140. The gate insulating film 160 may be formed of a single layer of a silicon oxide film or a silicon nitride film, or a multiple-layered structure thereof. However, the present example is not limited thereto and the gate insulating film 160 may be formed of various materials. The gate insulating film 160 only needs to insulate the active layer 130A and the gate electrode 140. Accordingly, in FIG. 1a, the gate insulating film 160 is formed only on the active layer 130A. Alternatively, the gate insulating film 160 may be formed over the entire flexible substrate 110 including the active layer 130A. When the gate insulating film 160 is formed over the entire flexible substrate 110, the gate insulating film 160 may be formed to have contact holes through which portions of the active layer 130A are exposed, and the contact holes may expose a portion of the source region and a portion of the drain region of the active layer 130A.

    [0025] In FIG. 1a, the gate electrode 140 is illustrated as having substantially the same size with the gate insulating film 160. That is, the contacting surface of the gate electrode 140 and the contacting surface of the gate insulating film 160 interfacing each other have the substantially the same size. In the present disclosure, the two elements are said to have "substantially the same size" even when the two elements do not have the exact same size caused by fabrication process (i.e., deviation due to the fabrication process). For instance, either the gate electrode 140 or the gate insulating film 160 may be formed slightly larger than the other element due to being over-etched during the fabrication process. In such a case, the gate electrode 140 and the gate insulating film 160 may be formed to have a tapered shape such that the surface of the gate electrode 140 and the surface of gate insulating film 160 at the interface have slightly different sizes.

    [0026] The interlayer insulating film 170 is formed on the gate electrode 140. The interlayer insulating film 170 may be formed of the same material as that of the gate insulating film 160, and may be formed to include a silicon oxide film, a silicon nitride film, or a multi-layer structure thereof. However, the present example is not limited thereto, and the interlayer insulating film 170 may be formed of various materials. The interlayer insulating film 170 is formed over the entire flexible substrate 110, and includes contact holes for exposing a portion of the source region and a portion of the drain region of the active layer 130A.

    [0027] The buffer layer 120 is formed on the flexible substrate 110. The buffer layer 120 is formed between the flexible substrate 110 and the active layer 130A. The buffer layer 120 reduces permeation of moisture or other impurities through the flexible substrate 110, and further, planarizes the surface of the flexible substrate 110. The buffer layer 120 includes a reflective metal layer 121 and an insulating layer 122. A material for the insulating layer 122 may be selected according to a type of the flexible substrate 110 or a type of the thin film transistor 100A. For example, the insulating layer 122 may be selected according to interfacial characteristics between the insulating layer 122 and the active layer 130A according to a structure of the thin film transistor 100A. In the thin film transistor 100A having the coplanar structure as shown in FIG. 1a, the insulating layer 122 may be formed of a silicon oxide film, a silicon nitride film, or a multi-layered structure thereof.

    [0028] The buffer layer 120 protects the oxide semiconductor that constitutes the active layer 130A by hindering the progress of external light towards the oxide semiconductor. The reflective metal layer 121 is disposed in the buffer layer 120, and surrounded by the insulating layer 122. Since the reflective metal layer 121 blocks the external light, the reflective metal layer 121 may be referred to as a shielding layer or a light-shielding layer. While the external light projecting perpendicular to the oxide semiconductor can be reflected by the reflective metal layer 121, light projected in some other angle may still reach the oxide semiconductor. In order to optimize blocking of the external light projecting towards the active layer 130A, the distance between the active layer 130A and the reflective metal layer 121 may be equal to or less than 3 µm.

    [0029] When light is incident on the active layer 130A while bias voltage is applied to the thin film transistor 100A, pairs of electrons and holes are broken in the active layer 130A to generate electrons in a channel region. This changes the operating characteristics of the oxide semiconductor. For example, the electrons may be generated in the channel region and causes the threshold voltage Vth of the thin film transistor 100A to fluctuate, thereby making the thin film transistor 100A unreliable for its intended use.

    [0030] Referring to FIG. 1a, in the thin film transistor 100A, the reflective metal layer 121 is disposed to overlap the active layer 130A, and the size of the reflective metal layer 121 may be equal to or greater than that of the active layer 130A such that the reflective metal layer 121 entirely overlaps the active layer 130A. More specifically, the size of the reflective metal layer 121 can be equal to or greater than the channel region defined by the gate electrode 140. Accordingly, the reflective metal layer 121 may shield active layer 130A from the external light, along with the gate electrode 140, the source electrode 151, and the drain electrode 152. In particular, the reflective metal layer 121 serves to block external light incident from the bottom of the active layer 130A, thereby shielding the bottom surface of the active layer 130A.

    [0031] FIG. 1b is a cross-sectional view illustrating a thin film transistor. In FIGS. 1a and 1b, elements denoted by the same reference numerals with different English alphabets are substantially the same, and thus a repeated explanation thereof will not be given.

    [0032] An active layer 130B is formed on a buffer layer 120 such that the active layer 130B is formed over the entire buffer layer 120. The active layer may be formed by depositing an oxide semiconductor material on the buffer layer 120 and then patterning the oxide semiconductor material to leave only an oxide semiconductor having a size enough to form the active layer. This process, however, requires an additional mask process for patterning the oxide semiconductor material, complicating the manufacturing process and increasing the production costs. In the thin film transistor 100B illustrated in FIG. 1b, however, the active layer 130B is formed over the entire buffer layer 120. In this setting, the aforementioned mask process is not needed, and thus simplifies the overall fabrication process and reduces the production cost of the thin film transistor. Further, with the reduced tact time, manufacturing yield may also improve.

    [0033] A reflective metal layer 121 of the buffer layer 120 may completely overlap at least a portion of the gate electrode 140. In the example shown in FIG. 1b, the reflective metal layer 121 is formed to be larger than the gate electrode 140, and thus overlaps the channel region defined by gate electrode 140. However, the reliability of the thin film transistor 100B can be maintained so long as the channel region of the active layer 130B is shielded from the external light. Accordingly, the size of the reflective metal layer 121 can vary depending on the size of the channel region as well as the vertical distance between the reflective metal layer 121 and the active layer 130B.

    [0034] In some examples, the thin film transistor includes a plurality of insulating layers with different refractive indices to shield the oxide semiconductor from the external light. As shown in FIG. 2a, a buffer layer 220A includes a first insulating layer 222A, a reflective metal layer 221A, and a second insulating layer 223A, which are sequentially disposed between the flexible substrate 210 and the active layer 230. In addition to reducing permeation of light, the difference between the refractive indices of the first insulating layer 222A and the second insulating layer 223A causes the external light entering from the bottom of the flexible substrate 210 to be reflected at the interface of the first and the second insulating layers (222A, 223A).

    [0035] In the exemplary thin film transistor 200A, the reflective metal layer 221A is configured to protect the active layer 230 from the external light incident from the bottom of the flexible substrate 210 at the region where the reflective meal layer 221A overlaps the active layer 230. In the non-overlapping region, the multi-layered buffer layer 220A including the first insulating layer 222A and the second insulating layer 223A protects the active layer 230 from external light projected in an angle towards the active layer 230.

    [0036] When light moves from a medium having a high refractive index to a medium having a low refractive index, light incident at an incident angle greater than a critical angle at an interface between the media does not pass through the interface between the media and is totally reflected. For example, the first insulating layer 222A may be a silicon nitride film having a refractive index of 1.8, and the second insulating layer 223A may be a silicon oxide film having a refractive index of 1.45. Accordingly, the light traveling through the insulating layers (222A, 223A) at an incident angle greater than the critical angle cannot pass through buffer layer 220A due to the total internal reflection at the interface between the first insulating layer 222A and the second insulating layer 223A.

    [0037] An increase in the total internal reflection of light within the buffer layer can be obtained by providing additional number of insulating layers with different refractive indices. Depending on the total number of insulation layers and the difference between their refractive indices, the stability of the thin film transistor can be maintained even without employing the reflective metal layer. The buffer layer 220B of the example shown in FIG. 2b is formed with a stack of four insulation layers. The first insulating layer 222B and the third insulating layer 224B can be formed to have the same refractive index, while the second insulating layer 223B and the fourth insulating layer 225B have the same refractive index. For instance, the first insulating layer 222B and the third insulating layer 224B may be formed of silicon nitride having refractive indices of 1.8, while the second insulating layer 223B and the fourth insulating layer 225B may be formed of silicon oxide having refractive indices of 1.45. The materials for forming the insulating layers and the stacking order of the insulating layers are not limited by this example. As such, the materials for forming each of the insulating layers can be selected from a variety of materials, and the insulating layers can be arranged so that more total internal reflection of the external light occurs at the interfaces between the two adjacent insulating layers. For example, the insulation layer of the buffer layer 230 may be disposed on the substrate 210 in the order of their refractive index so that the insulation layer with higher refractive index is formed closer to the source of external light and the insulation layer with lower refractive index is formed closer to the active layer 230..

    [0038] In one example, the reflective metal layer described above can be used in conjunction with the stack of insulating layers to further enhance the protection afforded by the buffer layer. In FIG. 2c, the reflective metal layer 221C is illustrated as being formed directly on the substrate 210 or within the first insulating layer 222C, and additional insulating layers (e.g., second, third and fourth insulation layers 223C, 224C, 225C) are disposed on the reflective metal layer 221C and the first insulating layer 222C. As previously discussed, the amount of light reaching the active layer 230 can vary based on the distance between the reflective metal layer 221C and the active layer 230. Similarly, the reflective metal layer 221C may be disposed on or within other insulation layers, which may be closer to or farther away from the active layer 230 by considering a variety of factors including, but are not limited to, the size of the channel region in the active layer 230, the angle of light projected from the light source and/or difference of refractive indices between the insulation layers.

    [0039] FIG. 3a is a cross-sectional view illustrating a thin film transistor 300A. A flexible substrate 310, an active layer 330, a gate insulating film 360, and a gate electrode 340 of FIG. 3a are substantially the same as the flexible substrate 110, the active layer 130A, the gate insulating film 160, and the gate electrode 140 of FIG. 1a.

    [0040] An interlayer insulating film 370 is formed on the gate electrode 340. The interlayer insulating film 370 may be formed of the same material as that of the gate insulating film 360, for example, silicon oxide, silicon nitride and the likes. Likewise, the interlayer insulating film 370 may be formed as a stack of layers that are formed of such materials. The interlayer insulating film 370 may be formed over the entire flexible substrate 310, and include contact holes that expose some portions of the active layer 330. As illustrated in FIG. 3a, the contact holes can be formed to expose at least a portion of each side surface of the active layer 330. Additionally, the contact holes may further expose at least portions of the upper surface of the active layer 330. Otherwise, the interlayer insulating film 370 is substantially the same as the interlayer insulating film 170 of FIG. 1a.

    [0041] The source electrode 351 and the drain electrode 352 are formed on the interlayer insulating film 370. The source electrode 351 and the drain electrode 352 may be electrically connected to a source region and a drain region of the active layer 330 through the contact holes formed in the interlayer insulating film 370 and/or the gate insulating film 360. Accordingly, the source electrode 351 and the drain electrode 352 contact at least portions of the side surface of the active layer 330, and additionally contact at least portions of the upper surface of the active layer 330. In this setting, the contact surface areas between the active layer 330 and the source electrode 351 and between the active layer 330 and the drain electrode 352 are increased, thereby reducing the resistances between the active layer 330, and the source electrode 351 and the drain electrode 352. In addition, due to the aforementioned configuration, the source electrode 351 and the drain electrode 352 can be utilized to protect the active layer 330 from the external light incident from the side surface and the upper surface of the active layer 330. Otherwise, the source electrode 351 and the drain electrode 352 are substantially the same as the source electrode 131 and the drain electrode 132 of FIG. 1a.

    [0042] FIG. 3b is a cross-sectional view illustrating a thin film transistor 300B which has been modified from the thin film transistor 300A. Namely, a buffer layer 320, which includes a reflective metal layer 321 and an insulating layer 322, exists between the substrate 310 and the active layer 330. Accordingly, due to the aforementioned configuration, the reflective metal layer 321 can be utilized to additionally protect the active layer 330 from the external light incident from the bottom surface of the active layer 330.

    [0043] FIG. 4a is a cross-sectional view illustrating a thin film transistor 400A according to the invention which has been modified from the thin film transistor 300A of FIG. 3a. Namely, the contact holes formed through the interlayer insulating film 470 and/or gate insulating film 460 have a different configuration from the contact holes of FIG. 3a. The contact holes are angled (i.e. sloped and not perpendicular to the substrate 410) towards the active layer 430 such that only the side surfaces of the active layer 430 are exposed. By employing such angled contact holes, the fabrication of the active layer 430, the gate insulating film 460 and the gate electrode 440 can be simplified. For example, the number of masks used in fabricating the thin film transistor 400A can be reduced in comparison to that of the thin film transistor 300A in FIG. 3a.

    [0044] Accordingly, due to the aforementioned configuration, the source and drain electrodes 451, 452 formed in the angled contact holes can be utilized to protect the active layer 430 from the external light incident from the side surface of the active layer 430. Additionally, due to the shape of the contact holes, the gate electrode 440 is substantially the same size as the active layer 430.

    [0045] FIG. 4b is a cross-sectional view illustrating a thin film transistor 400B according to the invention which has been modified from the thin film transistor 400A. Namely, a buffer layer 420, which includes a reflective metal layer 421 and an insulating layer 422, exists between the substrate 410 and the active layer 430. Accordingly, due to the aforementioned configuration, the reflective metal layer 421 can be utilized to additionally protect the active layer 430 from the external light incident from the bottom surface of the active layer 430.

    [0046] FIG. 5 is a cross-sectional view illustrating a thin film transistor 500, which combines the features of certain examples described above. The thin film transistor 500 includes various light blocking elements (e.g. buffer layers 520, reflective metal layer 521, source/drain electrodes 551,552) to shield the bottom and side surfaces of the active layer 530 from light. That is, the thin film transistor 500 employs the buffer layer 520 including the reflective metal layer 521, and also employs source/drain electrodes (551, 552) that cover the side surfaces of the active layer 530 to maintain the stability of the thin film transistor 500. The reflective metal layer 521 protects the bottom surface of the active layer 530 from the external light. The stack of insulating layers (522, 523, 524, 525) in the buffer layer 520 have different refractive indices and thus reflects the light projected towards the active layer 530 at an angle greater than the critical angle. The source/drain electrodes (551, 552) shield the active layer 530 from the external light incident from the side. The use of different types of light blocking elements thus provides a high degree of protection against external light.

    [0047] FIG. 6 is a graph for explaining the light reliability of a thin film transistor that employs some of the features described above. In particular, the graph of FIG. 6 represents the relationship between the changes in threshold voltage and the light exposure time of the thin film transistor. The dashed line represents the changes in the threshold voltage of a thin film transistor, which does not use the buffer layer described in the present disclosure. The solid line represents the changes in the threshold voltage of a thin film transistor, which uses the buffer layer including a plurality of insulation layers with difference refractive indices. As shown in the graph, it is found that the decrease in the threshold voltage of the thin film transistor in a given time is significantly lower in the thin film transistor utilizing the plurality of insulating layers than the thin film transistor without the insulating layers. Referring to FIG. 6, at six hours of the light exposure time, the changes in the threshold voltage was found to be -6.00 when a plurality of insulation layers is used. In contrast, at six hours of the light exposure time, the changes in the threshold voltage were found to be -8.00 when a plurality of insulation layers is not used. Accordingly, such difference in the changes in the threshold voltage denotes that the negative bias illumination thermal stress (NBITS) is improved about 25% in comparison to the case where the buffer layer is not formed with the plurality of insulation layers. When the reflective metal layer is additionally used, the NBITS can be additionally improved.

    [0048] FIGS. 7a and 7b are cross-sectional views illustrating a thin film transistor 700A, 700B. A flexible substrate 710, a buffer layer 720, an active layer 730, a gate insulating film 760, a gate electrode 740, an interlayer insulating film 770, a source electrode 751, and a drain electrode 752 of FIGS. 7a and 7b are substantially the same as those of FIG. 1a.

    [0049] The reflective metal layer 721 causes an additional channel region to be formed at the lower portion of the active layer 730. In order to provide the additional channel region, a reflective metal layer 721 included in the buffer layer 720 is electrically connected to the gate electrode 740. Such structure may be referred to as a dual gate structure.

    [0050] Accordingly, when the gate electrode 740 and reflective metal layer 721 are commonly addressable, the same voltage can be applied to the gate electrode 740 and the reflective metal layer 721. In detail, when a voltage is applied to the gate electrode 740 and the reflective metal layer 721, charges are accumulated at the interface between the active layer 730 and the gate insulating film 760 to form an upper channel region 731, and charges are accumulated at the interface between the active layer 730 and the insulating layer 722 of the buffer layer 720 to form a lower channel region 732. When using the reflective metal layer 721 for forming the lower channel region 732, the reflective metal layer 721 and the active layer 730 should be spaced apart by a predetermined distance that is sufficient to form the lower channel region 732. For example, the distance between the reflective metal layer 721 and the active layer 730 may range from 500 Å to 2000 Å. It should be noted that the distance between the reflective metal layer 721 and the active layer 730 may be greater (e.g., 3 microns) if the reflective metal layer 721 is only used for the purpose of shielding light without having to provide a lower channel region 732 for the dual gate structure.

    [0051] Since an area where charges may move in the thin film transistor 700A having a dual gate structure is greater than an area in a thin film transistor having a single gate structure, a channel resistance of the thin film transistor 700A, that is, a resistance between the active layer 730, and the source electrode 751 and the drain electrode 752 may be reduced. Because the upper channel region 731 and the lower channel region 732 are formed on both surfaces of the active layer 730, the mobility, the off-current Ioff (i.e., reduced) and the on-current Ion (i.e., increased) characteristics of the thin film transistor 700A can be improved. In addition, if the reflective metal layer 721 is configured as an individually addressable gate electrode (i.e., separate from the gate electrode 740) the threshold voltage Vth of the thin film transistor 700A can be easily adjusted to a desired level by adjusting a magnitude of a bias voltage.

    [0052] Referring to FIG. 7b, the gate electrode 740 is branched out from a gate line 741 electrically connected to a pad unit (not shown) for receiving a variety of signals for controlling the thin film transistor 700B. The reflective metal layer 721 is electrically connected to at least a portion of the gate line 741 via a contact hole formed through the buffer layer 720 and/or the interlayer insulating film 770.

    [0053] Thin film transistors according to various embodiments of the present invention may be used in various applications. For example, the thin film transistors may be used in various display devices having different types of display elements operatively connected to and controlled by thin film transistors. Examples of such display devices are an organic light-emitting display device, an LCD device and an electric paper display (EPD) device. As for the OLED device, each sub pixel typically employs a switching transistor and a driving transistor. The switching transistor transfers a data signal to the driving transistor, which controls the organic emission layer to emit light at a pixel or sub pixel. The OLED device may further include a thin film transistor for a compensation circuit that prevents an abnormal operation of the OLED device. Any one of these thin film transistors in the OLED device may be any of the exemplary thin film transistors described in the present disclosure. Also, the LCD device includes a plurality of pixel regions, and includes a plurality of thin film transistors for independently driving the plurality of pixel regions, and the plurality of thin film transistors used in the LCD device may also be any of the exemplary thin film transistors described in the present disclosure. The EPD device includes a lower substrate, an upper substrate, a pixel electrode, a common electrode, and an optical medium layer. The optical medium layer is disposed between the upper substrate and the lower substrate, and includes a fluid and color charged particles dispersed in the fluid. The EPD device includes a plurality of thin film transistors for independently driving the plurality of pixel regions. When using the thin film transistors described herein, the operating stability and performance of the OLED, LCD or EPD device can be improved.

    [0054] Such devices may be implemented as a transparent display device. In order to show the object behind the display device, the external light must be able to pass through the display device to some extent, and may degrade the stability of a thin film transistor using the oxide semiconductor. As such, the thin film transistor described in the present disclosure can be employed in the transparent display device to maintain the operation stability of the device.

    [0055] Referring to FIG. 8, the thin film transistors 800 shown in examples described above formed on a flexible substrate 810 may be supported by a support substrate 815 used as a temporary base for supporting and protecting the flexible substrate 810 during the fabrication process. Such support substrate 815 needs to be removed or released. During the removal or release process, the active layer 830 may be subjected to external light. However, because of the reflective metal layer 821 and/or one or more insulation layers according to the examples described herein, the active layer 830 is protected from such external light during the removal or release process.

    [0056] The present invention has been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

    [0057] The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

    [0058] The breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.


    Claims

    1. A thin film transistor (400A; 400B) comprising:

    an oxide semiconductor layer (430) formed on a flexible substrate (410);

    a gate electrode (440) formed on the oxide semiconductor layer (430), a first surface of the oxide semiconductor layer (430) facing the gate electrode (440);

    a source electrode (451) and a drain electrode (452) electrically connected to the oxide semiconductor layer (430), respectively, the oxide semiconductor layer (430), gate electrode (440), source electrode (451) and drain electrode (452) arranged in a coplanar transistor configuration; and

    a light-blocking element (451, 452) arranged to shield a second surface of the oxide semiconductor layer (430) from external light,

    wherein the second surface of the oxide semiconductor layer (430) is a side surface of the oxide semiconductor layer (430), the light-blocking element (451, 452) shielding the side surface of the oxide semiconductor layer (430) from the external light,

    wherein the light-blocking element (451, 452) comprises:

    a portion of at least one of the drain electrode (452) and the source electrode (451) that covers the side surface of the oxide semiconductor layer (430),

    wherein the at least one of the drain electrode (452) and the source electrode (451) contacts only the second surface of the oxide semiconductor layer (430).


     
    2. The thin film transistor (400A; 400B) of claim 1, wherein the at least one of the drain electrode and (452) the source electrode (451) angles towards the oxide semiconductor layer (430).
     
    3. The thin film transistor (400A; 400B) of any one of claims 1 or 2, further comprising an interlayer insulating film (470) formed on the gate electrode (440) and on the flexible substrate (410).
     
    4. The thin film transistor (400A; 400B) of claims 2 and 3, wherein the interlayer insulating film (470) comprises contact holes angled towards the oxide semiconductor layer (430) such that only the side surfaces of the oxide semiconductor layer (430) are exposed.
     
    5. The thin film transistor (400A; 400B) of claim 4, wherein the contact holes comprise:

    a first contact hole in the interlayer insulating film (470) exposing a first side surface of the oxide semiconductor layer (430); and

    a second contact hole in the interlayer insulating film (470) exposing a second side surface of the oxide semiconductor layer (430).


     
    6. The thin film transistor (400A; 400B) of claim 5, wherein the source electrode (451) contacts the first side surface of the oxide semiconductor layer (430) via the first contact hole and the drain electrode (452) contacts the second side surface of the oxide semiconductor layer (430) via the second contact hole.
     


    Ansprüche

    1. Dünnfilmtransistor (400A; 400B), aufweisend:

    eine Oxidhalbleiterschicht (430), die auf einem flexiblen Substrat (410) ausgebildet ist;

    eine Gateelektrode (440), die auf der Oxidhalbleiterschicht (430) ausgebildet ist, wobei eine erste Oberfläche der Oxidhalbleiterschicht (430) der Gateelektrode (440) zugewandt ist;

    eine Sourceelektrode (451) und eine Drainelektrode (452), die jeweils elektrisch mit der Oxidhalbleiterschicht (430) verbunden sind, wobei die Oxidhalbleiterschicht (430), die Gateelektrode (440), die Sourceelektrode (451) und die Drainelektrode (452) in einer koplanaren Transistorkonfiguration angeordnet sind, und

    ein lichtblockierendes Element (451, 452), das angeordnet ist, um eine zweite Oberfläche der Oxidhalbleiterschicht (430) gegen externes Licht abzuschirmen,

    wobei die zweite Oberfläche der Oxidhalbleiterschicht (430) eine Seitenoberfläche der Oxidhalbleiterschicht (430) ist, wobei das lichtblockierende Element (451, 452) die Seitenoberfläche der Oxidhalbleiterschicht gegen das externe Licht abschirmt,

    wobei das lichtblockierende Element (451, 452) aufweist:

    einen Abschnitt von mindestens einer der Drainelektrode (452) und der Sourceelektrode (451), der die Seitenfläche der Oxidhalbleiterschicht (430) bedeckt,

    wobei die mindestens eine der Drainelektrode (452) und der Sourceelektrode (451) nur die zweite Oberfläche der Oxidhalbleiterschicht (430) kontaktiert.


     
    2. Dünnfilmtransistor (400A, 400B) nach Anspruch 1, wobei die mindestens eine der Drainelektrode (452) und der Sourceelektrode (451) in Richtung der Oxidhalbleiterschicht (430) abgewinkelt ist.
     
    3. Dünnfilmtransistor (400A, 400B) nach einem der Ansprüche 1 oder 2, ferner aufweisend einen auf der Gateelektrode (440) und auf dem flexiblen Substrat (410) ausgebildeten Zwischenschichtisolierfilm (470).
     
    4. Dünnfilmtransistor (400A, 400B) nach Anspruch 2 und 3, wobei der Zwischenschichtisolierfilm (470) Kontaktlöcher aufweist, die in Richtung der Oxidhalbleiterschicht (430) derart abgewinkelt sind, dass nur die Seitenoberflächen der Oxidhalbleiterschicht (430) freigelegt sind.
     
    5. Dünnfilmtransistor (400A, 400B) nach Anspruch 4, wobei die Kontaktlöcher aufweisen:

    ein erstes Kontaktloch in dem Zwischenschichtisolierfilm (470), das eine erste Seitenfläche der Oxidhalbleiterschicht (430) freilegt, und

    ein zweites Kontaktloch in dem Zwischenschichtisolierfilm (470), das eine zweite Seitenfläche der Oxidhalbleiterschicht (430) freilegt.


     
    6. Dünnfilmtransistor (400A, 400B) nach Anspruch 5, wobei die Sourceelektrode (451) die erste Seitenoberfläche der Oxidhalbleiterschicht (430) durch das erste Kontaktloch kontaktiert und die Drainelektrode (452) die zweite Seitenoberfläche der Oxidhalbleiterschicht (430) durch das zweite Kontaktloch kontaktiert.
     


    Revendications

    1. Transistor à couches minces (400A ; 400B) comprenant :

    une couche oxyde - semi-conducteur (430) formée sur un substrat souple (410) ;

    une électrode de grille (440) formée sur la couche oxyde - semi-conducteur (430), une première surface de la couche oxyde - semi-conducteur (430) faisant face à l'électrode de grille (440) ;

    une électrode de source (451) et une électrode de drain (452) connectées électriquement à la couche oxyde - semi-conducteur (430), respectivement, la couche oxyde - semi-conducteur (430), l'électrode de grille (440), l'électrode de source (451) et l'électrode de drain (452) étant agencées en une configuration de transistor coplanaire ; et

    un élément de blocage de la lumière (451, 452) étant agencé afin de protéger la seconde surface de la couche oxyde - semi-conducteur (430) de la lumière extérieure,

    où la seconde surface de la couche oxyde - semi-conducteur (430) est une surface latérale de la couche oxyde - semi-conducteur (430), l'élément de blocage de la lumière (451, 452) protégeant la surface latérale de la couche oxyde - semi-conducteur (430) de la lumière extérieure,

    où l'élément de blocage de la lumière (451, 452) comprend :
    une partie de l'une au moins de l'électrode de drain (452) et de l'électrode de source (451) qui couvre la surface latérale de la couche oxyde - semi-conducteur (430), où l'électrode de drain (452) et / ou l'électrode de source (451) entrent en contact seulement avec la seconde surface de la couche oxyde - semi-conducteur (430).


     
    2. Transistor à couches minces (400A ; 400B) selon la revendication 1, où l'électrode de drain (452) et / ou l'électrode de source (451) font un angle vers la couche oxyde - semi-conducteur (430).
     
    3. Transistor à couches minces (400A ; 400B) selon la revendication 1 ou 2, comprenant en outre un film isolant de couche intermédiaire (470) formé sur l'électrode de grille (440) et sur le substrat souple (410).
     
    4. Transistor à couches minces (400A ; 400B) selon les revendications 2 et 3, où le film isolant de couche intermédiaire (470) comprend des trous de contact qui font un angle vers la couche oxyde - semi-conducteur (430) de telle sorte que seules les surfaces latérales de la couche oxyde - semi-conducteur (430) soient exposées.
     
    5. Transistor à couches minces (400A ; 400B) selon la revendication 4, où les trous de contact comprennent :

    un premier trou de contact dans le film isolant de couche intermédiaire (470) exposant une première surface latérale de la couche oxyde - semi-conducteur (430) ; et

    un second trou de contact dans le film isolant de couche intermédiaire (470) exposant une seconde surface latérale de la couche oxyde - semi-conducteur (430).


     
    6. Transistor à couches minces (400A ; 400B) selon la revendication 5, où l'électrode de source (451) entre en contact avec la première surface latérale de la couche oxyde - semi-conducteur (430) par l'intermédiaire du premier trou de contact, et l'électrode de drain (452) entre en contact avec la seconde surface latérale de la couche oxyde - semi-conducteur (430) par l'intermédiaire du second trou de contact.
     




    Drawing


















    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description