(19)
(11)EP 2 950 438 A1

(12)EUROPEAN PATENT APPLICATION
published in accordance with Art. 153(4) EPC

(43)Date of publication:
02.12.2015 Bulletin 2015/49

(21)Application number: 13898642.7

(22)Date of filing:  04.12.2013
(51)International Patent Classification (IPC): 
H02M 7/48(2007.01)
(86)International application number:
PCT/CN2013/088535
(87)International publication number:
WO 2015/081517 (11.06.2015 Gazette  2015/23)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME

(71)Applicant: Sungrow Power Supply Co., Ltd.
Hefei, Anhui 230088 (CN)

(72)Inventors:
  • HU, Bing
    Hefei Anhui 230088 (CN)
  • XUE, Liying
    Hefei Anhui 230088 (CN)
  • ZHANG, Yanhu
    Hefei Anhui 230088 (CN)
  • ZHOU, Lingbing
    Hefei Anhui 230088 (CN)

(74)Representative: Bösl, Raphael Konrad 
Isenbruck Bösl Hörschler LLP Patentanwälte Prinzregentenstraße 68
81675 München
81675 München (DE)

  


(54)FIVE LEVEL INVERTER


(57) A five level inverter comprises six switch tubes (QH1, QH2, QL1, QL2, QL3, QL4), two inductors (L1, L2), four capacitor units (C1, C2, C3, C4) and two reverse current preventing devices (D1, D2). The common terminal of the third capacitor unit (C3) and the fourth capacitor unit (C4) is connected with the common terminal of the first capacitor unit (C1) and the second capacitor unit (C2). The third capacitor unit (C3) and the fourth capacitor unit (C4) are used as the output filter circuit of the inverter, and the common terminal of the third capacitor unit (C3) and the fourth capacitor unit (C4) is used as the midpoint of the DC bus. In the inverter, the electric potential of the midpoint of the DC bus or the positive or the negative pole of the DC power supply (DC) relative to the midpoint of the output filter circuit is relatively stable, and surge voltage with power frequency or high frequency relative to ground will not occur at the positive or the negative pole of the DC bus, thus the leakage current problem will not appear. Additionally, the output efficiency of the five level inverter is relatively high, so that the five level inverter is adapted to the application field of photovoltaic power generation and so on.




Description

FIELD



[0001] The disclosure relates to the technical field of power electronics, and in particular to a five-level inverter.

BACKGROUND



[0002] An inverter, which is adapted to convert a direct-current voltage outputted from a direct-current power supply into an alternative-current voltage and output the alternative-current voltage to a load circuit, is widely used in the field of photovoltaic power generation and wind power generation. However, a parasitic capacitance between the direct-current power supply (for example, a solar panel) and ground may produce a leakage current during operation of the inverter, which can be problematic because the leakage current would impair the quality of the outputted electric power, reduce the efficiency of the inverter, and harm the human body, thereby reducing reliability of the inverter.

[0003] Currently, inverters with various topologies such as H5, H6 and HERIC have been developed to address the problem of current leakage. However, these inverters are three-level inverter with lower efficiency. In contrast, a five-level inverter has a higher efficiency. Currently, there is an increasing interest in reducing the leakage current in the five-level inverter. For example, an existing five-level inverter is shown in Figure 1. During operation of the five-level inverter, a power-frequency jump in a potential of a positive pole of the direct-current power supply DC, relative to a negative pole of the output, i.e. point C, may occur. The power-frequency jumping voltage, when applied across a parasitic capacitor between the positive pole (or the negative pole) of the direct-current power supply DC and ground, may produce a leakage current spike.

[0004] In order to solve the technique issues, a five-level inverter is provided according to the disclosure to reduce the leakage current and enhance efficiency and reliability of the inverter.

[0005] The technical solutions as follows are provided according to the disclosure.

[0006] A five-level inverter is provided according to the disclosure, which includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first capacitor unit, a second capacitor unit, a third capacitor unit, a fourth capacitor unit, a first inductor, a second inductor, a first reverse flow preventive element and a second reverse flow preventive element; where
a positive pole of a direct-current power supply is connected to a first terminal of the first switch and a first terminal of the first capacitor unit; a negative pole of the direct-current power supply is connected to a first terminal of the second switch and a second terminal of the second capacitor unit;
a second terminal of the first switch is connected to a first terminal of the first reverse flow preventive element, a first terminal of the third switch and a first terminal of the fifth switch;
a second terminal of the first reverse flow preventive element is connected to a second terminal of the first capacitor unit, a first terminal of the second capacitor unit and a first terminal of the second reverse flow preventive element;
a second terminal of the second reverse flow preventive element is connected to a second terminal of the second switch, a first terminal of the fourth switch and a first terminal of the sixth switch;
a second terminal of the third switch is connected to a first terminal of the first inductor and a second terminal of the fourth switch; a second terminal of the fifth switch is connected to a first terminal of the second inductor and a second terminal of the sixth switch;
a second terminal of the first inductor is connected to a first terminal of the third capacitor unit; a second terminal of the second inductor is connected to a second terminal of the fourth capacitor unit;
a second terminal of the third capacitor unit and a first terminal of the fourth capacitor unit are connected to the second terminal of the first capacitor unit;
the first reverse flow preventive element is configured to prevent a current from flowing from the first terminal of the first reverse flow preventive element to the second terminal of the first reverse flow preventive element in a case that the first switch is turned on;
the second reverse flow preventive element is configured to prevent a current from flowing from the first terminal of the second reverse flow preventive element to the second terminal of the second reverse flow preventive element in a case that the second switch is turned on; and
the second terminal of the first inductor and the second terminal of the second inductor are alternate-current output terminals of the inverter.

[0007] Preferably, a current flows from the first terminal of the first switch to the second terminal of the first switch in a case that the first switch is turned on; a current flows from the first terminal of the third switch to the second terminal of the third switch in a case that the third switch is turned on; and a current flows from the first terminal of the fifth switch to the second terminal of the fifth switch in a case that the fifth switch is turned on; and
a current flows from the second terminal of the second switch to the first terminal of the second switch in a case that the second switch is turned on; a current flows from the second terminal of the fourth switch to the first terminal of the fourth switch in a case that the fourth switch is turned on; and a current flows from the second terminal of the sixth switch to the first terminal of the sixth switch in a case that the sixth switch is turned on.

[0008] Preferably, the inverter is configured to operate in six active operation modes which includes a first operation mode, a second operation mode, a third operation mode, a fourth operation mode, a fifth operation mode and a sixth operation mode; where
the first switch, the second switch, the third switch and the sixth switch are turned on, and the fourth switch and the fifth switch are turned off, in a case that the inverter is in the first operation mode;
the inverter is configured to operate in a first operation sub-mode or a second operation sub-mode in a case that the inverter is in the second operation mode; the first switch, the third switch and the sixth switch are turned on, the second switch, the fourth switch and the fifth switch are turned off, the second terminal of the first capacitor unit is in a charging state, in a case that the inverter is in the first operation sub-mode; and the second switch, the third switch and the sixth switch are turned on, the first switch, the fourth switch and the fifth switch are turned off, and the second terminal of the first capacitor unit is in a discharging state, in a case that the inverter is in the second operation sub-mode;
the third switch and the sixth switch are turned on, and the first switch, the second switch, the fourth switch and the fifth switch are turned off, in a case that the inverter is in the third operation mode;
the first switch, the second switch, the fourth switch and the fifth switch are turned on, and the third switch and the sixth switch are turned off, in a case that the inverter is in the fourth operation mode;
the inverter is configured to operate in a third operation sub-mode or a fourth operation sub-mode in a case that the inverter is in the fifth operation mode; the first switch, the fourth switch and the fifth switch are turned on, the second switch, the third switch and the sixth switch are turned off, and the second terminal of the first capacitor unit is in the charging state, in a case that the inverter is in the third operation sub-mode; and the second switch, the fourth switch and the fifth switch are turned on, the first switch, the third switch and the sixth switch are turned off, and the second terminal of the first capacitor unit is in the discharging state, in a case that the inverter is in the fourth operation sub-mode; and
the fourth switch and the fifth switch are turned on, and the first switch, the second switch, the third switch and the sixth switch are turned off, in a case that the inverter is in the sixth operation mode.

[0009] Preferably, a period of a periodic signal outputted by the inverter includes a first time interval, a second time interval, a third time interval, a fourth time interval, a fifth time interval and a sixth time interval; where
the inverter is configured to operate in the second operation mode and the third operation mode alternately during each of the first time interval and the third time interval;
the inverter is configured to operate in the first operation mode and the second operation mode alternately during the second time interval;
the inverter is configured to operate in the fifth operation mode and the sixth operation mode alternately during each of the fourth time interval and the sixth time interval; and
the inverter is configured to operate in the fourth operation mode and the fifth operation mode alternately during the fifth time interval.

[0010] Preferably, the second terminal of the first capacitor unit is in a same charge-discharge state during the first time interval, the second time interval and the third time interval; and is in a same charge-discharge state during the fourth time interval, the fifth time interval and the sixth time interval, where the same charge-discharge state of the second terminal of the first capacitor unit during fourth time interval, the fifth time interval and the sixth time interval is opposite to the same charge-discharge state of the second terminal of the first capacitor unit during the first time interval, the second time interval and the third time interval; or
the second terminal of the first capacitor unit is in a same charge-discharge state during the first time interval, a latter half of the second time interval, the fourth time interval and a latter half of the fifth time interval; and is in a same charge-discharge state during a first half of the second time interval, the third time interval, a first half of the fifth time interval and the sixth time interval, where the same charge-discharge state of the second terminal of the first capacitor unit during the first half of the second time interval, the third time interval, the first half of the fifth time interval and the sixth time interval is opposite to the same charge-discharge state of the second terminal of the first capacitor unit during the first time interval, the latter half of the second time interval, the fourth time interval and the latter half of the fifth time interval; or
the second terminal of the first capacitor unit is in a same charge-discharge state during the first time interval, a latter half of the second time interval, a first half of the fifth time interval and the sixth time interval; and is in a same charge-discharge state during a first half of the second time interval, the third time interval, the fourth time interval and a latter half of the fifth time interval, where the same charge-discharge state of the second terminal of the first capacitor unit during the first half of the second time interval, the third time interval, the fourth time interval and the latter half of the fifth time interval is opposite to the same charge-discharge state of the second terminal of the first capacitor unit during the first time interval, the latter half of the second time interval, the first half of the fifth time interval and the sixth time interval.

[0011] Preferably, the inverter is configured to operate in three passive operation modes which includes a seventh operation mode, a eighth operation mode and a ninth operation mode; where
the first switch, the second switch, the third switch and the sixth switch are turned on, and the fourth switch and the fifth switch are turned off, in a case that the inverter is in the seventh operation mode;
the third switch, the fourth switch, the fifth switch and the sixth switch are turned on, and the first switch and the second switch are turned off, in a case that the inverter is in the eighth operation mode; and
the first switch, the second switch, the fourth switch and the fifth switch are turned on, and the third switch and the sixth switch are turned off, in a case that the inverter is in the ninth operation mode.

[0012] Preferably, the first reverse flow preventive element is a first diode, and the second reverse flow preventive element is a second diode; where
the first terminal of the first reverse flow preventive element is a cathode of the first diode, and the second terminal of the first reverse flow preventive element is an anode of the first diode; and
the first terminal of the second reverse flow preventive element is a cathode of the second diode, and the second terminal of the second reverse flow preventive element is an anode of the second diode.

[0013] Preferably, the first reverse flow preventive element is the seventh switch, and the second reverse flow preventive element is the eighth switch; where
the seventh switch is turned off in a case that the first switch is turned on; and
the eighth switch is turned off in a case that the second switch is turned on.

[0014] Preferably, the second terminal of the first inductor is further connected to a positive pole of an alternate-current grid via the third inductor, and the second terminal of the second inductor is further connected to a negative pole of the alternate-current grid via the fourth inductor.

[0015] Preferably, the direct-current power supply is a photovoltaic power supply.

[0016] It can be seen from the above technical solution that, in the five level inverter according to the disclosure, the third capacitor unit and the fourth capacitor unit function as an output filtering circuit of the inverter, the second terminal of the first capacitor is a midpoint of a direct-current bus, and a common terminal of the third capacitor unit and the fourth capacitor unit is connected to a second terminal of the first capacitor unit, thereby a potential of the midpoint of the direct-current bus (or the positive pole or the negative pole of the direct-current power supply) relative to a midpoint of the output filtering circuit may be relatively stable, and the voltage jump may not occur. Thus the problem of the current leakage may be avoided, and efficiency and reliability of the inverter may be enhanced.

BRIEF DESCRIPTION OF THE DRAWINGS



[0017] 

Figure 1 is a circuit diagram of an existing five-level inverter;

Figure 2 is a circuit diagram of a five-level inverter according to an embodiment of the disclosure;

Figure 3a is a circuit diagram of the inverter shown in Figure 2 in a first operation mode;

Figure 3b is a circuit diagram of the inverter shown in Figure 2 in a first operation sub-mode;

Figure 3c is a circuit diagram of the inverter shown in Figure 2 in a second operation sub-mode;

Figure 3d is a circuit diagram of the inverter shown in Figure 2 in a third operation mode;

Figure 3e is a circuit diagram of the inverter shown in Figure 2 in a fourth operation mode;

Figure 3f is a circuit diagram of the inverter shown in Figure 2 in a third operation sub-mode;

Figure 3g is a circuit diagram of the inverter shown in Figure 2 in a fourth operation sub-mode;

Figure 3h is a circuit diagram of the inverter shown in Figure 2 in a sixth operation mode;

Figure 4 is a schematic diagram of a mode switching control fashion of a first allocation scheme for a corresponding charge-discharge state of a midpoint of a direct-current bus;

Figure 5 is a schematic diagram of a mode switching control fashion of a second allocation scheme for a corresponding charge-discharge state of the midpoint of the direct-current bus;

Figure 6 is a schematic diagram of a mode switching control fashion of a third allocation scheme for a corresponding charge-discharge state of the midpoint of the direct-current bus;

Figure 7a is a circuit diagram of the inverter shown in Figure 2 in a seventh operation mode;

Figure 7b is a circuit diagram of the inverter shown in Figure 2 in an eighth operation mode;

Figure 7c is a circuit diagram of the inverter shown in Figure 2 in a ninth operation mode; and

Figure 8 is a circuit diagram of the inverter shown in Figure 2 according to a preferred embodiment of the disclosure.


DETAILED DESCRIPTION OF THE EMBODIMENTS



[0018] During operation of the inverter, a power-frequency or high-frequency voltage jump in a potential of a direct-current power supply, with respect to an output negative pole (at the same potential as ground) may occur. The voltage jump may produce a leakage current when applied across the parasitic capacitor between the direct-current power supply (for example, the solar panel) and ground. The leakage current can be problematic because the leakage current would impair the quality of the outputted electric power, reduce the efficiency of the inverter, and harm the human body, thereby reducing reliability of the inverter. For example, an existing five-level inverter is shown in Figure 1. During operation of the five-level inverter, a power-frequency jump in a potential of the direct-current power supply DC relative to an output negative pole, i.e. point C, may occur. That is, the power-frequency jump occurs in a potential of a midpoint of the bus which is a common terminal of the capacitor C1 and a capacitor C2 or in a potential of a negative pole of the direct-current power supply DC relative to an output negative pole. The output negative pole is typically in connection with a N wire of the grid which has almost the same potential as the ground. The power-frequency jumping voltage, when applied across a parasitic capacitor between the positive pole (or the negative pole) of the direct-current power supply DC and ground, may produce a leakage current spike.

[0019] A five-level inverter is provided according to the disclosure to address the problem of current leakage and enhance efficiency and reliability of the inverter.

[0020] To make the above object, features and advantages of the disclosure more obvious and easy to be understood, in the following, particular embodiments of the disclosure will be explained in detail in conjunction with the drawings.

[0021] Referring to Figure 2, a five-level inverter according an embodiment of the disclosure is shown. In the present embodiment, the five-level inverter includes: a first switch QH1, a second switch CH2, a third switch QL1, a fourth switch QL2, a fifth switch QL3, a sixth switch QL4, a first capacitor unit C1, a second capacitor unit C2, a third capacitor unit C3, a fourth capacitor unit C4, a first inductor L1, a second inductor L2, a first reverse flow preventive element and a second reverse flow preventive element.

[0022] A positive pole of a direct-current power supply DC is connected to a first terminal of the first switch QH1 and a first terminal of the first capacitor unit C1; a negative pole of the direct-current power supply DC is connected to a first terminal of the second switch QH2 and a second terminal of the second capacitor unit C2.

[0023] A second terminal of the first switch QH1 is connected to a first terminal of the first reverse flow preventive element, a first terminal of the third switch QL1 and a first terminal of the fifth switch QL3.

[0024] A second terminal of the first reverse flow preventive element is connected to a second terminal of the first capacitor unit C1, a first terminal of the second capacitor unit C2 and a first terminal of the second reverse flow preventive element.

[0025] A second terminal of the second reverse flow preventive element is connected to a second terminal of the second switch QH2 ,a first terminal of the fourth switch QL2 and a first terminal of the sixth switch QL4.

[0026] A second terminal of the third switch QL1 is connected to a first terminal of the first inductor L1 and a second terminal of the fourth switch QL2; a second terminal of the fifth switch QL3 is connected to a first terminal of the second inductor L2 and a second terminal of the sixth switch QL4.

[0027] A second terminal of the first inductor L1 is connected to a first terminal of the third capacitor unit C3; a second terminal of the second inductor L2 is connected to a second terminal of the fourth capacitor unit C4.

[0028] A second terminal of the third capacitor unit C3 and a first terminal of the fourth capacitor unit C4 are connected to the second terminal of the first capacitor unit C1.

[0029] The first reverse flow preventive element is configured to prevent a current from flowing from the first terminal of the first reverse flow preventive element to the second terminal of the first reverse flow preventive element in a case that the first switch QH1 is turned on; the second reverse flow preventive element is configured to prevent a current from flowing from the first terminal of the second reverse flow preventive element to the second terminal of the second reverse flow preventive element in a case that the second switch QH2 is turned on.

[0030] The second terminal of the first inductor L1 and the second terminal of the second inductor L2 are alternate-current output terminals of the inverter which may be connected to a alternate-current grid.

[0031] It can be seen from the present embodiments that, in the five-level inverter, a second terminal of the third capacitor unit C3 and a first terminal of the fourth capacitor unit C4 are connected to the second terminal of the first capacitor unit C1. In other words, a common terminal of the third capacitor unit C3 and the fourth capacitor unit C4 is connected to a midpoint of the direct-current bus (i.e., a second terminal of the first capacitor C1). Thus a potential of the midpoint of the direct-current bus relative to the common terminal of the third capacitor unit C3 and the fourth capacitor unit C4 is relatively stable. That is, a potential of the positive pole or the negative pole of the direct-current power supply DC relative to the common terminal of the third capacitor unit C3 and the fourth capacitor unit C4 is relatively stable. The power-frequency or high frequency voltage jump would not occur. The third capacitor unit C3 and the fourth capacitor unit C4 function as an output filtering circuit of the inverter which is typically in connection with a N wire of the grid which has almost the same potential as the ground. Therefore no voltage jump would occur at the positive pole (or negative pole) of the direct-current power supply DC, with respect to ground, thereby avoiding the problem of current leakage, and efficiency and reliability of the inverter may be enhanced. Further, the five-level inverter according to the embodiment is a double-buck circuit and only six switches are used. Therefore the five-level inverter offers a simple configuration and a lower cost.

[0032] According to the present embodiment, an alternate-current gird ug may be connected between two output terminals of the inverter. The inverter according to the present embodiment is applicable in the field of photovoltaic power generation, and the direct-current power supply DC may be a PV (Photo Voltaics) power supply.

[0033] According to the present embodiment, the first switch QH1 and the second switch QH2 may be high-frequency switches, and may perform switching actions at a high frequency during the operation of the inverter. The third switch QL1, the fourth switch QL2, the fifth switch QL3 and the sixth switch QL4 may be low-frequency switches, and may perform switching actions at a low frequency during the operation of the inverter. The term "high frequency" used in the present disclosure is generally referred to a frequency above 1kHz, and the term "low frequency" is generally referred to a frequency below 1kHz (which is typically the power frequency, for example, at 50 Hz).

[0034] According to the present embodiment, each of the first switch QH1, the second switch QH2, the third switch QL1, the fourth switch QL2, the fifth switch QL3 and the sixth switch QL4 can be any type of switch, such as IGBT and MOS, and each of the switches can be connected with a reverse diode in parallel. In a case that each of the switches is connected with a reverse diode in parallel, a current flows from the first terminal of the first switch QH1 to the second terminal of the first switch QH1 in a case that the first switch QH1 is turned on, that is, an anode of the reverse diode connected in parallel with the first switch QH1 is connected to the second terminal of the first switch QH1, and a cathode of the reverse diode is connected to the first terminal of the first switch QH1. A current flows from the first terminal of the third switch QL1 to the second terminal of the third switch QL1 in a case that the third switch QL1 is turned on; and a current flows from the first terminal of the fifth switch QL3 to the second terminal of the fifth switch QL3 in a case that the fifth switch QL3 is turned on. A current flows from the second terminal of the second switch QH2 to the first terminal of the second switch QH2 in a case that the second switch QH2 is turned on, that is, an anode of the reverse diode connected in parallel with the second switch QH2 is connected to the first terminal of the second switch QH2, and a cathode of the reverse diode connected in parallel with the second switch QH2 is connected to the second terminal of the first switch QH2; a current flows from the second terminal of the fourth switch QL2 to the first terminal of the fourth switch QL2 in a case that the fourth switch QL2 is turned on; and a current flows from the second terminal of the sixth switch QL4 to the first terminal of the sixth switch QL4 in a case that the sixth switch QL4 is turned on.

[0035] In the present embodiment, each of the first capacitor unit, the second capacitor unit, the third capacitor unit and the fourth capacitor unit may be an element including capacitors, and the number of the capacitors included in each capacitor unit is not limited. In order to balance the circuit as much as possible, a capacitance of the first capacitor unit may be made equal to a capacitance of the second capacitor unit, or the difference between the capacitance of the first capacitor unit and the capacitance of the second capacitor unit may be made below a first predetermined threshold; and a capacitance of the third capacitor unit may be made equal to a capacitance of the fourth capacitor unit, or the difference between the capacitance of the third capacitor unit and the capacitance of the fourth capacitor unit may be made below a second predetermined threshold. The first predetermined threshold and the second predetermined threshold may be set according to requirements, and may or may not be equal. In order to balance the circuit as much as possible, an inductance of the first inductor may be equal to an inductance of the second inductor, or the difference between the inductance of the first inductor and the inductance of the second inductor may be within a threshold range.

[0036] It should be noted that, in the present embodiment, the first reverse flow preventive element is configured to prevent a current from flowing from the first terminal of the first reverse flow preventive element to the second terminal of the first reverse flow preventive element in a case that the first switch QH1 is turned on. The second reverse flow preventive element is configured to prevent a current from flowing from the first terminal of the second reverse flow preventive element to the second terminal of the second reverse flow preventive element in a case that the second switch QH2 is turned on. As shown in Figure 2, each of the first reverse flow preventive element and the second reverse flow preventive element may be a diode, that is, the first reverse flow preventive element is a diode D1 and the second reverse flow preventive element is a diode D2. That is to say, the first terminal of the first reverse flow preventive element is a cathode of the first diode D1, and the second terminal of the first reverse flow preventive element is an anode of the first diode D1; and the first terminal of the second reverse flow preventive element is a cathode of the second diode D2, and the second terminal of the second reverse flow preventive element is an anode of the second diode D2. Each of the diode D1 and the diode D2 may be such as a silicon carbide diode or a fast recovery diode.

[0037] Alternatively, the first reverse flow preventive element and the second reverse flow preventive element may be other devices besides diodes, which is not limited in the disclosure. For example, the first reverse flow preventive element and the second reverse flow preventive element may also be switches. As an example, the first reverse flow preventive element is a seventh switch and the second reverse flow preventive element is an eighth switch. In a case that the first switch QH1 is turned on, the seventh switch is turned off to prevent a current from flowing from the first terminal of the first reverse flow preventive element to the second terminal of the first reverse flow preventive element, and the seventh switch is turned on in a case that the first switch QH1 is turned off. In a case that the second switch QH2 is turned on, the eighth switch is turned off to prevent a current from flowing from the first terminal of the second reverse flow preventive element to the second terminal of the second reverse flow preventive element, and the eighth switch is turned on in a case that the second switch QH2 is turned off. Each of the seventh switch and the eighth switch may be a MOS transistor which may reduce on-state losses.

[0038] It should be noted that, the inverter according to the embodiments of the disclosure is applicable to applications where active power is required and applications where both reactive power and active power are required. Hereinafter, various operation modes of the inverter will be described in conjunction with the drawings.

[0039] Referring to Figure 3a to 3h, six active power operation modes of the inverter according to the present embodiment are described, which includes a first operation mode, a second operation mode, a third operation mode, a fourth operation mode, a fifth operation mode and a sixth operation mode.

[0040] As shown in Figure 3a, a positive level 2 is outputted by the inverter in a case that the inverter according to the present embodiment is in the first operation mode. In this case, the first switch QH1, the second switch QH2, the third switch QL1 and the sixth switch QL4 are turned on, and the fourth switch QL2 and the fifth switch QL3 are turned off. The first reverse flow preventive element can prevent a current from flowing from a common terminal of the first switch QH1 and the third switch QL1 to a common terminal of the first capacitor unit C1 and the second capacitor unit C2, and the second reverse flow preventive element can prevent a current from flowing from the common terminal of the first capacitor unit C1 and the second capacitor unit C2 to a common terminal of the second switch QH2 and the fourth switch QL2. In a case that the first reverse flow preventive element and the second reverse flow preventive element are switches, both of the switches are turned off. A current flows through the first switch QH1, the third switch QL1, the first inductor L1, the alternate-current grid ug, the second inductor L2, the sixth switch QL4, the second switch QH2, the second capacitor unit C2, and the first capacitor unit C1 successively.

[0041] A small current flows through a connection circuit between the common terminal of the first capacitor unit C1 and the second capacitor unit C2 and the common terminal of the third capacitor unit C3 and the fourth capacitor unit C4 in a case that the inverter is in the first operation mode, and the current can be relatively low in a case that the third capacitor unit C3 has a capacitance approximating to that of the fourth capacitor unit C4, the first capacitor unit C1 has a capacitance approximating to that of the second capacitor unit C2, and the first inductor L1 has a inductance approximating to that of the second inductor L2.

[0042] A positive level 1 is outputted by the inverter in a case that the inverter according to the present embodiment is in the second operation mode. In this case, the inverter may operate in a first operation sub-mode or a second operation sub-mode, which will be described in detail respectively in the following.

[0043] As shown in Figure 3b, in a case that the inverter according to the present embodiment is in the first operation sub-mode, the first switch QH1, the third switch QL1 and the sixth switch QL4 are turned on, the second switch QH2, the fourth switch QL2 and the fifth switch QL3 are turned off. In this case, the second terminal of the first capacitor unit C1 (i.e., the common terminal of the first capacitor unit C1 and the second capacitor unit C2) is in a charging state. The first reverse flow preventive element can prevent a current from flowing from the common terminal of the first switch QH1 and the third switch QL1 to the common terminal of the first capacitor unit C1 and the second capacitor unit C2. In a case that the first reverse flow preventive element is a switch, the switch is turned off, and in a case that the second reverse flow preventive element is a switch, the switch is turned on. A current flows through the first switch QH1, the third switch QL1, the first inductor L1, the alternate-current grid ug, the second inductor L2, the sixth switch QL4, the second reverse flow preventive element, and the first capacitor unit C1 successively.

[0044] As shown in Figure 3c, in a case that the inverter according to the present embodiment is in the second operation sub-mode, the second switch CH2, the third switch QL1 and the sixth switch QL4 are turned on, the first switch QH1, the fourth switch QL2 and the fifth switch QL3 are turned off, and the second terminal of the first capacitor unit C1 (i.e., the common terminal of the first capacitor unit C1 and the second capacitor unit C2) is in a discharging state. The second reverse flow preventive element can prevent a current from flowing from the common terminal of the first capacitor unit C1 and the second capacitor unit C2 to the common terminal of the second switch QH2 and the fourth switch QL2. In a case that the second reverse flow preventive element is a switch, the switch is turned off, and in a case that the first reverse flow preventive element is a switch, the switch is turned on. A current flows through the first reverse flow preventive element, the third switch QL1, the first inductor L1, the alternate-current grid ug, the second inductor L2, the sixth switch QL4, the second switch QH2, and the second capacitor unit C2 successively.

[0045] A current flows through a connection circuit between a common terminal of the first capacitor unit C1 and the second capacitor unit C2 and a common terminal of the third capacitor unit C3 and the fourth capacitor unit C4 in a case that the inverter is in the first operation sub-mode or the second operation sub-mode.

[0046] It can be seen that a positive level 1 is outputted by the inverter in each of the above two operation sub-mode. However, the difference lies in that, the second terminal of the first capacitor unit C1 is in the charging state in a case that the inverter is in the first operation sub-mode, and the second terminal of the first capacitor unit C1 is in the discharging state in a case that the inverter is in the second operation sub-mode.

[0047] As shown in Figure 3d, a positive level 0 is outputted by the inverter in a case that the inverter is in the third operation mode. In this case, the third switch QL1 and the sixth switch QL4 are turned on, and the first switch QH1, the second switch QH2, the fourth switch QL2 and the fifth switch QL3 are turned off. In a case that the first reverse flow preventive element and the second reverse flow preventive element are switches, both of the switches are turned on. A current flows through the first reverse flow preventive element, the third switch QL1, the first inductor L1, the alternate-current grid ug, the second inductor L2, the sixth switch QL4, and the second reverse flow preventive element successively.

[0048] A small current also flows through a connection circuit between the common terminal of the first capacitor unit C1 and the second capacitor unit C2 and the common terminal of the third capacitor unit C3 and the fourth capacitor unit C4 in a case that the inverter is in the third operation mode, and the small current can be relatively low in a case that the third capacitor unit C3 has a capacitance approximating to that of the fourth capacitor unit C4, the first capacitor unit C1 has a capacitance approximating to that of the second capacitor unit C2, and the first inductor L1 has a inductance approximating to that of the second inductor L2.

[0049] As shown in Figure 3e, a negative level 2 is outputted by the inverter in a case that the inverter according to the present embodiment is in the fourth operation mode. In this case, the first switch QH1, the second switch QH2, the fourth switch QL2 and the fifth switch QL3 are turned on, and the third switch QL1 and the sixth switch QL4 are turned off. The first reverse flow preventive element can prevent a current from flowing from the common terminal of the first switch QH1 and the third switch QL1 to the common terminal of the first capacitor unit C1 and the second capacitor unit C2, and the second reverse flow preventive element can prevent a current from flowing from the common terminal of the first capacitor unit C1 and the second capacitor unit C2 to the common terminal of the second switch QH2 and the fourth switch QL2. In a case that the first reverse flow preventive element and the second reverse flow preventive element are switches, both of the switches are turned off. A current flows through the first switch QH1, the fifth switch QL3, the second inductor L2, the alternate-current grid ug, the first inductor L1, the fourth switch QL2, the second switch QH2, the second capacitor C2, and the first capacitor C1 successively.

[0050] A small current flows through a connection circuit between the common terminal of the first capacitor unit C1 and the second capacitor unit C2 and the common terminal of the third capacitor unit C3 and the fourth capacitor unit C4 in a case that the inverter is in the fourth operation mode, and the small currents can be relatively low in a case that the third capacitor unit C3 has a capacitance approximating to that of the fourth capacitor unit C4, the first capacitor unit C1 has a capacitance approximating to that of the second capacitor unit C2, and the first inductor L1 has a inductance approximating to that of the second inductor L2.

[0051] A negative level 1 is outputted by the inverter in a case that the inverter according to the present embodiment is in the fifth operation mode. In this case, the inverter may operate in a third operation sub-mode or a fourth operation sub-mode, which will be described in detail respectively in the following.

[0052] As shown in Figure 3f, in a case that the inverter according to the present embodiment is in the third operation sub-mode, the first switch QH1, the fourth switch QL2 and the fifth switch QL3 are turned on, the second switch QH2, the third switch QL1 and the sixth switch QL4 are turned off. In this case, the second terminal of the first capacitor unit C1 (i.e., the common terminal of the first capacitor unit C1 and the second capacitor unit C2) is in a charging state. The first reverse flow preventive element can prevent a current from flowing from the common terminal of the first switch QH1 and the third switch QL1 to the common terminal of the first capacitor unit C1 and the second capacitor unit C2. In a case that the first reverse flow preventive element is a switch, the switch is turned off, and in a case that the second reverse flow preventive element is a switch, the switch is turned on. A current flows through the first switch QH1, the fifth switch QL3, the second inductor L2, the alternate-current grid ug, the first inductor L1, the fourth switch QL2, the second reverse flow preventive element, and the first capacitor unit C1 successively.

[0053] As shown in Figure 3g, in a case that the inverter according to the present embodiment is in the fourth operation sub-mode, the second switch QH2, the fourth switch QL2 and the fifth switch QL3 are turned on, the first switch QH1, the third switch QL1 and the sixth switch QL4 are turned off, and the second terminal of the first capacitor unit C1 (i.e., the common terminal of the first capacitor unit C1 and the second capacitor unit C2) is in the discharging state. The second reverse flow preventive element can prevent a current from flowing from the common terminal of the first capacitor unit C1 and the second capacitor unit C2 to the common terminal of the second switch QH2 and the fourth switch QL2. In a case that the second reverse flow preventive element is a switch, the switch is turned off, and in a case that the first reverse flow preventive element is a switch, the switch is turned on. A current flows through the first reverse flow preventive element, the fifth switch QL3, the second inductor L2, the alternate-current grid ug, the first inductor L1, the fourth switch QL2, the second switch QH2, and the second capacitor unit C2 successively.

[0054] A current flows through a connection circuit between the common terminal of the first capacitor unit C1 and the second capacitor unit C2 and the common terminal of the third capacitor unit C3 and the fourth capacitor unit C4 in a case that the inverter is in the third operation sub-mode or the fourth operation sub-mode.

[0055] It can be seen that a negative level 1 is outputted by the inverter in each of the above two operation sub-mode. However, the difference lies in that, the second terminal of the first capacitor unit C1 is in the charging state in a case that the inverter is in the third operation sub-mode, and the second terminal of the first capacitor unit C1 is in the discharging state in a case that the inverter is in the fourth operation sub-mode.

[0056] As shown in Figure 3h, a negative level 0 is outputted by the inverter in a case that the inverter according to the present embodiment is in the sixth operation mode. In this case, the fourth switch QL2 and the fifth switch QL3 are turned on, and the first switch QH1, the second switch QH2, the third switch QL1 and the sixth switch QL4 are turned off. In a case that the first reverse flow preventive element and the second reverse flow preventive element are switches, both of the switches are turned on. A current flows through the first reverse flow preventive element, the fifth switch QL3, the second inductor L2, the alternate-current grid ug, the first inductor L1, the fourth switch QL2, and the second reverse flow preventive element successively.

[0057] A small current also flows through a connection circuit between the common terminal of the first capacitor unit C1 and the second capacitor unit C2 and the common terminal of the third capacitor unit C3 and the fourth capacitor unit C4 in a case that the inverter is in the sixth operation mode, and the small current can be relatively low in a case that the third capacitor unit C3 has a capacitance approximating to that of the fourth capacitor unit C4, the first capacitor unit C1 has a capacitance approximating to that of the second capacitor unit C2, and the first inductor L1 has a inductance approximating to that of the second inductor L2.

[0058] The inverter may output a periodic signal in each of the above six active operation modes. A period of the periodic signal outputted by the inverter includes a first time interval, a second time interval, a third time interval, a fourth time interval, a fifth time interval and a sixth time interval; where the inverter outputs a positive voltage during the first time interval, the second time interval and the third time interval, and outputs a negative voltage during the fourth time interval, the fifth time interval and the sixth time interval.

[0059] The inverter is configured to operate in the second operation mode and the third operation mode alternately and output a positive level 1 and a positive level 0 alternately during each of the first time interval and the third time interval.

[0060] The inverter is configured to operate in the first operation mode and the second operation mode alternately and output a positive level 1 and a positive level 2 alternately during the second time interval.

[0061] The inverter is configured to operate in the fifth operation mode and the sixth operation mode alternately and output a negative level 1 and a negative level 0 alternately during each of the fourth time interval and the sixth time interval.

[0062] The inverter is configured to operate in the fourth operation mode and the fifth operation mode alternately and output a negative level 1 and a negative level 2 alternately during the fifth time interval.

[0063] It should be noted that, the inverter may specifically operate in the first operation sub-mode or the second operation sub-mode in a case that the inverter is in the second operation mode, and the inverter may specifically operate in the third operation sub-mode or the fourth operation sub-mode in a case that the inverter is in the fifth operation mode. The second terminal of the first capacitor C1 is in the charging state in a case that the inverter is in the first operation sub-mode and the third operation sub-mode, and in the discharging state in a case that the inverter is in the second operation sub-mode and the fourth operation sub-mode. Thus it is preferred that, in a period, a duration for which the second terminal of the capacitor C1 (i.e., the midpoint of the direct-current bus) is in the charging state may be made equal to a duration for which the second terminal of the capacitor C1 (i.e., the midpoint of the direct-current bus) is in the discharging state, or the difference between the duration for which the second terminal of the capacitor C1 (i.e., the midpoint of the direct-current bus) is in the charging state and the duration for which the second terminal of the capacitor C1 (i.e., the midpoint of the direct-current bus) is in the discharging state may be made below a predetermined threshold by adjusting the allocation of the second operation mode and the fifth operation mode, thereby stabilizing a voltage at the midpoint of the direct-current bus as much as possible. Hereinafter, three allocation schemes for stabilizing the voltage at the midpoint of the direct-current bus as much as possible will be described.

[0064] In a first allocation scheme, the second terminal of the first capacitor unit is in the same state, which may be the charging state or the discharging state, during the first time interval, the second time interval and the third time interval.

[0065] The second terminal of the first capacitor unit is in the same charge-discharge state during the fourth time interval, the fifth time interval and the sixth time interval, where the same charge-discharge state of the second terminal of the first capacitor unit during fourth time interval, the fifth time interval and the sixth time interval is opposite to the charge-discharge state of the second terminal of the first capacitor unit during the first time interval, the second time interval and the third time interval. For example, in a case that the second terminal of the first capacitor unit is in the charging state during the first time interval, the second time interval and the third time interval, the second terminal of the first capacitor unit should be in the discharging state during the fourth time interval, the fifth time interval and the sixth time interval; and in a case that the second terminal of the first capacitor unit is in the discharging state during the first time interval, the second time interval and the third time interval, the second terminal of the first capacitor unit should be in the charging state during the fourth time interval, the fifth time interval and the sixth time interval.

[0066] Particularly, in a case that the second terminal of the first capacitor unit is in the charging state during the first time interval (or the third time interval), it is indicated that the inverter operates in the first operation sub-mode and the third operation mode alternately during the first time interval (or the third time interval), and in a case that the second terminal of the first capacitor unit is in the discharging state during the first time interval (or the third time interval), it is indicated that the inverter operates in the second operation sub-mode and the third operation mode alternately during the first time interval (or the third time interval); in a case that the second terminal of the first capacitor unit is in the charging state during the second time interval, it is indicated that the inverter operates in the first operation sub-mode and the first operation mode alternately during the second time interval, and in a case that the second terminal of the first capacitor unit is in the discharging state during the second time interval, it is indicated that the inverter operates in the second operation sub-mode and the first operation mode alternately during the second time interval.

[0067] In a case that the second terminal of the first capacitor unit is in the charging state during the fourth time interval (or the sixth time interval), it is indicated that the inverter operates in the third operation sub-mode and the sixth operation mode alternately during the fourth time interval (or the sixth time interval), and in a case that the second terminal of the first capacitor unit is in the discharging state during the fourth time interval (or the sixth time interval), it is indicated that the inverter operates in the fourth operation sub-mode and the sixth operation mode alternately during the fourth time interval (or the sixth time interval); in a case that the second terminal of the first capacitor unit is in the charging state during the fifth time interval, it is indicated that the inverter operates in the third operation sub-mode and the fourth operation mode alternately during the fifth time interval, and in a case that the second terminal of the first capacitor unit is in the discharging state during the fifth time interval, it is indicated that the inverter operates in the fourth operation sub-mode and the fourth operation mode alternately during the fifth time interval.

[0068] A mode switching control fashion for the allocation scheme is described in detail below with reference to Figure 4. As shown in Figure 4, the inverter is configured to be in a B mode and a D mode alternately during each of the first time interval T1 and the third time interval T3, in an A mode and the D mode alternately during the second time interval T2, in a C mode and the D mode alternately during each of the fourth time interval T4 and the sixth time interval T6, and to be in the A mode and the C mode alternately during the fifth time interval T5. It should be noted that, Figure 4 is a schematic diagram of mode switching control for the inverter. Therefore, in Figure 4, a signal of a negative level outputted by the inverter is reversed to a signal of a positive level.

[0069] Particularly, the A mode is the first operation mode in which the positive level 2 is outputted or the fourth operation mode in which the negative level 2 is outputted; the B mode is the third operation mode in which the positive level 0 is outputted or the sixth operation mode in which the negative level 0 is outputted; the C mode is the first operation sub-mode in which the positive level 1 is outputted and the voltage at the midpoint of the direct-current bus is in a charging state or the third operation sub-mode in which the negative level 1 is outputted and the voltage at the midpoint of the direct-current bus is in a charging state; and the D mode is the second operation sub-mode in which the positive level 1 is outputted and the voltage at the midpoint of the direct-current bus is in a discharging state or the fourth operation sub-mode in which the negative level 1 is outputted and the voltage at the midpoint of the direct-current bus is in a discharging state.

[0070] As can be seen from Figure 4, the voltage at the midpoint of the direct-current bus is in the discharging state during the first time interval T1, the second time interval T2 and the third time interval T3, which are first half period of the periodic signal, and the voltage at the midpoint of the direct-current bus is in the charging stage during the fourth time interval T4, the fifth time interval T5 and the sixth time interval T6, which are latter half period of the periodic signal. Generally, the duration of the first time interval, the duration of the third time interval, the duration of the fourth time interval and the duration of the sixth time interval are all equal to each other, and the duration of the second time interval is equal to the duration of the fifth time interval. Therefore, in this allocation scheme, a charging duration of the voltage at the midpoint of the direct-current bus is equal to a discharging duration of the voltage at the midpoint of the direct-current bus, thereby ensuring that the voltage at the midpoint of the direct-current bus is stabilized.

[0071] In a second allocation scheme, the second terminal of the first capacitor unit is in the same state, which may be the charging state or the discharging state, during the first time interval, a latter half of the second time interval, a first half of the fifth time interval and the sixth time interval.

[0072] The second terminal of the first capacitor unit is in the same charge-discharge state during a first half of the second time interval, the third time interval, the fourth time interval and a latter half of the fifth time interval, where the same charge-discharge state of the second terminal of the first capacitor unit during the first half of the second time interval, the third time interval, the fourth time interval and the latter half of the fifth time interval is opposite to the charge-discharge state of the second terminal of the first capacitor unit during the first time interval, the latter half of the second time interval, the first half of the fifth time interval and the sixth time interval. For example, in a case that the second terminal of the first capacitor unit is in the charging state during the first time interval, the latter half of the second time interval, the first half of the fifth time interval and the sixth time interval, the second terminal of the first capacitor unit should be in the discharging state during the first half of the second time interval, the third time interval, the fourth time interval and the latter half of the fifth time interval; and in a case that the second terminal of the first capacitor unit is in the discharging state during the first time interval, the latter half of the second time interval, the first half of the fifth time interval and the sixth time interval, the second terminal of the first capacitor unit should be in the charging state during the first half of the second time interval, the third time interval, the fourth time interval and the latter half of the fifth time interval.

[0073] A mode switching control fashion for the allocation scheme is described in detail below with reference to Figure 5. As shown in Figure 5, the inverter is configured to be in a B mode and a D mode alternately during each of the first time interval T1 and the sixth time interval T6, in an A mode and the D mode alternately during each of the latter half of the second time interval T2 and the first half of the fifth time interval T5, in the B mode and the C mode alternately during each of the third time interval T3 and the fourth time interval T4, and in the A mode and the C mode alternately during each of the first half of the second time interval T2 and the latter half of the fifth time interval T5. It should be noted that, Figure 5 is a schematic diagram of mode switching control for the inverter. Therefore, in Figure 5, a signal of negative level outputted by the inverter is reversed to a signal of positive level.

[0074] As can be seen from Figure 5, the voltage at the midpoint of the direct-current bus is in the discharging state during the first time interval T1, a latter half of the second time interval T2, a first half of the fifth time interval T5 and the sixth time interval T6, and the voltage at the midpoint of the direct-current bus is in the charging stage during the third time interval T3, the fourth time interval T4, the first half of the second time interval T2, and the later half of the fifth time interval T5. Therefore, in this allocation scheme, a charging duration of the voltage at the midpoint of the direct-current bus is equal to a discharging duration of the voltage at the midpoint of the direct-current bus, thereby ensuring that the voltage at the midpoint of the direct-current bus is stabilized.

[0075] In a third allocation scheme, the second terminal of the first capacitor unit is in the same state, which may be the charging state or the discharging state, during the first time interval, a latter half of the second time interval, a fourth time interval and a later half of the fifth time interval.

[0076] The second terminal of the first capacitor unit is in the same charge-discharge state during a first half of the second time interval, the third time interval, a first half of the fifth time interval, and the sixth time interval, where the same charge-discharge state of the second terminal of the first capacitor unit during the first half of the second time interval, the third time interval, the first half of the fifth time interval, and the sixth time interval is opposite to the charge-discharge state of the second terminal of the first capacitor unit during the first time interval, the latter half of the second time interval, the fourth time interval and the later half of the fifth time interval. For example, in a case that the second terminal of the first capacitor unit is in the charging state during the first time interval, the latter half of the second time interval, the fourth time interval and the later half of the fifth time interval, the second terminal of the first capacitor unit should be in the discharging state during the first half of the second time interval, the third time interval, the first half of the fifth time interval, and the sixth time interval; and in a case that the second terminal of the first capacitor unit is in the discharging state during the first time interval, the latter half of the second time interval, the fourth time interval and the later half of the fifth time interval, the second terminal of the first capacitor unit should be in the charging state during the first half of the second time interval, the third time interval, the first half of the fifth time interval, and the sixth time interval.

[0077] A mode switching control fashion for the allocation scheme is described in detail below with reference to Figure 6. As shown in Figure 6, the inverter is configured to be in a B mode and a D mode alternately during each of the first time interval T1 and the fourth time interval T4, in an A mode and the D mode alternately during each of the latter half of the second time interval T2 and the later half of the fifth time interval T5, in the B mode and the C mode alternately during each of the third time interval T3 and the sixth time interval T6, and in the A mode and the C mode alternately during each of a first half of the second time interval T2 and a first half of the fifth time interval T5. It should be noted that, Figure 6 is a schematic diagram of mode switching control for the inverter. Therefore, in Figure 6, a signal of negative level outputted by the inverter is reversed to a signal of positive level.

[0078] As can be seen from Figure 6, the voltage at the midpoint of the direct-current bus is in the discharging state during the first time interval T1, the later half of the second time interval T2, the later half of the fifth time interval T5, and the fourth time interval T4, and the voltage at the midpoint of the direct-current bus is in the charging stage during the third time interval T3, the sixth time interval T6, the first half of the second time interval T2, and the first half of the fifth time interval T5. Therefore, in this allocation scheme, a charging duration of the voltage at the midpoint of the direct-current bus is equal to a discharging duration of the voltage at the midpoint of the direct-current bus, thereby ensuring that the voltage at the midpoint of the direct-current bus is stabilized.

[0079] In the above three allocation schemes, each of charge and discharge of the midpoint of the direct-current bus is performed once during one period in the first allocation scheme thereby resulting in a power-frequency (typically 50Hz) harmonic, each of charge and discharge of the midpoint of the direct-current bus is performed three times during one period in the second allocation scheme thereby resulting in a harmonic at a frequency which are several times the power frequency, and each of charge and discharge of the midpoint of the direct-current bus is performed four times during one period in the third allocation scheme. Obviously, the third allocation scheme has the highest charge-discharge frequency, and therefore has the lowest bus voltage ripple, while the first allocation scheme has the lowest charge-discharge frequency, and therefore has the highest bus voltage ripple.

[0080] As shown in Figure 7a to 7c, the inverter according to the present embodiment is configured to operate in three passive operation modes which includes a seventh operation mode, an eighth operation mode and a ninth operation mode.

[0081] As shown in Figure 7a, a positive level 1 is outputted by the inverter in a case that the inverter according to the present embodiment is in the seventh operation mode. In this case, the first switch QH1, the second switch QH2, the third switch QL1 and the sixth switch QL4 are turned on, and the fourth switch QL2 and the fifth switch QL3 are turned off. The first reverse flow preventive element can prevent a current from flowing from a common terminal of the first switch QH1 and the third switch QL1 to a common terminal of the first capacitor unit C1 and the second capacitor unit C2, and the second reverse flow preventive element can prevent a current from flowing from the common terminal of the first capacitor unit C1 and the second capacitor unit C2 to a common terminal of the second switch QH2 and the fourth switch QL2. In a case that the first reverse flow preventive element and the second reverse flow preventive element are switches, both of the switches are turned off. A current flows through the first switch QH1, the third switch QL1, the first inductor L1, the alternate-current grid ug, the second inductor L2, the sixth switch QL4, the second switch QH2, the second capacitor unit C2, and the first capacitor unit C1 successively. The current may also flow through the above path reversely.

[0082] A small current flows through a connection circuit between the common terminal of the first capacitor unit C1 and the second capacitor unit C2 and the common terminal of the third capacitor unit C3 and the fourth capacitor unit C4 in a case that the inverter is in the seventh operation mode, and the small current can be relatively low in a case that the third capacitor unit C3 has a capacitance approximating to that of the fourth capacitor unit C4, the first capacitor unit C1 has a capacitance approximating to that of the second capacitor unit C2, and the first inductor L1 has a inductance approximating to that of the second inductor L2.

[0083] As shown in Figure 7b, a level 0 is outputted by the inverter in a case that the inverter according to the present embodiment is in the eighth operation mode. In this case, the third switch QL1, the fourth switch QL2, the fifth switch QL3 and the sixth switch QL4 are turned on, and the first switch QH1 and the second switch QH2 are turned off. In a case that the first reverse flow preventive element and the second reverse flow preventive element are switches, both of the switches are turned on. A current flows through the first reverse flow preventive element, the third switch QL1, the first inductor L1, the alternate-current grid ug, the second inductor L2, the sixth switch QL4, and the second reverse flow preventive element successively. The current may also flow through the first reverse flow preventive element, the fifth switch QL3, the second inductor L2, the alternate-current grid ug, the first inductor L1, the fourth switch QL2, and the second reverse flow preventive element successively.

[0084] A small current flows through a connection circuit between the common terminal of the first capacitor unit C1 and the second capacitor unit C2 and the common terminal of the third capacitor unit C3 and the fourth capacitor unit C4 in a case that the inverter is in the eighth operation mode, and the small current can be relatively low in a case that the third capacitor unit C3 has a capacitance approximating to that of the fourth capacitor unit C4, the first capacitor unit C1 has a capacitance approximating to that of the second capacitor unit C2, and the first inductor L1 has a inductance approximating to that of the second inductor L2.

[0085] As shown in Figure 7c, a negative level 1 is outputted by the inverter in a case that the inverter according to the present embodiment is in the ninth operation mode. In this case, the first switch QH1, the second switch CH2, the fourth switch QL2 and the fifth switch QL3 are turned on, and the third switch QL1 and the sixth switch QL4 are turned off. The first reverse flow preventive element can prevent a current from flowing from a common terminal of the first switch QH1 and the third switch QL1 to a common terminal of the first capacitor unit C1 and the second capacitor unit C2, and the second reverse flow preventive element can prevent a current from flowing from the common terminal of the first capacitor unit C1 and the second capacitor unit C2 to a common terminal of the second switch QH2 and the fourth switch QL2. In a case that the first reverse flow preventive element and the second reverse flow preventive element are switches, both of the switches are turned off. A current flows through the first switch QH1, the fifth switch QL3, the second inductor L2, the alternate-current grid ug, the first inductor L1, the fourth switch QL2, the second switch QH2, the second capacitor unit C2, and the first capacitor unit C1 successively. The current may also flow through the above path reversely.

[0086] A small current flows through a connection circuit between the common terminal of the first capacitor unit C1 and the second capacitor unit C2 and the common terminal of the third capacitor unit C3 and the fourth capacitor unit C4 in a case that the inverter is in the ninth operation mode, and the small current can be relatively low in a case that the third capacitor unit C3 has a capacitance approximating to that of the fourth capacitor unit C4, the first capacitor unit C1 has a capacitance approximating to that of the second capacitor unit C2, and the first inductor L1 has a inductance approximating to that of the second inductor L2.

[0087] An inductor for filtering may be connected in serial between each of the two output terminals of the inverter according to the present embodiment and the alternate-current grid to achieve a better current quality of the alternate-current grid. As shown in Figure 8, the second terminal of the first inductor L1 also may be connected to the positive pole of the alternate-current grid ug via a third inductor L3, and the second terminal of the second inductor L2 also may be connected to the negative pole of the alternate-current grid ug via a fourth inductor L4, where the inductance values of the third inductor L3 and the fourth inductor L4 are relatively small as compared to the first inductor L1 and the second inductor L2.

[0088] Those described above are only preferable embodiments of the disclosure. It should be noted that, for the skilled in the art, improvements and modifications may also be made without departing from the principle of the disclosure. Those improvements and modifications should also be included in the scope of protection of the disclosure.


Claims

1. A five-level inverter, comprising: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first capacitor unit, a second capacitor unit, a third capacitor unit, a fourth capacitor unit, a first inductor, a second inductor, a first reverse flow preventive element and a second reverse flow preventive element; wherein
a positive pole of a direct-current power supply is connected to a first terminal of the first switch and a first terminal of the first capacitor unit; a negative pole of the direct-current power supply is connected to a first terminal of the second switch and a second terminal of the second capacitor unit;
a second terminal of the first switch is connected to a first terminal of the first reverse flow preventive element, a first terminal of the third switch and a first terminal of the fifth switch;
a second terminal of the first reverse flow preventive element is connected to a second terminal of the first capacitor unit, a first terminal of the second capacitor unit and a first terminal of the second reverse flow preventive element;
a second terminal of the second reverse flow preventive element is connected to a second terminal of the second switch, a first terminal of the fourth switch and a first terminal of the sixth switch;
a second terminal of the third switch is connected to a first terminal of the first inductor and a second terminal of the fourth switch; a second terminal of the fifth switch is connected to a first terminal of the second inductor and a second terminal of the sixth switch;
a second terminal of the first inductor is connected to a first terminal of the third capacitor unit; a second terminal of the second inductor is connected to a second terminal of the fourth capacitor unit;
a second terminal of the third capacitor unit and a first terminal of the fourth capacitor unit are connected to the second terminal of the first capacitor unit;
the first reverse flow preventive element is configured to prevent a current from flowing from the first terminal of the first reverse flow preventive element to the second terminal of the first reverse flow preventive element in a case that the first switch is turned on;
the second reverse flow preventive element is configured to prevent a current from flowing from the first terminal of the second reverse flow preventive element to the second terminal of the second reverse flow preventive element in a case that the second switch is turned on; and
the second terminal of the first inductor and the second terminal of the second inductor are alternate-current output terminals of the inverter.
 
2. The inverter according to claim 1, wherein a current flows from the first terminal of the first switch to the second terminal of the first switch in a case that the first switch is turned on; a current flows from the first terminal of the third switch to the second terminal of the third switch in a case that the third switch is turned on; and a current flows from the first terminal of the fifth switch to the second terminal of the fifth switch in a case that the fifth switch is turned on; and
a current flows from the second terminal of the second switch to the first terminal of the second switch in a case that the second switch is turned on; a current flows from the second terminal of the fourth switch to the first terminal of the fourth switch in a case that the fourth switch is turned on; and a current flows from the second terminal of the sixth switch to the first terminal of the sixth switch in a case that the sixth switch is turned on.
 
3. The inverter according to claim 1, wherein the inverter is configured to operate in six active operation modes which comprises a first operation mode, a second operation mode, a third operation mode, a fourth operation mode, a fifth operation mode and a sixth operation mode; wherein
the first switch, the second switch, the third switch and the sixth switch are turned on, and the fourth switch and the fifth switch are turned off, in a case that the inverter is in the first operation mode;
the inverter is configured to operate in a first operation sub-mode or a second operation sub-mode in a case that the inverter is in the second operation mode; the first switch, the third switch and the sixth switch are turned on, the second switch, the fourth switch and the fifth switch are turned off, the second terminal of the first capacitor unit is in a charging state, in a case that the inverter is in the first operation sub-mode; and the second switch, the third switch and the sixth switch are turned on, the first switch, the fourth switch and the fifth switch are turned off, and the second terminal of the first capacitor unit is in a discharging state, in a case that the inverter is in the second operation sub-mode;
the third switch and the sixth switch are turned on, and the first switch, the second switch, the fourth switch and the fifth switch are turned off, in a case that the inverter is in the third operation mode;
the first switch, the second switch, the fourth switch and the fifth switch are turned on, and the third switch and the sixth switch are turned off, in a case that the inverter is in the fourth operation mode;
the inverter is configured to operate in a third operation sub-mode or a fourth operation sub-mode in a case that the inverter is in the fifth operation mode; the first switch, the fourth switch and the fifth switch are turned on, the second switch, the third switch and the sixth switch are turned off, and the second terminal of the first capacitor unit is in the charging state, in a case that the inverter is in the third operation sub-mode; and the second switch, the fourth switch and the fifth switch are turned on, the first switch, the third switch and the sixth switch are turned off, and the second terminal of the first capacitor unit is in the discharging state, in a case that the inverter is in the fourth operation sub-mode; and
the fourth switch and the fifth switch are turned on, and the first switch, the second switch, the third switch and the sixth switch are turned off, in a case that the inverter is in the sixth operation mode.
 
4. The inverter according to claim 3, wherein a period of a periodic signal outputted by the inverter comprises a first time interval, a second time interval, a third time interval, a fourth time interval, a fifth time interval and a sixth time interval; wherein
the inverter is configured to operate in the second operation mode and the third operation mode alternately during each of the first time interval and the third time interval;
the inverter is configured to operate in the first operation mode and the second operation mode alternately during the second time interval;
the inverter is configured to operate in the fifth operation mode and the sixth operation mode alternately during each of the fourth time interval and the sixth time interval; and
the inverter is configured to operate in the fourth operation mode and the fifth operation mode alternately during the fifth time interval.
 
5. The inverter according to claim 4, wherein the second terminal of the first capacitor unit is in a same charge-discharge state during the first time interval, the second time interval and the third time interval; and is in a same charge-discharge state during the fourth time interval, the fifth time interval and the sixth time interval, wherein the charge-discharge state of the second terminal of the first capacitor unit during fourth time interval, the fifth time interval and the sixth time interval is opposite to the charge-discharge state of the second terminal of the first capacitor unit during the first time interval, the second time interval and the third time interval; or
the second terminal of the first capacitor unit is in a same charge-discharge state during the first time interval, a latter half of the second time interval, the fourth time interval and a latter half of the fifth time interval; and is in a same charge-discharge state during a first half of the second time interval, the third time interval, a first half of the fifth time interval and the sixth time interval, wherein the charge-discharge state of the second terminal of the first capacitor unit during the first half of the second time interval, the third time interval, the first half of the fifth time interval and the sixth time interval is opposite to the charge-discharge state of the second terminal of the first capacitor unit during the first time interval, the latter half of the second time interval, the fourth time interval and the latter half of the fifth time interval; or
the second terminal of the first capacitor unit is in a same charge-discharge state during the first time interval, a latter half of the second time interval, a first half of the fifth time interval and the sixth time interval; and is in a same charge-discharge state during a first half of the second time interval, the third time interval, the fourth time interval and a latter half of the fifth time interval, wherein the charge-discharge state of the second terminal of the first capacitor unit during the first half of the second time interval, the third time interval, the fourth time interval and the latter half of the fifth time interval is opposite to the charge-discharge state of the second terminal of the first capacitor unit during the first time interval, the latter half of the second time interval, the first half of the fifth time interval and the sixth time interval.
 
6. The inverter according to any one of claims 1 to 5, wherein the inverter is configured to operate in three passive operation modes which comprises a seventh operation mode, a eighth operation mode and a ninth operation mode; wherein
the first switch, the second switch, the third switch and the sixth switch are turned on, and the fourth switch and the fifth switch are turned off, in a case that the inverter is in the seventh operation mode;
the third switch, the fourth switch, the fifth switch and the sixth switch are turned on, and the first switch and the second switch are turned off, in a case that the inverter is in the eighth operation mode; and
the first switch, the second switch, the fourth switch and the fifth switch are turned on, and the third switch and the sixth switch are turned off, in a case that the inverter is in the ninth operation mode.
 
7. The inverter according to any one of claims 1 to 5, wherein the first reverse flow preventive element is a first diode, and the second reverse flow preventive element is a second diode; wherein
the first terminal of the first reverse flow preventive element is a cathode of the first diode, and the second terminal of the first reverse flow preventive element is an anode of the first diode; and
the first terminal of the second reverse flow preventive element is a cathode of the second diode, and the second terminal of the second reverse flow preventive element is an anode of the second diode.
 
8. The inverter according to any one of claims 1 to 5, wherein the first reverse flow preventive element is the seventh switch, and the second reverse flow preventive element is the eighth switch; wherein
the seventh switch is turned off in a case that the first switch is turned on; and the eighth switch is turned off in a case that the second switch is turned on.
 
9. The inverter according to any one of claims 1 to 5, wherein the second terminal of the first inductor is further connected to a positive pole of an alternate-current grid via a third inductor, and the second terminal of the second inductor is further connected to a negative pole of the alternate-current grid via a fourth inductor.
 
10. The inverter according to any one of claims 1 to 5, wherein the direct-current power supply is a photovoltaic power supply.
 




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