(19)
(11)EP 2 972 642 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
29.04.2020 Bulletin 2020/18

(21)Application number: 14723159.1

(22)Date of filing:  12.03.2014
(51)International Patent Classification (IPC): 
H03F 3/45(2006.01)
G05F 1/575(2006.01)
(86)International application number:
PCT/US2014/023962
(87)International publication number:
WO 2014/159507 (02.10.2014 Gazette  2014/40)

(54)

USB REGULATOR WITH CURRENT BUFFER TO REDUCE COMPENSATION CAPACITOR SIZE AND PROVIDE FOR WIDE RANGE OF ESR VALUES OF EXTERNAL CAPACITOR

USB-REGLER MIT STROMPUFFER FÜR REDUZIERTE KOMPENSATIONSKONDENSATORGRÖSSE UND ZUR BEREITSTELLUNG EINES WEITEN BEREICHS VON ESR-WERTEN EINES EXTERNEN KONDENSATORS

RÉGULATEUR USB AVEC TAMPON DE COURANT PERMETTANT DE RÉDUIRE LA DIMENSION DU CONDENSATEUR DE COMPENSATION ET DE FOURNIR UNE LARGE GAMME DE VALEURS ESR DE CONDENSATEUR EXTERNE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 14.03.2013 US 201361780985 P
11.03.2014 US 201414204011

(43)Date of publication of application:
20.01.2016 Bulletin 2016/03

(73)Proprietor: Microchip Technology Incorporated
Chandler, AZ 85224-6199 (US)

(72)Inventors:
  • ZHOU, Huamin
    Chandler, AZ 85286 (US)
  • MARTIN, Woowai
    Phoenix, AZ 85048 (US)
  • ALBINA, Cristian
    Chandler, AZ 85224 (US)
  • SCHLUNDER, Fritz
    Gilbert, AZ 85296 (US)
  • LE, Minh
    Gilbert, AZ 85233 (US)

(74)Representative: sgb europe 
Lechnerstraße 25a
82067 Ebenhausen
82067 Ebenhausen (DE)


(56)References cited: : 
EP-A2- 1 191 416
US-A1- 2006 192 538
US-B1- 7 312 598
US-A1- 2005 168 272
US-A1- 2009 009 147
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description


    [0001] The present disclosure relates to USB voltage regulators, and, more particularly, to a USB voltage regulator having a current buffer to reduce compensation capacitor size and provide for a wide range of external compensation capacitor ESR values.

    [0002] USB voltage regulators operate with extremely low equivalent series resistance (ESR) values, for example around 10 milliohms. This ESR value is not very accurate because the ceramic capacitor manufacturers rarely specify the value of ESR in their data sheets. Additionally, the exact value depends on the size/voltage rating design of the external capacitor, and can vary based on user connection topology (circuit board layout and components used thereon), e.g., putting multiple small capacitors in parallel, thereby reducing ESR; or using thin/long printed circuit board traces to connect to the capacitor, thereby adding copper trace resistance ESR. Typically the externally compensated low-drop out (LDO) voltage regulator uses large value external capacitors for stability with a limited range of ESR ratings. The ESR values will heavily impact the design of LDO voltage regulators due to its variable zero pole locations depending upon the load conditions. Therefore existing products having a USB interface use standard voltage regulator architectures that require very large external capacitor sizes with variations of ESR values in order to keep the voltage regulator stable.

    [0003] Referring to Figures 1 and 1A, depicted are various frequency response graphs showing different ESR situations. Figure 1(a) shows a desired normal frequency response. Figure 1(b) shows a situation where the ESR is too high. Figure 1A(c) shows a situation where the ESR is too low. And Figure 1A(d) shows ESRs resulting in the dreaded "tunnel of death."

    [0004] US Patent Application Publication US 2005/0168272 discloses a voltage regulator with improved load regulation using adaptive biasing. US Patent Application Publication US 2006/0192538 discloses a low drop-out voltage regulator with enhanced frequency compensation. European Patent Application Publication EP 1 191 416 discloses a voltage regulator with high power supply ripple rejection.

    [0005] Therefore a need exists to significantly improve the range of external capacitors with small to large ESR values and reduce the size of the internal compensation capacitance value for stabilizing an associated voltage regulator, especially a low-drop out (LDO) voltage regulator. This and other objects can be achieved by a voltage regulator as defined in the independent claim. Further enhancements are characterized in the dependent claims.

    [0006] According to an embodiment, a voltage regulator may comprise: an operational amplifier; a gm enhanced current buffer driver; an output power driver, wherein the current buffer driver may be coupled between the operational amplifier and the output power driver; a current feedback circuit coupled between the output power driver and the current buffer driver; a feedback loop coupled between the output power driver and the operational amplifier, a biasing circuit coupled to the current buffer driver to set a biasing ratio for gm-boost of the current buffer driver, and an enable/disable function may be provided to enable/disable the biasing circuit for reducing standby current.

    [0007] According to a further embodiment, a gm-boost circuit may be coupled to the current buffer driver. According to a further embodiment, the gm-boost circuit increases the current buffer driver input impedance. According to a further embodiment, the gm-boost circuit enables the current buffer driver to have a large gm value. According to a further embodiment, a compensation capacitor may be coupled between the output power driver and a cascode node of the operational amplifier. According to a further embodiment, the voltage regulator may be a low drop out (LDO) voltage regulator. According to a further embodiment, the operational amplifier may have a first input adapted for coupling to a voltage reference, and a second input coupled to the feedback loop. According to a further embodiment, the operational amplifier may be a low gain and high bandwidth amplifier. According to a further embodiment, the low gain and high bandwidth amplifier may be a folded-cascode amplifier. According to a further embodiment, the operational amplifier may comprise diode connected PMOS transistors for lowering an output impedance of the folded-cascode amplifier. According to a further embodiment, the current buffer driver may be an operational transconductance amplifier (OTA).

    [0008] According to a further embodiment, the current feedback circuit may sense a current change at the output power driver. According to a further embodiment, the current feedback circuit may provide transient enhancement for improved load regulation. According to a further embodiment, the current feedback circuit may provide a feedback voltage from an output voltage node. According to a further embodiment, the current buffer driver may have a low output impedance. According to a further embodiment, capacitors in the biasing circuit may be provided for improving noise immunity thereof. According to a further embodiment, the voltage regulator may be a USB voltage regulator. According to a further embodiment, the current buffer driver may have low input impedance and may provide a high frequency pole that may not substantially affect the voltage regulator dominant pole.

    [0009] A more complete understanding of the present disclosure may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein:

    Figures 1 and 1A illustrate various frequency response graphs showing different ESR situations;

    Figure 2 illustrates a schematic block diagram of a USB voltage regulator, according to a specific example embodiment of this disclosure;

    Figures 3, 3A and 3B illustrate in combination a schematic diagram of a folded-cascode amplifier having bias, gm-boost, current driver and current feedback circuits, according to a specific embodiment of this disclosure; and

    Figures 4 and 5 illustrate transient and regulation response curves, according to the teachings of this disclosure.



    [0010] In typical low-drop out regulator (LDO) designs, the output load is not always constant. As the load changes, the pole location at the output varies from relatively high frequency (full load, e.g., >30 mA) to very low frequency (no load or very low load, e.g., < 100µA), resulting in difficulty in separating the output pole and the gate pole due to large power PMOS transistor size. A USB regulator has a very large power PMOS transistor as an output driver due to the large transition range in load currents, typically from very low, less than 250 µA to very large at about 60 mA. Due to this unique application, SoC (system on chip) design (capacitor-less architecture) is very hard to achieve. An external capacitor is needed for USB LDO voltage regulator applications. The external capacitor may have very different ESR (equivalent series resistance) values ranging from a few milliohms to tens of ohms causing the output pole-zero locations to shift drastically. Therefore a need exists to push the gate pole of the last stage PMOS power transistor to a higher frequency when using external capacitors in, for example but not limited to, a USB LDO voltage regulator.

    [0011] According to various embodiments, a voltage regulator may comprise a large gm (transconductance) current driver (low impedance current buffer amplifier) added between a first stage operation amplifier (OpAmp) and a last stage power transistor, e.g., p-channel metal oxide semiconductor (PMOS) transistor. This current buffer allows a significant reduction of the maximum internal compensation capacitance to about 3.7 picofarads, and the working range of the external load capacitance from about 0.4 microfarads to about 4.7 microfarads. In addition, the current buffer, according to the teachings of this disclosure, offers the circuit designer a wider range of external capacitor sizes to choose from. The current buffer compensation circuit described and claimed herein allows reduced external capacitor size that increases the overall circuit board layout efficiency and flexibility of capacitor choices. In addition, according to various embodiments, the voltage regulator, e.g., USB voltage regulator, may consume less power by, for example but is not limited to, using low-drop out (LDO) voltage regulator circuit designs, according to the teachings of this disclosure.

    [0012] According to various embodiments, various values of ESR may be handled by separating the poles inside of the voltage regulator circuit sufficiently to create an approximate one pole system. Referring to Figure 2, depicted is a schematic block diagram of a voltage regulator, according to a specific example embodiment of this disclosure. The regulator may comprise a low-gain operational amplifier (OpAmp) 202, a low-impedance current buffer driver 204, and a power output driver 206, e.g., PMOS. The key to being able to use smaller value internal and external capacitances is to have a large gm current driver buffer amplifier 204 between the first stage OpAmp 202 and the last stage power output driver 206. The voltage regulator of Figure 2 may further comprise biasing circuits 208, current feedback 210, a feedback loop 212, a compensation capacitor 214 and a gm-boost circuit 218. This voltage regulator may supply power (voltage and current) to an external load and capacitor 216 and may further be used as a USB voltage regulator.

    [0013] The implementation of the OpAmp 202 as a folded-cascode configuration is due to its unique architecture which results in a single pole at the output that minimizes the complexity of its compensation. The current buffer driver 204 acts like a low impedance driver which connects between the OpAmp 202 and the output driver 206. Since the output driver 206 may provide very large amounts of switching current during power supply operation, the gate capacitance is significantly high due to the size of the driver, thereby resulting in the generation of a pole at relatively low frequency. Thus the current buffer driver 204 pushes this pole to a high frequency beyond unity-gain frequency due to its low-impedance characteristics in order to get the pole-splitting effect. To achieve this, it is necessary to provide a fairly large gm value of the current buffer driver 204. The gm-boost circuit 218 may provide a gm-boost technique that will increase the impedance value of the current buffer driver 204 with the help of the current feedback 210 which may sense the current change at the output of the output driver 206. The current feedback 210 also may behave like a transient enhancement circuit which will help with load regulation of the regulator during, for example but is not limited to, USB power supply operation.

    [0014] The input stage OpAmp 202 may be a low-gain, high-bandwidth amplifier comprising diode connected PMOS transistors that lower the output impedance of the folded-cascode amplifier. Referring to Figures 3, 3A and 3B, depicted in combination is a schematic diagram of a folded-cascode amplifier having gm-boost, current driver and current feedback circuits, according to a specific embodiment of this disclosure. A folded-cascode amplifier design was selected for the input stage OpAmp 202 for the following reasons: (1) The architecture forms only one pole at the output of the folded stage which reduces the complexity of frequency compensation, (2) it provides a good driving capability for the source follower stage of the current buffer 204 shown in Figure 3B placed thereafter due to its characteristics of being an OTA (Operational Transconductance Amplifier) that may be adapted to drive a capacitive load such as the gate of transistor 384, and (3) its uniqueness of the folded stage (transistors 360 and 366 shown in Figure 3A) may be used as an indirect compensation node E.

    [0015] Shown in Figure 3 is the bias circuit 208 for the USB regulator. Transistors 320, 330, 334 and 336 may be shut off during disabling/power down operation to make sure this circuit will consume substantially no DC current. Capacitors 322 and 342 are coupling capacitors to improve the VDD noise cancelation making sure the gates of transistors 324, 326 and 328 are moving the same way as VDD (node A) to cancel the power noise resulting with Vsg noise = 0. 342 acts similarly to help transistor 340 have better ground noise immunity resulting in Vgs noise = 0. Node M is the enable signal coming to the regulator circuit so that the module can be turned off when disabled.

    [0016] The output stage (transistors 350, 360 and 366) from the OpAmp 202 (Figure 3A, node C) then connects to the gate of the PMOS second stage transistor 384. The low impedance looking into the amplifier function of the current buffer 204 and source of transistor 384 creates a fairly high frequency pole that would be irrelevant to interact with the system dominant pole, which connects to the power PMOS transistor 380 in the power output driver 206, thereby having more efficient pole-splitting, and allowing easier frequency compensation. The current driver stage transistor 384 (in the current buffer 204) of the regulator circuit shown in Figure 3B creates a low impedance environment using the current buffer (transistors 384 and 394, and resistor 372) to separate the poles seen on the big power output driver 206 comprising transistor 380 and the internal stages of the regulator (OpAmp 202, Figure 3A, node C). By literally pushing the pole at the gate of transistor 380 to a high frequency domain, effectively leaves the only dominant pole at the output (node C) of the OpAmp 202 during full-load conditions. To achieve such operation, a gm-boost stage may be used.

    [0017] The gm-boost stage 218 may comprise transistors 368, 370, 374, 376, 378, 382, 396, 394, 400, 402, 384 and resistor 372 shown in Figure 3B of the current buffer 204. The current driver may comprise transistors 370, 384 and 394, and resistor 372 shown in Figure 3B of the current buffer 204, and the current feedback circuits 210 may comprise transistors 374, 376, 378, 400, 402, and 394 shown in Figure 3B of the current buffer 204. The gm of the PMOS current buffer driver 204 may comprise transistor 384 and may be coupled to two sources of currents, one from the bias network and the other as current feedback 210 comprising transistors 378, 400, 402 and 376 from the power output stage 206 that may comprise transistor 380. The bias network may be fixed by transistor 396. Then these currents are ratio'ed in transistors 368 and 370 to provide a sufficient amount of current for the driver transistor 384 but not enough to increase more current based upon a limited current mirror by transistor 396.

    [0018] The feedback network 212 may comprise transistor 380, the resistors 388 and 390 may be coupled to the output transistor 380, and may actively provide current to the current driver transistor 384 when the regulation circuit experiences different output load conditions. This feedback network 212 provides feedback voltage to one differential input (transistor 356, Figure 3A, node D) of the OpAmp 202 to compare with a reference voltage (from a voltage reference not shown) connected to the other differential input (transistor 354, Figure 3A, node H). The only compensation capacitor required between the output stage of the OpAmp 202 node C in Figure 3A and the output stage of the regulator above resistor 388 coupled to output node N in Figure 3B need only be sized to make sure that the poles are even further well separated. This value is limited to a small number which helps in stabilizing the regulator system. With the simple current buffer 204 comprising transistors 368, 370, 374, 376, 378, 382, 396, 394, 400, 402, 384 and resistor 372, the voltage regulator acts like a pseudo "one-pole" system that is independent from the output pole changing so long as it falls within the bandwidth of the system. Thus, the range of ESR is extended along with the output capacitance. Therefore a wider range of external capacitors may be effectively used, according to the teachings of this disclosure.

    [0019] Referring to Figures 4 and 5, depicted are transient and regulation response curves, according to the teachings of this disclosure. Shown are line transient response graphs reflecting the AC response of the system wherein the regulator output is stable with supply voltage change in transient. These graphs show the regulator system using a small compensation capacitor is stable.


    Claims

    1. A voltage regulator, comprising:

    an operational amplifier (202);

    a current buffer driver (204);

    an output power driver (206), wherein the current buffer driver (204) is coupled between the operational amplifier (202) and the output power driver (206);

    a current feedback circuit (210) coupled between the output power driver (206) and the current buffer driver (204); and

    a feedback loop (212) coupled between the output power driver (206) and the operational amplifier (202),

    characterized in that

    the current buffer driver (204) is a gm enhanced current buffer driver (204), and wherein the voltage regulator further comprises a biasing circuit (208) coupled to the current buffer driver (204) for providing a gm-boost of the gm enhanced current buffer driver (204) and an enable/disable function to enable/disable the biasing circuit (208) for reducing standby current.


     
    2. The voltage regulator according to claim 1, further comprising a gm-boost circuit (218) coupled to the current buffer driver (204), wherein the gm-boost circuit (218) increases the current buffer driver input impedance.
     
    3. The voltage regulator according to claim 1 or 2, further comprising a gm-boost circuit (218) coupled to the current buffer driver (204), wherein the gm-boost circuit (218) enables the current buffer driver (204) to have a gm value that is large enough to be able to use smaller value internal and external capacitances.
     
    4. The voltage regulator according to one of the preceding claims, further comprising a compensation capacitor (214) coupled between the output power driver (206) and a cascode node of the operational amplifier (202).
     
    5. The voltage regulator according to one of the preceding claims, wherein the voltage regulator is a low drop out (LDO) voltage regulator.
     
    6. The voltage regulator according to one of the preceding claims, wherein the voltage regulator is a USB voltage regulator.
     
    7. The voltage regulator according to one of the preceding claims, wherein the operational amplifier (202) has a first input adapted for coupling to a voltage reference, and a second input coupled to the feedback loop (212).
     
    8. The voltage regulator according to one of the preceding claims, wherein the operational amplifier (202) is a low gain and high bandwidth amplifier, preferably a folded-cascode amplifier.
     
    9. The voltage regulator according to claim 8, wherein the operational amplifier (202) comprises diode connected PMOS transistors for lowering an output impedance of the folded-cascode amplifier.
     
    10. The voltage regulator according to one of the preceding claims, wherein the current buffer driver (202) is an operational transconductance amplifier (OTA).
     
    11. The voltage regulator according to one of the preceding claims, wherein the current feedback circuit (210) senses a current change at the output power driver (206) and/or provides transient enhancement for improved load regulation.
     
    12. The voltage regulator according to one of the preceding claims, wherein the current feedback circuit provides a feedback voltage from an output voltage node.
     
    13. The voltage regulator according to one of the preceding claims 3-12, further comprising capacitors (322, 342) in the biasing circuit (208) for improving noise immunity thereof.
     
    14. The voltage regulator according to one of the preceding claims, wherein the current buffer driver (204) has low input impedance and provides a high frequency pole that does not substantially affect the voltage regulator dominant pole.
     
    15. The voltage regulator according to one of the preceding claims, wherein the current buffer (204) comprises a resistor coupled in series with a PMOS field effect transistor (FET) and a NMOS FET, wherein the PMOS FET is controlled by an output of the operational amplifier (202) and the NMOS FET is coupled with a current mirror (374, 376, 378, 400, 402).
     


    Ansprüche

    1. Spannungsregler, der aufweist:

    einen Operationsverstärker (202);

    einen Strompuffertreiber (204);

    einen Ausgangsleistungstreiber (206), wobei der Strompuffertreiber (204) zwischen den Operationsverstärker (202) und den Ausgangsleistungstreiber (206) gekoppelt ist;

    eine Stromrückkopplungsschaltung (210), die zwischen den Ausgangsleistungstreiber (206) und den Strompuffertreiber (204) gekoppelt ist; und

    eine Rückkopplungsschleife (212), die zwischen den Ausgangsleistungstreiber (206) und den Operationsverstärker (202) gekoppelt ist,

    dadurch gekennzeichnet, dass

    der Strompuffertreiber (204) ein gm-verstärkter Strompuffertreiber (204) ist, und wobei der Spannungsregler weiterhin eine Vorspannungsschaltung (208) aufweist, die mit dem Strompuffertreiber (204) gekoppelt ist, um eine gm-Verstärkung des gm-verstärkten Strompuffertreibers (204) und eine Aktivierungs- / Deaktivierungsfunktion zum Aktivieren / Deaktivieren der Vorspannungsschaltung (208) zum Reduzieren des Standby-Stroms bereitzustellen.


     
    2. Spannungsregler gemäß Anspruch 1, der weiterhin eine mit dem Strompuffertreiber (204) gekoppelte Spannungserhöhungsschaltung (218) aufweist, wobei die Spannungserhöhungsschaltung (218) die Strompuffertreibereingangsimpedanz erhöht.
     
    3. Spannungsregler gemäß Anspruch 1 oder 2, der weiterhin eine mit dem Strompuffertreiber (204) gekoppelte Spannungserhöhungsschaltung (218) aufweist, wobei die Spannungserhöhungsschaltung (218) dem Strompuffertreiber (204) ermöglicht einen gm-Wert aufzuweisen, der groß genug ist, um zu ermöglichen, dass kleinere interne und externe Kapazitäten verwendet werden.
     
    4. Spannungsregler gemäß einem der vorhergehenden Ansprüche, der weiterhin einen Kompensationskondensator (214) aufweist, der zwischen den Ausgangsleistungstreiber (206) und einen Kaskodeknoten des Operationsverstärkers (202) gekoppelt ist.
     
    5. Spannungsregler gemäß einem der vorhergehenden Ansprüche, wobei der Spannungsregler ein Low-Drop-Out- (LDO-) Spannungsregler ist.
     
    6. Spannungsregler gemäß einem der vorhergehenden Ansprüche, wobei der Spannungsregler ein USB-Spannungsregler ist.
     
    7. Spannungsregler gemäß einem der vorhergehenden Ansprüche, wobei der Operationsverstärker (202) einen ersten Eingang aufweist, der zum Koppeln mit einer Spannungsreferenz geeignet ist, und einen zweiten Eingang, der mit der Rückkopplungsschleife (212) gekoppelt ist.
     
    8. Spannungsregler gemäß einem der vorhergehenden Ansprüche, wobei der Operationsverstärker (202) ein Verstärker mit niedriger Verstärkung und hoher Bandbreite ist, vorzugsweise ein Folded-Cascode-Verstärker.
     
    9. Spannungsregler gemäß Anspruch 8, wobei der Operationsverstärker (202) mit Dioden verbundene PMOS-Transistoren zum Verringern einer Ausgangsimpedanz des Folded-Cascode-Verstärkers aufweist.
     
    10. Spannungsregler gemäß einem der vorhergehenden Ansprüche, wobei der Strompuffertreiber (202) ein Operations-Transkonduktanzverstärker (OTA) ist.
     
    11. Spannungsregler gemäß einem der vorhergehenden Ansprüche, wobei die Stromrückkopplungsschaltung (210) eine Stromänderung am Ausgangsleistungstreiber (206) erfasst und / oder eine vorübergehende Verstärkung für eine verbesserte Lastregelung bereitstellt.
     
    12. Spannungsregler gemäß einem der vorhergehenden Ansprüche, wobei die Stromrückkopplungsschaltung eine Rückkopplungsspannung von einem Ausgangsspannungsknoten bereitstellt.
     
    13. Spannungsregler gemäß einem der vorhergehenden Ansprüche 3 bis 12, der weiterhin Kondensatoren (322, 342) in der Vorspannungsschaltung (208) zum Verbessern der Störfestigkeit von dieser aufweist.
     
    14. Spannungsregler gemäß einem der vorhergehenden Ansprüche, wobei der Strompuffertreiber (204) eine niedrige Eingangsimpedanz aufweist und einen Hochfrequenzpol bereitstellt, der den dominanten Pol des Spannungsreglers im Wesentlichen nicht beeinflusst.
     
    15. Spannungsregler gemäß einem der vorhergehenden Ansprüche, wobei der Strompuffer (204) einen Widerstand aufweist, der mit einem PMOS-Feldeffekttransistor (FET) und einem NMOS-FET in Reihe gekoppelt ist, wobei der PMOS-FET durch einen Ausgang des Operationsverstärkers (202) gesteuert wird und der NMOS-FET mit einem Stromspiegel (374, 376, 378, 400, 402) gekoppelt ist.
     


    Revendications

    1. Régulateur de tension, comprenant :

    un amplificateur opérationnel (202) ;

    un circuit d'attaque de tampon de courant (204) ;

    un circuit d'attaque de puissance de sortie (206), dans lequel le circuit d'attaque de tampon de courant (204) est couplé entre l'amplificateur opérationnel (202) et le circuit d'attaque de puissance de sortie (206) ;

    un circuit de rétroaction de courant (210) couplé entre le circuit d'attaque de puissance de sortie (206) et le circuit d'attaque de tampon de courant (204) ; et

    une boucle de rétroaction (212) couplée entre le circuit d'attaque de puissance de sortie (206) et l'amplificateur opérationnel (202) ;

    caractérisé en ce que :
    le circuit d'attaque de tampon de courant (204) est un circuit d'attaque de tampon de courant à transconductance, gm, améliorée (204), et dans lequel le régulateur de tension comprend en outre un circuit de polarisation (208) couplé au circuit d'attaque de tampon de courant (204) en vue de fournir une amplification de transconductance du circuit d'attaque de tampon de courant à transconductance améliorée (204) et une fonction d'activation/désactivation destinée à activer/désactiver le circuit de polarisation (208) pour réduire un courant d'attente.


     
    2. Régulateur de tension selon la revendication 1, comprenant en outre un circuit d'amplification de transconductance (218) couplé au circuit d'attaque de tampon de courant (204), dans lequel le circuit d'amplification de transconductance (218) augmente l'impédance d'entrée de circuit d'attaque de tampon de courant.
     
    3. Régulateur de tension selon la revendication 1 ou 2, comprenant en outre un circuit d'amplification de transconductance (218) couplé au circuit d'attaque de tampon de courant (204), dans lequel le circuit d'amplification de transconductance (218) permet au circuit d'attaque de tampon de courant (204) de présenter une valeur de transconductance qui est suffisamment grande pour pouvoir utiliser des capacités internes et externes de valeur inférieure.
     
    4. Régulateur de tension selon l'une quelconque des revendications précédentes, comprenant en outre un condensateur de compensation (214) couplé entre le circuit d'attaque de puissance de sortie (206) et un nœud cascode de l'amplificateur opérationnel (202).
     
    5. Régulateur de tension selon l'une quelconque des revendications précédentes, dans lequel le régulateur de tension est un régulateur de tension à faible chute (LDO).
     
    6. Régulateur de tension selon l'une quelconque des revendications précédentes, dans lequel le régulateur de tension est un régulateur de tension USB.
     
    7. Régulateur de tension selon l'une quelconque des revendications précédentes, dans lequel l'amplificateur opérationnel (202) présente une première entrée adaptée en vue d'un couplage à une référence de tension, et une seconde entrée couplée à la boucle de rétroaction (212).
     
    8. Régulateur de tension selon l'une quelconque des revendications précédentes, dans lequel l'amplificateur opérationnel (202) est un amplificateur à faible gain et à bande passante élevée, de préférence un amplificateur cascode replié.
     
    9. Régulateur de tension selon la revendication 8, dans lequel l'amplificateur opérationnel (202) comprend des transistors PMOS connectés en diode pour abaisser une impédance de sortie de l'amplificateur cascode replié.
     
    10. Régulateur de tension selon l'une quelconque des revendications précédentes, dans lequel le circuit d'attaque de tampon de courant (202) est un amplificateur de transconductance opérationnel (OTA).
     
    11. Régulateur de tension selon l'une quelconque des revendications précédentes, dans lequel le circuit de rétroaction de courant (210) détecte une variation de courant au niveau du circuit d'attaque de puissance de sortie (206) et/ou fournit une amélioration transitoire pour une régulation de charge améliorée.
     
    12. Régulateur de tension selon l'une quelconque des revendications précédentes, dans lequel le circuit de rétroaction de courant fournit une tension de rétroaction à partir d'un nœud de tension de sortie.
     
    13. Régulateur de tension selon l'une quelconque des revendications 3 à 12, comprenant en outre des condensateurs (322, 342) dans le circuit de polarisation (208) en vue d'améliorer l'immunité au bruit de ce dernier.
     
    14. Régulateur de tension selon l'une quelconque des revendications précédentes, dans lequel le circuit d'attaque de tampon de courant (204) présente une impédance d'entrée faible et fournit un pôle haute fréquence qui n'affecte pas sensiblement le pôle dominant de régulateur de tension.
     
    15. Régulateur de tension selon l'une quelconque des revendications précédentes, dans lequel le circuit d'attaque de tampon de courant (204) comprend une résistance couplée en série avec un transistor à effet de champ (FET) PMOS et un transistor à effet de champ (FET) NMOS, dans lequel le transistor à effet de champ PMOS est commandé par une sortie de l'amplificateur opérationnel (202) et le transistor à effet de champ NMOS est couplé à un miroir de courant (374, 376, 378, 400, 402).
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description