(19)
(11)EP 3 002 781 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
09.10.2019 Bulletin 2019/41

(21)Application number: 14838639.4

(22)Date of filing:  19.08.2014
(51)Int. Cl.: 
H01L 21/331  (2006.01)
H01L 29/08  (2006.01)
H01L 29/739  (2006.01)
H01L 29/32  (2006.01)
(86)International application number:
PCT/CN2014/084720
(87)International publication number:
WO 2015/024502 (26.02.2015 Gazette  2015/08)

(54)

MANUFACTURING METHOD FOR REVERSE CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR

HERSTELLUNGSVERFAHREN FÜR RÜCKWÄRTSLEITENDEN BIPOLAREN TRANSISTOR MIT ISOLIERTEM GATE

PROCÉDÉ DE FABRICATION POUR UN TRANSISTOR BIPOLAIRE À GRILLE ISOLÉE À CONDUCTION INVERSE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 23.08.2013 CN 201310374240

(43)Date of publication of application:
06.04.2016 Bulletin 2016/14

(73)Proprietor: CSMC Technologies Fab2 Co., Ltd.
Jiangsu 214028 (CN)

(72)Inventors:
  • ZHANG, Shuo
    Jiangsu 214028 (CN)
  • RUI, Qiang
    Jiangsu 214028 (CN)
  • WANG, Genyi
    Jiangsu 214028 (CN)
  • DENG, Xiaoshe
    Jiangsu 214028 (CN)

(74)Representative: Manitz Finsterwald Patent- und Rechtsanwaltspartnerschaft mbB 
Martin-Greif-Strasse 1
80336 München
80336 München (DE)


(56)References cited: : 
CN-A- 1 691 349
CN-A- 102 916 042
CN-A- 103 125 023
US-B1- 6 482 681
US-B2- 8 299 495
CN-A- 102 741 982
CN-A- 103 035 691
US-A1- 2009 184 338
US-B2- 7 557 386
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    FIELD OF THE INVENTION



    [0001] The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method of manufacturing the reverse conducting insulated gate bipolar transistor. Related technology is known from CN 103 035 691 A.

    BACKGROUND OF THE INVENTION



    [0002] The insulated gate bipolar transistor (IGBT) generally is a common power switching device controlled by a voltage. It has the features of a large input capacitance, a high input resistance, high voltage resistance, a high work temperature, a simple control circuit and the like, and becomes a main device of the power electronics apparatus at the present stage. The reverse conducting insulated gate bipolar transistor is a new IGBT device, and it integrates an IGBT structure and a reverse conducting diode structure on a same chip, which can improve the passage of non-balanced carriers and optimizing the tail current. The reverse conducting IGBT device has many advantages of a small size, a high power density, a low cost, a high reliability and the like.

    [0003] The method of manufacturing the reverse conducting diode structure at the back side of the device in the method of manufacturing the common reverse conducting IGBT has two main manners. A method of manufacturing the reverse conducting diode structure of the reverse conducting IGBT is implemented by using two back side photoetching processes. Particularly, a P+ type area is formed by firstly performing selective implantation and diffusion processes, and then an N+ type area is formed by performing selective implantation and diffusion processes again. As a result, the N+ and P+ areas can be formed at intervals on the back side of the reverse conducting IGBT. The interval N+ and P+ areas are the reverse conducting diode structure. The back side N+ area of the reverse conducting IGBT formed by using this manufacturing method is shallower, and has a higher requirement for controlling the process. Once the doping concentration of the N+ area becomes higher, when the formed reverse conducting IGBT is forward conducted, a large implantation effect can be formed, resulting in losing the function of the reverse conducting IGBT.

    [0004] Another method of manufacturing the reverse conducting diode structure of the reverse conducting IGBT is described as follows. After the front side process is performed and the back side P+ layer is formed, digging of the trench is performed, and then the reverse conducting diode structure of the reverse conducting IGBT is finally formed by filling back side metal in the trench. The method of manufacturing the reverse conducting diode structure of the reverse conducting IGBT mainly use the means of digging of the trench and filling of the back side metal to form he reverse conducting diode structure. However, because the metal in the trench at the back side of the reverse conducting IGBT is limited by requirement of collector metal of the reverse conducting IGBT, the parameters of the reverse conducting diode can be adjusted only by adjusting the width and depth of the dug trench, resulting in troubling of the adjusting process and a high requirement of controlling the process. Therefore, from the above process methods, it can be understood that the common method of manufacturing the reverse conducting diode structure at the back side of the reverse conducting IGBT device has a higher requirement of controlling the manufacturing process, and a larger difficulty of manufacturing.

    SUMMARY OF THE INVENTION



    [0005] On the basis of this, it is necessary to provide a method of manufacturing a reverse conducting insulated gate bipolar transistor, which can reduce the requirement of controlling the process, and reduce the difficulty of manufacturing.

    [0006] A method of manufacturing a reverse conducting insulated gate bipolar transistor, is defined by claim 1.

    [0007] In one of embodiments, after forming the back side metal layer by performing the back side metalized process at the back side of the N-type substrate, the method further comprises controlling a carrier lifetime at a partial area in the N-type substrate by a local radiation technique.

    [0008] In one of embodiments, the local radiation technique radiates the N-type substrate by using electron or proton.

    [0009] In one of embodiments, the trench formed at the back side of the N-type substrate is of a rectangle shape.

    [0010] In one of embodiments, a depth of the trench formed at the back side of the N-type substrate is from 1 to 20µm, a width thereof is from 1 to 30µm, and a distance between two adjacent trenches is 50 to 300µm.

    [0011] In one of embodiments, the polysilicon deposited in the trench formed at the back side of the N-type substrate is N-type polysilicon.

    [0012] In one of embodiments, a doping concentration of the polysilicon deposited in the trench formed at the back side of the N-type substrate is from 1E17 to 1E21cm-3.

    [0013] In one of embodiments, from the N-type substrate to an external, the back side metal layer comprises aluminum, titanium, nickel and silver, which are laminated in that order.

    [0014] In one of embodiments, the dielectric layer is made of silicon dioxide and boro-phospho-silicate glass.

    [0015] In one of embodiments, the protecting layer is made of silicon nitride.

    [0016] The method of manufacturing the reverse conducting insulated gate bipolar transistor described above uses polysilicon to fill the trench at the back side of the reverse conducting insulated gate bipolar transistor. The parameters of the reverse conducting diode at the back side of the reverse conducting insulated gate bipolar transistor can be controlled by only precisely controlling the doping concentration of polysilicon, resulting in a lower requirement of controlling the process. The method of manufacturing the reverse conducting insulated gate bipolar transistor has a lower requirement of controlling the manufacturing process, and a less difficulty of manufacturing.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0017] 

    Fig. 1 shows a flow chart of a method of manufacturing the reverse conducting insulated gate bipolar transistor in an embodiment;

    Figs. 2 to 17 are schematic diagrams of corresponding reverse conducting insulated gate bipolar transistor in the manufacturing method of the field stop insulated gate bipolar transistor shown in Fig. 1.


    DETAILED DESCRIPTION OF THE EMBODIMENTS



    [0018] Referring to Fig. 1, in an embodiment, the method of manufacturing the reverse conducting insulated gate bipolar transistor is provided, which includes the following steps.

    [0019] In step Sill, an N-type substrate 110 is prepared. As shown in Fig. 2, the N-type substrate 110 is an N-type silicon substrate.

    [0020] In step S112, a gate oxide layer 121 is grown at a front side of the N-type substrate 110. As shown in Fig. 3, the thickness of the gate oxide layer 121 is from 600 angstroms to 1500 angstroms.

    [0021] In step S113, a polysilicon gate 122 is deposited on the gate oxide layer 121, as shown in Fig. 3.

    [0022] In step S114, a P well 123 is formed on the N-type substrate 110 by photoetching, etching and ion-implanting processes (referring to Fig. 5). Referring to Fig. 4, an implantation window of the P well 123 is formed by selectively etching the polysilicon gate 122 and the gate oxide layer 121 by the photoetching process. Referring to Fig. 5, a P-type impurity is implanted to the implantation window of the P well 123 by the self-aligned implantation process, and the P well 123 is formed by a drive-in process.

    [0023] In step S115, an N+ region 124 and a front side P+ region 125 are formed in the P well 123 by photoetching and ion-implanting processes (referring to Fig. 7). Referring to Fig. 6, ions are selectively implanted to the P well 123 by the photoetching process, and the N+ region 124 is formed by the drive-in process. Referring to Fig. 7, ions are selectively implanted to the P well 123 by the photoetching process, and the front side P+ region 125 is formed by the drive-in process. The N+ region 124 is mainly configured as an emitter of the reverse conducting insulated gate bipolar transistor.

    [0024] In step S116, a dielectric layer 126 is deposited at the front side of the N-type substrate 110. As shown in Fig. 8, the dielectric layer 126 is made of silicon dioxide and boro-phospho-silicate glass.

    [0025] In step S117, a protecting layer 127 is deposited on the dielectric layer 126. As shown in Fig. 9, the protecting layer is made of silicon nitride.

    [0026] In step S118, the N-type substrate 110 is ground by a back side grinding process. In step 118, the N-type substrate 110 is ground to the required thickness.

    [0027] In step S121, a back side P+ region 131 is formed by implanting a P-type impurity to a back side of the N-type substrate 110, as shown in Fig. 10.

    [0028] In step S122, a trench 132 is formed at the back side of the N-type substrate 110 by photoetching and etching processes. As shown in Fig. 11, in the embodiment, the trench 132 formed at the back side of the N-type substrate 110 is of a rectangle shape. Of course, the trench 132 formed at the back side of the N-type substrate 110 is of a circle, an oval, a trapezium and other appropriate shapes. When the trench 132 formed at the back side of the N-type substrate 110 is of a rectangle shape, a depth of the trench 132 is from 1 to 20µm, a width thereof is from 1 to 30µm, and a distance between two adjacent trenches 132 is from 50 to 300µm.

    [0029] In step S123, the trench 132 is filled by depositing polysilicon at the back side of the N-type substrate 110, and the polysilicon at an area outside of the trench 132 is etched. As shown in Fig. 12, in step S123, the reverse conducting diode is formed by filling polysilicon in the trench 132. The parameters of the reverse conducting diode at the back side of the manufactured reverse conducting insulated gate bipolar transistor can be adjusted by adjusting the doping concentration of polysilicon in the trench 132, so that the difficulty of the adjusting process is low and it is easy to control the process. Therefore, the manufacturing difficulty of the reverse conducting insulated gate bipolar transistor can be reduced. Of course, the parameters of the reverse conducting diode at the back side of the reverse conducting insulated gate bipolar transistor can be also adjusted by adjusting a width and a depth of the trench 132, or by adjusting the doping concentration of polysilicon in the trench 132 and the width and the depth of the trench 132 at the same time. Therefore, the difficulty of the adjusting process of the reverse conducting insulated gate bipolar transistor can be reduced, and then the manufacturing difficulty thereof is reduced. In the embodiment, the polysilicon deposited in the trench 132 formed at the back side of the N-type substrate 110 is N-type polysilicon. The doping concentration of the polysilicon deposited in the trench 132 is 1E17 to 1E21cm-3.

    [0030] In step S124, the protecting layer 127 at the front side of the N-type substrate is removed, as shown in Fig. 13.

    [0031] In step S125, a contact hole for shorting the N+ region 124 and the front side P+ region 125 is formed by selectively etching the dielectric layer 126, and a front side metal layer 128 is formed. As shown in Fig. 14, from the manufacturing flow of the reverse conducting insulated gate bipolar transistor described above, it can be understood that step S122 and step S123 are performed after performing step S116. In other words, forming the trench 132 at the back side of the N-type substrate 110 and depositing the polysilicon in the trench 132 are performed after performing depositing the dielectric layer 126 at the front side of the N-type substrate 110 rather than after performing the whole front side process of the reverse conducting insulated gate bipolar transistor. Such a manufacturing method has the following advantages. Firstly, after the P-type impurity is implanted at the back side of the N-type substrate 110 in step S121, the following front side thermal processes such as the hole reflow process (the hole reflow process is in forming the contact hole for shorting the N+ region 124 and the front side P+ region 125 by selectively etching the dielectric layer 126 and forming a front side metal layer 128 of step S125, and the temperature of the step S125 is about 850 degrees centigrade) and so on are performed. The activity of the P-type impurity at the back side of the N-type substrate 110 is very high without performing the annealing process individually. Therefore, the step of the thermal annealing of the P-type impurity at the back side of the N-type substrate 110 can be omitted. Further, the polysilicon in the trench 123 at the back side of the N-type substrate 110 and the polysilicon of the front side are processed separately, thus easily controlling the doping concentration of the polysilicon.

    [0032] In step S126, a passivation layer 129 is deposited at the front side of the N-type substrate 110. As shown in Fig. 15, here, a pad area is formed by performing the etching process.

    [0033] In step S127, a back side metal layer 133 is formed by performing a back side metalized process at the back side of the N-type substrate 110. In the embodiment, from the N-type substrate to an external, the back side metal layer 133 at the back side of the N-type substrate 110 comprises aluminum, titanium, nickel and silver, which are laminated in that order. In other words, the outermost layer is metal silver.

    [0034] In step S128, a carrier lifetime at a partial area 111 in the N-type substrate 110 is controlled by a local radiation technique. As shown in Fig. 17, in the embodiment, the local radiation technique radiates the N-type substrate 110 by using electron or proton to control the life of the carrier at a partial area 111 in the N-type substrate 110. Therefore, manufacturing of the reverse conducting insulated gate bipolar transistor is completed.

    [0035] The method of manufacturing the reverse conducting insulated gate bipolar transistor described above uses polysilicon for filling the trench at the back side of the reverse conducting insulated gate bipolar transistor. Thus, the parameters of the reverse conducting diode at the back side of the reverse conducting insulated gate bipolar transistor can be controlled by only precisely controlling the doping concentration of polysilicon, resulting in a lower requirement of controlling the process. Therefore, the method of manufacturing the reverse conducting insulated gate bipolar transistor has a lower requirement of controlling the manufacturing process, and a less difficulty of manufacturing.

    [0036] Although the invention is illustrated and described herein with reference to specific embodiments, the invention is not intended to be limited to the details shown. Rather, various modifications may be made within the scope of the claims and without departing from the invention.


    Claims

    1. A method of manufacturing a reverse conducting insulated gate bipolar transistor, comprising the following steps in sequence:

    preparing (S111) an N-type substrate (110);

    growing (S112) a gate oxide layer (121) at a front side of the N-type substrate (110);

    depositing (S113) a polysilicon gate (122) on the gate oxide layer (121);

    forming (S114) a P well (123) on the N-type substrate (110) by photoetching, etching and ion-implanting processes;

    forming (S115) an N+ region (124) and a front side P+ region (125) in the P well (123) by photoetching and ion-implanting processes;

    depositing (S116) a dielectric layer (126) at the front side of the N-type substrate (110);

    depositing (S117) a protecting layer (127) on the dielectric layer (126);

    grinding (S118) the N-type substrate (110) by a back side grinding process;

    forming (S121) a back side P+ region (131) by implanting a P-type impurity to a back side of the N-type substrate (110);

    forming (S122) a trench (132) at the back side of the N-type substrate (110) by photoetching and etching processes;

    filling (S123) the trench (132) by depositing polysilicon at the back side of the N-type substrate (110), and etching the polysilicon positioned at an area outside of the trench (132);

    removing (S124) the protecting layer (127) at the front side of the N-type substrate (110);

    selectively etching (S125) the dielectric layer (126) to form a contact hole for shorting the N+ region (124) and the front side P+ region (125), and forming (S125) a front side metal layer (128);

    depositing (S126) a passivation layer (129) at the front side of the N-type substrate (110); and

    performing (S127) a back side metallization process at the back side of the N-type substrate (110), and forming a back side metal layer (133).


     
    2. The method of manufacturing the reverse conducting insulated gate bipolar transistor of claim 1, characterized in that, after forming (S127) the back side metal layer (133) by performing the back side metalized process at the back side of the N-type substrate (110), the method further comprises controlling (S128) a carrier lifetime at a partial area (111) in the N-type substrate (110) by a local radiation technique.
     
    3. The method of manufacturing the reverse conducting insulated gate bipolar transistor of claim 2, characterized in that, the local radiation technique radiates the N-type substrate (110) by using electron or proton.
     
    4. The method of manufacturing the reverse conducting insulated gate bipolar transistor of claim 1, characterized in that, the trench (132) formed at the back side of the N-type substrate (110) is of a rectangle shape.
     
    5. The method of manufacturing the reverse conducting insulated gate bipolar transistor of claim 4, characterized in that, a depth of the trench (132) formed at the back side of the N-type substrate (110) is from 1 to 20µm, a width thereof is from 1 to 30µm, and a distance between two adjacent trenches is from 50 to 300µm.
     
    6. The method of manufacturing the reverse conducting insulated gate bipolar transistor of claim 1, characterized in that, the polysilicon deposited in the trench (132) formed at the back side of the N-type substrate (110) is N-type polysilicon.
     
    7. The method of manufacturing the reverse conducting insulated gate bipolar transistor of claim 6, characterized in that, a doping concentration of the polysilicon deposited in the trench (132) formed at the back side of the N-type substrate (110) is 1E17 to 1E21cm-3.
     
    8. The method of manufacturing the reverse conducting insulated gate bipolar transistor of any one of claims 1 to 7, characterized in that, from the N-type substrate (110) to an external, the back side metal layer (133) comprises aluminum, titanium, nickel and silver, which are laminated in that order.
     
    9. The method of manufacturing the reverse conducting insulated gate bipolar transistor of any one of claims 1 to 7, characterized in that, the dielectric layer (126) is made of silicon dioxide and boro-phospho-silicate glass.
     
    10. The method of manufacturing the reverse conducting insulated gate bipolar transistor of any one of claims 1 to 7, characterized in that, the protecting layer (127) is made of silicon nitride.
     


    Ansprüche

    1. Verfahren zum Herstellen eines rückwärtsleitenden Bipolartransistors mit isoliertem Gate, mit den folgenden Schritten in Folge:

    Herstellen (S111) eines Substrats (110) vom N-Typ;

    Aufwachsen (S112) einer Gateoxidschicht (121) auf einer Vorderseite des Substrats (110) vom N-Typ;

    Abscheiden (S113) eines Polysiliziumgates (122) auf der Gateoxidschicht (121);

    Formen (S114) einer P-Wanne (123) auf dem Substrat (110) vom N-Typ durch Photoätz-, Ätz- und lonenimplantationsprozesse;

    Formen (S115) eines N+-Gebietes (124) und eines vorderseitigen P+-Gebietes (125) in der P-Wanne (123) durch Photoätz- und lonenimplantationsprozesse;

    Abscheiden (S116) einer dielektrischen Schicht (126) auf der Vorderseite des Substrats (110) vom N-Typ;

    Abscheiden (S117) einer Schutzschicht (127) auf der dielektrischen Schicht (126);

    Schleifen (S118) des Substrats (110) vom N-Typ durch einen rückseitigen Schleifprozess;

    Formen (S121) eines rückseitigen P+-Gebietes (131) durch Implantieren einer Unreinheit vom P-Typ auf einer Rückseite des Substrats (110) vom N-Typ;

    Formen (S122) eines Grabens (132) auf der Rückseite des Substrats (110) vom N-Typ durch Photoätz- und Ätzprozesse;

    Füllen (S123) des Grabens (132) durch Abscheiden von Polysilizium auf der Rückseite des Substrats (110) vom N-Typ und Ätzen des Polysiliziums, das an einem Bereich außerhalb des Grabens (132) positioniert ist;

    Entfernen (S124) der Schutzschicht (127) an der Vorderseite des Substrats (110) vom N-Typ;

    selektives Ätzen (S125) der dielektrischen Schicht (126), um ein Kontaktloch zum Kurzschließen des N+-Gebietes (124) und des vorderseitigen P+-Gebietes (125) zu bilden, und Formen (S125) einer vorderseitigen Metallschicht (128);

    Abscheiden (S126) einer Passivierungsschicht (129) an der Vorderseite des Substrats (110) vom N-Typ; und

    Ausführen (S127) eines rückseitigen Metallisierungsprozesses auf der Rückseite des Substrats (110) vom N-Typ und Formen einer rückseitigen Metallschicht (133).


     
    2. Verfahren zum Herstellen des rückwärtsleitenden Bipolartransistors mit isoliertem Gate nach Anspruch 1, dadurch gekennzeichnet, dass nach dem Formen (S127) der rückseitigen Metallschicht (133) durch Ausführen des Prozesses zur rückseitigen Metallisierung auf der Rückseite des Substrats (110) vom N-Typ das Verfahren ferner umfasst, dass eine Trägerlebensdauer auf einem Teilbereich (111) in dem Substrat (110) vom N-Typ durch eine lokale Bestrahlungstechnik gesteuert (S128) wird.
     
    3. Verfahren zum Herstellen des rückwärtsleitenden Bipolartransistors mit isoliertem Gate nach Anspruch 2, dadurch gekennzeichnet, dass die lokale Bestrahlungstechnik das Substrat (110) vom N-Typ durch Verwendung von Elektronen oder Protonen bestrahlt.
     
    4. Verfahren zum Herstellen des rückwärtsleitenden Bipolartransistors mit isoliertem Gate nach Anspruch 1, dadurch gekennzeichnet, dass der Graben (132), der auf der Rückseite des Substrats (110) vom N-Typ gebildet ist, eine rechteckige Form aufweist.
     
    5. Verfahren zum Herstellen des rückwärtsleitenden Bipolartransistors mit isoliertem Gate nach Anspruch 4, dadurch gekennzeichnet, dass eine Tiefe des Grabens (132), der auf der Rückseite des Substrats (110) vom N-Typ geformt ist, 1 bis 20 µm beträgt, eine Breite desselben zwischen 1 und 30 µm liegt und eine Distanz zwischen zwei benachbarten Gräben zwischen 50 und 300 µm liegt.
     
    6. Verfahren zum Herstellen des rückwärtsleitenden Bipolartransistors mit isoliertem Gate nach Anspruch 1, dadurch gekennzeichnet, dass das Polysilizium, das in dem Graben (132) abgeschieden ist, der an der Rückseite des Substrats (110) vom N-Typ gebildet ist, ein Polysilizium vom N-Typ ist.
     
    7. Verfahren zum Herstellen des rückwärtsleitenden Bipolartransistors mit isoliertem Gate nach Anspruch 6, dadurch gekennzeichnet, dass eine Dotierkonzentration des Polysiliziums, das in dem Graben (132) abgeschieden ist, der an der Rückseite des Substrats (110) vom N-Typ gebildet ist, 1E17 bis 1E21 cm-3 ist.
     
    8. Verfahren zum Herstellen des rückwärtsleitenden Bipolartransistors mit isoliertem Gate nach einem der Ansprüche 1 bis 7, dadurch gekennzeichnet, dass die rückseitige Metallschicht (133) von dem Substrat (110) vom N-Typ zu einer Außenseite Aluminium, Titan, Nickel und Silber umfasst, die in dieser Reihenfolge laminiert sind.
     
    9. Verfahren zum Herstellen des rückwärtsleitenden Bipolartransistors mit isoliertem Gate nach einem der Ansprüche 1 bis 7, dadurch gekennzeichnet, dass die dielektrische Schicht (126) aus Siliziumdioxid und Borphosphosilikatglas besteht.
     
    10. Verfahren zum Herstellen des rückwärtsleitenden Bipolartransistors mit isoliertem Gate nach einem der Ansprüche 1 bis 7, dadurch gekennzeichnet, dass die Schutzschicht (127) aus Siliziumnitrid besteht.
     


    Revendications

    1. Procédé de fabrication d'un transistor bipolaire à grille isolée à conduction inverse, comprenant, en séquence, les étapes suivantes consistant à :

    préparer (S111) un substrat de type N (110) ;

    faire croître (S112) une couche d'oxyde de grille (121) sur une face avant du substrat de type N (110) ;

    déposer (S113) une grille en polysilicium (122) sur la couche d'oxyde de grille (121) ;

    former (S114) un puits P (123) sur le substrat de type N (110) par des processus de photogravure, de gravure et d'implantation ionique ;

    former (S115) une région N+ (124) et une région P+ de face avant (125) dans le puits P (123) par des processus de photogravure et d'implantation ionique ;

    déposer (S116) une couche diélectrique (126) sur la face avant du substrat de type N (110) ;

    déposer (S117) une couche protectrice (127) sur la couche diélectrique (126) ;

    rectifier (S118) le substrat de type N (110) par un processus de rectification de face arrière ;

    former (S121) une région P+ de face arrière (131) en implantant une impureté de type P dans une face arrière du substrat de type N (110) ;

    former (S122) une tranchée (132) sur la face arrière du substrat de type N (110) par des processus de photogravure et de gravure ;

    remplir (S123) la tranchée (132) en déposant du polysilicium sur la face arrière du substrat de type N (110) et graver le polysilicium positionné sur une zone extérieure de la tranchée (132) ;

    éliminer (S124) la couche protectrice (127) sur la face avant du substrat de type N (110) ;

    graver sélectivement (S125) la couche diélectrique (126) pour former un trou de contact pour court-circuiter la région N+ (124) et la région P+ de face avant (125), et former (S125) une couche métallique de face avant (128) ;

    déposer (S126) une couche de passivation (129) sur la face avant du substrat de type N (110) ; et

    effectuer (S 127) un processus de métallisation de face arrière sur la face arrière du substrat de type N (110) et former une couche métallique de face arrière (133).


     
    2. Procédé de fabrication du transistor bipolaire à grille isolée à conduction inverse selon la revendication 1, caractérisé en ce que, après avoir formé (S127) la couche métallique de face arrière (133) en effectuant le processus de métallisation de face arrière sur la face arrière du substrat de type N (110), le procédé consiste en outre à commander (S128) une durée de vie des porteurs sur une zone partielle (111) du substrat de type N (110) par une technique d'irradiation locale.
     
    3. Procédé de fabrication du transistor bipolaire à grille isolée à conduction inverse selon la revendication 2, caractérisé en ce que la technique d'irradiation locale irradie le substrat de type N (110) en utilisant des électrons ou des protons.
     
    4. Procédé de fabrication du transistor bipolaire à grille isolée à conduction inverse selon la revendication 1, caractérisé en ce que la tranchée (132) formée sur la face arrière du substrat de type (110) N a une forme rectangulaire.
     
    5. Procédé de fabrication du transistor bipolaire à grille isolée à conduction inverse selon la revendication 4, caractérisé en ce que la profondeur de la tranchée (132) formée sur la face arrière du substrat de type N (110) est de 1 à 20 µm, sa largeur est de 1 à 30 µm et la distance entre deux tranchées adjacentes est de 50 à 300 µm.
     
    6. Procédé de fabrication du transistor bipolaire à grille isolée à conduction inverse selon la revendication 1, caractérisé en ce que le polysilicium déposé dans la tranchée (132) formée sur la face arrière du substrat de type N (110) est du polysilicium de type N.
     
    7. Procédé de fabrication du transistor bipolaire à grille isolée à conduction inverse selon la revendication 6, caractérisé en ce que la concentration de dopage du polysilicium déposé dans la tranchée (132) formée sur la face arrière du substrat de type N (110) est de 1E17 à 1E21 cm3.
     
    8. Procédé de fabrication du transistor bipolaire à grille isolée à conduction inverse selon l'une quelconque des revendications 1 à 7, caractérisé en ce que, du substrat de type N (110) à un extérieur, la couche métallique de face arrière (133) comprend de l'aluminium, du titane, du nickel et de l'argent, qui sont stratifiés dans cet ordre.
     
    9. Procédé de fabrication du transistor bipolaire à grille isolée à conduction inverse selon l'une quelconque des revendications 1 à 7, caractérisé en ce que la couche diélectrique (126) est constituée de dioxyde de silicium et de verre au borophosphosilicate.
     
    10. Procédé de fabrication du transistor bipolaire à grille isolée à conduction inverse selon l'une quelconque des revendications 1 à 7, caractérisé en ce que la couche protectrice (127) est constituée de nitrure de silicium.
     




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    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description