(19)
(11)EP 3 022 843 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
06.05.2020 Bulletin 2020/19

(21)Application number: 14742323.0

(22)Date of filing:  16.07.2014
(51)International Patent Classification (IPC): 
H03K 19/0944(2006.01)
(86)International application number:
PCT/GB2014/052175
(87)International publication number:
WO 2015/008067 (22.01.2015 Gazette  2015/03)

(54)

ELECTRONIC CIRCUITS

ELEKTRONISCHE SCHALTUNGEN

CIRCUITS ÉLECTRONIQUES


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 17.07.2013 GB 201312809

(43)Date of publication of application:
25.05.2016 Bulletin 2016/21

(73)Proprietor: PragmatIC Printing Ltd
Sedgefield Durham TS21 3FG (GB)

(72)Inventors:
  • DE OLIVEIRA, Joao
    Longstanton CB24 3GY (GB)
  • WHITE, Scott Darren
    Cambridge CB23 7AW (GB)
  • RAMSDALE, Catherine
    Cambridge CB24 9JL (GB)

(74)Representative: HGF Limited 
Saviour House 9 St. Saviourgate
York YO1 8NQ
York YO1 8NQ (GB)


(56)References cited: : 
EP-A1- 2 221 973
EP-A2- 0 432 472
EP-A2- 0 055 570
US-A- 4 503 341
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description


    [0001] The present invention relates to electronic circuits, and in particular, although not exclusively, to electronic logic circuits, for example for use as building blocks in signal processing circuits and apparatus. Certain embodiments relate to flexible logic circuits.

    BACKGROUND



    [0002] Conventional semiconductor devices and related EDA tools/libraries are mostly based around CMOS logic circuits.

    [0003] CMOS uses complementary n-type and p-type transistors, and displaced the previous NMOS (n-type) technologies in the 1980s due to better power efficiency, higher noise margin, improved fan-out and easier integration. However, in flexible electronics NMOS is currently state-of-the-art and the lack of robust CMOS capability is a critical issue. In flexible electronics significant effort has been put into both NMOS and PMOS but there is a mismatch in achievable performance (e.g. mobilities). Complementary materials require very different deposition and patterning processes (e.g. solution-deposition vs. vacuum-deposition), thus combining the two into a single manufacturable process is very challenging.

    [0004] The main building block for digital logic is the inverter. Three main inverter variants of NMOS logic can be implemented.

    [0005] Figure 1a shows three prior art implementations of NMOS inverters, and fig. 1b shows a prior art CMOS inverter. The CMOS inverter flips between the PMOS and NMOS devices being active, such that they complement each other and minimal leakage at 0V.

    [0006] The three NMOS variants, as illustrated in fig. 1a, all have benefits and drawbacks (footprint, power efficiency, noise margin), and are used today in "Flexible Electronics" due to the absence of a commercially viable manufacturing route to CMOS. However, this limits the ease of design as well as the degree of integration and complexity that can be achieved. Noise margin dictates the number of logic gates which can be cascaded, i.e. the complexity of the overall circuit. This is sensitive to variations in threshold voltage (the voltage at which the transistor turns-on) and channel-length (as channel-length reduces to minimise footprint the noise margin is lower).

    [0007] Figure 2a illustrates that as the variation in threshold voltage (DVT) for PMOS increases the yield of gates (n) drops (DVT -0.15V is a reasonable production benchmark; the same is true for NMOS as PMOS); fig. 2b illustrates that CMOS (C-TFT) is able to yield significantly higher numbers of gates (stages) than PMOS (P-TFT) even with a relatively large variation in threshold voltage (□VT∼0.5V) (see IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 4, APRIL 2006 601, "Influence of Transistor Parameters on the Noise Margin of Organic Digital Circuits", Stijn De Vusser, Jan Genoe, and Paul Heremans, and IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 1, JANUARY 2010 201, "Noise-Margin Analysis for Organic Thin-Film Complementary Technology", Dieter Bode, Cedric Rolin, Sarah Schols, Maarten Debucquoy, Soeren Steudel, Gerwin H. Gelinck, Jan Genoe, and Paul Heremans). Examples of logic circuits using FET devices are given in documents EP0055570 A2 and EP2221973 A1.

    [0008] Figure 3 illustrates another prior art logic gate implemented in CMOS, namely a NAND gate. Two PMOS transistors are connected in parallel between the output terminal and first supply rail (Vdd), each of these transistors receiving a respective one of inputs A and B. Two NMOS devices are connected in series between the output terminal and a second supply rail (ground, or Vss in this example), each also receiving a respective one of inputs A and B.

    BRIEF SUMMARY OF THE DISCLOSURE



    [0009] The invention is defined in independent claim 1. It is an aim of certain embodiments of the invention to solve, mitigate or obviate, at least partly, at least one of the problems and/or disadvantages associated with the prior art. Certain embodiments aim to provide at least one of the advantages described below.

    [0010] Certain embodiments aim to provide electronic building blocks analogous to conventional CMOS building blocks, for incorporation in circuits, for example flexible circuits.

    [0011] According to a first aspect of the present invention there is provided an electronic circuit, for example a logic circuit, comprising:

    an input terminal; an output terminal; a first supply rail; a second supply rail;

    a first field effect transistor, FET, of a first type (e.g. having a first polarity, i.e. having a channel of a first polarity) and having respective gate, source and drain terminals;

    second, third, and fourth FETs each of said first type and each having respective gate, source and drain terminals;

    a first load resistor; and a second load resistor,

    wherein

    the source of the first FET is connected to the first supply rail,

    the drain of the first FET and the source of the second FET are connected to the output terminal,

    the drain of the second FET is connected to the second supply rail,

    the gate of the third FET and the gate of the fourth FET are connected to the input terminal,

    the drain of the third FET is connected to the second supply rail,

    the first load resistor is connected between the first supply rail and the source of the third FET,

    the second load resistor is connected between the drain of the fourth FET and the second supply rail,

    the gate of the first FET is connected to a node between the source of the third FET and the first load resistor such that a voltage at the source of the third FET is applied to the gate of the first FET, and

    the gate of the second FET is connected to a node between the drain of the fourth FET and the second load resistor such that a voltage at the drain of the fourth FET is applied to the gate of the second FET.



    [0012] Circuits in accordance with this first aspect may be arranged as inverters and/or may be incorporated in NOR and NAND circuits, also embodying the present invention.

    [0013] It will be appreciated that the "input terminal" may also be described as a first terminal, a first or input node, or simply an input. The "input terminal" is not necessarily a terminal arranged to enable external connection to the circuit. Instead, the term "input terminal" simply means a part of the defined circuit to which a signal (e.g. voltage) may be input. Thus, in certain embodiments, the nominal input terminal may be connected (e.g. permanently) to some other component or portion of a larger circuit of which the defined circuit forms part. Similarly, the "output terminal" may also be described as a second terminal, a second or output node, or simply an output. The output terminal is a part of the defined circuit at which an output signal is developed, and in certain embodiments may be connected to another component or portion of a larger circuit of which the defined circuit forms part. The electronic circuit may also be described as a circuit module.

    [0014] Further aspects and embodiments are defined by the accompanying claims.

    [0015] It will be appreciated that certain embodiments of the invention can be described as incorporating 'NCMOS' technology, which is a novel quasi-CMOS design/technology made entirely from NMOS devices, invented by the present inventors. Compared to flexible CMOS, this provides major benefits in terms of manufacture because NMOS processing can be directly applied.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0016] Embodiments of the invention are further described hereinafter with reference to the accompanying drawings, in which:

    Figure 1a illustrates three NMOS inverter configurations in accordance with the prior art;

    Fig. 1b illustrates a CMOS inverter in accordance with the prior art;

    Fig. 2a illustrates the effect of variation in threshold voltage on the yield of gates;

    Fig. 2b illustrates the difference between the yield of gates for CMOS and PMOS technologies;

    Fig. 3 illustrates a CMOS NAND gate in accordance with the prior art;

    Fig. 4 illustrates an inverter circuit embodying the invention;

    Fig. 5 illustrates a NAND circuit embodying the invention;

    Fig. 6 illustrates an inverter circuit embodying the invention and comprising four transistors and two resistors;

    Fig. 7 illustrates a HEX inverter embodying the invention and comprising 24 transistors and 12 resistors;

    Fig. 8 illustrates a five-stage ring oscillator embodying the invention;

    Fig. 9 illustrates a NOR circuit embodying the invention and comprising six transistors and three resistors;

    Fig. 10 illustrates another NOR gate embodying the invention and comprising six transistors and two resistors;

    Fig. 11 illustrates another NOR circuit embodying the invention and comprising six transistors and three resistors;

    Fig. 12 illustrates another NOR circuit embodying the invention and comprising six transistors and three resistors;

    Fig. 13 illustrates another NOR circuit embodying the invention and comprising eight transistors and four resistors'

    Fig. 14 illustrates a quad NOR circuit embodying the invention and comprising 24 transistors and 12 resistors;

    Fig. 15 illustrates a dual SR latch circuit embodying the invention;

    Fig. 16 illustrates a NAND circuit embodying the invention and comprising six transistors and three resistors;

    Fig. 17 illustrates another NAND circuit embodying the invention and comprising six transistors and two resistors;

    Fig. 18 illustrates another NAND circuit embodying the invention and comprising six transistors and three resistors;

    Fig. 19 illustrates another NAND circuit embodying the invention and comprising six transistors and three resistors;

    Fig. 20 illustrates a quad NAND circuit embodying the invention and comprising 24 transistors and 12 resistors;

    Fig. 21 illustrates a buffer circuit embodying the invention and comprising four transistors and two resistors;

    Fig. 22 illustrates a HEX buffer circuit embodying the invention and comprising 24 transistors and 12 resistors;

    Fig. 23 illustrates a D-type flip-flop circuit embodying the invention and comprising 17 transistors and 7 resistors; and

    Fig. 24 illustrates a Quad clock divider circuit embodying the invention and comprising 68 transistors and 28 resistors.


    DETAILED DESCRIPTION



    [0017] Figure 4 illustrates an inverter embodying the present invention, and incorporating the NCMOS concept/technology invented by the present inventors.

    [0018] The device comprises four NMOS transistors (Q1, Q2, Q3, and Q4) and two loads R1 and R2, which can also be described as polarising load elements (and can take the form, in certain embodiments, of resistors, N-type enhancement loads or N-type depletion loads). Essentially it is a hybrid between NMOS and CMOS, hence the name NCMOS.

    [0019] In the terminology of claim 1, Q1 is the first FET, Q2 is the second FET, and so on. The first supply rail 3 is Vdd in this example, and the second supply rail 4 is Vss or ground. Input terminal 1 and output terminal 2 are labelled, and the source, drain, and gate terminals of each of the FETs are labelled, as S, D, and G respectively. The connections between the various terminals are as defined in claim 1. In this example, the respective connections between the source and drain terminals of the first and second FETs Q1, Q2 and the rails and output terminal are direct (i.e. not via another component, device, or circuit element), but in alternative embodiments one or more of the connections may not be direct (e.g. see below and the description of the NAND gate of figure 5). Thus, the term "connected" may, in certain embodiments, be interpreted as "coupled", encompassing both direct connection (via no intermediate circuit component) and indirect connection (via one or more intermediate circuit components, including passive devices, such as resistors for example, and/or active devices, such as further FETs for example).

    [0020] Figure 4 is a schematic of the NCMOS inverter of this first embodiment. The top three devices/circuit elements (i.e. first and third FETs Q1, Q3 and first load R1, as circled by the upper broken line in the figure) create a "virtual PMOS transistor", using the top left transistor Q3 and its polarising load R1 as an inverter to the switching top-right NMOS transistor Q1. The bottom three devices (second and fourth FETs Q2, Q4 and second load R2, as circled by the lower broken line) are needed to create a NMOS transistor equivalent in switching timing to the top "virtual PMOS transistor". The bottom left transistor Q4 and its polarising load R2 behave as a follower to the switching bottom right NMOS transistor Q2.

    [0021] The major benefits of the architecture are:
    The ability to use existing commercially viable NMOS transistors and processes.

    [0022] FanOut comparable to CMOS, and better than NMOS (or PMOS).

    [0023] Noise margin comparable to CMOS, and better than NMOS (or PMOS).

    [0024] Use existing design and simulation electronic design automation (EDA) tools and libraries, speeding up the possible complexity design of "Flexible Electronics".

    [0025] Extends to other fundamental building-blocks: NOR, NAND
    Can be implemented on any process technology (oxide, organic, n-type, p-type, ...)
    NCMOS matches well with the applicant's planar device technology which is 1000x smaller than other printed logic. The extra devices required for NCMOS is offset by the incredibly small footprint of the planar devices. This provides the applicant with a compelling unique offering for printed logic.

    [0026] NCMOS brings with it most of the implementation advantages of CMOS (high noise margin and low power consumption) and also enables extensive CMOS modelling libraries to be used once the basic NCMOS design has been modelled, which is a huge benefit over unipolar logic. This will save significant time and cost and accelerates the development of complex logic in flexible electronics. The basic NCMOS building blocks (NOT, NAND, NOR) in certain embodiments are implemented in circuit designs.

    [0027] From a lifetime perspective NCMOS also has advantages over NMOS because the lower power consumption allows a longer lifetime for battery driven products, which is where many applications for flexible logic reside.

    [0028] However, there are trade-offs to be made with NCMOS. For example, a NOR gate will require 9 devices in NCMOS whereas the equivalent CMOS needs only 4 and an NMOS block requires only 3. If the higher number of devices leads to increased footprint then throughput will be reduced and costs will increase. Additionally, in simple circuits, NMOS yield may outweigh the NCMOS yield because complexity is not an issue and the greater number of devices needed for NCMOS will directly impact yield. Circuit speed may also be detrimentally impacted by NCMOS because of the greater number of devices required.

    [0029] Certain embodiments comprise circuits formed in processes producing many thousands of transistor-based circuits on each wafer, and may be integrated into products such as (but not limited to) greetings cards, bottle labels, security ID cards or toys and games, for example. The incorporation of NCMOS into appropriate designs enhances the functionality achievable. In different applications, depending on the various levels of circuit complexity, a balance between the choice of NCMOS or NMOS should be considered; for a given design a hybrid of these technologies may, or may not, be appropriate.

    [0030] Hybrid designs of NMOS and NCMOS may be appropriate in certain embodiments. This can be accommodated in design software and, indeed, combinations of CMOS and NMOS devices are already used in the design of conventional silicon chips. Certain embodiments are timers made with both NCMOS and NMOS logic and/or a hybrid of both.

    [0031] Referring now to Fig. 5, this illustrates a NAND circuit embodying the invention. In the language of claim 1, the first to fourth FETs are devices Q1a, Q2a, Q3a, and Q4a respectively, and the first and second loads are R1a and R2a. The input terminal 1 is a first input terminal A, and the gate comprises the configuration shown in Fig. 5b to provide gate drives to the first and second transistors via terminals 12 and 11 respectively (which are also labelled as A2 and A1 respectively in the figure). The circuit comprises a fifth FET of the same type and connected between the first supply rail 3 and the output terminal 2, in parallel with the first FET Q1A. The circuit further comprises a sixth FET Q2b of the same type and connected in series with the second FET Q2a between the output terminal 2 and the second rail 4. In other words, the source of the sixth FET is connected to the drain of the second FET, and the drain of the sixth FET is connected to ground in this example. Thus, it will be appreciated that in this example the drain of the second FET Q2a is connected to the second rail 4, but not directly. Instead, it is connected to that rail via the source-drain conductive channel of the sixth FET Q2b.

    [0032] In this circuit, the gate drives to the fifth and sixth FETs Q1b, Q2b are provided by the circuit portion shown in Fig. 5c. This circuit portion generally has the same configuration as the circuit portion shown in Fig. 5b. It includes a second input terminal 10, B which provides a gate drive to a seventh FET Q3b and an eighth FET Q4b, each of which have the same type as all the other transistors shown in the figure. The circuit portion of Fig. 5c includes a third load R1b and a fourth load R2b. The connections between these various circuit components are the same as in the circuit of Fig. 5b and will be apparent from the figure. Thus, the circuit portion of Fig. 5c, supplied with the second input B, provides a drive to the gate of the fifth FET Q1b via terminal 102, B2, and a drive to the gate terminal of the sixth FET Q2b via terminal 101, B1.

    [0033] Referring now to Fig. 6, this shows an inverter circuit embodying the invention and having the same general configuration as the circuit shown in Fig. 4. In this example, the input terminal 1 provides an inverter input (labelled A in the figure) and the output terminal 2 provides the inverter output (labelled Y). It will be appreciated that the combination of the third FET Q3 and first load R1 provide, or act as, an inverter or inverter stage, and the combination of the fourth FET Q4 and second load R2 provide a follower stage or module. The inverter is generally indicated by reference numeral 100.

    [0034] Referring now to Fig. 7, this shows a HEX inverter circuit embodying the invention. In this embodiment, the HEX inverter circuit is provided in a dual in-line package (DIP) module, having 14 contacts, labelled 1 to 14 in the figure. In certain embodiments, these contacts may take the form of contact pins or contact pads, for example. The HEX inverter comprises six inverters 100, each inverter being as shown in Fig. 6. Each inverter 100 is connected between a respective pair of the contacts, with the first inverter 100 having its input A connected to contact 1 and its output Y connected to contact 2, etc. Contact 14 is connected to the first supply rail 3, and contact 7 is connected to the second supply rail 4. Although the illustrated embodiment is in the form of a DIP module , alternative embodiments may provide an inverter circuit, such as a HEX inverter circuit as illustrated, on a printed interconnect sheet.

    [0035] Referring now to Fig. 8, this illustrates a five-stage ring oscillator embodying the invention and based on the HEX inverter of Fig. 7. The circuit of Fig. 8 comprises the same arrangement of six inverters 100 connected to respective pairs of contacts, but also provides additional connections between the contacts as illustrated in the figure. Thus, contact 1 is connected to contact 6, contact 6 is connected to contact 9, etc.

    [0036] Referring now to Fig. 9, this shows a NOR circuit, where the first to sixth FETs are labelled Q1 - Q6 respectively, and the first to third loads are labelled R1 - R3 respectively. The follower, inverter, and CMOS stages in the figure together provide a circuit, having an input terminal labelled 1 and an output terminal 2, which provides the output Y of the NOR circuit. The circuit has a first NOR input A, and a second NOR input B. The first supply rail is labelled 3, and the second supply rail (which is ground in this example) is labelled 4. The fifth and sixth FETs together with third load R3 effectively provide an NMOS NOR stage, delivering a NOR output to input terminal 1 according to the input provided to A and B.

    [0037] Referring now to Fig. 10, this shows another NOR circuit embodying the invention and having the structure defined by claim 13 as dependent upon claim 1. In this embodiment, rather than having just a single third FET, the circuit comprises a pair of "third" FETs, labelled Q3A and Q3B in the figure. In the language of claim 13, Q3A and Q3B are "a third pair of FETs". The first FET of that pair (ie Q3A) has its gate connected to the first NOR input A, and the second of the pair (Q3B) has its gate connected to the second NOR input B. Similarly, rather than a single fourth FET (as was the case in the inverter circuit of Fig. 4 or Fig. 6) this circuit comprises a pair of "fourth" FETs, referred to as "a fourth pair of FETs" in the language of claim 13. The connections between the various components in Fig. 10 are as defined by claim 13.

    [0038] Referring now to Fig. 11, this shows another NOR circuit embodying the invention. This circuit incorporates an inverter 100 as illustrated in Fig. 6, with the output terminal 2 providing the output Y of the NOR circuit. The circuit arrangement is as defined by claim 14. Thus, the input terminal 1 is driven by the output of an OR stage which comprises fifth and sixth FETs and a third load R3. The gates of the fifth and sixth FETs are connected respectively to the first and second NOR inputs A, B, the sources of the fifth and sixth transistors are connected to the high supply rail three, and the drains of the fifth and sixth FETs are connected via resistor R3 to ground. Thus, the channels of the fifth and sixth transistors are arranged in parallel between the upper supply rail and load resistor R3.

    [0039] Referring now to Fig. 12, this shows another NOR circuit embodying the invention, and again incorporating an inverter circuit 100 as illustrated in Fig. 6, The overall arrangement of the circuit is as defined by claim 15. In this arrangement, the drains of the fifth and sixth FETs are connected together and to the input terminal 1 of the inverter circuit 100 that input terminal 1 is connected via load R3 to ground. The first NOR input A is connected to the gate and source of the fifth FET, and the second NOR input B is connected to the gate and source of the sixth transistor.

    [0040] Referring now to Fig. 13, this shows another NOR circuit embodying the invention. The arrangement of the circuit elements is one with the first FET being Q1A, the first pair of FETs being Q1A and Q1B, the second FET being Q2A, the second pair of FETs being Q2A and Q2B , the third FET being Q3A, the third pair of FETs being Q3A and Q3B, the fourth transistor being Q4A, the fourth pair of FETs being Q4A and Q4B, the first load being R1A, the first pair of loads being R1A and R1B, the second load being R2A, and the second pair of load being R2A and R2B. As can be seen, the gate of Q1A is connected to the source of Q3A, the gate of Q1B is connected to the source of Q3B, the gate of Q2A is connected to the drain of Q4A, and the gate of Q2B is connected to the drain of Q4B. Q3A and R1A together provide an inverter stage, as do the combination of Q3B and R1B. The combination of Q4A and R2A provides a follower module, as does the combination of Q4B and R2B. The first and second pairs of FETs provide a NOR stage.

    [0041] Referring now to Fig. 14, this shows a quad NOR circuit embodying the invention, and incorporating four NOR circuits in accordance with any other aspect or embodiment of the invention. The connections between the inputs and outputs of the NOR circuits to the 14 contacts are as shown in the figure. Thus, the first NOR circuit 101 has its output Y connected to contact 1, its first input A connected to contact 2, and its second input B connected to contact 3, etc.

    [0042] Referring now to Fig. 15, this shows a dual SR latch circuit embodying the invention and based on the quad NOR circuit of Fig. 14. Fig. 15 shows the additional connections between the contacts to provide the dual SR latch function. Thus, contact 1 is connected to contact 5, contact 3 is connected to contact 4, etc., as shown in the figure.

    [0043] Referring now to Fig. 16, this shows a NAND circuit 102 embodying the invention. The arrangement of the various circuit components is one where the first to sixth FETs are labelled Q1 - Q6 respectively, and the first to third loads are labelled R1 - R3 respectively. The fifth and sixth transistors have their channels connected in series, between third load (resistor R3) and ground. The fifth and sixth FETs and resistor R3 provide a NAND stage, which delivers a NAND input to input terminal 1 according to the signals provided to NAND inputs A and B.

    [0044] Referring now to Fig. 17, this shows another NAND circuit embodying the invention. This NAND circuit 102 comprises a pair of third FETs (Q3A and Q3B), with their channels arranged in series between first load R1 and ground. The circuit also comprises a pair of fourth FETs Q4A and Q4B, arranged with their channels connected in series between the upper supply rail and second load R2.

    [0045] Referring now to Fig. 18, this shows another NAND circuit embodying the invention, and comprising an inverter 100 as illustrated in Fig. 6. This circuit includes an AND stage comprising fifth and sixth FETs Q5 and Q6, connected in series with third load resistor R3 between the supply rails 3, 4. The voltage at the drain of the sixth FET is supplied to the input terminal 1 of the inverter.

    [0046] Referring now to Fig. 19, this shows another NAND circuit embodying the invention. Here, the fifth and sixth transistors have their source terminals respectively connected to the first and second inputs A, B, the gate of each of the fifth and sixth FETs is tied to its respective drain, and the drain terminals are connected to the input terminal 1 of the inverter stage 100. Load resistor R3 is connected between supply rail 3 and the input terminal 1.

    [0047] Referring now to Fig. 20, this illustrates a quad NAND circuit embodying the invention, and comprising four NAND circuits in accordance with any other aspect or embodiment of the invention. The connections of the respective NAND circuit inputs and outputs to the 14 contacts are as shown in the figure.

    [0048] Referring now to Fig. 21, this shows a buffer.

    [0049] Fig. 22 illustrates a HEX buffer circuit and comprising six buffer circuits 103 as shown in Fig. 21. Again, the connections of the buffer inputs and outputs to the contacts are as illustrated in the figure.

    [0050] Referring now to Fig. 23, this illustrates a D-type flip-flop circuit embodying the invention having a first supply rail 3, a second supply rail 4, a clock input (CLK), a "D" input, and providing two outputs Q and Q prime. This particular flip-flop circuit comprises one inverter 100 embodying the invention, and six NAND circuits embodying the invention, connected as shown in the figure. The flip-flop circuit also comprises two CMOS output stages, each of which comprises a respective pair of FETs, having their channels connected in series between the two supply rails, and a node between the respective pair of FETs being connected to the respective output terminal (Q or Q prime).

    [0051] Referring now to Fig. 24, this shows a quad clock divider circuit embodying the invention, and comprising four flip-flop circuits as shown in Fig. 23. The connections of the respective flip-flop input and outputs to the contact pins are as shown in the figure.

    [0052] It will be appreciated that, whilst the above-described embodiments have incorporated NMOS devices, in further alternative embodiments, the FETs employed may be PMOS devices. Thus, in certain embodiments, all of the FETs incorporated in the circuit may be NMOS devices, and in certain alternative embodiments all of the FETs incorporated in the circuit may be PMOS devices. In other words, in certain embodiments the first type is NMOS, and in certain alternative embodiments the first type is PMOS.

    [0053] Throughout the description and claims of this specification, the words "comprise" and "contain" and variations of them mean "including but not limited to", and they are not intended to (and do not) exclude other moieties, additives, components, integers or steps. Throughout the description and claims of this specification, the singular encompasses the plural unless the context otherwise requires. In particular, where the indefinite article is used, the specification is to be understood as contemplating plurality as well as singularity, unless the context requires otherwise.

    [0054] Features, integers, characteristics, compounds, chemical moieties or groups described in conjunction with a particular aspect, embodiment or example of the invention are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive. The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

    [0055] The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application.


    Claims

    1. An electronic circuit comprising:

    an input terminal (1);

    an output terminal (2);

    a first supply rail (3);

    a second supply rail (4);

    a first field effect transistor (Q1), FET, of a first type and having respective gate, source and drain terminals;

    a second FET (Q2) of said first type and having respective gate, source and drain terminals;

    a third FET (Q3) of said first type and having respective gate, source and drain terminals;

    a fourth FET (Q4) of said first type and having respective gate, source and drain terminals;

    a first load resistor (R1); and

    a second load resistor (R2),

    wherein

    the source of the first FET (Q1) is connected to the first supply rail,

    the drain of the first FET (Q1) and the source of the second FET (Q2) are connected to the output terminal,

    the drain of the second FET (Q2) is connected to the second supply rail,

    the gate of the third FET (Q3) and the gate of the fourth FET (Q4) are connected to the input terminal,

    the drain of the third FET (Q3) is connected to the second supply rail,

    the first load resistor (R1) is connected between the first supply rail and the source of the third FET (Q3),

    the second load resistor (R2) is connected between the drain of the fourth FET (Q4) and the second supply rail,

    the gate of the first FET (Q1) is connected to a node between the source of the third FET (Q3) and the first load resistor (R1) such that a voltage at the source of the third FET (Q3) is applied to the gate of the first FET (Q1), and

    the gate of the second FET (Q2) is connected to a node between the drain of the fourth FET (Q4) and the second load resistor (R2) such that a voltage at the drain of the fourth FET (Q4) is applied to the gate of the second FET (Q2).


     
    2. A circuit in accordance with claim 1, wherein said first type is one of enhancement mode and depletion mode.
     
    3. A circuit in accordance with any preceding claim, wherein said first type is NMOS.
     
    4. A circuit in accordance with any preceding claim, wherein the circuit is a logic circuit.
     
    5. A circuit in accordance with claim 4, wherein the logic circuit is one of: an inverter; a NOT gate; a NAND gate; and a NOR gate.
     
    6. A circuit in accordance with any preceding claim, wherein the circuit is an inverter, and the drain of the second FET (Q2) is connected directly to the second supply rail.
     
    7. A circuit in accordance with any one of claims 1 to 5, wherein the circuit is a NAND circuit and the drain of the second FET (Q2) is connected to the second rail via the channel of a further FET (Q2b) of said first type.
     
    8. A circuit in accordance with claim 7, wherein the NAND circuit further comprises: a second input terminal (B); fifth (Q1b), sixth (Q2b), seventh (Q3b), and eighth (Q4b) FETs each of said first type and each having respective gate, source and drain terminals; and third (R1b) and fourth (R2b) load resistors.
     
    9. An inverter circuit comprising a circuit in accordance with any one of claims 1 to 6, wherein said input terminal is arranged as an input of the inverter circuit and said output terminal is arranged as an output of the inverter circuit.
     
    10. A HEX inverter circuit comprising six inverter circuits, each in accordance with claim 9.
     
    11. A circuit module comprising fourteen contacts and a HEX inverter circuit in accordance with claim 10, wherein each inverter circuit is connected between a respective pair of said contacts, one of said contacts is connected to the first supply rail, and another of said contacts is connected to the second supply rail.
     
    12. A ring oscillator circuit comprising six inverter circuits, each in accordance with claim 9.
     
    13. A NOR circuit comprising a circuit in accordance with any one of claims 1 to 6, the NOR circuit further comprising a first NOR input, A, and a second NOR input, B, wherein said output terminal is arranged as an output of the NOR circuit, said input terminal is arranged as said first NOR input, A, said third FET (Q3) being one of a third pair of FETs, the second FET (Q2) of said third pair of FETs having a gate connected to the second NOR input, B, a source connected to the source of said third FET (Q3), and a drain connected to said second supply rail, the fourth FET (Q4) being one of a fourth pair of FETs, the second FET (Q2) of said fourth pair of FETs having a gate connected to B, a source connected to the first supply rail, and a drain connected to the gate of said second FET (Q2).
     
    14. A NOR circuit comprising a circuit in accordance with any one of claims 1 to 6, the NOR circuit further comprising a first NOR input, A, a second NOR input, B, fifth and sixth FETs of said first type, and a third load resistor, wherein said output terminal is arranged as an output of the NOR circuit, A is connected to a gate of the fifth FET, B is connected to a gate of the sixth FET, the sources of the fifth and sixth FETs are each connected to the first supply rail, the drains of the fifth and sixth FETs are each connected to said input terminal, and the third load resistor (R3) is connected between said input terminal and the second supply rail.
     
    15. A NOR circuit comprising a circuit in accordance with any one of claims 1 to 6, the NOR circuit further comprising a first NOR input, A, a second NOR input, B, fifth and sixth FETs of said first type, and a third load resistor, wherein said output terminal is arranged as an output of the NOR circuit, A is connected to a gate and a source of the fifth FET, B is connected to a gate and a source of the sixth FET, the drains of the fifth and sixth FETs are each connected to said input terminal, and the third load resistor (R3) is connected between said input terminal and the second supply rail.
     


    Ansprüche

    1. Elektronische Schaltung, aufweisend:

    einen Eingangsanschluss (1);

    einen Ausgangsanschluss (2);

    eine erste Versorgungsschiene (3);

    eine zweite Versorgungsschiene (4);

    einen ersten Feldeffekttransistor (Q1), FET, eines ersten Typs und mit jeweiligen Gate-, Source- und Drain-Anschlüssen;

    einen zweiten FET (Q2) des ersten Typs und mit jeweiligen Gate-, Source- und Drain-Anschlüssen;

    einen dritten FET (Q3) des ersten Typs und mit jeweiligen Gate-, Source- und Drain-Anschlüssen;

    einen vierten FET (Q4) des ersten Typs und mit jeweiligen Gate-, Source- und Drain-Anschlüssen;

    einen ersten Lastwiderstand (R1); und

    einen zweiten Lastwiderstand (R2), wobei der Source-Anschluss des ersten FET (Q1) mit der ersten Versorgungsschiene verbunden ist, der Drain-Anschluss des ersten FET (Q1) und der Source-Anschluss des zweiten FET (Q2) mit dem Ausgangsanschluss verbunden sind, der Drain-Anschluss des zweiten FET (Q2) mit der zweiten Versorgungsschiene verbunden ist, der Gate-Anschluss des dritten FET (Q3) und der Gate-Anschluss des vierten FET (Q4) mit dem Eingangsanschluss verbunden sind, der Drain-Anschluss des dritten FET (Q3) mit der zweiten Versorgungsschiene verbunden ist, der erste Lastwiderstand (R1) zwischen der ersten Versorgungsschiene und dem Source-Anschluss des dritten FET (Q3) verbunden ist, der zweite Lastwiderstand (R2) zwischen dem Drain-Anschluss des vierten FET (Q4) und der zweiten Versorgungsschiene verbunden ist, der Gate-Anschluss des ersten FET (Q1) mit einem Knoten zwischen dem Source-Anschluss des dritten FET (Q3) und dem ersten Lastwiderstand (R1) verbunden, sodass eine Spannung an dem Source-Anschluss des dritten FET (Q3) an den Gate-Anschluss des ersten FET (Q1) angelegt wird, und der Gate-Anschluss des zweiten FET (Q2) mit einem Knoten zwischen dem Drain-Anschluss des vierten FET (Q4) und dem zweiten Lastwiderstand (R2) verbunden ist, sodass eine Spannung an dem Drain-Anschluss des vierten FET (Q4) an den Gate-Anschluss des zweiten FET (Q2) angelegt wird.


     
    2. Schaltung nach Anspruch 1, wobei der erste Typ von einem Anreicherungsmodus und Verarmungsmodus ist.
     
    3. Schaltung nach einem der vorhergehenden Ansprüche, wobei der erste Typ NMOS ist.
     
    4. Schaltung nach einem der vorhergehenden Ansprüche, wobei die Schaltung eine logische Schaltung ist.
     
    5. Schaltung nach Anspruch 4, wobei die logische Schaltung eine ist von:

    einem Inverter;

    einem NICHT-Gatter;

    einem NICHT-UND-Gatter; und

    einem NICHT-ODER-Gatter.


     
    6. Schaltung nach einem der vorhergehenden Ansprüche, wobei die Schaltung ein Inverter ist, und der Drain-Anschluss des zweiten FET (Q2) direkt mit der zweiten Versorgungsschiene verbunden ist.
     
    7. Schaltung nach einem der Ansprüche 1 bis 5, wobei die Schaltung eine NICHT-UND-Schaltung ist, und der Drain-Anschluss des zweiten FET (Q2) mit der zweiten Versorgungsschiene über den Kanal eines weiteren FET (Q2b) des ersten Typs verbunden ist.
     
    8. Schaltung nach Anspruch 7, wobei die NICHT-UND-Schaltung ferner aufweist:

    einen zweiten Eingangsanschluss (B);

    fünfte (Q1b), sechste (Q2b), siebte (Q3b) und achte (Q4b) FETs jeweils des ersten Typs und die jeweils Gate-, Source- und Drain-Anschlüsse haben; und

    dritte (R1b) und vierte (R2b) Lastwiderstände.


     
    9. Inverterschaltung, aufweisend eine Schaltung nach einem der Ansprüche 1 bis 6, wobei der Eingangsanschluss als ein Eingang der Inverterschaltung angeordnet wird, und der Ausgangsanschluss als ein Ausgang der Inverterschaltung angeordnet ist.
     
    10. HEX-Inverterschaltung, aufweisend sechs Inverterschaltungen jeweils nach Anspruch 9.
     
    11. Schaltungsmodul, aufweisend vierzehn Kontakte und eine HEX-Inverterschaltung nach Anspruch 10, wobei jede Inverterschaltung zwischen einem jeweiligen Paar der Kontakte verbunden ist, wobei einer der Kontakte mit der ersten Versorgungsschiene verbunden ist und ein anderer der Kontakte mit der zweiten Versorgungsschiene verbunden ist.
     
    12. Ringsoszillatorschaltung aufweisend sechs Inverterschaltungen jeweils nach Anspruch 9.
     
    13. NICHT-ODER-Schaltung, aufweisend eine Schaltung nach einem der Ansprüche 1 bis 6, wobei die NICHT-ODER-Schaltung ferner einen ersten NICHT-ODER-Eingang A und einen zweiten NICHT-ODER-Eingang B aufweist, wobei der Ausgangsanschluss als ein Ausgang der NICHT-ODER-Schaltung angeordnet ist, der Eingangsanschluss als der erste NICHT-ODER-Eingang A angeordnet ist, wobei der dritte FET (Q3) einer von einem dritten Paar von FETs ist, der zweite FET (Q2) des dritten Paars von FETs einen Gate-Anschluss hat, der mit dem zweiten NICHT-ODER-Eingang B verbunden ist, ein Source-Anschluss mit dem Source-Anschluss des dritten FET (Q3) verbunden ist, und ein Drain-Anschluss mit der zweiten Versorgungsschiene verbunden ist, wobei der vierte FET (Q4) einer von einem vierten Paar von FETs ist, der zweite FET (Q2) des vierten Paars von FETs einen Gate-Anschluss, der mit B verbunden ist, einen Source-Anschluss, der mit der ersten Versorgungsschiene verbunden ist, und einen Drain-Anschluss hat, der mit dem Gate-Anschluss des zweiten FET (Q2) verbunden ist.
     
    14. NICHT-ODER-Schaltung, aufweisend eine Schaltung nach einem der Ansprüche 1 bis 6, wobei die NICHT-ODER-Schaltung ferner einen ersten NICHT-ODER-Eingang A, einen zweiten NICHT-ODER-Eingang B, fünfte und sechste FETs des ersten Typs und einen dritten Lastwiderstand aufweist, wobei der Ausgangsanschluss als ein Ausgang der NICHT-ODER-Schaltung angeordnet ist, A mit einem Gate-Anschluss des fünften FET verbunden ist, B mit einem Gate-Anschluss des sechsten FET verbunden ist, die Source-Anschlüsse der fünften und sechsten FETs jeweils mit der ersten Versorgungsschiene verbunden sind, die Drain-Anschlüsse der fünften und sechsten FETs jeweils mit dem Eingangsanschluss verbunden sind, und der dritte Lastwiderstand (R3) zwischen dem Eingangsanschluss und der zweiten Versorgungsschiene verbunden ist.
     
    15. NICHT-ODER-Schaltung, aufweisend eine Schaltung nach einem der Ansprüche 1 bis 6, wobei die NICHT-ODER-Schaltung ferner einen ersten NICHT-ODER-Eingang A, einen zweiten NICHT-ODER-Eingang B, fünfte und sechste FETs des ersten Typs und einen dritten Lastwiderstand aufweist, wobei der Ausgangsanschluss als ein Ausgang der NICHT-ODER-Schaltung angeordnet ist, A mit einem Gate-Anschluss und einem Source-Anschluss des fünften FET verbunden ist, B mit einem Gate-Anschluss und einem Source-Anschluss des sechsten FET verbunden ist, die Drain-Anschlüsse der fünften und sechsten FETs jeweils mit dem Eingangsanschluss verbunden sind, und der dritte Lastwiderstand (R3) zwischen dem Eingangsanschluss und der zweiten Versorgungsschiene verbunden ist.
     


    Revendications

    1. Circuit électronique comprenant :

    une borne d'entrée (1) ;

    une borne de sortie (2) ;

    un premier rail d'alimentation (3) ;

    un deuxième rail d'alimentation (4) ;

    un premier transistor à effet de champ (Q1), FET, d'un premier type, et possédant des bornes de grille, de source et de drain respectives ;

    un deuxième FET (Q2) dudit premier type, et possédant des bornes de grille, de source et de drain respectives ;

    un troisième FET (Q3) dudit premier type, et possédant des bornes de grille, de source et de drain respectives ;

    un quatrième FET (Q4) dudit premier type, et possédant des bornes de grille, de source et de drain respectives ;

    une première résistance de charge (R1) ; et

    une deuxième résistance de charge (R2), la source du premier FET (Q1) étant connectée au premier rail d'alimentation, le drain du premier FET (Q1) et la source du deuxième FET (Q2) étant connectés à la borne de sortie, le drain du deuxième FET (Q2) étant connecté au deuxième rail d'alimentation, la grille du troisième FET (Q3) et la grille du quatrième FET (Q4) étant connectées à la borne d'entrée, le drain du troisième FET (Q3) étant connecté au deuxième rail d'alimentation, la première résistance de charge (R1) étant connectée entre le premier rail d'alimentation et la source du troisième FET (Q3), la deuxième résistance de charge (R2) étant connectée entre le drain du quatrième FET (Q4) et le deuxième rail d'alimentation, la grille du premier FET (Q1) étant connectée à un nœud entre la source du troisième FET (Q3) et la première résistance de charge (R1) de sorte qu'une tension à la source du troisième FET (Q3) soit appliquée à la grille de la première FET (Q1), et la grille du deuxième FET (Q2) étant connectée à un nœud entre le drain du quatrième FET (Q4) et la deuxième résistance de charge (R2) de sorte qu'une tension au drain du quatrième FET (Q4) soit appliquée à la grille du deuxième FET (Q2).


     
    2. Circuit selon la revendication 1, ledit premier type étant un d'un mode de renforcement et un mode d'épuisement.
     
    3. Circuit selon une quelconque des revendications précédentes, ledit premier type étant un MOS à canal n.
     
    4. Circuit selon une quelconque des revendications précédentes, le circuit étant un circuit logique.
     
    5. Circuit selon la revendication 4, le circuit logique étant un
    d'un onduleur ;
    d'une grille NON ;
    d'une grille NON-ET ; et
    d'une grille NON-OU.
     
    6. Circuit selon une quelconque des revendications précédentes, le circuit étant un onduleur, et le drain du deuxième FET (Q2) étant connecté directement au deuxième rail d'alimentation.
     
    7. Circuit selon une quelconque des revendications 1 à 5, le circuit étant un circuit NON-ET, et le drain du deuxième FET (Q2) étant connecté directement au deuxième rail par le canal d'un autre FET (Q2b) dudit premier type.
     
    8. Circuit selon la revendication 7, le circuit NON-ET comprenant en outre :

    une deuxième borne d'entrée (B) ;

    des cinquième (Q1b), sixième (Q2b), septième (Q3b), et huitième (Q4b) FET, chacun dudit premier type, et possédant chacun des bornes de grille, de source et de drain ; et

    des troisième (R1b) et quatrième (R2b) résistances de charge.


     
    9. Circuit d'onduleur comprenant un circuit selon une quelconque des revendications 1 à 6, ladite borne d'entrée étant agencée comme une entrée du circuit d'onduleur, et ladite borne de sortie étant agencée comme une sortie du circuit d'onduleur.
     
    10. Circuit d'onduleur HEX comprenant six circuits d'onduleur, chacun selon la revendication 9.
     
    11. Module de circuit comprenant quatorze contacts et un circuit d'onduleur selon la revendication 10, chaque circuit d'onduleur étant connecté entre une paire respective desdits contacts, un desdits contacts étant connecté au premier rail d'alimentation, et un autre desdits contacts étant connecté au deuxième rail d'alimentation.
     
    12. Circuit d'oscillateur annulaire comprenant six circuits d'onduleur, chacun selon la revendication 9.
     
    13. Circuit NON-OU comprenant un circuit selon une quelconque des revendications 1 à 6, le circuit NON-OU comprenant en outre une première entrée NON-OU, A, et une deuxième entrée NON-OU, B, ladite borne de sortie étant agencée comme une sortie du circuit NON-OU, ladite borne d'entrée étant agencée comme ladite première entrée NON-OU, A, ledit troisième FET (Q3) étant un d'une troisième paire de FET, le deuxième FET (Q2) de ladite troisième paire de FET possédant une grille connectée à la deuxième entrée NON-OU, B, une source connectée à la source dudit troisième FET (Q3), et un drain connecté audit deuxième rail d'alimentation, le quatrième FET (Q4) étant un d'une quatrième paire de FET, le deuxième FET (Q2) de ladite quatrième paire de FET possédant une grille connectée à B, une source connectée au premier rail d'alimentation, et un drain connecté à la grille dudit deuxième FET (Q2).
     
    14. Circuit NON-OU comprenant un circuit selon une quelconque des revendications 1 à 6, le circuit NON-OU comprenant en outre une première entrée NON-OU, A, une deuxième entrée NON-OU, B, des cinquième et sixième FET dudit premier type, et une troisième résistance de charge, ladite borne de sortie étant agencée comme une sortie du circuit NON-OU, A étant connectée à une grille du cinquième FET, B étant connectée à une grille du sixième FET, les sources des cinquième et sixième FET étant connectées chacune au premier rail d'alimentation, les drains des cinquième et sixième FET étant chacun connectés à ladite borne d'entrée, et la troisième résistance de charge (R3) étant connectée entre ladite borne d'entrée et ledit deuxième rail d'alimentation.
     
    15. Circuit NON-OU comprenant un circuit selon une quelconque des revendications 1 à 6, le circuit NON-OU comprenant en outre une première entrée NON-OU, A, une deuxième entrée NON-OU, B, des cinquième et sixième FET dudit premier type, et une troisième résistance de charge, ladite borne de sortie étant agencée comme une sortie du circuit NON-OU, A étant connectée à une grille et une source du cinquième FET, B étant connectée à une grille et une source du sixième FET, les drains des cinquième et sixième FET étant connectés chacun à ladite borne d'entrée, et la troisième résistance de charge (R3) étant connectée entre ladite borne d'entrée et le deuxième rail d'alimentation.
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description




    Non-patent literature cited in the description