(19)
(11)EP 3 028 306 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
29.04.2020 Bulletin 2020/18

(21)Application number: 14748301.0

(22)Date of filing:  22.07.2014
(51)International Patent Classification (IPC): 
H01L 27/146(2006.01)
(86)International application number:
PCT/JP2014/003838
(87)International publication number:
WO 2015/015753 (05.02.2015 Gazette  2015/05)

(54)

BACK SURFACE RADIATION TYPE IMAGE SENSOR, IMAGING DEVICE, AND ELECTRONIC APPARATUS

BILDSENSOR MIT RÜCKSEITENBELEUCHTUNG, BILDGEBUNGSVORRICHTUNG UND ELEKTRONISCHE VORRICHTUNG

CAPTEUR D'IMAGE DE TYPE RAYONNEMENT PAR LA SURFACE ARRIÈRE, DISPOSITIF D'IMAGERIE ET APPAREIL ÉLECTRONIQUE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 29.07.2013 JP 2013156903

(43)Date of publication of application:
08.06.2016 Bulletin 2016/23

(73)Proprietor: Sony Corporation
Tokyo 108-0075 (JP)

(72)Inventor:
  • HAGITA, Tadahiro
    Kikuchi-gun Kumamoto 869-1102 (JP)

(74)Representative: MFG Patentanwälte Meyer-Wildhagen Meggle-Freund Gerhard PartG mbB 
Amalienstraße 62
80799 München
80799 München (DE)


(56)References cited: : 
WO-A1-2013/031707
US-A1- 2010 148 290
US-A1- 2012 273 683
JP-A- 2006 261 372
US-A1- 2011 140 225
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    Technical Field



    [0001] The present technology relates to a back surface radiation type image sensor, an imaging device, and an electronic apparatus and particularly, to a back surface radiation type image sensor, an imaging device, and an electronic apparatus that can realize a high image quality while equalizing a wiring density of a wiring layer.

    Background Art



    [0002] A general image sensor is called a surface radiation type image sensor and has a configuration in which, after an imaging element (photodiode) is formed on a substrate, a wiring layer is stacked, and a color filter and an on-chip lens are formed thereon. A general image sensor can be formed in this manner because the wiring layer may be formed after the imaging element is manufactured.

    [0003] In a wiring layer formed on an upper layer of the imaging element, a hole is formed to enable light to be transmitted in a pixel unit so as not to disturb reception of the light in the pixel unit. For this reason, in the surface radiation type image sensor, the light is partially reflected or shielded by the wiring layer around the hole, the light may not be appropriately received, and a subject may not be imaged at an original brightness.

    [0004] Therefore, a so-called back surface radiation type image sensor (or a back illuminated sensor) has been suggested; the back surface radiation type image sensor may have a structure in which, after the imaging element is manufactured, the wiring layer is stacked thereon, the substrate is reversed, the substrate of the back surface side is polished to a predetermined thickness, and light may be received from the back surface side. In the back surface radiation type image sensor, because the color filter and the on-chip lens are formed directly on the imaging element, the subject can be imaged at the original brightness without disturbing incidence of the light on the imaging element similar to the wiring layer in the surface radiation type image sensor.

    [0005] Recently, imaging devices using the back surface radiation type image sensor have been utilized in a variety of applications; accordingly, various application technologies of the back surface radiation type image sensor have been developed (refer to Patent Literature 1).

    [0006] US 2011/0140225 A1 discloses that in a first interlevel insulating film, a first region which is made of the first interlevel insulating film and in which first wiring films are not provided is formed to be located above a first light receiving part of the plurality of light receiving parts, and a second region which is made of the first interlevel insulating film and in which the first wiring films are not provided is formed to be located above a second light receiving part of the plurality of light receiving parts which is adjacent to the first light receiving part. A space between ones of the first wiring films with the first region interposed therebetween is larger than a space between ones of the first wiring films with the second region interposed therebetween.

    [0007] WO 2013/031707 discloses an image sensor that includes a first pixel having a first color filter, a first reflection region which reflects light from the first color filter, and a first photoelectric conversion portion arranged in a semiconductor layer and located between the first color filter and the first reflection region, and a second pixel including a second color filter, a second reflection region which reflects light from the second color filter, and a second photoelectric conversion portion arranged in the semiconductor layer and located between the second color filter and the second reflection region. Wavelength corresponding to a maximum transmittance of the first color filter is shorter than wavelength corresponding to a maximum transmittance of the second color filter. An area of the first reflection region is smaller than area of the second reflection region.

    Citation List


    Patent Literature



    [0008] PTL 1: JP 2013-120813 A

    Summary of Invention


    Technical Problem



    [0009] As described above, the back surface radiation type image sensor utilizes a structure in which the on-chip lens, the color filter, the imaging element, and the wiring layer are sequentially formed as viewed from an incidence direction of light and a support substrate is affixed to the wiring layer side becoming a back surface. For this reason, the back surface adhered to the support substrate is flattened by chemical mechanical polishing (CMP).

    [0010] However, the back surface radiation type image sensor is extraordinarily thin. For this reason, if the wiring density of the uppermost layer of the wiring layer is not equalized, it is difficult to flatten the wiring layer even though the wiring layer is polished by the CMP. In particular, because originally necessary wiring lines are small in the uppermost layer in the wiring layer of a pixel region, the wiring density becomes small and the wiring density may not be equalized in only the originally necessary wiring lines. Therefore, in the uppermost layer of the wiring layer, wiring lines called so-called dummy wiring lines that are not electrically connected are provided in the pixel region. Thereby, the wiring density is equalized.

    [0011] However, if the wiring density is defined by only a design, a portion of light, particularly, light having a longer wavelength transmits through an imaging element layer and is reflected by the dummy wiring lines; accordingly, this reflected light is received as reflection light by the imaging element layer again. As a result, for pixels in which the dummy wiring lines are arranged and which light of a color of a wavelength longer than a predetermined wavelength is transmitted, the imaging element receives each the incidence light and the reflection light of the wiring lines. For this reason, a signal having brightness more than the original brightness may be generated, the brightness may not be equalized, and stripe irregularities may occur along the dummy wiring lines.

    [0012] The present technology has been made in view of the above-described circumstances and realizes a back surface radiation type image sensor that can decrease an influence of light transmitting through an imaging element layer and reflected by dummy wiring lines while equally maintaining wiring densities of a pixel region and the other region in an uppermost layer of a wiring layer.

    Solution to Problem



    [0013] A solid-state back illuminated imaging sensor, also called back surface radiation type image sensor in the following, according to an embodiment of the present invention is set out in claim 1; cordingly in the back surface radiation type image sensor, dummy wiring lines adjust a wiring density in an uppermost layer of a pixel region.

    [0014] The dummy wiring lines are arranged in a pixel region in which light of a color of a wavelength shorter than the predetermined wavelength is received.

    [0015] The dummy wiring lines are arranged in a pixel region in which blue light is received.

    [0016] The dummy wiring lines are arranged in a pixel region in which green light is received.

    [0017] The back surface radiation type image sensor includes a pixel region in which blue light, green light, and red light are received.

    [0018] The back surface radiation type image sensor further includes a pixel region in which at least one of white light and infrared light is received.

    [0019] The predetermined wavelength is any wavelength of 400 to 600 nm.

    [0020] The dummy wiring lines are arranged in a pixel region in which light of a color with any wavelength of 400 to 600 nm as a peak and light of a color of a wavelength shorter than the wavelength of the color are received.

    [0021] The predetermined wavelength is any wavelength of 530 to 550 nm.

    [0022] The dummy wiring lines are arranged in a pixel region in which light of a color with any wavelength of 530 to 550 nm as a peak and light of a color of a wavelength shorter than the wavelength of the color are received.

    [0023] The dummy wiring lines have a width smaller than the pixel width.

    [0024] An electronic apparatus according to an embodiment of the present invention is disclosed in claim 7.

    [0025] In these embodiments in the back surface radiation type image sensor that has the dummy wiring lines adjusting the wiring density in the uppermost layer of the pixel region, the dummy wiring lines are arranged in a pixel region in which light of a wavelength shorter than the predetermined wavelength is received.

    [0026] In yet, another embodiment, a method of manufacturing a solid-state back illuminated imaging sensor according to claim 8 is provided.

    Advantageous Effects of Invention



    [0027] According to the first to third aspects of the present technology, particularly, an influence by reflection of wiring lines of a wiring layer is decreased while a wiring density in an uppermost layer of the wiring layer is equalized, so that a high image quality can be realized.

    Brief Description of Drawings



    [0028] 

    [fig.1]Fig. 1 is a diagram illustrating a lateral cross-section and a manufacturing process of a back surface radiation type image sensor to which the present technology is applied.

    [fig.2]Fig. 2 is a diagram illustrating an arrangement example of wiring lines and dummy wiring lines in an uppermost layer of a wiring layer.

    [fig.3]Fig. 3 is a diagram illustrating an influence of light having a long wavelength transmitting an imaging element layer and reflected by wiring lines.

    [fig.4]Fig. 4 is a diagram illustrating an influence of light having a long wavelength transmitting an imaging element layer and reflected by wiring lines.

    [fig.5]Fig. 5 is a diagram illustrating a relation of a wavelength and a transmission depth of light transmitting an imaging element layer.

    [fig.6]Fig. 6 is a diagram illustrating an arrangement example of dummy wiring lines in a first embodiment.

    [fig.7]Fig. 7 is a diagram illustrating an arrangement example of dummy wiring lines in a second embodiment.

    [fig.8]Fig. 8 is a diagram illustrating an arrangement example of dummy wiring lines in a third embodiment.

    [fig.9]Fig. 9 is a diagram illustrating an arrangement example of dummy wiring lines in a fourth embodiment.

    [fig. 10]Fig. 10 is a diagram illustrating an arrangement example of dummy wiring lines in a fifth embodiment.

    [fig. 11]Fig. 11 is a diagram illustrating an arrangement example of dummy wiring lines in a sixth embodiment.

    [fig. 12]Fig. 12 is a diagram illustrating an arrangement example of dummy wiring lines in a seventh embodiment.

    [fig.13]Fig. 13 is a diagram illustrating a relation of a wavelength of incidence light and a color of light received by each pixel.

    [fig. 14]Fig. 14 is a diagram illustrating a schematic configuration of a solid-state imaging device to which the present technology is applied.

    [fig.15]Fig. 15 is a block diagram illustrating a configuration example of an electronic apparatus to which the present technology is applied.


    Description of Embodiments



    [0029] Hereinafter, modes to carry out the present technology (hereinafter, referred to as embodiments) will be described. The following description will be made in the order described below.
    1. 1. First embodiment (example of case of arranging wiring lines at B and G pixel positions of RGB pixels)
    2. 2. Second embodiment (example of case of arranging dummy wiring lines made of narrow wiring lines at B and G pixel positions of RGB pixels)
    3. 3. Third embodiment (example of case of arranging dummy wiring line at B pixel position of RGB pixels)
    4. 4. Fourth embodiment (example of case of arranging dummy wiring line at B pixel position of RGBW pixels)
    5. 5. Fifth embodiment (example of case of arranging dummy wiring lines at B and G pixel positions of RGB-IR pixels)
    6. 6. Sixth embodiment (example of case of arranging dummy wiring lines made of narrow wiring lines at B and G pixel positions of RGB-IR pixels)
    7. 7. Seventh embodiment (example of case of arranging dummy wiring line at B pixel position of RGB-IR pixels)

    <1. First embodiment>


    <Lateral cross-section and manufacturing process of back surface radiation type image sensor>



    [0030] Fig. 1 illustrates a lateral cross-section and a manufacturing process of a back surface radiation type image sensor to which the present technology is directed.

    [0031] As illustrated by a state A of Fig. 1, in a back surface radiation type image sensor 11, an imaging element layer (photodiode layer) 22 is provided on a substrate 23 and a wiring layer 21 is formed at an uppermost layer. On an upper portion of the wiring layer 21, a polishing film 21a is formed. In the wiring layer 21, wiring lines 31 are arranged.

    [0032] As illustrated by a state B, the polishing film 21a is polished by chemical mechanical polishing (CMP) so that the polishing film 21a is flattened. That is, the polishing film 21a may be polished such that the upper surface of the polishing film 21a is generally flat.

    [0033] In addition, as illustrated by a state C, the polishing film 21a is affixed to a support substrate 24, in a state in which the upper and lower sides of the back surface radiation type image sensor 11 in the drawings (such as in Fig. 1) are reversed. Then, although not illustrated in the drawings, an uppermost surface (a backmost surface in the states A and B) of the substrate 23 in the state C of Fig. 1 is polished such that the imaging element layer 22 can receive light from a back surface (uppermost surface in the state C).

    <Equalization of wiring density of uppermost layer of wiring layer>



    [0034] As described above with reference to Fig. 1, the back surface radiation type image sensor 11 is finished by affixing the polishing film 21a of the wiring layer 21 onto the support substrate 24. Here, because an unevenness exists in the polishing film 21a due to the differences in a wiring density of the uppermost wiring lines of the wiring layer 21, it is necessary to equalize the wiring density in the uppermost layer of the wiring layer 21. Stated another way, by more uniformly distributing the wiring layer 21 throughout the wiring layer 22, it is possible to reduce an unevenness that occurs at the polishing film 21a.

    [0035] Necessary wiring lines of the uppermost layer of the wiring layer 21 in the back surface radiation type image sensor 11 are arranged as illustrated by wiring lines 31 of a left portion of Fig. 2. That is, in the uppermost layer of the wiring layer 21, the necessary wiring lines 31 are only arranged in a peripheral portion of a pixel region Z and rarely exist in the pixel region Z. However, because the wiring density may not be equalized in arrangements having only the necessary wiring lines as described above, an unevenness, as previously described, may exist in the polishing film 21a and the polishing film 21a may not adhere closely, or entirely, to the support substrate 24. Accordingly, an unevenness in the polishing film 21a may result in issues when adhering the polishing film 21a to the support substrate 24.

    [0036] For this reason, as illustrated by a right portion of Fig. 2, in the uppermost layer of the actual wiring layer 21, dummy wiring lines 41 are provided to equalize the wiring density; the dummy wiring lines 41 may be arranged in the pixel region Z in which the wiring lines 31 are originally unnecessary. Because the dummy wiring lines 41 are arranged to equalize the wiring density in the uppermost layer of the wiring layer 21 and maintain a flatness of the polishing film 21a after the CMP, the dummy wiring lines 41 do not function as the wiring lines 31.

    [0037] The wiring density in the uppermost layer of the wiring layer 21 is maintained almost equally by the dummy wiring lines 41 illustrated by the right portion of Fig. 2 and a flatness of the polishing film 21a after the CMP is obtained and/or maintained.

    <Reflection by dummy wiring line>



    [0038] However, as a method of arranging the dummy wiring lines 41 in the pixel region Z, if a pixel array is ignored and the dummy wiring lines 41 are arranged by considering only the design or the wiring density, lattice (stripe) irregularities illustrated by an upper right portion of Fig. 3 may occur.

    [0039] For example, in an upper right portion of Fig. 3, bright stripe irregularities (e.g. a lattice irregularity) are displayed as illustrated by an image PZ11 displayed as an enlarged region Z11 in an image P1. In addition, a lower right portion of Fig. 3 illustrates a waveform diagram G1 depicting a light reception level of the imaging element on a straight line L in the image PZ11 of the upper right portion of Fig. 3. That is, on the straight line L in the image PZ11, a light reception level of a region where a white lattice irregularity occurs is high and a light reception level of the other region is low.

    [0040] Such irregularities may be generated when incident light having a longer wavelength is transmitted through the imaging element layer 22, and is reflected by the dummy wiring lines 41, such that the light having the longer wavelength is received by the imaging element layer 22 again.

    [0041] As illustrated by Fig. 4, if incidence light L is converted into blue light LB, red light LR, and green light LG by blue, red, and green color filters BRG respectively, the light incident on the imaging element layer 22 is converted into a light reception signal by the imaging element of the imaging element layer 22. At this time, a portion of light having a longer wavelength, particularly, the red light LR and the green light LG, may not be absorbed by the imaging element layer 22 made of silicon Si (Epi); accordingly, such light may be transmitted through the imaging element layer 22 and may be reflected by the dummy wiring lines 41 of the wiring layer 21, such that the reflected light is incident on the imaging element layer 22.

    [0042] Fig. 5 generally illustrates an absorption ratio (0 to 1.0)
    at each depth (µm)
    for varying wavelengths of light; for example, light having a plurality of wavelengths ranging from 400 nm to 1005 nm may be transmitted through the silicon Si. A relation illustrated by Fig. 5 is only an example of a portion of the wavelengths of light and a similar relation may be applied to other wavelengths. As a relation between the light of other wavelengths and depths at which the light is absorbed by about 50%, the following is provided. When the wavelength of light is 460 nm, the depth at which about 50% of the light is absorbed is approximately
    0.32 µm,
    when the wavelength of light is 530 nm, the depth at which about 50% of the light is absorbed is approximately
    0.79 µm,
    when the wavelength of light is 610 nm, the depth at which about 50% of the light is absorbed is approximately
    1.50 µm,
    and when the wavelength of light is 700 nm, the depth at which about 50% of the light is absorbed is approximately
    3.00 µm.

    [0043] In general, the thickness of the imaging element layer 22 of the back surface radiation type image sensor 11 is, for example,
    about 2.6 µm to 3.0 µm.

    [0044] For this reason, in the case in which the wavelength of the red light LR is about 650 nm, as illustrated by Fig. 5, if the thickness of the imaging element layer 22 is about 3.0 µm,
    about 40% of the light is transmitted through the imaging element layer 22 and may be reflected by the dummy wiring lines 41. In addition, in the case in which the wavelength of the green light LG is about 550 nm, if the thickness of the imaging element layer 22 is about
    3.0 µm,
    about 10% of the light is transmitted through the imaging element layer 22 and may be reflected by the dummy wiring lines 41.

    [0045] For this reason, in the imaging element receiving the red light LR and the green light LG, because both directly incident light and light reflected by the dummy wiring lines 41 and then incident are received, a light reception level increases. That is, for the imaging elements receiving the red light LR and/or the green light LG, the reception level may be improperly increased because the imaging element receives both light directly incident on the imaging element and light that has been reflected by the dummy wiring lines 41. In particular, because a transmission ratio of the red light LR for the imaging element layer 22 is at a high level, the red light is received more brightly than other colors of light.

    [0046] As such, the portion of the red light LR or the green light LG is transmitted through the imaging element layer 22 and is reflected by the dummy wiring lines 41; the region where the light reception level increases becomes a lattice white portion such as in the image PZ11 of the upper right portion of Fig. 3 and the light reception level of the other region is low. For at least this reason, the lattice irregularity occurs. As illustrated by a region Z2 in a left portion of Fig. 3, a region where a light reception level increases and light is received brightly is a region where the dummy wiring lines 41 exist and the other region Z1 becomes a region where the dummy wiring lines 41 do not exist. The left portion of Fig. 3 is displayed by enlarging the lattice irregularity in the image PZ11 in the upper right portion of Fig. 3.

    <Example of dummy wiring line in uppermost layer of wiring layer>



    [0047] Therefore, in the back surface radiation type image sensor 11 to which the present technology is directed, as illustrated by Fig. 6, the dummy wiring lines 41 are arranged in a pixel region Z of the uppermost layer of the wiring layer 21.

    [0048] That is, as illustrated by Fig. 6, in the pixel region Z of a pixel array, the dummy wiring lines 41 of a pixel width are arranged only at positions corresponding to pixels (B pixels and G pixels) in which blue and green color filters B and G transmit blue light LB and green light LG having the relatively shorter wavelengths are arranged. That is, the width of the dummy wiring lines 41 may be substantially similar to the width of a pixel.

    [0049] As such, the dummy wiring lines 41 of a pixel width are not arranged in a region in which pixels (hereinafter, also called the R pixels) where red color filters R are arranged exist; accordingly, the red light LR having the longer wavelengths is received in the pixel region Z. Therefore, even though the red light LR may transmit through the imaging element layer 22, reflection of such transmitted light by the dummy wiring lines 41 can be reduced.

    [0050] As a result, because light reflected by the dummy wiring lines 41 is not incident on the imaging element layer 22, the occurrence of the lattice irregularity (stripe irregularity) is reduced. In addition, because the wiring density in the polishing film 21a of the wiring layer 21 can be almost equalized as a whole (that is, the wiring density within the pixel region z may be substantially equal for all pixels), the occurrence of the lattice irregularity can be suppressed while the achieving a desired flatness of the polishing film 21a by the CMP. Fig. 6, illustrates an array of pixels in the pixel region Z; R, G, and B pixels are displayed as "R", "G", and "B".

    <2. Second embodiment>


    <Dummy wiring line made of narrow wiring line>



    [0051] The example of the case in which the dummy wiring lines 41 have a pixel width has been described above. However, if the dummy wiring lines 41 have the pixel width, the red light LR or the green light LG of the adjacent pixels may be transmitted through the imaging element layer 22 and thus may be reflected. Therefore, the dummy wiring lines 41 may be configured of narrower wiring lines having a width smaller than that of a pixel width.

    [0052] Fig. 7 illustrates a wiring example in the uppermost layer of the wiring layer 21 in the pixel region Z in which dummy wiring lines 41' made of narrow wiring lines are utilized as the dummy wiring lines 41.

    [0053] That is, as illustrated by Fig. 7, in the pixel region Z, the dummy wiring lines 41' made of narrow wiring lines having a width that is smaller than a pixel width are arranged at positions only corresponding to regions where the B pixels and the G pixels are arranged, according to the pixel array.

    [0054] As such, the narrow wiring lines are arranged as illustrated by the dummy wiring lines 41' made of the narrow wiring lines in the uppermost layer of the wiring layer 21 of Fig. 7. Therefore, even though the red light LR in the pixels where the adjacent color filters R are arranged or the green light LG in the pixels where the color filters G are arranged may transmit through the imaging element layer 22, a reflection of the transmitted light can further be suppressed. As a result, the occurrence of the lattice irregularity can be further suppressed while the flatness of the polishing film 21a by the CMP is maintained.

    <3. Third embodiment>


    <Example of case of arranging dummy wiring line in only B pixel>



    [0055] The example of the case in which the dummy wiring lines 41 are arranged in the regions of the B pixels and the G pixels in the pixel region Z has been described. However, because a portion of the green light LG transmits through the imaging element layer 22 in regions where the G pixels exist, the green light may be reflected by the dummy wiring lines 41 (or the dummy wiring lines 41' made of the narrow wiring lines). Therefore, the dummy wiring lines 41 (or the dummy wiring lines 41' made of the narrower wiring lines) may be arranged only in the regions where the B pixels exist.

    [0056] Fig. 8 illustrates a wiring example of the case in which the dummy wiring lines 41 are arranged only in the regions where the B pixels in the uppermost layer of the wiring layer 21 in the pixel region Z exist. That is, as illustrated by Fig. 8, in the pixel region Z, the dummy wiring lines 41 having a pixel width are arranged only at positions corresponding to the pixels where the B pixels are arranged.

    [0057] As such, the dummy wiring lines 41 are arranged only in the B pixels as illustrated by the dummy wiring lines 41 in the uppermost layer of the wiring layer 21 of Fig. 8. Therefore, even though the red light LR and the green light LG may be reflected by the dummy wiring lines 41, the reflection thereof can be suppressed. As a result, the occurrence of the lattice irregularity can be further suppressed while the flatness of the polishing film 21a by the CMP is maintained. Although not illustrated in the drawings, instead of the dummy wiring lines 41, the dummy wiring lines 41' made of the narrower wiring lines may be arranged. The dummy wiring lines 41' made of the narrow wiring lines are arranged, so that the reflection from the adjacent G and R pixels is further decreased.

    <4. Fourth embodiment>


    <Arrangement of dummy wiring line in only B pixel among four pixels of RGBW>



    [0058] The example of the case in which the dummy wiring lines 41 are arranged in the regions of the B pixels and the G pixels among the RGB pixels in the pixel region Z or the positions corresponding to the B pixels has been described above. However, in the pixel region Z including the RGB pixels and pixels where white color filters W are arranged (hereinafter, also called the W pixels), the dummy wiring lines 41 may be arranged for only the B pixels among the RGBW pixels.

    [0059] Fig. 9 illustrates a wiring example in which the dummy wiring lines 41 are arranged only in the regions where the B pixels in the uppermost layer of the wiring layer 21 of the pixel region Z including the RGBW pixels exist. As such, the dummy wiring lines 41 are arranged in only the B pixels as illustrated by the dummy wiring lines 41 in the uppermost layer of the wiring layer 21 of Fig. 9. Therefore, even though the red light LR, the green light LG, and white light LW (the red light LR and the green light LG included therein) including components reflected by the dummy wiring lines 41 transmit through the imaging element layer 22, the reflection thereof can be suppressed. As a result, the occurrence of lattice irregularities can be further suppressed while the flatness of the polishing film 21a by the CMP is maintained. Although not illustrated in the drawings, instead of the dummy wiring lines 41, the dummy wiring lines 41' made of the narrower wiring lines may be arranged. The dummy wiring lines 41' made of the narrow wiring lines are arranged, so that the reflection from the adjacent G and R pixels can be further decreased. However, because a transmission ratio of the green light LG transmitting the G pixels for the imaging element layer 22 is relatively low, the dummy wiring lines 41 (or 41') may be arranged for the G pixels in addition to the B pixels.

    <5. Fifth embodiment>


    <Arrangement of dummy wiring lines in B and G pixels among four pixels of RGB-IR>



    [0060] The example of the case in which the dummy wiring lines 41 are arranged only at the positions corresponding to the regions of the B pixels among the RGBW pixels in the pixel region Z has been described above. However, in the pixel region Z that includes the RGB pixels and pixels where color filters IR of infrared light are arranged (hereinafter, also called the IR pixels), the dummy wiring lines 41 may be arranged for the B and G pixels among the pixels RGB-IR.

    [0061] Fig. 10 illustrates a wiring example of the case in which the dummy wiring lines 41 are arranged only in the regions where the B and G pixels in the uppermost layer of the wiring layer 21 in the pixel region Z including the RGB-IR pixels exist.

    [0062] As such, the dummy wiring lines 41 are arranged only at the positions corresponding to the B and G pixels as illustrated by the dummy wiring lines 41 in the uppermost layer of the wiring layer 21 of Fig. 10. Therefore, even though the red light LR and the infrared light LIR including components reflected by the dummy wiring lines 41 transmit through the imaging element layer 22, the reflection thereof can be suppressed. As a result, the occurrence of the lattice irregularity can be suppressed while the flatness of the polishing film 21a by the CMP is maintained.

    <6. Sixth embodiment>


    <Arrangement of dummy wiring lines made of narrow wiring lines in only B and G pixels among four pixels of RGB-IR>



    [0063] The example of the case in which the dummy wiring lines 41 are arranged at the positions corresponding to the regions of the B and G pixels among the RGB-IR pixels in the pixel region Z has been described above. However, instead of the dummy wiring lines 41, the dummy wiring lines 41' made of the narrow wiring lines may be arranged.

    [0064] Fig. 11 illustrates a wiring example of the case in which the dummy wiring lines 41' made of the narrow wiring lines are arranged only in the regions where the B and G pixels in the uppermost layer of the wiring layer 21 in the pixel region Z including the RGB-IR pixels exist.

    [0065] As such, the dummy wiring lines 41' are arranged at only the positions corresponding to the B and G pixels as illustrated by the dummy wiring lines 41' made of the narrow wiring lines in the uppermost layer of the wiring layer 21 of Fig. 11. Therefore, even though the red light LR and the infrared light LIR including components reflected by the dummy wiring lines 41' transmit through the imaging element layer 22, the reflection thereof can be further suppressed. As a result, the occurrence of the lattice irregularity can be further suppressed while the flatness of the polishing film 21a by the CMP is maintained.

    <7. Seventh embodiment>


    <Arrangement of dummy wiring line in only B pixel among four pixels of RGB-IR>



    [0066] The example of the case in which the dummy wiring lines 41' are arranged only at the positions corresponding to the regions of the B and G pixels among the RGB-IR pixels in the pixel region Z has been described above. However, the dummy wiring lines 41 may be arranged only at the positions of the B pixels.

    [0067] Fig. 12 illustrates a wiring example of the case in which the dummy wiring lines 41 are arranged only in the regions where the B pixels in the uppermost layer of the wiring layer 21 in the pixel region Z including the RGB-IR pixels exist.

    [0068] As such, the dummy wiring lines 41 are arranged only at the positions corresponding to the B pixels as illustrated by the dummy wiring lines 41 in the uppermost layer of the wiring layer 21 of Fig. 12. Therefore, even though the red light LR, the green light LG, and the infrared light LIR, including components reflected by the dummy wiring lines 41, transmit through the imaging element layer 22, the reflection thereof can be further suppressed. As a result, the occurrence of the lattice irregularity can be suppressed while the flatness of the polishing film 21a by the CMP is maintained.

    [0069] Although not illustrated in the drawings, instead of the dummy wiring lines 41, the dummy wiring lines 41' made of the narrow wiring lines may be utilized and arranged. The dummy wiring lines 41' made of the narrow wiring lines are arranged, so that reflection of the green light LG, the red light LR, and the infrared light LIR of the adjacent G, R, and IR pixels can be further decreased.

    <Color and wavelength of pixel>



    [0070] The example of the case in which the arrangement positions of the dummy wiring lines 41 (or the dummy wiring lines 41' made of the narrow wiring lines) are specified according to the positions of the colors (the R pixel, the G pixel, the B pixel, the W pixel, and the IR pixel) of the light transmitting to the pixels has been described. However, the dummy wiring lines 41 (or the dummy wiring lines 41' made of the narrow wiring lines) may be arranged to correspond to the pixels of colors of the wavelengths shorter than the predetermined wavelengths.

    [0071] That is, for example, as illustrated by Fig. 13, when 570 nm is set as a predetermined wavelength T, the dummy wiring lines 41 (or the dummy wiring lines 41' made of the narrow wiring lines) may be arranged at the positions where the pixels of a color with a wavelength shorter than the predetermined wavelength T (= 570 nm) as a peak exist.

    [0072] In this case, when pixels are pixels of three colors of RGB, the dummy wiring lines 41 (or the dummy wiring lines 41' made of the narrow wiring lines) are arranged at only the positions where the B and G pixels with the wavelength shorter than the wavelength of 570 nm as a peak exist.

    [0073] In addition, when pixels are pixels of three colors of magenta, cyan, and yellow (MCY), the dummy wiring lines 41 (or the dummy wiring lines 41' made of the narrow wiring lines) are arranged only at the positions where the cyan pixels having a wavelength shorter than the wavelength of 570 nm as a peak exist.

    [0074] At an upper step of Fig. 13, a color distribution set to the pixels of the additive three primary colors (RGB) with each wavelength as a peak is illustrated; at a lower portion of Fig. 13, a color distribution set to the pixels of the subtractive three primary colors (MCY) with each wavelength as a peak is illustrated. In Fig. 13, the case in which the wavelength of 570 nm is the predetermined wavelength T is illustrated.

    [0075] When the predetermined wavelength T is set and the dummy wiring lines 41 (or the dummy wiring lines 41' made of the narrow wiring lines) are arranged at only the positions of the pixels of the color of the wavelength shorter than the wavelength of the B pixels, any wavelength of 400 nm to 600 nm is set as the predetermined wavelength T and the dummy wiring lines 41 (or the dummy wiring lines 41' made of the narrow wiring lines) are arranged in the pixel region in which the light of the color with the predetermined wavelength T as the peak and the light of the color of the wavelength shorter than the wavelength of the color are received. In addition, the range may be further narrowed such that any wavelength of 530 nm to 550 nm may be set as the predetermined wavelength T and the dummy wiring lines 41 (or the dummy wiring lines 41' made of the narrow wiring lines) are arranged in the pixel region in which the light of the color with the predetermined wavelength T as the peak and the light of the color of the wavelength shorter than the wavelength of the color are received. In addition, when the dummy wiring lines 41 (or the dummy wiring lines 41' made of the narrow wiring lines) are arranged at the positions of the pixels having wavelengths shorter than the wavelength of the G pixels and the dummy wiring lines 41 (or the dummy wiring lines 41' made of the narrow wiring lines) are arranged in the pixel region in which the light of the color with the predetermined wavelength T as the peak and the light of the color of the wavelength shorter than the wavelength of the color are received.

    [0076] As described above, according to the present technology, in the back surface radiation type image sensor, the influence of light reflected by the wiring lines of the wiring layer is reduced while the wiring density in the uppermost layer of the wiring layer is equalized, so that noise can be decreased and a high image quality can be realized.

    [0077] Fig. 14 is a diagram illustrating a schematic configuration of a solid-state imaging device to which the present technology is applied. This solid-state imaging device 50 includes, for example, a CMOS image sensor.

    [0078] The solid-state imaging device 50 of Fig. 14 includes a pixel region (a so-called pixel array) 53 in which pixels 52 including a plurality of photoelectric conversion portions are regularly arranged in a two-dimensional array on the semiconductor substrate 51 and a peripheral circuit portion.

    [0079] Each of the pixels 52 includes, for example, a photodiode which is the photoelectric conversion portion and a plurality of pixel transistors (so-called MOS transistors).

    [0080] In addition, the pixels 52 may have a shared pixel structure. This pixel shared structure is formed by a plurality of photodiodes, a plurality of transfer transistors, a single shared floating diffusion, and another shared transistor.

    [0081] The peripheral circuit portion includes a vertical driving circuit 54, a column signal processing circuit 55, a horizontal driving circuit 56, an output circuit 57, a control circuit 58, and the like.

    [0082] The control circuit 58 receives an input clock and data for commanding an operation mode and the like, and outputs data such as internal information of the solid-state imaging device. In other words, the control circuit 58 generates a clock signal used as a reference of operations of the vertical driving circuit 54, the column signal processing circuit 55, the horizontal driving circuit 56, and the like, and control signals on the basis of a vertical synchronization signal, a horizontal synchronization signal, and a master clock. In addition, these signals are input to the vertical driving circuit 54, the column signal processing circuit 55, the horizontal driving circuit 56, and the like.

    [0083] The vertical driving circuit 54 including, for example, shift registers, selects a pixel driving line, and supplies a pulse for driving the pixels to the selected pixel driving line so as to drive the pixels in the unit of a row. In other words, the vertical driving circuit 54 sequentially selectively scans the respective pixels 52 of the pixel region 53 in the vertical direction in the unit of a row, and supplies a pixel signal based on signal charge which is generated according to a light receiving amount in, for example, the photodiode which is a photoelectric conversion portion of each pixel 52, to the column signal processing circuit 55 via a vertical signal line 59.

    [0084] The column signal processing circuit 55 is disposed, for example, for each column of the pixels 52, and performs a signal process such as noise removal on signals output from the pixels 52 of one row for each pixel column. In other words, the column signal processing circuit 55 performs signal processes such as CDS for removing fixed pattern noise unique to the pixels 52, signal amplification, and AD conversion. In an output end of the column signal processing circuit 55, a horizontal selection switch (not shown) is provided so as to be connected to a horizontal signal line 61.

    [0085] The horizontal driving circuit 56 includes, for example, shift registers, sequentially outputs horizontal scanning pulses so as to sequentially select the respective column signal processing circuits 55, thereby outputting a pixel signal from each of the column signal processing circuits 55 to the horizontal signal line 61.

    [0086] The output circuit 57 performs a signal process on the signals which are sequentially supplied from the respective column signal processing circuits 55 via the horizontal signal line 61 so as to be output. For example, only buffering may be performed, or black level adjustment, column disparity correction, a variety of digital signal processes, and the like may be performed. An input and output terminal 60 sends and receives signals to and from an external device.

    [0087] The solid-state imaging device 51 shown in Fig. 14 includes a rear surface irradiation type CMOS image sensor with a three-layer stacked structure. For example, the pixels 52 shown in Fig. 14 are sensor circuits formed in the first semiconductor substrate, and the peripheral circuits are logical circuits formed in the second semiconductor substrate or memory circuits formed in the third semiconductor substrate.

    [0088] Fig. 15 is a block diagram illustrating a configuration example of a camera apparatus which is an electronic apparatus to which the present technology is applied.

    [0089] A camera apparatus 70 in Fig. 15 includes an optical unit 71 including a lens group and the like, a solid-state imaging device (imaging device) 72 which employs the above-described respective configurations of the pixels 72, and a DSP circuit 73 which is a camera signal processing circuit. In addition, the camera apparatus 70 includes a frame memory 74, a display unit 75, a recording unit 76, an operation unit 77, and a power supply unit 78. The DSP circuit 73, the frame memory 74, the display unit 75, the recording unit 76, the operation unit 77, and the power supply unit 78 are connected to each other via a bus line 79.

    [0090] The optical unit 71 receives incident light (image light) from a subject so as to be imaged on an imaging surface of the solid-state imaging device 72. The solid-state imaging device 72 converts a light amount of the incident light which is imaged on the imaging surface by the optical unit 71 into an electric signal in the unit of a pixel and outputs the electric signal as a pixel signal. The solid-state imaging device related to the above-described embodiments may be used as the solid-state imaging device 72.

    [0091] The display unit 75 includes, for example, a panel type display device such as a liquid crystal panel or an organic electroluminescence (EL) panel, and displays moving images or still images captured by the solid-state imaging device 72. The recording unit 76 records moving images or still images captured by the solid-state imaging device 72 on a recording medium such as a video tape or a digital versatile disk (DVD).

    [0092] The operation unit 77 issues operation commands for various functions of the camera apparatus 70 in response to an operation by a user. The power supply unit 78 appropriately supplies a variety of power which is operation power of the DSP circuit 73, the frame memory 74, the display unit 75, the recording unit 76, and the operation unit 77, to the supply targets.

    Reference Signs List



    [0093] 

    11 Back surface radiation type image sensor

    21 Wiring layer

    21a Polishing film

    22 Imaging element layer

    23 Substrate

    24 Support substrate

    31 Wiring line

    41, 41' Dummy wiring lines

    70 Camera apparatus

    72 Solid-state imaging device




    Claims

    1. A solid-state back illuminated imaging sensor comprising:

    a substrate (23); and

    an imaging element layer (22) having a plurality of imaging elements, the imaging element layer (22) located between the substrate (23) and a wiring layer (21) having a plurality of wiring lines (31, 41, 41') comprising wiring lines (31) which are electrically connected and dummy wiring lines (41, 41') which are not electrically connected, wherein the dummy wiring lines (41, 41') of the wiring layer (21) are arranged in pixel regions (Z) below one or more imaging elements configured to receive light having a wavelength less than a predetermined wavelength, the predetermined wavelength being any wavelength of 400 to 600 nm, the wiring lines (31) which are electrically connected are arranged in a peripheral portion of the pixel regions (Z),

    the wiring lines (31) which are electrically connected are located in an upper most layer of the wiring layer, where upper most refers to the direction in which the substrate (23), the imaging element layer (22) and the wiring layer (21) are stacked on each other, and

    the dummy wiring lines (41, 41') of the wiring layer (21) are not arranged in pixel regions (Z) configured to receive light having a wavelength greater than the predetermined wavelength,

    the solid-state back illuminated imaging sensor being characterized in that the dummy wiring lines (41, 41') are located in the upper most layer of the wiring layer, and

    the dummy wiring lines (41, 41') of the upper most layer of the wiring layer are distributed within the wiring layer such that a wiring density is equal.


     
    2. The solid-state back illuminated imaging sensor according to claim 1, wherein the plurality of imaging elements located within the imaging element layer (22) are configured to receive red light, blue light, and green light, and
    wherein the dummy wiring lines (41, 41') are arranged in pixel regions configured to receive green light and blue light and dummy wiring lines are not arranged in pixel regions configured to receive red light.
     
    3. The solid-state back illuminated imaging sensor according to claim 1, wherein the plurality of imaging elements located within the imaging element layer are configured to receive red light, blue light, and green light, and
    wherein the dummy wiring lines (41, 41') are arranged in pixel regions configured to receive blue light and dummy wiring lines (41, 41')are not arranged in pixel regions configured to receive green light and red light.
     
    4. The solid-state back illuminated imaging sensor according to claim 1, wherein the plurality of imaging elements located within the imaging element layer (22) are configured to receive red light, blue light, green light, and white light, and
    wherein the dummy wiring lines (41, 41') are arranged in pixel regions configured to receive blue light and dummy wiring lines (41, 41') are not arranged in pixel regions configured to receive green light, red light, and white light.
     
    5. The solid-state back illuminated imaging sensor according to claim 1, wherein the dummy wiring lines (41, 41') of the upper most layer of the wiring layer arranged in pixel regions configured to receive light have a width that is smaller than a width of a pixel of the imaging element layer.
     
    6. The solid-state back illuminated imaging sensor according to claim 1, further including a polishing layer (21a) located above the wiring layer (21), wherein the upper surface of the polishing layer (21a) is flat.
     
    7. An electronic apparatus comprising the solid-state back illuminated imaging sensor as defined in anyone of the preceding claims.
     
    8. A method of manufacturing a solid-state back illuminated imaging sensor, the method comprising:

    forming an imaging element layer (22) between a substrate (23) and a wiring layer (21); and

    forming a plurality of wiring lines (31, 41, 41') at an upper layer of the wiring layer (31), the wiring lines (31, 41, 41') comprising wiring lines (31) which are electrically connected and dummy wiring lines (41, 41') which are not electrically connected, wherein the dummy wiring lines (41, 41') of the wiring layer are arranged in pixel regions (Z) below one or more imaging elements configured to receive light having a wavelength less than a predetermined wavelength, the predetermined wavelength being any wavelength of 400 to 600 nm, the wiring lines (31) which are electrically connected are arranged in a peripheral portion of the pixel regions (Z), the dummy wiring lines (41, 41') and the wiring lines (31) which are electrically connected are located in an upper most layer of the wiring layer,
    where upper most refers to the direction in which the substrate (23), the imaging element layer (22) and the wiring layer (21) are stacked on each other, the dummy wiring lines (41, 41') of the upper most layer of the wiring layer are distributed within the wiring layer such that a wiring density is equal, and the dummy wiring lines (41, 41') of the wiring layer (21) are not arranged in pixel regions (Z) configured to receive light having a wavelength greater than the predetermined wavelength.


     
    9. The method of manufacturing according to claim 8, further including: polishing a polishing film (21a) located on an upper portion of the wiring layer (21) and thereafter affixing the polished polishing film to a support substrate (24).
     


    Ansprüche

    1. Rückseitenbeleuchteter Festkörper-Bildgebungssensor, umfassend:

    ein Substrat (23); und

    eine Bildgebungselementschicht (22) mit mehreren Bildgebungselementen, wobei sich die Bildgebungselementschicht (22) zwischen dem Substrat (23) und einer Verdrahtungsschicht (21) mit mehreren Verdrahtungsleitungen (31, 41, 41'), umfassend Verdrahtungsleitungen (31), die elektrisch angeschlossen sind, und Dummy-Verdrahtungsleitungen (41, 41'), die nicht elektrisch angeschlossen sind, befindet, wobei die Dummy-Verdrahtungsleitungen (41, 41') der Verdrahtungsschicht (21) in Pixelgebieten (Z) unter einem oder mehreren Bildgebungselementen angeordnet sind, ausgebildet zum Empfangen von Licht mit einer Wellenlänge unter einer vorbestimmten Wellenlänge, wobei die vorbestimmte Wellenlänge eine beliebige Wellenlänge von 400 bis 600 nm ist, wobei die Verdrahtungsleitungen (31), die elektrisch angeschlossen sind, in einem peripheren Abschnitt der Pixelgebiete (Z) angeordnet sind, wobei sich die Verdrahtungsleitungen (31), die elektrisch angeschlossen sind, in einer obersten Schicht der Verdrahtungsschicht befinden, wobei sich Oberste auf die Richtung bezieht, in der das Substrat (23), die Bildgebungselementschicht (22) und die Verdrahtungsschicht (21) aufeinander gestapelt sind und

    die Dummy-Verdrahtungsleitungen (41, 41') der Verdrahtungsschicht (21) nicht in Pixelgebieten (Z) angeordnet sind, ausgebildet zum Empfangen von Licht mit einer Wellenlänge größer als der vorbestimmten Wellenlänge,

    wobei der rückseitenbeleuchtete Festkörper-Bildgebungssensor dadurch gekennzeichnet ist, dass

    sich die Dummy-Verdrahtungsleitungen (41, 41') in der obersten Schicht der Verdrahtungsschicht befinden,

    die Dummy-Verdrahtungsleitungen (41, 41') der obersten Schicht der Verdrahtungsschicht innerhalb der Verdrahtungsschicht derart verteilt sind, dass eine Verdrahtungsdichte gleich ist.


     
    2. Rückseitenbeleuchteter Festkörper-Bildgebungssensor nach Anspruch 1, wobei sich die mehreren Bildgebungselemente, die sich innerhalb der Bildgebungselementschicht (22) befinden, ausgebildet sind zum Empfangen von rotem Licht, blauem Licht und grünem Licht, und
    wobei die Dummy-Verdrahtungsleitungen (41, 41') in Pixelgebieten angeordnet sind, ausgebildet zum Empfangen von grünem Licht und blauem Licht, und Dummy-Verdrahtungsleitungen nicht in Pixelgebieten angeordnet sind, ausgebildet zum Empfangen von rotem Licht.
     
    3. Rückseitenbeleuchteter Festkörper-Bildgebungssensor nach Anspruch 1, wobei sich die mehreren Bildgebungselemente, die sich innerhalb der Bildgebungselementschicht befinden, ausgebildet sind zum Empfangen von rotem Licht, blauem Licht und grünem Licht, und
    wobei die Dummy-Verdrahtungsleitungen (41, 41') in Pixelgebieten angeordnet sind, ausgebildet zum Empfangen von blauem Licht, und Dummy-Verdrahtungsleitungen (41,41') nicht in Pixelgebieten angeordnet sind, ausgebildet zum Empfangen von grünem Licht und rotem Licht.
     
    4. Rückseitenbeleuchteter Festkörper-Bildgebungssensor nach Anspruch 1, wobei sich die mehreren Bildgebungselemente, die sich innerhalb der Bildgebungselementschicht (22) befinden, ausgebildet sind zum Empfangen von rotem Licht, blauem Licht, grünem Licht und weißem Licht, und
    wobei die Dummy-Verdrahtungsleitungen (41, 41') in Pixelgebieten angeordnet sind, ausgebildet zum Empfangen von blauem Licht, und Dummy-Verdrahtungsleitungen (41, 41') nicht in Pixelgebieten angeordnet sind, ausgebildet zum Empfangen von grünem Licht, rotem Licht und weißem Licht.
     
    5. Rückseitenbeleuchteter Festkörper-Bildgebungssensor nach Anspruch 1, wobei die Dummy-Verdrahtungsleitungen (41, 41') der obersten Schicht der Verdrahtungsschicht in Pixelgebieten angeordnet sind, ausgebildet zum Empfangen von Licht mit einer Breite, die kleiner ist als eine Breite eines Pixels der Bildgebungselementschicht.
     
    6. Rückseitenbeleuchteter Festkörper-Bildgebungssensor nach Anspruch 1, weiterhin mit einer Polierschicht (21a), die sich über der Verdrahtungsschicht (21) befindet, wobei die obere Oberfläche der Polierschicht (21a) flach ist.
     
    7. Elektronikvorrichtung, umfassend den rückseitenbeleuchteten Festkörper-Bildgebungssensor wie in einem der vorhergehenden Ansprüche definiert.
     
    8. Verfahren zum Herstellen eines rückseitenbeleuchteten Festkörper-Bildgebungssensors, wobei das Verfahren umfasst:

    Ausbilden einer Bildgebungselementschicht (22) zwischen einem Substrat (23) und einer Verdrahtungsschicht (21); und

    Ausbilden von mehreren Verdrahtungsschichten (31, 41, 41') an einer oberen Schicht der Verdrahtungsschicht (31), wobei die Verdrahtungsleitungen (31, 41, 41') Verdrahtungsleitungen (31) umfassen, die elektrisch angeschlossen sind, und Dummy-Verdrahtungsleitungen (41, 41'), die nicht elektrisch angeschlossen sind, wobei die Dummy-Verdrahtungsleitungen (41, 41') der Verdrahtungsschicht (21) in Pixelgebieten (Z) unter einem oder mehreren Bildgebungselementen angeordnet sind, ausgebildet zum Empfangen von Licht mit einer Wellenlänge unter einer vorbestimmten Wellenlänge, wobei die vorbestimmte Wellenlänge eine beliebige Wellenlänge von 400 bis 600 nm ist, wobei die Verdrahtungsleitungen (31), die elektrisch angeschlossen sind, in einem peripheren Abschnitt der Pixelgebiete (Z) angeordnet sind, wobei sich die Dummy-Verdrahtungsleitungen (41,41') und die Verdrahtungsleitungen (31), die elektrisch angeschlossen sind, in einer obersten Schicht der Verdrahtungsschicht befinden, wobei sich Oberste auf die Richtung bezieht, in der das Substrat (23), die Bildgebungselementschicht (22) und die Verdrahtungsschicht (21) aufeinander gestapelt sind die Dummy-Verdrahtungsleitungen (41, 41') der obersten Schicht der Verdrahtungsschicht innerhalb der Verdrahtungsschicht derart verteilt sind, dass eine Verdrahtungsdichte gleich ist und

    die Dummy-Verdrahtungsleitungen (41, 41') der Verdrahtungsschicht (21) nicht in Pixelgebieten (Z) angeordnet sind, ausgebildet zum Empfangen von Licht mit einer Wellenlänge größer als der vorbestimmten Wellenlänge.


     
    9. Verfahren zum Herstellen nach Anspruch 8, weiterhin beinhaltend:
    Polieren eines Polierfilms (21a, der sich auf einem oberen Abschnitt der Verdrahtungsschicht (21) befindet, und danach Anbringen des polierten Polierfilms an einem Trägersubstrat (24).
     


    Revendications

    1. Capteur d'imagerie à semi-conducteurs éclairé par l'arrière comprenant :

    un substrat (23) ; et

    une couche d'éléments d'imagerie (22) ayant une pluralité d'éléments d'imagerie, la couche d'éléments d'imagerie (22) étant située entre le substrat (23) et une couche de câblage (21) ayant une pluralité de lignes de câblage (31, 41, 41') comprenant des lignes de câblage (31) qui sont reliées électriquement et des lignes de câblage factices (41, 41') qui ne sont pas reliées électriquement, les lignes de câblage factices (41, 41') de la couche de câblage (21) étant disposées dans des régions de pixels (Z) au-dessous d'un ou plusieurs éléments d'imagerie configurées pour recevoir de la lumière ayant une longueur d'onde inférieure à une longueur d'onde prédéterminée, la longueur d'onde prédéterminée étant n'importe quelle longueur d'onde de 400 à 600 nm, les lignes de câblage (31) qui sont reliées électriquement étant disposées dans une partie périphérique des régions de pixels (Z),

    les lignes de câblage (31) qui sont reliées électriquement étant situées dans une couche la plus haute de la couche de câblage, la plus haute faisant référence à la direction dans laquelle le substrat (23), la couche d'éléments d'imagerie (22) et la couche de câblage (21) sont empilées les uns sur les autres, et

    les lignes de câblage factices (41, 41') de la couche de câblage (21) n'étant pas disposées dans des régions de pixels (Z) configurées pour recevoir de la lumière ayant une longueur d'onde supérieure à la longueur d'onde prédéterminée,

    le capteur d'imagerie à semi-conducteurs éclairé par l'arrière étant caractérisé en ce que

    les lignes de câblage factices (41, 41') sont situées dans la couche la plus haute de la couche de câblage, et

    les lignes de câblage factices (41, 41') de la couche la plus haute de la couche de câblage sont réparties à l'intérieur de la couche de câblage de telle sorte qu'une densité de câblage est égale.


     
    2. Capteur d'imagerie à semi-conducteurs éclairé par l'arrière selon la revendication 1,
    dans lequel la pluralité d'éléments d'imagerie situés à l'intérieur de la couche d'éléments d'imagerie (22) sont configurés pour recevoir de la lumière rouge, de la lumière bleue et de la lumière verte, et
    dans lequel les lignes de câblage factices (41, 41') sont disposées dans des régions de pixels configurées pour recevoir de la lumière verte et de la lumière bleue et les lignes de câblage factices ne sont pas disposées dans des régions de pixels configurées pour recevoir de la lumière rouge.
     
    3. Capteur d'imagerie à semi-conducteurs éclairé par l'arrière selon la revendication 1,
    dans lequel la pluralité d'éléments d'imagerie situés à l'intérieur de la couche d'éléments d'imagerie sont configurés pour recevoir de la lumière rouge, de la lumière bleue et de la lumière verte, et
    dans lequel les lignes de câblage factices (41, 41') sont disposées dans des régions de pixels configurées pour recevoir de la lumière bleue et les lignes de câblage factices (41, 41') ne sont pas disposées dans des régions de pixels configurées pour recevoir de la lumière verte et de la lumière rouge.
     
    4. Capteur d'imagerie à semi-conducteurs éclairé par l'arrière selon la revendication 1,
    dans lequel la pluralité d'éléments d'imagerie situés à l'intérieur de la couche d'éléments d'imagerie (22) sont configurés pour recevoir de la lumière rouge, de la lumière bleue, de la lumière verte et de la lumière blanche, et
    dans lequel les lignes de câblage factices (41, 41') sont disposées dans des régions de pixels configurées pour recevoir de la lumière bleue et les lignes de câblage factices (41, 41') ne sont pas disposées dans des régions de pixels configurées pour recevoir de la lumière verte, de la lumière rouge et de la lumière blanche.
     
    5. Capteur d'imagerie à semi-conducteurs éclairé par l'arrière selon la revendication 1, dans lequel les lignes de câblage factices (41, 41') de la couche la plus haute de la couche de câblage disposées dans des régions de pixels configurées pour recevoir de la lumière ont une largeur qui est inférieure à une largeur d'un pixel de la couche d'éléments d'imagerie.
     
    6. Capteur d'imagerie à semi-conducteurs éclairé par l'arrière selon la revendication 1, comportant en outre une couche de polissage (21a) située au-dessus de la couche de câblage (21), la surface supérieure de la couche de polissage (21a) étant plate.
     
    7. Appareil électronique comprenant un capteur d'imagerie à semi-conducteurs éclairé par l'arrière tel que défini dans l'une quelconque des revendications précédentes.
     
    8. Procédé de fabrication d'un capteur d'imagerie à semi-conducteurs éclairé par l'arrière, le procédé comprenant :

    la formation d'une couche d'éléments d'imagerie (22) entre un substrat (23) et une couche de câblage (21) ; et

    la formation d'une pluralité de lignes de câblage (31, 41, 41') au niveau d'une couche supérieure de la couche de câblage (31), les lignes de câblage (31, 41, 41') comprenant des lignes de câblage (31) qui sont reliées électriquement et des lignes de câblage factices (41, 41') qui ne sont pas reliées électriquement, les lignes de câblage factices (41, 41') de la couche de câblage étant disposées dans des régions de pixels (Z) au-dessous d'un ou plusieurs éléments d'imagerie configurées pour recevoir de la lumière ayant une longueur d'onde inférieure à une longueur d'onde prédéterminée, la longueur d'onde prédéterminée étant n'importe quelle longueur d'onde de 400 à 600 nm, les lignes de câblage (31) qui sont reliées électriquement étant disposées dans une partie périphérique des régions de pixels (Z), les lignes de câblage factices (41, 41') et les lignes de câblage (31) qui sont reliées électriquement étant situées dans une couche la plus haute de la couche de câblage,

    la plus haute faisant référence à la direction dans laquelle le substrat (23), la couche d'éléments d'imagerie (22) et la couche de câblage (21) sont empilés les uns sur les autres, les lignes de câblage factices (41, 41') de la couche la plus haute de la couche de câblage étant réparties à l'intérieur de la couche de câblage de telle sorte qu'une densité de câblage est égale, et les lignes de câblage factices (41, 41') de la couche de câblage (21) n'étant pas disposées dans des régions de pixels (Z) configurées pour recevoir de la lumière ayant une longueur d'onde supérieure à la longueur d'onde prédéterminée.


     
    9. Procédé de fabrication selon la revendication 8, comportant en outre :
    le polissage d'un film de polissage (21a) situé sur une partie supérieure de la couche de câblage (21), et ensuite, la fixation du film de polissage poli à un substrat de support (24).
     




    Drawing


















































    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description