(19)
(11)EP 3 035 536 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
29.04.2020 Bulletin 2020/18

(21)Application number: 14199426.9

(22)Date of filing:  19.12.2014
(51)International Patent Classification (IPC): 
H03L 7/091(2006.01)

(54)

An ADPLL having a TDC circuit with a dynamically adjustable offset delay

ADPLL mit einer TDC-Schaltung mit einer dynamisch anpassbaren Offset-Verzögerung

ADPLL doté d'un circuit convertisseur temps-numérique (TDC) ayant un retard de décalage dynamiquement réglable


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(43)Date of publication of application:
22.06.2016 Bulletin 2016/25

(73)Proprietor: Stichting IMEC Nederland
5656 AE Eindhoven (NL)

(72)Inventor:
  • Liu, Yao-Hong
    B-3001 Leuven (BE)

(74)Representative: Gevers Patents 
Intellectual Property House Holidaystraat 5
1831 Diegem
1831 Diegem (BE)


(56)References cited: : 
US-A1- 2009 096 535
US-B1- 8 570 082
  
  • JINGCHENG ZHUANG ET AL: "A low-power all-digital PLL architecture based on phase prediction", ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2012 19TH IEEE INTERNATIONAL CONFERENCE ON, IEEE, 9 December 2012 (2012-12-09), pages 797-800, XP032331578, DOI: 10.1109/ICECS.2012.6463539 ISBN: 978-1-4673-1261-5
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

Technical field



[0001] The present disclosure relates to an All-Digital-Phase-Locked-Loop (ADPLL) and more specifically to an ADPLL having a TDC with a dynamically adjustable offset delay.

Background art



[0002] Ultra-low-power (ULP) transceivers enable short-range networks of autonomous sensor nodes for wireless personal area network (WPAN) applications, e.g., Bluetooth Smart and Zigbee. RF Phase-Locked-Loops (PLL) for frequency synthesis and modulation consume a significant share of the total transceiver power, making sub-mW PLLs key to realize ULP WPAN radios. Compared to analog PLLs, all-digital PLLs (ADPLLs) are preferred in nanoscale CMOS as they offer benefit from smaller area overhead, programmability, capability of extensive self-calibrations, and easy portability. However, analog PLLs currently still dominate the field of ULP WPAN radios, since the time-to-digital-converter (TDC) of an ADPLL has traditionally been power hungry.

[0003] A known approach for minimising the power consumption of a TDC circuit in the ADPLL is to reduce the activity of the TDC so that it operates only within a predetermined observation window. Such a TDC is known from J. Zhuang, et al., "A Low-Power All-Digital PLL Architecture Based on Phase Prediction," ICECS, 2012, where a 2.1-2.7GHz fractional-N ADPLL for WPAN applications DTC-assisted snapshot TDC is presented. In this implementation TDC snapshotting is implemented to reduce the sampling rate of the TDC from FCKVD2 to FREF. A Digital-to-Time Converter (DTC) is provided for reducing the detection range of the TDC detection range to less than 1/10 of the DCO output signal period, leading to a significant power reduction. The accumulated fractional part of the frequency command word, FCWfrac, controls the DTC to delay the reference signal FREF such that the delayed reference clock FREFdly is almost aligned with CKVD2, once the loop is locked. FREFdly also triggers the snapshot to catch the first CKVD2 edge so that only one CKVD2 edge, CKVD2S, per reference period is fed to the TDC. By capturing only one edge, the snapshot technique guarantees that the TDC has the minimum activity and consume minimum power. Moreover, the snapshotting also minimize the supply switch noise during TDC operation. A reduced-range TDC operating at the reference frequency (32MHz) then compares the edge of CKVD2S with FREFdly to provide the fractional phase error, PHEF. This approach reduces both sampling speed and detection range of TDC, leading to around 200x power reduction. In the snapshot TDC, the narrow observation window is opened by the CKVD2s, which acts as a TDC enable signal, after the rising edge of FREFdly. Since the TDC captures only the first rising edge of the variable clock, CDVD2, after the rising edge of FREFdly, the timing of opening TDC observation window is critical. In order to compensate for the delay added by the snapshot circuit, a TDC "offset delay" (T1) is added between the rising edge of FREFdly and the TDC observation window. However, the TDC and snapshot circuit offset delays cannot be easily estimated due to parasitic or slow logic transitions introduced in the layout during the design phase or during operation. As a result, due to the mismatch between the TDC and snapshot offset delays the TDC may be activated outside of the predetermined observation window, thereby causing the TDC to generate an erroneous output code, resulting in the degradation of the overall PLL performance, e.g. by introducing unwanted phase noise, and sometimes may even lead to an unstable PLL locking.

[0004] US8570082 discloses an ADPLL that can account for variations in PVT conditions. The ADPLL has a controllable time-to-digital converter (TDC) arranged for determining a phase difference between a frequency reference signal and a local oscillator clock signal and for generating a phase error therefrom. A digitally controlled oscillator (DCO) varies a phase of the local oscillator clock signal based upon the phase error. A calibration unit determines an effect of variations in PVT conditions based upon the phase error and generates a TDC tuning word that adjusts a delay introduced by one or more of the plurality of variable delay elements to account for the variations in PVT conditions.

[0005] US20090096535 discloses a system for decreasing errors within an analog phase-locked loop, using an all-digital phase-locked loop (ADPLL) with only digital components and digital operations. By modulating certain parameters within the ADPLL by following an all-pass frequency response, a loop gain of the ADPLL may be modulated, and an available bandwidth of the ADPLL is broadened.

Summary of the disclosure



[0006] It is an aim of the present disclosure to provide an ADPLL system which does not show the drawbacks of the prior art.

[0007] This aim is achieved according to the disclosure with the ADPLL system showing the technical characteristics of the first independent claim.

[0008] More in particular, according to embodiments of the present disclosure an All-Digital-Phase-Locked-Loop (ADPLL) comprising a Digitally Controlled Oscillator, DCO, arranged for generating a DCO output signal, and a feedback loop comprising a set of components for controlling the DCO. The components provided in the feedback loop comprises a Time-to-Digital Converter, TDC, provided for performing phase detection within a predetermined observation window, the TDC being arranged for receiving at least a reference signal having a first offset delay and an enable signal having a second offset delay and defining the predetermined observation window. The TDC is arranged for generating a TDC output code indicative of the phase difference between the reference signal and the enable signal measured within the predetermined observation window. A subset of the components in the feedback loop are arranged for generating the enable signal from the DCO output signal, such that the enable signal contains a transition edge derived from the DCO output signal and is arranged for activating the TDC so as to measure the phase difference between the reference signal and the enable signal within the predetermined observation window. The set of components of the feedback loop comprises an offset calibration system, connected to the TDC output, which when activated is arranged for evaluating the difference between the first and second offset delay values by monitoring the TDC output code generated over a predetermined period of time and for adjusting said difference to position the predetermined observation window with respect to the reference signal.

[0009] It has been found that by providing a calibration system which when activated is arranged for evaluating the difference between the first and second offset delay values, the difference between the first and second offset delay values may be dynamically adjusted so that the TDC is activated within the predetermined observation window. By processing the TDC output code, which is indicative of the phase difference between the reference and the enable signal, it is possible to determine whether the reference signal arrived within the predetermined time difference from the enable signal. As a result based on the TDC output code generated over a predetermined period of time the delay difference between the first and second offset delay values may be adjusted to position the TDC observation window with respect to the reference signal, thereby ensuring that the TDC is operated within the predetermined observation window leading to a higher performing ADPLL.

[0010] According to embodiments of the present disclosure, the calibration system is provided with an offset calibration unit, which is connected to the TDC output. The calibration unit is arranged for performing the evaluation of the difference between the first and second offset delay values and accordingly generating a delay adjustment control signal. The calibration system may further be provided with a variable delay unit, which is connected to the offset calibration unit and arranged for adjusting the first offset delay on the basis of the delay adjustment control signal.

[0011] It has been found that by providing a calibration unit arranged for generating based on the TDC output code a delay adjustment control signal, which is used for controlling a variable delay unit, the first offset delay may be dynamically adjusted so that the reference signal arrives within the TDC observation window. In this way, offset delay adjustments may be effected without any external intervention purely based on the TDC output code. The delay adjustment control signal may be indicative of an offset delay adjustment value to be effected by the variable delay unit. The variable delay unit may be a digitally-controlled programmable variable delay arranged for adjusting the delay of the reference signal based on the delay adjustment control signal generated by the calibration unit, which may be indicative of the value by which the first offset delay needs to be adjusted so that the reference signal arrives within the predetermined observation window. In this way, any variations introduced in the first and second offset delay values may be compensated, thereby ensuring that the TDC operates in the predetermined observation window. As a result, with the system of the present disclosure any variations in the first and second offset delays may be dynamically compensated, thereby ensuring the correct functionality of the TDC, leading to a higher performing ADPLL.

[0012] According to embodiments of the present disclosure, the difference between the first and second offset delay values is adjusted in such a way that a transition edge of said reference signal is positioned substantially in the middle of said predetermined observation window.. By positioning the reference signal in the middle of the predetermined observation window it is ensured that the TDC is provided with sufficient margin to both previous and the proceeding DCO output signal cycles.

[0013] According to embodiments of the present disclosure, the calibration unit is arranged for evaluating the difference between the first and second offset delay values by accumulating the number of ones and zeros generated by the TDC output code over the predetermined period of time. For example, the calibration unit may be provided with at least one counter for counting the number of ones and zeros generated by the TDC output code over the predetermined period of time. For example, the counter may be arranged for the counting the number of ones and zeros generated by the Most Significant Bit (MSB) of the TDC output code. It has been found that by accumulating the number of ones and zeros in the TDC output code generated over a predetermined period of time provides a simple and effective way of determining whether the TDC is operated within the predetermined observation window. This is because the number of ones and zeros in the TDC output code generated over a predetermined period of time is directly related to the phase difference between the reference signal and the enable signal and vice versa. As a result, by observing the distribution of the ones and zeros in the TDC output code over the predetermined period of time the phase difference between the reference and enable signal may be easily evaluated.

[0014] According to embodiments of the present disclosure, the ADPLL may comprise a TDC offset control unit arranged for generating the delay adjustment control signal based on the accumulated number of ones and zeros in the TDC output code. In this way, the first offset delay of the reference signal may be dynamically adjusted without any external intervention. For example, the TDC offset control unit may be arranged for increasing the offset delay of the reference signal when the number of zeros is greater than the number of ones in the TDC output code. The TDC offset control unit may also be arranged for decreasing the offset delay of the reference signal when the number of ones is greater than the number of zeros.

Brief description of the drawings



[0015] The disclosure will be further elucidated by means of the following description and the appended figures.

Figure 1 shows a prior art ADPLL circuit.

Figure 2 shows a representation of the offset delays in an ADPLL TDC circuit.

Figure 3(a) and 3(b) shows a representation of TDC transfer curve when the TDC operates within the predetermined observation window.

Figures 4(a) to 4(b) and 5(a) to 5(b) show representations of the TDC transfer curve when it operates outside of the predetermined observation window.

Figure 6 shows a representation of a TDC according to embodiments of the present disclosure.

Figure 7 shows an example of an ADPLL phase locking procedure.


Detailed description of preferred embodiments



[0016] The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not necessarily correspond to actual reductions to practice of the disclosure.

[0017] Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. The terms are interchangeable under appropriate circumstances and the embodiments of the disclosure can operate in other sequences than described or illustrated herein.

[0018] Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. The terms so used are interchangeable under appropriate circumstances and the embodiments of the disclosure described herein can operate in other orientations than described or illustrated herein.

[0019] Furthermore, the various embodiments, although referred to as "preferred" are to be construed as exemplary manners in which the disclosure may be implemented rather than as limiting the scope of the disclosure.

[0020] The term "comprising", used in the claims, should not be interpreted as being restricted to the elements or steps listed thereafter; it does not exclude other elements or steps. It needs to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising A and B" should not be limited to devices consisting only of components A and B, rather with respect to the present disclosure, the only enumerated components of the device are A and B, and further the claim should be interpreted as including equivalents of those components.

[0021] Embodiments of the present disclosure will be explained with reference to the examples shown in figures 1 to 7.

[0022] Figure 1 shows an example of an ADPLL circuit 10, which is arranged for generating using a Digital Control Oscillator (DCO) 11 a DCO output signal, e.g. CKV, having a predetermined frequency. The ADPLL is arranged for receiving a reference frequency signal, e.g. FREF, and generate based on a Frequency Code Word (FCW), which may be multiple of the reference signal, the desired DCO output signal, e.g. CKV. In order to ensure that the DCO is maintained stable within the desired frequency range, the ADPLL may be provided with a feedback loop comprising a set of components for controlling the DCO. The components in the feedback loop comprise components for phase detection, which may be done in stages by means of for example a subset for detecting a coarse part of the phase e.g. using a phase incrementor for detecting the integer part of the phase, and a subset for detecting a fine part of the phase, for example a subset for detecting the fractional part of the phase. One of such components for detecting a fine part or a fractional part of the phase may be a Time-to-Digital Converter (TDC) 15 arranged for performing phase detection within a predetermined observation window. The TDC 15 may be arranged for receiving at least a reference signal having a first offset delay and an enable signal having a second offset delay and defining the predetermined observation window. The TDC 15 may be arranged for generating a TDC output code indicative of the phase difference between the reference signal and the enable signal measured within the predetermined observation window. For example, the TDC 15 may be arranged for measuring the fractional phase differences between the significant edge of the enable signal and the reference signal and accordingly generate a TDC output indicative of the fractional phase error (PHEf). The TDC 15 may be arranged for performing phase detection between a reference signal and an enable signal derived from the DCO output signal, e.g. CKV, within a predetermined observation window. To generate the enable signal, the feedback loop may be provided with a first subset of components arranged for generating the enable signal based on a reduced rate DCO output signal, e.g. CKVD2, generated from a multiphase divider 13 such that the enable signal contains a transition edge derived from the DCO output signal. The enable signal generated may be arranged for activating the TDC 15 so as to measure the phase difference between the reference signal and the enable signal within the predetermined observation window. For example, the first subset of components may comprise a snapshotting circuit 14, which may be triggered by the reference signal for generating an enable signal representing at least one edge of the reduced rate DCO signal, e.g. CKVD2. In this way, only one edge of the reduced rate DCO signal, e.g. may be fed to the TDC per reference period, thereby reducing the activity of the TDC 15 leading to a reduced power consumption. By using the reference signal, e.g. FREF, for generating the enable signal which in turns activates the TDC 15, the sampling rate of the TDC 15 may be reduced to the frequency rate of the reference signal. In order to reduce the dynamic range of the TDC 15, a second subset of components may be provided, which may be arranged for positioning the reference signal within the predetermined observation window of the TDC. For example, this may be achieved by providing a Digital-to-Time Converter (DTC) 16, which may be arranged for delaying the reference signal, e.g., FREFdly, based on a phase setting control signal generated on the basis of FCW. In this way, a reduced range TDC 15 may be provided for performing the fractional phase detection, thereby reducing the area overhead of the ADPLL 10.

[0023] In order to ensure that the reference signal, e.g., FREFdly, arrives within the predetermined observation window, an offset delay (T1) may be provided in the TDC 15 to compensate for the offset delay (T2) introduced by the first subset of components in the feedback loop arranged for generating the enable signal, e.g. the snapshot circuit, as shown in figure 2. Therefore, the reference and enable signal are provided with a first (T1), and second (T2) offset delay. In this way, the reference and enable signal are sampled by the TDC 15 within the TDC observation window as shown in figure 3a. The first offset delay, e.g. TDC offset delay (T1) may be chosen to be around half the DCO output signal period, e.g. half the CLVD2 period, more than the second offset delay e.g. snapshot delay T2, such that the TDC observation window is placed at the centre of the TDC transfer curve so as to be provided with sufficient margin to both previous and the proceeding DCO output signal cycles, as show in figure 3b.

[0024] However, due to process variation, noise or other parasitic introduced in the layout of the ADPLL or during operation, the TDC offset delay (T1) and the snapshot offset delay (T2) may be different from the desired values. As a result the TDC 15 may operate outside of the predetermined observation window. Figure 4a shows the case when the TDC offset delay is too short. In this case, the TDC offset delay T1 is not sufficient to compensate the delay introduced by the snapshot circuit T2. As a result, the snapshot circuit 14 will have more chances to miss the expected CKVD2 edge and capture the next CKVD2 edge. Therefore, the probability of the TDC output code having more ones than zeros will be higher than expected as shown in figure 4b. This behaviour may be considered to be equivalent to the TDC observation window being placed close to the previous detection CKVD2 cycle. Similarly in figure 5a, the TDC offset delay (T1) may be longer than the snapshot circuit delay (T2) resulting in the snapshot circuit 14 to capture the previous CKVD2 edge instead of the expected edge. As a result, the TDC output code will have a higher probability to generate more zeros than ones, as shown in figure 5b.

[0025] According to embodiments of the present disclosure, in order to compensate for variations in the first and second offset delays, the TDC circuit 15 may be provided with an offset calibration system, as shown in figure 6. The offset calibration system, may be connected to the TDC output, which when activated may be arranged for evaluating the difference between the first and second offset delay values by monitoring the TDC output code generated over a predetermined period of time. Based on the TDC output code the calibration system may be arranged for adjusting the difference between the first (T1) and second (T2) offset delay values so as to position the predetermined observation window with respect to the reference signal. As a result, any variations in the first (T1) and second (T2) offset delay values may be compensated, thereby ensuring that the reference and enable signals are sampled by the TDC within the predetermined observation window. It has been found that by providing a calibration system which when activated is arranged for evaluating the difference between the first and second offset delay values, the difference between the first and second offset delay values may be dynamically adjusted so that the TDC is activated within the predetermined observation window. By processing the TDC output code, which is indicative of the phase difference between the reference signal and the enable signal, it is possible to determine whether the reference signal arrived within the predetermined time difference from the enable signal. As a result based on the TDC output code generated over a predetermined period of time the delay difference between the first and second offset delay values may be adjusted to position the TDC observation window with respect to the reference signal.

[0026] According to embodiments of the present disclosure, the calibration system may comprise an offset calibration unit 152, as shown in figure 6, connected to the TDC output and arranged for evaluating the difference between the first (T1) and second (T2) offset delays values and accordingly generate a delay adjustment control signal. The calibration system may further comprise a variable delay unit 153 connected to the offset calibration unit 152 and arranged for adjusting the first offset delay on the basis of the delay adjustment control signal. The variable delay unit may be part of the TDC 15. It has been found that by providing a calibration unit 152 arranged for generating based on the TDC output code a delay adjustment control signal, which is used for controlling a variable delay unit 153, the first offset delay may be dynamically adjusted such that the TDC observation window is placed at the centre of the TDC transfer curve. For example, the calibration system may be arranged for adjusting the difference between the first (T1) and second (T2) offset delay values in such a way that a transition edge of said reference signal is positioned substantially in the middle of said predetermined observation window, e.g by positioning the transition edge of the reference signal in the middle of the TDC transfer function. By providing a calibration system, the offset delay adjustments may be effected without any external intervention purely based on the TDC output code. The delay adjustment control signal may be indicative of an offset delay adjustment value to be effected by the variable delay unit. For example, the variable delay unit 153 may be a digitally-controlled programmable variable delay arranged for adjusting the delay of the reference signal, FREFdly,, based on the delay adjustment control signal generated by the calibration unit 152, which may be indicative of the value by which the first offset delay (T1) needs to be adjusted so that the reference signal arrives within the predetermined observation window. In this way, any variations introduced in the first and second offset delay values may be compensated, thereby ensuring that the TDC operates in the predetermined observation window. As a result, with the system of the present disclosure any variations in the first (T1) and second offset (T2) delay values may be dynamically adjusted, thereby ensuring the correct functionality of the TDC, which may lead to a higher performing ADPLL.

[0027] According to embodiments of the present disclosure, the calibration unit may be further arranged for adjusting the second offset T2 in a similar manner to that described above with regards to the adjustments effected to the first offset. For example, the calibration unit may be arranged for adjusting based on the TDC output the second offset T2 by means of a variable delay unit. Furthermore, the calibration unit may be arranged for adjusting on the basis of the TDC output both the first and second offset delays T1 and T2 by means of at least one variable delay unit.According to embodiments of the present disclosure, the calibration unit 152 may be arranged for evaluating the difference between the first and second offset delay values by accumulating the number of ones and zeros in the TDC output code generated over a predetermined period of time. For example, this may be achieved by providing at least one counter 157, which is arranged for counting the number of ones and zeros in the TDC output code. For example, the counter 157 may be connected to the Most Significant Bit (MSB) of the TDC output code, and arranged for counting the number of ones and zeros generated by the MSB over a predetermined period of time.

[0028] According to embodiments of the present disclosure, a calibration unit 152 may be provided with a TDC offset control unit 156 arranged for generating the delay adjustment control signal, which is used for controlling the variable delay unit 153. The TDC offset control unit 156 may be arranged for generating based on the value of the counter, a delay adjustment control signal for adjusting the first offset delay value (T1). For example, the TDC offset control unit 156 may be arranged for increasing the offset delay of the reference signal when the number of zeros is greater than the number of ones in the TDC output code. Alternative, the TDC offset control unit 156 may be arranged for decreasing the offset delay of the reference signal when the number of ones is greater than the number of zeros.

[0029] According to embodiments of the present disclosure, the TDC 15 may be a flash TDC arranged for generating a TDC output code indicative of the phase difference between the reference signal and the enable signal measured within the predetermined observation window. However, other TDC architecture know in the art may be employed. The TDC 15, as shown in figure 6, may be provided with a number of delay stages 154, each arranged for comparing the reference signal to the enable signal.

[0030] According to embodiments of the present disclosure, the calibration system may be activated off-line, i.e. when the ADPLL is not in operation, so as to calibrate the first (T1) and second (T2) offset delays before operating the ADPLL. According to alternative embodiments, the calibration system may be activated on-line, i.e. before every phase dictation by the TDC. In this way, any variations introduced in the first and second offset delay values due to noise or temperature during the operation of the ADPLL may be compensated.

[0031] Figure 7 shows an example of measuring the TDC transfer function during ADPLL phase locking. Phase locking in PLLs has two phases. First is frequency acquisition which bring the variable clock frequency close to the targeted frequency. Once the variable clock (CKVD2) is close enough to the targeted frequency, the PLL may move to the second phase, phase tracking, to align the phases between variable and reference clocks. If the TDC, which acts as a phase difference digitizer, gives an output approaching zero, then it means the phases of the two clocks are aligned. During the frequency acquisition phase, the phase difference between the reference phase, e.g., FREFdly, and variable clock, e.g., CKVD2, continuously rotates, and the TDC gives an output which continuously sweeps all of the codes, as shown in Fig. 7. This behaviour may be explained by the fact that the phase difference between the reference phase and variable phase is continuously rotating because of the frequency difference between the variable clock and targeted output. Hence, by reading out the TDC output during the frequency acquisition phase, the TDC transfer curve can be directly measured.


Claims

1. An All-Digital-Phase-Locked-Loop (10), ADPLL, comprising a Digitally Controlled Oscillator (11), DCO, arranged for generating a DCO output signal from a Frequency Code Word, FCW, and a feedback loop comprising a set of components for controlling the DCO (11), the ADPLL being arranged to receive a reference frequency signal (FREF), the components comprising:

a Time-to-Digital Converter (15), TDC, provided for performing phase detection within a predetermined observation window, the TDC (15) being arranged for receiving at least a delayed reference signal (FREFdly) having a first offset delay and an enable signal (CKVD2S) having a second offset delay and defining the predetermined observation window, the TDC (15) being arranged for generating a TDC output code (TDCout) indicative of the phase difference between the delayed reference signal (FREFdly) and the enable signal (CKVD2S) measured within the predetermined observation window; and

a subset of components (12, 13, 14) arranged for generating the enable signal (CKVDS2s) from the DCO output signal, such that the enable signal (CKVDS2s) contains a transition edge derived from the DCO output signal and is arranged for activating the TDC (15) so as to measure the phase difference between the delayed reference signal (FREFdly) and the enable signal (CKVDS2s) within the predetermined observation window;

characterised in that the set of components of the feedback loop comprises an offset calibration system (152), connected to the TDC output (TDCout), which when activated is arranged for evaluating the difference between the first and second offset delay values by monitoring the TDC output code (TDCout) generated over a predetermined period of time and for adjusting said difference to position the predetermined observation window with respect to the delayed reference signal (FREFdly).


 
2. The ADPLL (10) of claim 1, wherein the offset calibration system comprises an offset calibration unit (152), connected to the TDC output and arranged for performing said evaluation and accordingly generating a delay adjustment control signal, and a variable delay unit (153) connected to the offset calibration unit (152) and arranged for adjusting the first offset delay on the basis of the delay adjustment control signal.
 
3. The ADPLL (10) of claim 2, wherein the variable delay unit (153) is part of the TDC (15).
 
4. The ADPLL (10) of any one of the claims 1-3, wherein the offset calibration system is arranged for adjusting said difference in such a way that a transition edge of said reference signal is positioned substantially in the middle of said predetermined observation window.
 
5. The ADPLL (10) of any one of the claims 1-3, wherein the offset calibration system is arranged for adjusting said difference in such a way that a transition edge of said reference signal is positioned substantially in the middle of the TDC transfer curve.
 
6. The ADPLL (10) of any one of the preceding claims, wherein the calibration system is arranged for evaluating the difference between the first and second offset delay values by counting the number of ones and zeros generated by the Most Significant Bit of the TDC output code.
 
7. The ADPLL of claim 6, wherein the offset calibration system comprises a TDC offset control unit (156) arranged for increasing the first offset delay when the number of zeros is greater than the number of ones in the TDC output code.
 
8. The ADPLL (10) of claim 6 or 7, wherein the TDC offset control unit (156) is arranged for decreasing the first offset delay when the number of ones is greater than the number of zeros.
 
9. The ADPLL (10) of any one of the preceding claims, wherein the feedback loop comprises components arranged for detecting a coarse part of the phase and components, among which the TDC (15), for detecting a fine part of the phase.
 
10. The ADPLL (10) of any one of the preceding claims, wherein the feedback loop comprises components arranged for detecting an integer part of the phase and components, among which the TDC (15), for detecting a fractional part of the phase.
 
11. The ADPLL (10) of any one of the preceding claims, wherein the TDC (15) is a flash TDC.
 
12. A method for operating an All-Digital-Phase-Locked-Loop (10), ADPLL, comprising a Digitally Controlled Oscillator (11), DCO, arranged for generating a DCO output signal, and a feedback loop comprising a set of components for controlling the DCO (11), the ADPLL being arranged to receive a reference frequency signal (FREF), the method comprising the steps of:

a) activating a Time-to-Digital Converter (15), TDC, arranged for performing phase detection within a predetermined observation window, the TDC (15) being arranged for receiving at least a delayed reference signal (FREFdly) having a first offset delay and an enable signal (CKVD2S) having a second offset delay and defining the predetermined observation window, wherein the step of activating the TDC (15) comprises the steps of :

a1) providing a delayed reference signal (FREFdly) to the TDC (15), and

a2) generating by means of a subset of components (12, 13, 14) the enable signal (CKVD2s) from the DCO output signal, such that the enable signal contains (CKVD2s) a transition edge derived from the DCO output signal and is arranged for activating the TDC (15) so as to measure the phase difference between the delayed reference signal (FREFdly) and the enable signal (CKVD2s) within the predetermined observation window;

b) generating by means of the TDC (15) a TDC output code (TDCout) indicative of the phase difference between the delayed reference signal (FREFdly) and the enable signal (CKVD2s) measured within the predetermined observation window; and

c) performing an offset delay calibration step by means of a calibration system (152) connected to the TDC output,

characterised in that the calibration step comprising the steps of:

c1) evaluating the difference between the first and second offset delay values by monitoring the TDC output code (TDCout) generated over a predetermined period of time, and

c2) adjusting said difference to position the predetermined observation window with respect to the delayed reference signal (FREFdly).


 
13. The method of claim 12, wherein the offset delay calibration step comprises the steps of:
generating a delay adjustment control signal based on the difference between the first and second offset delay values detected during the evaluation step, and applying the delay adjustment control signal to a variable delay unit (153) to adjust the first offset delay.
 
14. The method of claim 12 or 13, wherein the offset delay calibration step is performed off-line.
 
15. The method of claim 12 or 13, wherein the offset calibration step performed is performed on-line during a frequency acquisition stage before activating the TDC (15) for phase locking.
 


Ansprüche

1. Eine vollständig digitale Phasenregelschleife (10), ADPLL, welche einen digital gesteuerten Oszillator (11), DCO, umfasst, angeordnet, um ein DCO-Ausgangssignal aus einem Frequenz-Codewort, FCW, und eine Rückkopplungsschleife zu erzeugen, welche einen Satz von Komponenten zur Steuerung des DCO (11) umfasst, wobei die ADPLL angeordnet ist, um ein Referenz-Frequenzsignal (FREF) zu empfangen, wobei die Komponenten Folgendes umfassen:

einen Time-to-Digital Converter (15), TDC, bereitgestellt, um innerhalb eines vorgegebenen Beobachtungsfensters eine Phasenerkennung durchzuführen, wobei der TDC (15) angeordnet ist, um zumindest ein verzögertes Referenzsignal (FREFdly) zu empfangen, welches eine erste Offset-Verzögerung und ein Freigabesignal (CKVD2s) mit einer zweiten Offset-Verzögerung hat und ein vorgegebenes Beobachtungsfenster definiert, wobei der TDC (15) angeordnet ist, um einen TDC-Ausgangscode (TDCout) zu erzeugen, welcher den Phasenunterschied zwischen dem verzögerten Referenzsignal (FREFdly) und dem Freigabesignal (CKVD2s) anzeigt, der innerhalb des vorgegebenen Beobachtungsfensters gemessen wird; und

einen Teilsatz von Komponenten (12, 13, 14), angeordnet, um das Freigabesignal (CKVDS2s) aus dem DCO-Ausgangssignal zu erzeugen, sodass das Freigabesignal (CKVDS2s) einen Flankenwechsel abgeleitet vom DCO-Ausgangssignal enthält und angeordnet ist, um den TDC (15) zu aktivieren, um den Phasenunterschied zwischen dem verzögerten Referenzsignal (FREFdly) und dem Freigabesignal (CKVDS2s) innerhalb des vorgegebenen Beobachtungsfensters zu messen;

dadurch gekennzeichnet, dass der Satz von Komponenten der Rückkopplungsschleife ein Offset-Kalibriersystem (152) umfasst, verbunden mit dem TDC-Ausgang (TDCout), der, wenn aktiviert, angeordnet ist, um die Differenz zwischen dem ersten und dem zweiten Offset-Verzögerungswert durch Überwachen des TDC-Ausgangscodes (TDCout), erzeugt über einen vorgegebenen Zeitraum, zu beurteilen und um die erwähnte Differenz anzupassen, um das vorgegebene Beobachtungsfenster in Bezug zum verzögerten Referenzsignal (FREFdly) zu positionieren.


 
2. Die ADPLL (10) nach Anspruch 1, wobei das Offset-Kalibriersystem eine Offset-Kalibriereinheit (152) umfasst, verbunden mit dem TDC-Ausgang und angeordnet, um die erwähnte Beurteilung durchzuführen und dieser entsprechend ein Verzögerungsanpassungs-Steuersignal zu erzeugen, und eine variable Verzögerungseinheit (153), verbunden mit der Offset-Kalibriereinheit (152) und angeordnet, um die erste Offset-Verzögerung auf Grundlage des Verzögerungsanpassungs-Steuersignals anzupassen.
 
3. Die ADPLL (10) nach Anspruch 2, wobei die variable Verzögerungseinheit (153) Teil des TDC (15) ist.
 
4. Die ADPLL (10) nach irgendeinem der Ansprüche 1 bis 3, wobei das Offset-Kalibriersystem angeordnet ist, um die erwähnte Differenz so anzupassen, dass ein Flankenwechsel des erwähnten Referenzsignals im Wesentlichen in der Mitte des erwähnten vorgegebenen Beobachtungsfensters positioniert ist.
 
5. Die ADPLL (10) nach irgendeinem der Ansprüche 1 bis 3, wobei das Offset-Kalibriersystem angeordnet ist, um die erwähnte Differenz so anzupassen, dass ein Flankenwechsel des erwähnten Referenzsignals im Wesentlichen in der Mitte der TDC-Übertragungskennlinie positioniert ist.
 
6. Die ADPLL (10) nach irgendeinem der vorigen Ansprüche, wobei das Kalibriersystem angeordnet ist, um die Differenz zwischen dem ersten und dem zweiten Offset-Verzögerungswert zu beurteilen, indem die Anzahl der Einsen und Nullen, erzeugt durch das höchstwertige Bit des TDC-Ausgangscodes, gezählt wird.
 
7. Die ADPLL nach Anspruch 6, wobei das Offset-Kalibriersystem eine TDC-Offset-Steuereinheit (156) umfasst, angeordnet, um die erste Offset-Verzögerung zu erhöhen, wenn die Anzahl von Nullen größer ist als die Anzahl von Einsen im TDC-Ausgangscode.
 
8. Die ADPLL (10) nach Anspruch 6 oder 7, wobei die TDC-Offset-Steuereinheit (156) angeordnet ist, um die erste Offset-Verzögerung zu senken, wenn die Anzahl von Einsen größer ist als die Anzahl von Nullen.
 
9. Die ADPLL (10) nach irgendeinem der vorigen Ansprüche, wobei die Rückkopplungsschleife Komponenten umfasst, angeordnet, um einen groben Teil der Phase zu erkennen, und Komponenten, darunter der TDC (15), um einen feinen Teil der Phase zu erkennen.
 
10. Die ADPLL (10) nach irgendeinem der vorigen Ansprüche, wobei die Rückkopplungsschleife Komponenten umfasst, angeordnet, um einen ganzzahligen Teil der Phase zu erkennen, und Komponenten, darunter der TDC (15), um einen Bruchteil der Phase zu erkennen.
 
11. Die ADPLL (10) nach irgendeinem der vorigen Ansprüche, wobei der TDC (15) ein Flash-TDC ist.
 
12. Ein Verfahren zum Betrieb einer vollständig digitalen Phasenregelschleife (10), ADPLL, welches einen digital gesteuerten Oszillator (11), DCO, umfasst, angeordnet, um ein DCO-Ausgangssignal und eine Rückkopplungsschleife zu erzeugen, welche einen Satz von Komponenten zur Steuerung des DCO (11) umfasst, wobei die ADPLL angeordnet ist, um ein Referenz-Frequenzsignal (FREF) zu empfangen, wobei das Verfahren folgende Schritte umfasst:

a) Aktivieren eines Time-to-Digital Converters (15), TDC, angeordnet, um Phasenerkennung innerhalb eines vorgegebenen Beobachtungsfensters durchzuführen, wobei der TDC (15) angeordnet ist, um zumindest ein verzögertes Referenzsignal (FREFdly) mit einer ersten Offset-Verzögerung und ein Freigabesignal (CKVD2s) mit einer zweiten Offset-Verzögerung zu empfangen und das vorgegebene Beobachtungsfenster zu definieren, wobei der Schritt des Aktivierens des TDC (15) folgende Schritte umfasst:

a1) Bereitstellen eines verzögerten Referenzsignals (FREFdly) für den TDC (15), und

a2) Erzeugen mittels eines Teilsatzes von Komponenten (12, 13, 14) des Freigabesignals (CKVD2s) aus dem DCO-Ausgangssignal, sodass das Freigabesignal (CKVD2s) einen Flankenwechsel abgeleitet vom DCO-Ausgangssignal enthält und angeordnet ist, um den TDC (15) zu aktivieren, um den Phasenunterschied zwischen dem verzögerten Referenzsignal (FREFdly) und dem Freigabesignal (CKVD2s) innerhalb des vorgegebenen Beobachtungsfensters zu messen;

b) Erzeugen mittels des TDC (15) eines TDC-Ausgangscodes (TDCout), welcher den Phasenunterschied zwischen dem verzögerten Referenzsignal (FREFdly) und dem Freigabesignal (CKVD2s), gemessen innerhalb des vorgegebenen Beobachtungsfensters, anzeigt; und

c) Durchführen eines Schrittes des Kalibrierens der Offset-Verzögerung mittels eines Kalibriersystems (152) verbunden mit dem TDC-Ausgang,

dadurch gekennzeichnet, dass der Schritt des Kalibrierens folgende Schritte umfasst:

c1) Beurteilen der Differenz zwischen dem ersten und dem zweiten Offset-Verzögerungswert durch Überwachen des TDC-Ausgangscodes (TDCout), erzeugt über einen vorgegebenen Zeitraum, und

c2) Anpassen der erwähnten Differenz, um das vorgegebene Beobachtungsfenster in Bezug zum verzögerten Referenzsignal (FREFdly) zu positionieren.


 
13. Das Verfahren nach Anspruch 12, wobei der Schritt des Kalibrierens der Offset-Verzögerung die folgenden Schritte umfasst:
Erzeugen eines Verzögerungsanpassungs-Steuersignals basierend auf der Differenz zwischen dem ersten und dem zweiten Offset-Verzögerungswert, der während des Beurteilungsschrittes erkannt wird, und Anwenden des Verzögerungsanpassungs-Steuersignals auf eine variable Verzögerungseinheit (153), um die erste Offset-Verzögerung anzupassen.
 
14. Das Verfahren nach Anspruch 12 oder 13, wobei der Schritt des Kalibrierens der Offset-Verzögerung offline durchgeführt wird.
 
15. Das Verfahren nach Anspruch 12 oder 13, wobei der Schrittes des Kalibrierens der Offset-Verzögerung online während einer Frequenzerfassungsstufe durchgeführt wird bevor der TDC für die Phasenverriegelung aktiviert wird.
 


Revendications

1. Boucle à verrouillage de phase tout-numérique (ADPLL) (10) comprenant un oscillateur à commande numérique (DCO) (11), conçu pour générer un signal de sortie de DCO à partir d'un mot de code de fréquence (FCW), et une boucle de rétroaction comprenant un ensemble de composants permettant de commander le DCO (11), l'ADPLL étant conçue pour recevoir un signal de fréquence de référence (FREF), les composants comprenant :

un convertisseur temps-numérique (TDC) (15) prévu pour effectuer une détection de phase dans une fenêtre d'observation prédéterminée, le TDC (15) étant conçu pour recevoir au moins un signal de référence retardé (FREFdly) ayant un premier retard de décalage et un signal de validation (CKVD2s) ayant un second retard de décalage et définissant la fenêtre d'observation prédéterminée, le TDC (15) étant conçu pour générer un code de sortie du TDC (TDCout) indiquant la différence de phase entre le signal de référence retardé (FREFdly) et le signal de validation (CKVD2s) mesuré dans la fenêtre d'observation prédéterminée ; et

un sous-ensemble de composants (12, 13, 14) conçus pour générer le signal de validation (CKVDS2s) à partir du signal de sortie du DCO, de sorte que le signal de validation (CKVDS2s) contient un front de transition dérivé du signal de sortie du DCO et est conçu pour activer le TDC (15) de manière à mesurer la différence de phase entre le signal de référence retardé (FREFdly) et le signal de validation (CKVDS2s) dans la fenêtre d'observation prédéterminée ;

caractérisée en ce que l'ensemble de composants de la boucle de rétroaction comprend un système d'étalonnage de décalage (152), relié à la sortie du TDC (TDCout), lequel, lorsqu'il est activé, est conçu pour évaluer la différence entre les première et seconde valeurs de retard de décalage en surveillant le code de sortie du TDC (TDCout) généré sur une période prédéterminée et pour régler ladite différence afin de positionner la fenêtre d'observation prédéterminée par rapport au signal de référence retardé (FREFdly).


 
2. ADPLL (10) selon la revendication 1, dans laquelle le système d'étalonnage de décalage comprend une unité d'étalonnage de décalage (152), reliée à la sortie du TDC et conçue pour effectuer ladite évaluation et générer en conséquence un signal de commande de réglage de décalage, et une unité de retard variable (153) reliée à l'unité d'étalonnage de décalage (152) et conçue pour régler le premier retard de décalage en fonction du signal de commande de réglage de décalage.
 
3. ADPLL (10) selon la revendication 2, dans laquelle l'unité de retard variable (153) fait partie du TDC (15).
 
4. ADPLL (10) selon l'une quelconque des revendications 1 à 3, dans laquelle le système d'étalonnage de décalage est conçu pour régler ladite différence d'une manière telle qu'un front de transition dudit signal de référence soit positionné sensiblement au milieu de ladite fenêtre d'observation prédéterminée.
 
5. ADPLL (10) selon l'une quelconque des revendications 1 à 3, dans laquelle le système d'étalonnage de décalage est conçu pour régler ladite différence d'une manière telle qu'un front de transition dudit signal de référence soit positionné sensiblement au milieu de la courbe de transfert du TDC.
 
6. ADPLL (10) selon l'une quelconque des revendications précédentes, dans laquelle le système d'étalonnage est conçu pour évaluer la différence entre les première et seconde valeurs de retard de décalage en comptant le nombre de uns et de zéros générés par le bit de poids fort du code de sortie du TDC.
 
7. ADPLL (10) selon la revendication 6, dans laquelle le système d'étalonnage de décalage comprend une unité de commande de décalage du TDC (156) conçue pour augmenter le premier retard de décalage lorsque le nombre de zéros est supérieur au nombre de uns dans le code de sortie du TDC.
 
8. ADPLL (10) selon les revendications 6 ou 7, dans laquelle l'unité de commande de décalage du TDC (156) est conçue pour diminuer le premier retard de décalage lorsque le nombre de uns est supérieur au nombre de zéros.
 
9. ADPLL (10) selon l'une quelconque des revendications précédentes, dans laquelle la boucle de rétroaction comprend des composants conçus pour détecter une partie grossière de la phase et des composants, parmi lesquels le TDC (15), permettant de détecter une partie fine de la phase.
 
10. ADPLL (10) selon l'une quelconque des revendications précédentes, dans laquelle la boucle de rétroaction comprend des composants conçus pour détecter une partie entière de la phase et des composants, parmi lesquels le TDC (15), permettant de détecter une partie fractionnaire de la phase.
 
11. ADPLL (10) selon l'une quelconque des revendications précédentes, dans laquelle le TDC (15) est un TDC flash.
 
12. Procédé de fonctionnement d'une boucle à verrouillage de phase tout-numérique (ADPLL) (10) comprenant un oscillateur à commande numérique (DCO) (11), conçu pour générer un signal de sortie de DCO, et une boucle de rétroaction comprenant un ensemble de composants permettant de commander le DCO (11), l'ADPLL étant conçue pour recevoir un signal de fréquence de référence (FREF), le procédé comprenant les étapes suivantes :

a) activation d'un convertisseur temps-numérique (TDC) (15) conçu pour effectuer une détection de phase dans une fenêtre d'observation prédéterminée, le TDC (15) étant conçu pour recevoir au moins un signal de référence retardé (FREFdly) ayant un premier retard de décalage et un signal de validation (CKVD2s) ayant un second retard de décalage et définissant la fenêtre d'observation prédéterminée, dans lequel l'étape d'activation du TDC (15) comprend les étapes suivantes :

a1) fourniture d'un signal de référence retardé (FREFdly) au TDC (15), et

a2) génération, au moyen d'un sous-ensemble de composants (12, 13, 14),du signal de validation (CKVD2s) à partir du signal de sortie du DCO, de sorte que le signal de validation (CKVD2s) contient un front de transition dérivé du signal de sortie du DCO et est conçupour activer le TDC (15) de manière à mesurer la différence de phase entre le signal de référence retardé (FREFdly) et le signal de validation (CKVD2s) dans la fenêtre d'observation prédéterminée ;

b) génération, au moyen du TDC (15), d'un code de sortie du TDC (TDCout) indiquant la différence de phase entre le signal de référence retardé (FREFdly) et le signal de validation (CKVD2s) mesuré dans la fenêtre d'observation prédéterminée ; et

c) réalisation d'une étape d'étalonnage de décalage au moyen d'un système d'étalonnage (152) relié à la sortie du TDC,

caractérisé en ce que l'étape d'étalonnage comprend les étapes suivantes :

c1) évaluation de la différence entre les première et seconde valeurs de retard de décalage par surveillance du code de sortie du TDC (TDCout) généré sur une période prédéterminée, et

c2) réglage de ladite différence afin de positionner la fenêtre d'observation prédéterminée par rapport au signal de référence retardé (FREFdly).


 
13. Procédé selon la revendication 12, dans lequel l'étape d'étalonnage du retard de décalage comprend les étapes suivantes :
génération d'un signal de commande de réglage de retard en fonction de la différence entre les première et seconde valeurs de retard de décalage détectées durant l'étape d'évaluation, et application du signal de commande de réglage de retard à une unité de retard variable (153) pour régler le premier retard de décalage.
 
14. Procédé selon les revendications 12 ou 13, dans lequel l'étape d'étalonnage de retard de décalage est réalisée hors ligne.
 
15. Procédé selon les revendications 12 ou 13, dans lequel l'étape réalisée d'étalonnage de décalage est réalisée en ligne lors d'un stade d'acquisition de fréquence avant l'activation du TDC (15) pour le verrouillage de phase.
 




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Cited references

REFERENCES CITED IN THE DESCRIPTION



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Patent documents cited in the description




Non-patent literature cited in the description