(19)
(11)EP 3 067 924 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
29.04.2020 Bulletin 2020/18

(21)Application number: 15193187.0

(22)Date of filing:  05.11.2015
(51)International Patent Classification (IPC): 
H01L 23/498(2006.01)

(54)

COMPOSITE SOLDER BALL, SEMICONDUCTOR PACKAGE USING THE SAME, SEMICONDUCTOR DEVICE USING THE SAME AND MANUFACTURING METHOD THEREOF

VERBUNDLÖTKUGEL, HALBLEITERGEHÄUSE DAMIT, HALBLEITERBAUELEMENT DAMIT UND HERSTELLUNGSVERFAHREN DAFÜR

BILLE DE SOUDURE COMPOSITE, BOÎTIER DE SEMI-CONDUCTEUR UTILISANT CELLE-CI, DISPOSITIF À SEMI-CONDUCTEURS UTILISANT CELLE-CI ET SON PROCÉDÉ DE FABRICATION


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 13.03.2015 US 201562132683 P
21.10.2015 US 201514918698

(43)Date of publication of application:
14.09.2016 Bulletin 2016/37

(73)Proprietor: MediaTek Inc.
Hsin-Chu 300 (TW)

(72)Inventors:
  • CHENG, Tao
    Zhubei City, Hsinchu County 302 (TW)
  • HSU, Wen-Sung
    Zhubei City, Hsinchu County 302 (TW)
  • LIN, Shih-Chin
    Taoyuan City 335 (TW)

(74)Representative: Krauns, Christian 
Wallinger Ricker Schlotter Tostmann Patent- und Rechtsanwälte Partnerschaft mbB Zweibrückenstraße 5-7
80331 München
80331 München (DE)


(56)References cited: : 
JP-A- 2007 075 856
JP-B1- 5 408 401
JP-B1- 5 585 750
US-A1- 2009 256 256
US-A1- 2015 061 129
US-B1- 6 786 385
JP-A- 2011 029 395
JP-B1- 5 435 182
US-A1- 2006 071 330
US-A1- 2011 156 264
US-B1- 6 337 445
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    FIELD OF THE INVENTION



    [0001] The invention relates to a solder ball, a semiconductor package using the same, a semiconductor device using the same and a manufacturing method thereof, and more particularly to a composite solder ball, a semiconductor package using the same, a semiconductor device using the same and a manufacturing method thereof.

    BACKGROUND OF THE INVENTION



    [0002] In the electronics industry, high integration and multiple functions with high performance become essential for new products. And meanwhile, high integration may cause higher manufacturing cost, since the manufacturing cost is in proportional to its size. Therefore, demanding on miniaturization of integrated circuit (IC) packages has become more and more critical.

    [0003] Package-on-package (PoP) is now the fastest growing semiconductor package technology since it is a cost-effective solution to high-density system integration in a single package. In a PoP structure, various packages are integrated in a single semiconductor package to reduce the size. Accordingly, there exists a need to provide a semiconductor package to overcomes, or at least reduces the above-mentioned problems.

    [0004] Therefore, it is important to increase the performance of the 3D graphic processing circuit while reducing the consumption of the electric power and extending the operating time of the mobile device. The US 2015/061129 discloses forming a bump electrode on an electrode pad using a Cu core ball in which a core material is covered with solder plating, and a board which has bump electrodes such as semiconductor chip or printed circuit board mounts such a bump electrode. A flux is coated on a substrate and the bump electrodes are then mounted on the electrode pad. In a step of heating, the electrode pad and the Cu core ball are molten to the solder plating, the heating rate of the substrate is set to not less than 0.01 °C/sec and to less than 0.3 °C/sec.

    SUMMARY OF THE INVENTION



    [0005] The problem of the present invention is solved by a composite solder ball according to the independent claim 1 as well as by a manufacturing method of a semiconductor package according to the independent claim 6. The dependent claims refer to advantageous further developments of the present invention. In one embodiment of the invention, a composite solder ball is provided. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer.

    [0006] In another embodiment of the invention, a semiconductor package is provided. The semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.

    [0007] In another embodiment of the invention, a semiconductor device is provided. The semiconductor device includes a semiconductor package and a second semiconductor component. The second semiconductor component is disposed on the second substrate of the semiconductor package. The semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.

    [0008] In another embodiment of the invention, a manufacturing method of a semiconductor package is provided. The manufacturing method includes the following steps. A first substrate is provided; a first semiconductor component is disposed on the first substrate; a second substrate is provided; a plurality of composite solder balls are disposed on the second substrate; the first substrate is connected to the second substrate by way of the composite solder balls facing the first substrate, wherein the composite solder balls are disposed between the first substrate and the second substrate.

    [0009] Numerous objects, features and advantages of the invention will be readily apparent upon a reading of the following detailed description of embodiments of the invention when taken in conjunction with the accompanying drawings. However, the drawings employed herein are for the purpose of descriptions and should not be regarded as limiting.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0010] The above objects and advantages of the invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

    FIG. 1 illustrates a diagram of a semiconductor package according to an embodiment of the invention;

    FIG. 2 illustrates a diagram of a semiconductor package according to another embodiment of the invention;

    FIG. 3 illustrates a diagram of a semiconductor device according to another embodiment of the invention;

    FIGS 4A to 4F illustrate manufacturing processes of the semiconductor package of FIG. 1; and

    FIG. 5 illustrates a manufacturing process of the semiconductor package of FIG. 2.


    DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS



    [0011] FIG. 1 illustrates a diagram of a semiconductor package 100 according to an embodiment of the invention. The semiconductor package 100 includes a first substrate 110, a second substrate 120, a first semiconductor component 130, a plurality composite solder balls 140, a package body 150 and a plurality of conductive contacts 160.

    [0012] The first substrate 110 is, for example, a multi-layered coreless substrate. The first substrate 110 includes a plurality of pads 111 for electrically connected to the composite solder balls 140. The second substrate 120 is, for example, an interposer.

    [0013] The first semiconductor component 130 may be disposed on and electrically connected to the first substrate 110 through the composite solder balls 140. The second substrate 120 may be electrically connected to the first semiconductor component 130 through the composite solder balls 140 and the second substrate 120.

    [0014] In the present embodiment, the first semiconductor component 130 is coupled to an upper surface 110u of the first substrate 110 in a "face-down" orientation and electrically connected to the first substrate 110 via a plurality of conductive contacts 131. This configuration is sometimes referred to as "flip-chip". The conductive contact 131 may be solder ball, conductive pillar, etc.

    [0015] In other embodiments, the first semiconductor component 130 may be coupled to the first substrate 110 in a "face-up" orientation, and electrically connected to the first substrate 110 via a plurality of conductive bond wires (not shown). The first semiconductor component 130 may be an active chip or a passive component, such as a resistor, an inductor or a capacitor. In another embodiment, the number of the first semiconductor component 130 may be several.

    [0016] Each composite solder ball 140 includes a core 141, a barrier layer 142 and an encapsulating layer 143. The barrier layer 142 is disposed between the core 141 and the encapsulating layer 143. For example, the barrier layer 142 directly or indirectly encapsulates the core 141, and the encapsulating layer 143 directly or indirectly encapsulates the barrier layer 142.

    [0017] The melting point of the core 141 may be higher than the melting point of the encapsulating layer 143, such that the core 141 may be prevented from melting and deforming during reflow process, Therefore, it is possible to prevent an outer diameter D1 of the core 141 from expanding, and accordingly the minimum interval P1 between adjacent two composite solder balls 140 do not be narrowed, such that adjacent two composite solder balls 140 may be prevented from being electrically short to each other, and the density of the composite solder balls 140 may be increased.

    [0018] In one embodiment, the core 141 may be made of a material including tin, bismuth or a combination thereof. In another embodiment, the core 141 may be made of a material in absence of copper. As a result, the outer diameter D1 of the core 141 may be reduced, such that the outer diameter D2 of the encapsulating layer 143 encapsulating the core 141 may be reduced and/or the thickness of the semiconductor package 100 may be reduced. In one embodiment, after reflow, the encapsulating layer 143 has the outer diameter D2 ranging between 120 µm and 130 µm.

    [0019] In addition, the melting point of the barrier layer 142 may be higher than the melting point of the core 141, such that the barrier layer 142 can restrict the outer diameter D1 of the core 141 and accordingly can prevent the core 141 from over-deforming during reflow process. Furthermore, since the barrier layer 142 can restrict the outer diameter D1 of the core 141, the core 141 may be made a material having hardness and/or strength lower than that of the barrier layer 142. For example, the barrier layer 142 may be made of a material including nickel whose hardness and/or strength is larger than the core 141.

    [0020] In addition, the encapsulating layer 143 may be pre-solder. Under such design, the semiconductor package 100 may omit extra pre-solder which is pre-applied on the first substrate 110 and/or the second substrate 120. In one embodiment, the encapsulating layer 143 may be made of an alloy material including at least two of tin, silver and copper.

    [0021] The package body 150 is formed between the first substrate 110 and the second substrate 120 and encapsulates the first semiconductor component 130 and the composite solder balls 140.

    [0022] The package body 150 can include, for example, a Novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant. Suitable fillers also can be included, such as powdered SiO2.

    [0023] The conductive contacts 160 are disposed on a bottom surface 110b of the first substrate 110. The semiconductor package 100 is disposed on and electrically connected to an exterior circuit, such as a circuit board. The conductive contact 160 may be solder ball, conductive pillar, etc.

    [0024] FIG. 2 illustrates a diagram of a semiconductor package 200 according to another embodiment of the invention. The semiconductor package 200 includes the first substrate 110, the second substrate 120, the first semiconductor component 130, the composite solder balls 140, an under fill 250 and a plurality of conductive contacts 160.

    [0025] The under fill 250 is formed between the first semiconductor component 130 and the first substrate 110 and encapsulates a plurality of conductive contacts 131 of the first semiconductor component 130.

    [0026] In the present embodiment, the semiconductor package 200 omits the package body 150. In another embodiment, the semiconductor package 200 may further includes the package body 150 encapsulating the first semiconductor component 130, the composite solder balls 140 and the under fill 250.

    [0027] FIG. 3 illustrates a diagram of a semiconductor device 300 according to another embodiment of the invention. The semiconductor device 300 includes a semiconductor package 100 and a second semiconductor component 360. The second semiconductor component 360 may be, for example, a memory, a semiconductor component rather than memory, another semiconductor package, active component, passive component, etc. The second semiconductor component 360 is disposed on and electrically connected to the second substrate 120 of the semiconductor package 100 through a plurality of conductive contacts 361. The conductive contact 361 may be solder ball, pillar, etc.

    [0028] FIGS. 4A to 4F illustrate manufacturing processes of the semiconductor package 100 of FIG. 1.

    [0029] Referring to FIG. 4A, the first substrate 110 is provided.

    [0030] Referring to FIG. 4B, the first semiconductor component 130 is disposed on the first substrate 110 using, for example, surface mount technology (SMT).

    [0031] Referring to FIG. 4C, the second substrate 120 is provided.

    [0032] Referring to FIG. 4D, a plurality of composite solder balls 140 are disposed on the second substrate 120 using, for example, ball mounting technology. Each composite solder ball 140 includes the core 141, the barrier layer 142 and the encapsulating layer 143. The barrier layer 142 is disposed between the core 141 and the encapsulating layer 143. For example, the barrier layer 142 directly or indirectly encapsulates the core 141, and the encapsulating layer 143 directly or indirectly encapsulates the barrier layer 142.

    [0033] Referring to FIG. 4E, the first substrate 110 is connected to the second substrate 120 by way of the composite solder balls 140 facing the first substrate 110, wherein the composite solder balls 140 are disposed between the first substrate 110 and the second substrate 120 for electrically connecting the first substrate 110 and the second substrate 120.

    [0034] After reflow process, the encapsulating layer 143 of the composite solder balls 140 is melted to solder with the pads 111 of the first substrate 110. Since the melting point of the core 141 is higher than the melting point of the encapsulating layer 143, the reflowing temperature may be sufficiently high. For example, the reflowing temperature may reach 245°C or higher, such that the encapsulating layer 143 can firm formed on the pads 111 of the first substrate 110, and the core 141 may be prevented from melting and/or over-deforming. In another embodiment, the reflowing temperature may approach or exceed the melting point of the core 141.

    [0035] In addition, the melting point of the barrier layer 142 is higher than the melting point of the core 141, such that, during reflow process, the barrier layer 142 can restrict the outer diameter D1 of the core 141 and accordingly can prevent the core 141 from over-deforming.

    [0036] Referring to FIG. 4F, the package body 150 is disposed over the upper surface 110u of the first substrate 110 and encapsulates the first semiconductor component 130. The package body 150 can be formed by various packaging technologies, such as, for example, compression molding, injection molding, transfer molding or dispensing technology.

    [0037] Then, the conductive contacts 160 of FIG. 1 may be disposed on the bottom surface of 110b of the first substrate 110 of IFG. 1 so as to form the semiconductor package 100 as illustrated in FIG. 1.

    [0038] FIG. 5 illustrates a manufacturing process of the semiconductor package 200 of FIG. 2. The under fill 250 is formed between the first substrate 110 and the first semiconductor component 130 and encapsulates the conductive contacts 131 using, for example, dispensing technology. In addition, the other formation steps of the semiconductor package 200 are similar to the corresponding steps of the semiconductor package 100 of FIG. 1, and the similarities are not repeated here.

    [0039] While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment.


    Claims

    1. A composite solder ball (140), comprising:

    a copper-free core (141);

    an encapsulating layer (143); and

    a barrier layer (142) disposed between the copper-free core (141) and the encapsulating layer (143);

    wherein a melting point of the barrier layer (142) is higher than a melting point of the copper-free core (141), the melting point of the copper-free core (141) is higher than a melting point of the encapsulating layer (143), characterized in

    that the copper-free core (141) is made of tin, bismuth or a combination thereof;

    that the encapsulating layer (143) is made of an alloy material including at least two of tin, silver and copper; and

    that the encapsulating layer (143) has an outer diameter (D1) ranging between 120 micrometers and 130 micrometers.


     
    2. A semiconductor package (100), comprising:

    a first substrate (110);

    a second substrate (120);

    a composite solder ball (140) as claimed in claim 1, disposed between the first substrate (110) and the second substrate (120) for electrically connecting the first substrate (110) and the second substrate (120); and

    a first semiconductor component, disposed between the first substrate (110) and the second substrate (120).


     
    3. The semiconductor package (100) as claimed in claim 2, wherein the second substrate (120) is an interposer.
     
    4. A semiconductor device (300), comprising:

    a semiconductor package as claimed in any one of claims 2 to 3; and

    a second semiconductor component (360), disposed on the second substrate (120) of the semiconductor package (100).


     
    5. The semiconductor device (300) as claimed in claim 4, wherein the second semiconductor component (360) is a memory device.
     
    6. A manufacturing method of a semiconductor package (100), wherein the method comprises:

    providing a first substrate (110);

    disposing a first semiconductor component on the first substrate (110);

    providing a second substrate (120);

    disposing a plurality of composite solder balls (140) on the second substrate (120);

    connecting the first substrate (110) and the second substrate (120) by way of the composite solder balls (140) facing the first substrate (110), wherein the composite solder balls (140) are disposed between the first substrate (110) and the second substrate (120), characterized in

    that each composite solder ball (140) comprises a copper-free core (141) made of tin, bismuth or a combination;

    that the encapsulating layer (143) is made of an alloy material including at least two of tin, silver and copper; and

    that the encapsulating layer (143) has an outer diameter (D1) ranging between 120 micrometers and 130 micrometers.


     
    7. The manufacturing method as claimed in claim 6, wherein the second substrate (120) is an interposer.
     


    Ansprüche

    1. Verbundlötkugel (140), welche aufweist:

    einen kupferfreien Kern (141),

    eine verkapselnde Schicht (143), und

    eine Barriereschicht (142), die zwischen dem kupferfreien Kern (141) und der verkapselnden Schicht (143) angeordnet ist,

    wobei ein Schmelzpunkt der Barriereschicht (142) höher als ein Schmelzpunkt des kupferfreien Kerns (141) ist und wobei der Schmelzpunkt des kupferfreien Kerns (141) höher als der Schmelzpunkt der verkapselnden Schicht (143) ist, dadurch gekennzeichnet,

    dass der kupferfreie Kern (141) aus einem Zinn, einem Bismuth oder einer Kombination davon hergestellt worden ist,

    dass die verkapselnde Schicht (143) aus einem Legierungsmaterial hergestellt worden ist, das mindestens zwei von einem Silber, einem Zinn oder einem Kupfer enthält, und

    dass die verkapselnde Schicht (143) einen äußeren Durchmesser (D1) in einem Bereich von 120 bis 130 Mikrometer aufweist.


     
    2. Halbleitergehäuse (100), welches aufweist:

    ein erstes Substrat (110),

    ein zweites Substrat (120),

    eine Verbundlötkugel (140) nach Anspruch 1, welche zwischen dem ersten Substrat (110) und dem zweiten Substrat (120) angeordnet ist, um das erste Substrat (110) und das zweite Substrat (120) elektrisch zu verbinden, und

    eine erste Halbleiterkomponente, die zwischen dem ersten Substrat (110) und dem zweiten Substrat (120) angeordnet ist.


     
    3. Halbleitergehäuse (100) nach Anspruch 2, wobei das zweite Substrat (120) ein Interposer ist.
     
    4. Halbleitervorrichtung (300), welche aufweist:

    ein Halbleitergehäuse nach einem der Ansprüche 2 bis 3, und

    eine zweite Halbleiterkomponente (360), welche auf dem zweiten Substrat (120) des Halbleitergehäuses (100) angeordnet ist.


     
    5. Halbleitervorrichtung (300) nach Anspruch 4, wobei die zweite Halbleiterkomponente (360) eine Speichervorrichtung ist.
     
    6. Herstellungsverfahren eines Halbleitergehäuses (100), wobei das Verfahren umfasst:

    ein Bereitstellen eines ersten Substrats (110),

    ein Anordnen einer ersten Halbleiterkomponente auf dem ersten Substrat (110),

    ein Bereitstellen eines zweiten Substrats (120),

    ein Anordnen einer Vielzahl von Verbundlötkugeln (140) auf dem zweiten Substrat (120),

    ein Verbinden des ersten Substrats (110) und des zweiten Substrats (120) über die Verbundlötkugeln (140), die dem ersten Substrat (110) zugewandt sind, wobei die Verbundlötkugeln (140) zwischen dem ersten Substrat (110) und dem zweiten Substrat (120) angeordnet sind, dadurch gekennzeichnet,

    dass jede der Verbundlötkugeln (140) aufweist:

    einen kupferfreien Kern (141), der aus einem Zinn, einem Bismuth oder einer Kombination davon hergestellt worden ist,

    dass die verkapselnde Schicht (143) aus einer Legierung hergestellt worden ist, die mindestens zwei von einem Silber, einem Zinn oder einem Kupfer enthält, und

    dass die verkapselnde Schicht (143) einen äußeren Durchmesser (D1) in einem Bereich von 120 bis 130 Mikrometer aufweist.


     
    7. Herstellungsverfahren nach Anspruch 6, wobei das zweite Substrat (120) ein Interposer ist.
     


    Revendications

    1. Bille de soudure composite (140), comprenant :

    un noyau exempt de cuivre (141) ;

    une couche d'encapsulation (143) ; et

    une couche barrière (142) disposée entre le noyau exempt de cuivre (141) et la couche d'encapsulation (143) ;

    dans laquelle un point de fusion de la couche barrière (142) est supérieur à un point de fusion du noyau exempt de cuivre (141), le point de fusion du noyau exempt de cuivre (141) est supérieur à un point de fusion de la couche d'encapsulation (143), caractérisée

    en ce que le noyau exempt de cuivre (141) est constitué d'étain, de bismuth ou d'une combinaison de ceux-ci ;

    en ce que la couche d'encapsulation (143) est constituée d'un matériau d'alliage incluant au moins deux éléments parmi l'étain, l'argent et le cuivre ; et

    en ce que la couche d'encapsulation (143) possède un diamètre externe (D1) variant entre 120 micromètres et 130 micromètres.


     
    2. Boîtier de semi-conducteur (100), comprenant :

    un premier substrat (110) ;

    un second substrat (120) ;

    une bille de soudure composite (140) selon la revendication 1, disposée entre le premier substrat (110) et le second substrat (120) pour connecter électriquement le premier substrat (110) et le second substrat (120) ; et

    un premier composant semi-conducteur, disposé entre le premier substrat (110) et le second substrat (120).


     
    3. Boîtier de semi-conducteur (100) selon la revendication 2, dans lequel le second substrat (120) est un élément d'interposition.
     
    4. Dispositif à semi-conducteurs (300), comprenant :

    un boîtier de semi-conducteur selon l'une quelconque des revendications 2 à 3 ; et

    un second composant semi-conducteur (360), disposé sur le second substrat (120) du boîtier de semi-conducteur (100).


     
    5. Dispositif à semi-conducteurs (300) selon la revendication 4, dans lequel le second composant semi-conducteur (360) est un dispositif de mémoire.
     
    6. Procédé de fabrication d'un boîtier de semi-conducteur (100), dans lequel le procédé comprend :

    la fourniture d'un premier substrat (110) ;

    la disposition d'un premier composant semi-conducteur sur le premier substrat (110) ;

    la fourniture d'un second substrat (120) ;

    la disposition d'une pluralité de billes de soudure composites (140) sur le second substrat (120) ;

    la connexion du premier substrat (110) et du second substrat (120) par le biais des billes de soudure composites (140) faisant face au premier substrat (110), dans lequel les billes de soudure composites (140) sont disposées entre le premier substrat (110) et le second substrat (120), caractérisé

    en ce que chaque bille de soudure composite (140) comprend un noyau exempt de cuivre (141) constitué d'étain, de bismuth ou d'une combinaison ;

    en ce que la couche d'encapsulation (143) est constituée d'un matériau d'alliage incluant au moins deux éléments parmi l'étain, l'argent et le cuivre ; et

    en ce que la couche d'encapsulation (143) possède un diamètre externe (D1) variant entre 120 micromètres et 130 micromètres.


     
    7. Procédé de fabrication selon la revendication 6, dans lequel le second substrat (120) est un élément d'interposition.
     




    Drawing


























    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description