(19)
(11)EP 3 077 884 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
09.01.2019 Bulletin 2019/02

(21)Application number: 14793376.6

(22)Date of filing:  16.10.2014
(51)International Patent Classification (IPC): 
H02M 3/158(2006.01)
G05F 1/46(2006.01)
(86)International application number:
PCT/US2014/060851
(87)International publication number:
WO 2015/084492 (11.06.2015 Gazette  2015/23)

(54)

INSTANTANEOUS LOAD CURRENT MONITORING

ECHTZEITLASTSTROMÜBERWACHUNG

SURVEILLANCE DE COURANT DE CHARGE INSTANTANÉE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 04.12.2013 US 201314096868

(43)Date of publication of application:
12.10.2016 Bulletin 2016/41

(73)Proprietor: Apple Inc.
Cupertino CA 95014 (US)

(72)Inventors:
  • SEARLES, Shawn
    Cupertino, CA 95014 (US)
  • FLETCHER, Jay B.
    Cupertino, CA 95014 (US)

(74)Representative: Lang, Johannes 
Bardehle Pagenberg Partnerschaft mbB Patentanwälte, Rechtsanwälte Prinzregentenplatz 7
81675 München
81675 München (DE)


(56)References cited: : 
WO-A1-2008/035033
US-A1- 2012 313 571
US-A1- 2012 200 277
US-B2- 7 180 274
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    BACKGROUND


    Technical Field



    [0001] This disclosure is directed to integrated circuits, and more particularly, to voltage regulators having circuits for sensing instantaneous load current.

    Description of the Related Art



    [0002] As the integrated circuit (IC) features sizes have decreased, the number of functions integrated on new ICs has increased. For example, a system-on-a-chip (SoC) may include multiple processor cores, a graphic processing unit, various interface circuits, and so forth. Some SoCs (as well as other types of ICs) may also implement a voltage regulator on the same die as the other functional units. The voltage regulator may provide power to various ones of the functional units. In some cases, the voltage regulator may provide multiple voltages to different functional units via different power nodes.

    [0003] Each of the different functional units of an IC may place various current demands on the voltage regulator in accordance with their respective workloads. In some cases, if the voltage regulator is unable to fully meet the current demanded by a particular functional block, a voltage droop may occur on the power node supplying power to that particular functional block. Bulk capacitance between the power node and a reference (e.g., ground) node may supply some of the current, and eventually, may cause the voltage to return to a value within its specified range.

    [0004] US 2012/313571 A1 discloses a charging method and system for rationing charge or energy supplied by a host to a portable device.

    [0005] US 7 180 274 B2 discloses a switching voltage regulator operating without a discontinuous mode.

    SUMMARY



    [0006] A method and apparatus for monitoring instantaneous load current is disclosed. In one embodiment, an integrated circuit includes a voltage regulator and at least one functional unit implemented thereon. The voltage regulator includes a supply circuit configured to provide a voltage to the functional unit, and a sense circuit configured to determine an amount of current provided to the functional unit by the supply circuit. The sense circuit may determine the instantaneous load current being provided to the functional unit. An indication circuit is configured to provide, to the functional unit, an indication of the amount of current supplied thereto by the supply circuit.

    [0007] In one embodiment, a method includes a voltage regulator providing a supply voltage to a functional unit, and a sense circuit within the voltage regulator determining the amount of current provided to the functional unit. The voltage regulator and the sense circuit are implemented on a common integrated circuit die. An indication circuit is coupled to the sense circuit, and is configured to provide an indication (e.g., in the form a of a digital code) to the functional unit such that the latter is informed of the amount of current it is consuming.

    [0008] Generally speaking, the disclosure is directed to determining an instantaneous current drawn from a voltage regulator by a load circuit, and providing an indication of the instantaneous current to the load circuit.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0009] The following detailed description makes reference to the accompanying drawings, which are now briefly described.

    Fig. 1 is a block diagram of one embodiment of an IC.

    Fig. 2 is a block diagram of one embodiment of a voltage regulator circuit.

    Fig. 3 is a schematic diagram of one embodiment of a voltage regulator circuit.

    Fig. 4 is a flow diagram illustrating one embodiment of a method for determining and providing information regarding an instantaneous load current.

    Fig. 5 is a block diagram of one embodiment of an exemplary system.



    [0010] While the disclosed subject matter is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the subject matter to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the disclosed subject matter as defined by the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description. As used throughout this application, the word "may" is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words "include", "including", and "includes" mean including, but not limited to.

    [0011] Various units, circuits, or other components may be described as "configured to" perform a task or tasks. In such contexts, "configured to" is a broad recitation of structure generally meaning "having circuitry that" performs the task or tasks during operation. As such, the unit/circuit/component can be configured to perform the task even when the unit/circuit/component is not currently on. In general, the circuitry that forms the structure corresponding to "configured to" may include hardware circuits. Similarly, various units/circuits/components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase "configured to." Reciting a unit/circuit/component that is configured to perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112, paragraph six interpretation for that unit/circuit/component.

    DETAILED DESCRIPTION OF EMBODIMENTS



    [0012] Turning now to Fig. 1, a block diagram of one embodiment of an IC is shown. In the exemplary embodiment, IC 10 includes functional units 12, 14, 16, and 18, and a voltage regulator 20. Each of the functional units is configured to perform one of the functions of IC 10. Various types of functional units may be implemented on IC 10, which in one embodiment, may be a system-on-a-chip (SoC). Such functional unit types may include processor cores, graphics processing units, interface units, and so on. In general, the functional units may be any type of circuitry, and may be digital, analog, and/or mixed signal.

    [0013] Voltage regulator 20 in the embodiment shown may comprise a number of voltage regulation circuits therein, each of which is configured to regulate and provide a supply voltage to a corresponding load circuit. In this example, voltage regulator 20 provides voltage Vdd1 to a first load circuit, functional unit 12, Vdd2 to a second load circuit, functional unit 14, and Vdd3 to a third load circuit that includes functional units 16 and 18. In addition to providing a supply voltage to each of these load circuits, voltage regulator 20 in the embodiment shown is configured to provide indications of current consumption to each functional unit that makes up one of the load circuits. Functional unit 12 in the embodiment shown is configured to receive indication IL1 while functional unit 14 is configured to receive indication IL2. Functional units 16 and 18, which together provide a single load (since they are both connected to Vdd3) are configured to receive indication IL3.

    [0014] In one embodiment, the indications may provide information regarding the instantaneous current consumption. Since voltage regulator 20 is implemented on the same IC die in this embodiment, the instantaneous current may be converted into an indication and provided to a respective load with very little latency. In some embodiments, the indications may be provided as a digital value or code, although this is not a requirement for all embodiments.

    [0015] While it is noted that voltage regulator 20 in the embodiment shown is configured to provide multiple supply voltages, embodiments wherein a voltage regulator provide only a single supply voltage are possible and contemplated. Generally speaking, a voltage regulator in accordance with this disclosure may provide as many or as few supply voltages as desired, and may as such be configured accordingly. Furthermore, a voltage regulator in accordance with this disclosure may be able to provide indications of current consumption (e.g., instantaneous current) to each load circuit that is coupled to a corresponding one of the supply voltage nodes. Furthermore, while various embodiments of a voltage regulator discussed herein are implemented as buck regulators, it is noted that the disclosure is not intended to be limiting in this regard.

    [0016] Moving on to Fig. 2, a block diagram of one embodiment of a voltage regulator in accordance with the disclosure. In the embodiment shown, voltage regulator 21 includes a supply circuit 22, a sense circuit 24, and an indication circuit 26. Supply circuit 22 in the embodiment shown is a regulation circuit configured to regulate the output voltage Vdd. As shown here, supply circuit 22 is configured to receive power through input V_in from another source (e.g., a power source external to the IC). Supply circuit 22 is further configured to generate an output voltage, Vdd, at a specified level. The specified level of the output voltage Vdd may in some cases be variable, while in other cases, may be static. The supply voltage is provided through inductor L to a load circuit, such as one or more of the exemplary functional units discussed above. Capacitor C in the illustrated embodiment may be representative of the bulk capacitance between Vdd and ground.

    [0017] Sense circuit 24 in the embodiment shown is coupled to receive Vdd from supply circuit 22, and is further coupled to receive a reference voltage, Vref. The reference voltage may be the desired voltage for Vdd. In some embodiments, Vref (and thus, Vdd) may be variable. In other embodiments, Vref and Vdd may both be static voltages.

    [0018] As will be discussed in further detail below, one embodiment of sense circuit 24 may include a voltage to current conversion circuit. In this particular embodiment, such a circuit may produce two output currents, I_scale and I_demand. I_scale may be a scaled version of the instantaneous current consumed by the load circuit coupled to receive Vdd. I_demand may be the current instantaneously demanded by the load circuit coupled to receive Vdd, and this current may be different from the actual instantaneous current. However, the demand current may nevertheless be a reflection of the current consumed by the load circuit, and may thus be indicative of the same.

    [0019] As used herein, the term "instantaneous current" may be defined as the current consumed (or demanded) at a given point in time. The value of this current (or the related demand current) may be captured and provided as an indication minimal latency.

    [0020] Voltage regulator 21 in the embodiment shown also includes an indication circuit 26. In this particular embodiment, indication circuit 26 includes a selection circuit 27 coupled to receive I_scale from sense circuit 24. Additionally, selection circuit 27 in the illustrated embodiment is also coupled to receive I_supply, which is the un-scaled instantaneous current provided to the load circuit by supply circuit 22. It is noted that embodiments are possible and contemplated in which only two or one of these currents is received by indication circuit 26. In embodiments where only one of these current values is received by indication circuit, selection circuit 27 can be omitted.

    [0021] The output of selection circuit 27 in the embodiment shown is coupled to analog-to-digital converter (A/D) 29, which is configured to convert the received current into an indication of instantaneous current a digital value, IL[n-1:0] having n bits. A/D 29 may be any suitable type of analog-to-digital converter. However, it is also noted that A/D 29 may be optional if it is desired to provide the indication as an analog value. In such cases, other circuitry may be provided if desired (e.g., to scale the analog signal to a specific range, etc.). The indication generated by indication circuit 26 may then be distributed to the load circuit (e.g., a functional unit) for further use/processing.

    [0022] Fig. 3 is a schematic diagram of one embodiment of a voltage regulator circuit. In the embodiment shown, voltage regulator 30 includes a supply circuit 32, a sense circuit 34, and an indication circuit 36. Supply circuit 32 is configured to provide voltage Vdd to a load circuit, represented here by resistor R_load.

    [0023] Supply circuit 32 in the embodiment shown functions as a buck converter, and includes bridge pre-drive circuit 35 which is configured to activate one of transistors P1 and N1. Supply circuit 32 also includes current comparator 37, which is coupled to receive the current outputs from the junction of P1 and N1, along with the demand current, and is configured to drive a corresponding signal to bridge pre-drive circuit 35. Inductor L and capacitor C in the embodiment shown serve the same functions as in the example shown in Fig. 2. The current output from N1, I_N1, is a valley current, while the current output from P1, I_P1, is a peak current. These currents are provided to the input 'In', which may be a dual input as shown in the drawing or alternatively, may be a single input.

    [0024] Sense circuit 34 in the embodiment shown includes amplifier A1, which is coupled to receive the reference voltage, Vref, on one of its input. In this example, Vref is received on the inverting input of A1, although in some embodiments the polarity may be reversed if the polarity of transistors P2, P3, and P4 is also reversed. The other input of A1 in this embodiment is coupled to the drain terminal of transistor P4, which is also coupled to resistor R_LL. As a result, the signal input to the non-inverting input of A1 in this embodiment is a voltage indicative of the actual voltage Vdd. The output signal generated by amplifier A1 is thus an indication of the difference between the desired value of Vdd (Vref), and the actual value of Vdd.

    [0025] Amplifier A1 along with transistors P2 and P3 combine to form a circuit that converts an output voltage into two different currents. Both of transistors P2 and P3 have gate terminals coupled to the output of amplifier A1, and are thus responsive to the voltage thereon. The current from the drain of transistor P2 in the embodiment shown is a scaled version of the load current, i.e. the current consumed by the load circuit (represented by I_load, the current through R_load in this drawing). The current from the drain of transistor P3 is the demand current, i.e. the current that is being demanded by the load circuit, which may be different from the actual load current. The difference between these two currents may be achieved by sizing transistors P2 and P3 differently from one another. Both the Scaled I_Load and Demand Current values may be indicative of instantaneous current consumption by the load circuit.

    [0026] It is noted that sense circuit 34 may be configured differently. For example, embodiments are possible and contemplated wherein only the scaled load current is produced, while in other embodiments, only the demand current is produced.

    [0027] Voltage regulator 30 in this embodiment also includes a sense circuit 36, which is similar to that shown in Fig. 2. The primary difference is the presence of sample/hold circuit 38. Supply circuit 32 in the embodiment shown is coupled to provide the sensed load current ('Sensed Current') to sample/hold circuit 38. The sensed current has a value that is effectively the same as the actual load current, with any difference therebetween being negligible. Since supply circuit 32 operates as a buck converter in this embodiment, the sensed current may rise and fall (in some cases, periodically) in accordance with the operation of transistors P1 and N1. Sample/hold circuit 38 may thus be timed to sample the sensed load current at a certain part of its cycle, e.g., at its peak. The sample may then be provided through selection circuit 27, if selected, to A/D 29 and converted to a digital value. It is noted however that sample/hold circuit 38 is optional, and may be omitted in other embodiments, such as one that uses a linear voltage regulator instead of a buck converter.

    [0028] Selection circuit 27 may alternatively select either the demand current or the scaled load current to be converted into the indication of instantaneous load current IL[n-1:0]. The selection may be made in accordance with selection signal(s) ('SEL'), which may be generated by a source external to indication circuit 36. In various embodiments, a control circuit, the load, circuit, software, or other source may cause generation of the selection signals.

    [0029] Fig. 4 is a flow diagram of one embodiment of a method for determining and providing information regarding an instantaneous load current. Method 400 as shown herein may be performed using the circuit/hardware embodiments discussed above in reference to Figs. 1-3. Furthermore, method 400 may also be performed by circuit/hardware embodiments not discussed here but are otherwise configured to perform the functions called for by the various method steps.

    [0030] Method 400 begins with the providing of a supply voltage, by a voltage regulator, to a load circuit (block 405). The voltage regulator may be specified to provide the supply voltage within a specified range of a desired value (e.g., 0.8 volts, ± 5%). The load circuit may be a functional unit of the IC in which it is implemented, and may include analog, digital, or mixed signal circuitry.

    [0031] Method 400 further includes determining the instantaneous current supplied to the load circuit by the voltage regulator (block 410). The instantaneous current may be directly tapped from a node in the voltage regulator (e.g., 'Sense Current' as shown in Fig. 3), or may be replicated (and possibly scaled) by other circuitry (e.g., the circuitry that generates 'Scaled I_Load' in Fig. 3). An indication of the instantaneous current provided to the load circuit may then be generated, with the indication also being provided to the load circuit (block 415). The indication may be a digital value in one embodiment, although embodiments in which the indication is provided in analog form are also possible and contemplated. The indication may be that of a scaled load current, the actual load current, or a current demanded by the load circuit, each of which may be reflective of the instantaneous current consumed.

    [0032] Turning next to Fig. 5, a block diagram of one embodiment of a system 150 is shown. In the illustrated embodiment, the system 150 includes at least one instance of the integrated circuit 10 coupled to external memory 158. The integrated circuit 10 is coupled to one or more peripherals 154 and the external memory 158. A power supply 156 is also provided which supplies the supply voltages to the integrated circuit 10 as well as one or more supply voltages to the memory 158 and/or the peripherals 154. In some embodiments, more than one instance of the integrated circuit 10 may be included (and more than one external memory 158 may be included as well).

    [0033] The peripherals 154 may include any desired circuitry, depending on the type of system 150. For example, in one embodiment, the system 150 may be a mobile device (e.g. personal digital assistant (PDA), smart phone, etc.) and the peripherals 154 may include devices for various types of wireless communication, such as WiFi, Bluetooth, cellular, global positioning system, etc. The peripherals 154 may also include additional storage, including RAM storage, solid-state storage, or disk storage. The peripherals 154 may include user interface devices such as a display screen, including touch display screens or multitouch display screens, keyboard or other input devices, microphones, speakers, etc. In other embodiments, the system 150 may be any type of computing system (e.g. desktop personal computer, laptop, workstation, tablet, etc.).

    [0034] The external memory 158 may include any type of memory. For example, the external memory 158 may be SRAM, dynamic RAM (DRAM) such as synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, LPDDR1, LPDDR2, etc.) SDRAM, RAMBUS DRAM, etc. The external memory 158 may include one or more memory modules to which the memory devices are mounted, such as single inline memory modules (SIMMs), dual inline memory modules (DIMMs), etc.

    [0035] Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.


    Claims

    1. An integrated circuit (10) comprising:

    a load circuit (12, 14, 16, 18); and

    a voltage regulator (20, 30), wherein the voltage regulator and the load circuit are integrated on a common integrated circuit die, wherein the voltage regulator includes:

    a regulation circuit (22, 32) configured to provide a supply voltage to the load circuit, the regulation circuit including a pre-drive circuit (35) coupled to respective gate terminals of a PMOS transistor (P1) and an NMOS transistor (N1);

    a sensing circuit (24, 34) configured to sense an amount of current supplied to the load circuit by the regulation circuit; and

    an indication circuit (26, 36) configured to provide, to the load circuit, an indication of the amount of current supplied thereto by the regulation circuit, wherein the indication circuit includes an analog-to-digital (A/D) converter (29) configured to provide the indication as a digital code (IL1) based on a received current, characterized in that

    the sensing circuit (24, 34) includes a voltage-to-current conversion circuit (A1, P2, P3, P4) receiving the output voltage (Vdd), a reference voltage (Vref) and configured to generate a first current (I_scale, Scaled I_Load) that is a scaled version of the amount of current supplied to the load circuit (12).


     
    2. The integrated circuit as recited in claim 1, wherein the voltage-to-current conversion circuit is further configured to generate a second current (I_demand, Demand Current) indicative of an amount of current demanded by the load circuit (12).
     
    3. The integrated circuit as recited in claim 1, wherein the voltage-to-current conversion circuit includes:

    an amplifier (A1) configured to generate an output voltage based on a difference between a reference voltage and a present value of the supply voltage;

    a first transistor (P2) having a gate terminal coupled to receive the output voltage, the first transistor being configured to generate the first current;

    a second transistor (P3) configured to a second current indicative of an amount of current demanded by the load circuit; and

    a third transistor (P4) configured to generate a voltage indicative of the present supply value of the supply voltage.


     
    4. The integrated circuit as recited in claim 1, wherein the indication circuit (26, 36) includes a selection circuit (27) having a first input coupled to receive, from the sensing circuit (24, 34), the first current indicative of amount of current supplied to the load circuit (12) by the regulation circuit (22, 32), and a second input coupled to receive, from a sample and hold circuit (38), a signal indicative of a current supplied to the load circuit (12) by the regulation circuit.
     
    5. The integrated circuit as recited in claim 4, wherein an output of the selection circuit (27) is coupled to the A/D converter (29), the A/D converter configured to provide the digital code (IL1) as a plurality of bits to the load circuit (12), the digital code indicative of a value of a current on a selected one of the first and second inputs of the selection circuit (27).
     
    6. The integrated circuit as recited in claim 4, further comprising a sample and hold circuit (38) coupled between the selection circuit (27) and a current node in the regulation circuit (22), wherein the sample and hold circuit is configured to sample a value of the third current and to provide the sampled value to the selection circuit.
     
    7. A method comprising:

    providing a supply voltage from a supply circuit (22, 32) of a voltage regulator (20) to a load circuit (12), wherein the voltage regulator and the load circuit are implemented on a common integrated circuit die, the voltage regulator including a pre-drive circuit (35) coupled to respective gate terminals of a PMOS transistor (P1) and an NMOS transistor (N1);

    determining, using a sensing circuit (24, 34) implemented in the voltage regulator, an amount of current provided from the voltage regulator to the load circuit; and

    providing, from an indication circuit (26, 36) to the load circuit, an indication of the amount of current provided to the load circuit, the indication circuit including an analog-to-digital (A/D) converter (29) configured to provide the indication as a digital code (IL1) based on a received current,

    the method being characterized by

    a voltage-to-current conversion circuit (A1, P2, P3, P4) of the sensing circuit generating a first current (I_scale) that is a scaled version of the amount of current provided to the load circuit.


     
    8. The method as recited in claim 7, wherein providing the indication comprises providing a digital code to the load circuit (12), the digital code being indicative of the amount of current provided to the load circuit.
     
    9. The method as recited in claim 8, wherein the digital code is generated by an analog-to-digital converter, ADC (29), and wherein the method further comprises a selection circuit (27) providing one of the following to the ADC:

    a current (I_scale, Scaled I_Load) indicative of amount of current supplied to the load circuit by the voltage regulator; and

    a current (I_supply, Sensed Current) equivalent to the current supplied to the load circuit (12).


     
    10. The method as recited in claim 9, further comprising:
    a sample and hold circuit (38) coupled sampling a value of the current (I_supply, Sensed Current) equivalent to the current supplied to the load circuit and providing the sampled value to the selection circuit (27).
     
    11. The method as recited in claim 7, further comprising the voltage-to-current conversion circuit (A1, P2, P3, P4) generating a current (I_scale, Scaled I_Load) indicative of an amount of current demanded by the load circuit (12).
     
    12. The method as recited in claim 7 further comprising:

    an amplifier (A1) of the voltage-to-current conversion circuit generating an output voltage based on a difference between a reference voltage and a present value of the
    supply voltage;

    a first transistor (P2) of the voltage-to-current conversion circuit generating the first current based on the output voltage;

    a second transistor (P3) of the voltage-to-current conversion circuit generating a second current indicative of an amount of current demanded by the load circuit; and

    a third transistor (P4) of the voltage-to-current conversion circuit generating a voltage indicative of the present supply value of the supply voltage.


     


    Ansprüche

    1. Integrierte Schaltung (10), umfassend:

    eine Lastschaltung (12, 14, 16, 18); und

    einen Spannungsregler (20, 30), wobei der Spannungsregler und die Lastschaltung auf einem gemeinsamen Chip einer integrierten Schaltung integriert sind, wobei der Spannungsregler Folgendes beinhaltet:

    eine Regelschaltung (22, 32), die konfiguriert ist, um eine Versorgungsspannung für die Lastschaltung bereitzustellen, wobei die Regelschaltung eine Voransteuerschaltung (35) beinhaltet, die mit entsprechenden Gate-Anschlüssen eines PMOS-Transistors (P1) und eines NMOS-Transistors (N1) gekoppelt ist;

    eine Abtastschaltung (24, 34), die konfiguriert ist, um eine Strommenge zu erfassen, die der Lastschaltung durch die Regelschaltung zugeführt wird; und

    eine Anzeigeschaltung (26, 36), die konfiguriert ist, um der Lastschaltung eine Anzeige der Strommenge bereitzustellen, die ihr durch die Regelschaltung zugeführt wird, wobei die Anzeigeschaltung einen Analog-Digital-(A/D)-Wandler (29) beinhaltet, der konfiguriert ist, um die Anzeige als digitalen Code (IL1) basierend auf einem empfangenen Strom bereitzustellen,

    dadurch gekennzeichnet, dass

    die Abtastschaltung (24, 34) eine Spannungs-zu-Strom-Umwandlungsschaltung (A1, P2, P3, P4) beinhaltet, die die Ausgangsspannung (Vdd) und eine Referenzspannung (Vref) empfängt und die konfiguriert ist, um einen ersten Strom (I_scale, Scaled I_Load) zu erzeugen, der eine skalierte Version der Menge des der Lastschaltung (12) zugeführten Stroms ist.


     
    2. Integrierte Schaltung nach Anspruch 1, wobei die Spannungs- zu-Strom-Umwandlungsschaltung ferner konfiguriert ist, um einen zweiten Strom (I_demand, Demand Current) zu erzeugen, der eine von der Lastschaltung (12) benötigte Strommenge anzeigt.
     
    3. Integrierte Schaltung nach Anspruch 1, worin die Spannungs- zu-Strom-Umwandlungsschaltung Folgendes beinhaltet:

    einen Verstärker (A1), der konfiguriert ist, um eine Ausgangsspannung basierend auf einer Differenz zwischen einer Referenzspannung und einem aktuellen Wert der Versorgungsspannung zu erzeugen;

    einen ersten Transistor (P2) mit einem Gate-Anschluss, der zum Empfangen der Ausgangsspannung gekoppelt ist, wobei der erste Transistor konfiguriert ist, um den ersten Strom zu erzeugen;

    einen zweiten Transistor (P3), der für einen zweiten Strom konfiguriert ist, der einen Betrag des von der Lastschaltung geforderten Stroms anzeigt; und

    einen dritten Transistor (P4), der konfiguriert ist, um eine Spannung zu erzeugen, die den aktuellen Versorgungswert der Versorgungsspannung anzeigt.


     
    4. Integrierte Schaltung nach Anspruch 1, wobei die Anzeigeschaltung (26, 36) eine Auswahlschaltung (27) mit einem ersten Eingang beinhaltet, der gekoppelt ist, um von der Abtastschaltung (24, 34) den ersten Strom zu empfangen, der die Menge des Stroms anzeigt, der der Lastschaltung (12) durch die Regelschaltung (22, 32) zugeführt wird, und einen zweiten Eingang, der gekoppelt ist, um von einer Abtast- und Halteschaltung (38) ein Signal zu empfangen, das einen Strom anzeigt, der von der Regelschaltung an die Lastschaltung (12) geliefert wird.
     
    5. Integrierte Schaltung nach Anspruch 4, wobei ein Ausgang der Auswahlschaltung (27) mit dem A/D-Wandler (29) gekoppelt ist, wobei der A/D-Wandler konfiguriert ist, um den digitalen Code (IL1) als eine Vielzahl von Bits an die Lastschaltung (12) bereitzustellen, wobei der digitale Code einen Wert eines Stroms an einem ausgewählten der ersten und zweiten Eingänge der Auswahlschaltung (27) anzeigt.
     
    6. Integrierte Schaltung nach Anspruch 4, ferner umfassend eine Abtast- und Halteschaltung (38), die zwischen der Auswahlschaltung (27) und einem Stromknoten in der Regelschaltung (22) gekoppelt ist, wobei die Abtast- und Halteschaltung konfiguriert ist, um einen Wert des dritten Stroms abzutasten und den abgetasteten Wert an die Auswahlschaltung weiterzugeben.
     
    7. Verfahren, umfassend:

    Bereitstellen einer Versorgungsspannung von einer Versorgungsschaltung (22, 32) eines Spannungsreglers (20) zu einer Lastschaltung (12), wobei der Spannungsregler und die Lastschaltung auf einem gemeinsamen Chip einer integrierten Schaltung implementiert sind, wobei der Spannungsregler eine Voransteuerschaltung (35) beinhaltet, die mit entsprechenden Gate-Anschlüssen eines PMOS-Transistors (P1) und eines NMOS-Transistors (N1) gekoppelt ist;

    Bestimmen einer Strommenge, die vom Spannungsregler an die Lastschaltung geliefert wird, unter Verwendung einer in dem Spannungsregler implementierten Abtastschaltung (24, 34); und

    Bereitstellen einer Anzeigevorrichtung (26, 36) für die Lastschaltung, die eine Anzeige der der Lastschaltung zugeführten Strommenge bereitstellt, wobei die Anzeigevorrichtung einen Analog-Digital (A/D)-Wandler (29) beinhaltet, der konfiguriert ist, um die Anzeige als digitalen Code (IL1) basierend auf einem empfangenen Strom bereitzustellen,

    wobei das Verfahren gekennzeichnet ist durch

    eine Spannungs-zu-Strom-Umwandlungsschaltung (A1, P2, P3, P4) der Abtastschaltung, die einen ersten Strom (I_scale) erzeugt, der eine skalierte Version der der Lastschaltung bereitgestellten Strommenge ist.


     
    8. Verfahren nach Anspruch 7, wobei das Bereitstellen der Anzeige das Bereitstellen eines digitalen Codes für die Lastschaltung (12) umfasst, wobei der digitale Code die Menge des der Lastschaltung zugeführten Stroms anzeigt.
     
    9. Verfahren nach Anspruch 8, wobei der digitale Code durch einen Analog-DigitalWandler, ADC (29), erzeugt wird, und worin das Verfahren ferner eine Auswahlschaltung (27) umfasst, die dem ADC eines der Folgenden bereitstellt:

    einen Strom (I_scale, Scaled I_Load), der die Menge des Stroms anzeigt, der der Lastschaltung von dem Spannungsregler zugeführt wird; und

    einen Strom (I_supply, Sensed Current), der äquivalent ist zu dem der Lastschaltung (12) zugeführten Strom.


     
    10. Verfahren nach Anspruch 9, ferner umfassend:
    eine Abtast- und Halteschaltung (38), die einen Wert des Stroms (I_supply, Sensed Current), der äquivalent ist zu dem der Lastschaltung zugeführten Strom, abtastet und den Abtastwert an die Auswahlschaltung (27) liefert.
     
    11. Verfahren nach Anspruch 7, ferner umfassend die Spannungs-zu-Strom-Umwandlungsschaltung (A1, P2, P3, P4), die einen Strom (I_scale, Scaled I_Load) erzeugt, der eine von der Lastschaltung (12) geforderte Strommenge anzeigt.
     
    12. Verfahren nach Anspruch 7, ferner umfassend:

    einen Verstärker (A1) der Spannungs-zu-Strom-Umwandlungsschaltung, der eine Ausgangsspannung basierend auf einer Differenz zwischen einer Referenzspannung und einem aktuellen Wert der Versorgungsspannung erzeugt;

    einen ersten Transistor (P2) der Spannungs-zu-Strom-Umwandlungsschaltung, der den ersten Strom basierend auf der Ausgangsspannung erzeugt;

    einen zweiten Transistor (P3) der Spannungs-zu-Strom-Umwandlungsschaltung, der einen zweiten Strom erzeugt, der eine von der Lastschaltung geforderte Strommenge anzeigt; und

    einen dritten Transistor (P4) der Spannungs-zu-Strom-Umwandlungsschaltung, der eine Spannung erzeugt, die den aktuellen Versorgungswert der Versorgungsspannung anzeigt.


     


    Revendications

    1. Un circuit intégré (10) comprenant :

    un circuit de charge (12, 14, 16, 18) ; et

    un régulateur de tension (20, 30), le régulateur de tension et le circuit de charge étant intégrés sur une puce commune de circuit intégré, le régulateur de tension comprenant :

    un circuit de régulation (22, 32) configuré pour délivrer une tension d'alimentation au circuit de charge, le circuit de régulation comprenant un circuit de pré-pilotage (35) couplé à des bornes de grille respectives d'un transistor PMOS (P1) et d'un transistor NMOS (N1) ;

    un circuit de détection (24, 34) configuré pour détecter un niveau de courant délivré au circuit de charge par le circuit de régulation ; et

    un circuit indicateur (26, 36) configuré pour délivrer, au circuit de charge, une indication du niveau de courant délivré à celui-ci par le circuit de régulation, le circuit indicateur comprenant un convertisseur analogique-vers-numérique (A/D) (29) configuré pour délivrer l'indication sous forme d'un code numérique (IL1) sur la base d'un courant reçu,

    caractérisé en ce que

    le circuit de détection (24, 34) comprend un circuit de conversion tension-vers-courant (A1, P2, P3, P4) recevant la tension de sortie (Vdd), une tension de référence (Vref) et configurée pour générer un premier courant (I_Scale, Scaled I_Load) qui est une version à une autre échelle du niveau de courant délivré au circuit de charge (12).


     
    2. Le circuit intégré tel qu'énoncé dans la revendication 1, dans lequel le circuit de conversion tension-vers-courant est en outre configuré pour générer un second courant (I_demand, Demand Current) représentatif d'un niveau de courant exigé par le circuit de charge (12).
     
    3. Le circuit intégré tel qu'énoncé dans la revendication 1, dans lequel le circuit de conversion tension-vers-courant comprend :

    un amplificateur (A1) configuré pour générer une tension de sortie basée sur une différence entre une tension de référence et une valeur actuelle de la tension d'alimentation ;

    un premier transistor (P2) possédant une borne de grille couplée pour recevoir la tension de sortie, le premier transistor étant configuré pour générer le premier courant ;

    un second transistor (P3) configuré pour générer un second courant représentatif d'un niveau de courant exigé par le circuit de charge ; et

    un troisième transistor (P4) configuré pour générer une tension représentative de la valeur d'alimentation actuelle de la tension d'alimentation.


     
    4. Le circuit intégré tel qu'énoncé dans la revendication 1, dans lequel le circuit indicateur (26, 36) comprend un circuit de sélection (27) possédant une première entrée couplée pour recevoir, du circuit de détection (24, 34), le premier courant représentatif d'un niveau de courant délivré au circuit de charge (12) par le circuit de régulation (22, 32), et une seconde entrée couplée pour recevoir, d'un circuit d'échantillonnage et maintien (38), un signal représentatif d'un courant délivré au circuit de charge (12) par le circuit de régulation.
     
    5. Le circuit intégré tel qu'énoncé dans la revendication 4, dans lequel une sortie du circuit de sélection (27) est couplée au convertisseur A/D (29), le convertisseur A/D étant configuré pour délivrer au circuit de charge (12) le code numérique (IL1) sous forme d'une pluralité de bits, le code numérique étant représentatif d'une valeur d'un courant sur une entrée sélectionnée parmi la première et la seconde entrée du circuit de sélection (27).
     
    6. Le circuit intégré tel qu'énoncé dans la revendication 4, comprenant en outre un circuit d'échantillonnage et maintien (38) couplé entre le circuit de sélection (27) et un noeud de courant du circuit de régulation (22), le circuit d'échantillonnage et maintien étant configuré pour échantillonner une valeur du troisième courant et pour délivrer la valeur échantillonnée au circuit de sélection.
     
    7. Un procédé comprenant :

    la délivrance d'une tension d'alimentation à un circuit de charge (12) depuis un circuit d'alimentation (22, 32) d'un régulateur de tension (20), le régulateur de tension et le circuit de charge étant implémentés sur une puce commune de circuit intégré, le régulateur de tension comprenant un circuit de pré-pilotage (35) couplé à des bornes de grille respectives d'un transistor PMOS (P1) et d'un transistor NMOS (N1) ;

    la détermination, à l'aide d'un circuit de détection (24, 34) implémenté dans le régulateur de tension, d'un niveau de courant délivré du régulateur de tension au circuit de charge ; et

    la délivrance au circuit de charge, depuis un circuit indicateur (26, 36), d'une indication du niveau de courant délivré au circuit de charge, le circuit indicateur comprenant un convertisseur analogique-vers-numérique (A/D) (29) configuré pour délivrer l'indication sous forme d'un code numérique (IL1) sur la base d'un courant reçu,

    le procédé étant caractérisé par

    un circuit de conversion tension-vers-courant (A1, P2, P3, P4) du circuit de détection générant un premier courant (I_Scale) qui est une version à une autre échelle du niveau de courant délivré au circuit de charge.


     
    8. Le procédé tel qu'énoncé dans la revendication 7, dans lequel la délivrance de l'indication comprend la délivrance au circuit de charge (12) d'un code numérique, le code numérique étant représentatif du niveau de courant délivré au circuit de charge.
     
    9. Le procédé tel qu'énoncé dans la revendication 8, dans lequel le code numérique est généré par un convertisseur analogique-vers-numérique, ADC (29), et dans lequel le procédé comprend en outre un circuit de sélection (27) délivrant à l'ADC l'un d'entre :

    un courant (I_Scale, Scaled I_Load) représentatif du niveau de courant délivré au circuit de charge par le régulateur de tension ; et

    un courant (I_supply, Sensed Current) équivalent au courant délivré au circuit de charge (12).


     
    10. Le procédé tel qu'énoncé dans la revendication 9, comprenant en outre :
    un circuit d'échantillonnage et maintien (38) couplé pour échantillonner une valeur du courant (I_supply, Sensed Current) équivalente au courant délivré au circuit de charge et délivrant la valeur échantillonnée au circuit de sélection (27).
     
    11. Le procédé tel qu'énoncé dans la revendication 7, comprenant en outre la génération par le circuit de conversion tension-vers-courant (A1, P2, P3, P4) d'un courant (I_Scale, Scaled I_Load) représentatif d'un niveau de courant exigé par le circuit de charge (12).
     
    12. Le procédé tel qu'énoncé dans la revendication 7 comprenant en outre :

    la génération par un amplificateur (A1) du circuit de conversion tension-vers-courant d'une tension de sortie basée sur une différence entre une tension de référence et une valeur actuelle de la tension d'alimentation ;

    la génération par un premier transistor (P2) du circuit de conversion tension-vers-courant du premier courant basé sur la tension de sortie ;

    la génération par un second transistor (P3) du circuit de conversion tension-vers-courant d'un second courant représentatif d'un niveau de courant exigé par le circuit de charge ; et

    la génération par un troisième transistor (P4) du circuit de conversion tension-vers-courant d'une tension représentative de la valeur d'alimentation actuelle de la tension d'alimentation.


     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description