(19)
(11)EP 3 082 046 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
08.07.2020 Bulletin 2020/28

(21)Application number: 14876707.2

(22)Date of filing:  20.05.2014
(51)International Patent Classification (IPC): 
G06F 11/10(2006.01)
(86)International application number:
PCT/CN2014/077931
(87)International publication number:
WO 2015/100917 (09.07.2015 Gazette  2015/27)

(54)

DATA ERROR CORRECTING METHOD AND DEVICE, AND COMPUTER STORAGE MEDIUM

VERFAHREN UND VORRICHTUNG ZUR DATENFEHLERKORREKTUR UND COMPUTERSPEICHERMEDIUM

PROCÉDÉ ET DISPOSITIF DE CORRECTION D'ERREUR DE DONNÉES, ET SUPPORT D'INFORMATIONS


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 30.12.2013 CN 201310749647

(43)Date of publication of application:
19.10.2016 Bulletin 2016/42

(73)Proprietor: Sanechips Technology Co., Ltd.
Yantian District Shenzhen Guangdong (CN)

(72)Inventor:
  • HUANG, Yiyuan
    Shenzhen 518055 (CN)

(74)Representative: Gevers Patents 
Intellectual Property House Holidaystraat 5
1831 Diegem
1831 Diegem (BE)


(56)References cited: : 
CN-A- 1 523 799
CN-A- 102 804 146
US-A- 5 502 732
US-A1- 2010 169 742
CN-A- 101 227 263
KR-A- 20080 090 135
US-A1- 2007 136 644
US-B1- 6 374 382
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    TECHNICAL FIELD



    [0001] The disclosure relates to an error correcting technology in the field of coding and decoding, and in particular to a method and apparatus for correcting data error, and a computer storage medium.

    BACKGROUND



    [0002] Currently, an Error Checking and Correcting (ECC) technology used in a Random Access Memory (RAM) is mainly implemented by using a Hamming code, and the technology has functions of correcting an error of 1 bit and detecting errors of 2 bits. The ECC technology is implemented usually aiming at a certain width of data bit, and typical widths of data bit may be 32 bits, 64 bits, 128 bits or the like. Data bits of original data may be regarded as a matrix in which the data bits are arranged in rows and columns, odd-even check is performed on the rows and the columns to generate a check code, and the check code and the original data are written into and saved in the RAM. During data reading, the original data and the check code are read out together from the RAM, a new check code may be generated by means of the same algorithm, and furthermore, an erroneous row and column during data reading can be determined by comparing the two check codes to obtain a difference therebetween, thereby determining an erroneous data bit during data reading.

    [0003] In the above method, it is necessary for a high-bit part and low-bit part of a data bit to participate in generation of each check code, when a data bit width changes, it is needed to change a polynomial generated from the matrix correspondingly, and therefore the method is lower in generality.

    [0004] US-A-2007/0136644 discloses a decoding device which decodes a (k+m) bit codeword in accordance with a check matrix. The codeword includes k-bit information symbols and an m-bit parity check code. The check matrix includes a unit matrix and a coefficient matrix. The most significant bit of each of a second vector to a last vector in the coefficient matrix is 1. Binary codes with values 1 to k-1 are sequentially arranged from the second vector to the last vector in a matrix which is obtained by excluding the most significant bits of the second to the last vectors from the matrix including the second to the last vectors. A first vector of the coefficient matrix disagrees with the other vectors in the check matrix, and the first vector is composed of a specified bit pattern having a most significant bit of 0.

    SUMMARY



    [0005] In view of this, the embodiments of the disclosure are intended to provide method and apparatus for correcting a data error, and a computer storage medium, which can improve the generality of an algorithm and reduce the scale of a check code.

    [0006] To this end, the technical solutions of the embodiments of the disclosure are implemented as follows.

    [0007] According to a first aspect of the disclosure, there is provided a method for correcting a data error in data having 2n data bits with n>2, as claimed in independent claim 1.

    [0008] According to a second aspect of the disclosure, there is provided an apparatus for correcting a data error in data having 2n data bits with n>2, as claimed independent claim 4.

    [0009] According to a third aspect of the disclosure, there is provided a computer storage medium as claimed in claim 7.

    [0010] According to an embodiment of the disclosure, a data error correcting method is provided, which may include that:

    a binary index number is set for each data bit in an order of data bits; a first check code generation expressions are obtained according to the binary index numbers, and a first check code is generated according to the first check code generation expressions; a second check code generation expressions are obtained according to the binary index numbers, and a second check code is generated according to the second check code generation expressions, the first check code is compared with the second check code to determine an erroneous data bit, and the erroneous data bit is corrected: and

    the step that the first check code generation expressions are obtained according to the binary index numbers and the first check code is generated according to the first check code generation expressions may include that: for the binary index numbers for the respective data bits, an exclusive-or operation is performed only on data bits for which corresponding bits of respective binary index numbers are 1 or 0, a first check code generation expression of each index number bit is obtained, and a result of the first check code generation expression of each index number bit is taken as a corresponding bit of the first check code.



    [0011] Preferably, the step that the second check code generation expressions are obtained according to the binary index numbers and the second check code is generated according to the second check code generation expressions may include that:
    an exclusive-or operation is performed on data bits of input data, for which corresponding bits of respective binary index numbers are 1 or 0 for the binary index numbers for the respective data bits of the input data, and a second check code generation expression of each index number bit is obtained, and a result of the second check code generation expression of each index number bit is taken as a corresponding bit of the second check code.

    [0012] Preferably, the step that the first check code is compared with the second check code to determine the erroneous data bit and the erroneous data bit is corrected may include that:
    an exclusive-or operation is performed on each bit of the first check code and a corresponding bit of the second check code to obtain a corresponding bit of a third check code, when it is determined that the corresponding bits of the first check code and the second check code are inconsistent according to the third check code, an erroneous data bit is determined according to the first check code generation expressions of the corresponding bits of the first check code, and the erroneous data bit is corrected.

    [0013] According to an embodiment of the disclosure, an apparatus for correcting data error is also provided, which may include: a setting module, a first check code generation module, a second check code generation module and a data processing module, wherein
    the setting module is configured to set a binary index number for each data bit in an order of data bits;
    the first check code generation module is configured to obtain a first check code generation expressions according to the binary index numbers, and to generate the first check code according to the first check code generation expressions;
    the second check code generation module is configured to obtain a second check code generation expressions according to the binary index numbers, and to generate a second check code according to the second check code generation expressions; and
    the data processing module is configured to compare the first check code with the second check code to determine an erroneous data bit, and correct the erroneous data bit;
    the first check code generation module may be configured to perform an exclusive-or operation only on data bits for which corresponding bits of respective binary index numbers are 1 or 0 for the binary index numbers for the respective data bits, and obtain a first check code generation expression of each index number bit, and take a result of the first check code generation expression of each index number bit as a corresponding bit of the first check code.

    [0014] Preferably, the second check code generation module may be configured to perform an exclusive-or operation on data bits of input data, for which corresponding bits of respective binary index numbers are 1 or 0 for the binary index numbers for the respective data bits of the input data, and obtain a second check code generation expression of each index number bit, and take a result of the second check code generation expression of each index number bit as a corresponding bit of the second check code.

    [0015] Preferably, the data processing module may be configured to perform an exclusive-or operation on each bit of the first check code and a corresponding bit of the second check code to obtain a corresponding bit of a third check code, determine, when it is determined that the corresponding bits of the first check code and the second check code are inconsistent according to the third check code, an erroneous data bit according to the first check code generation expressions of the corresponding bits of the first check code, and correct the erroneous data bit.

    [0016] According to an embodiment of the disclosure, a computer storage medium is also provided. Computer executable instructions may be stored in the computer storage medium and may be configured to perform the above method.

    [0017] By means of the method and apparatus for correcting data error, and the computer storage medium provided by the embodiments of the disclosure, an index number is set for each data bit, and a first check code is generated according to the index numbers; and a second check code is generated according to the first check code, the first check code is compared with the second check code to determine an erroneous data bit, and the erroneous data bit is corrected. In such a way, the first check code can be obtained on the basis of the index number set for each data bit, the second check code is obtained on the basis of the first check code, and the erroneous data bit is determined by comparing the first check code with the second check code; and as the above process is not limited by data bit width and only some pieces of data participate in generation of each check bit of the first check code and each check bit of the second check code, the method may be reused to various occasions while reducing the scales of the check codes, thereby having higher generality.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0018] 

    Fig. 1 is a schematic flowchart of an implementation of a data error correcting method embodiment of the disclosure;

    Fig. 2 is a schematic diagram showing data bits of 8-bit data according to an embodiment of the disclosure;

    Fig. 3 is a schematic diagram showing a correspondence relationship between data bits of 8-bit data and binary index numbers according to an embodiment of the disclosure;

    Fig. 4 is a schematic diagram of a composition structure of a data error correcting apparatus embodiment of the disclosure; and

    Fig. 5 is a schematic diagram of a circuit framework of a data error correcting apparatus embodiment of the disclosure.


    DETAILED DESCRIPTION



    [0019] In the embodiments of the disclosure, an index number is set for each data bit, and a first check code is generated according to the index numbers; and a second check code is generated according to the first check code, the first check code is compared with the second check code to determine an erroneous data bit, and the erroneous data bit is corrected and then output.

    [0020] In the embodiments of the disclosure, when it is needed to perform data reading or data writing, a reading/writing selection signal determines whether data reading or data writing is performed currently, and a binary index number is set for each data bit, there are a one-to-one correspondence relationship between the binary index numbers and the data bits.

    [0021] For the binary index numbers for the respective data bits, an exclusive-or operation is performed on data bits for which corresponding bits of respective binary index numbers are 1 or 0, and obtain a first check code generation expression of each index number bit; after the first check code generation expression of each index number bit is obtained, a result of the first check code generation expression of each index number bit is taken as a corresponding bit of the first check code, and in such a way, each check bit of the first check code may be obtained; and it can be seen that the number of bits of the first check code is identical to that of the binary index number.

    [0022] During data reading or data writing, the second check code is generated by means of an algorithm similar to an algorithm for generating the first check code, and correspondingly, the number of bits the second check code is identical to that of the first check code and that of the binary index number.

    [0023] In practical application, it is not needed to perform error correction for data writing, and therefore written data may be directly output after the first check code and the second check code are obtained; during data reading, if a certain data bit is erroneous, a corresponding bit in the second check code will change; and the erroneous data bit may be determined by comparing the first check code with the second check code, wherein the reading/writing selection signal may control an entire circuit to perform an error correcting operation or an operation of generating the first check code and the second check code.

    [0024] Specifically, during data reading, by performing an exclusive-or operation on corresponding bits of the first check code and the second check code, each corresponding bit of a third check code may be obtained, it may be concluded that a certain check bit of the first check code is inconsistent with a certain check bit of the second check code in a data reading process according to data of each check bit in the third check code, and then an erroneous data bit is obtained according to a first check code generation expression corresponding to the check bit.

    [0025] In practical application, the first check code is probably erroneous in an access process, so that an inspection check code is further set, and it is judged whether the first check code is erroneous in the access process by means of the change of the inspection check code; and if the first check code is erroneous, it is not needed to perform an error correcting operation, and it is directly reported, to an operating system, that the first check code is erroneous.

    [0026] The disclosure is further illustrated below in detail together with drawings and specific embodiments.

    [0027] According to an embodiment of the disclosure, a method for correcting data error is provided. Data input may be data writing or data reading, and a reading/writing selection signal determines whether data reading or data writing is performed currently. Fig. 1 is a schematic flowchart of an implementation of a data error correcting method embodiment of the disclosure. As shown in Fig. 1, by taking 8-bit data as an example, the method includes the steps as follows.

    [0028] Step 101: An index number is set for each data bit, and a first check code is generated according to the index numbers.

    [0029] In this step, each data bit is marked in an order of the data bits. As shown in Fig. 2, Fig. 2 is a schematic diagram showing data bits of 8-bit data according to an embodiment of the disclosure. The 8-bit data is marked with D0, D1, D2, D3, D4, D5, D6 and D7 from a low bit to a high bit, and therefore corresponding decimal index numbers, from a low bit to a high bit, of the 8-bit data are 0, 1, 2, 3, 4, 5, 6 and 7 in sequence; a binary index number corresponding to the decimal index number is set for each bit of the 8-bit data in order of data bits, the decimal index numbers 0-7 may be represented by 3-bit binary number respectively, and therefore the corresponding binary index numbers, from a low bit to a high bit, of the 8-bit data are 000, 001, 010, 011, 100, 101, 110 and 111 in sequence; and the binary index number of each data bit, represented by 3-bit binary number, is composed of a high bit, second low bit and low bit of the binary index number from left to right in sequence.

    [0030] Fig. 3 is a schematic diagram showing a correspondence relationship between data bits of 8-bit data and binary index numbers according to an embodiment of the disclosure. As shown in Fig. 3, the first check code may also be represented by 3-bit binary number, and correspondingly, the first check code represented by 3-bit binary number is composed of a high bit C2, second low bit C1 and low bit C0 of the first check code from left to right in sequence.

    [0031] Specifically, for the binary index numbers for the respective data bits, an exclusive-or operation is performed on data bits for which corresponding bits of respective binary index numbers are 1 or 0, and a first check code generation expression of each index number bit is obtained. For example, an exclusive-or operation is performed on data bits 1 in high bits, second low bits and low bits of respective index numbers, the first check code generation expression of each index number bit is obtained, and a specific operation process is shown in the following formulae:

    where C0 represents a result of performing an exclusive-or operation on all data bits for which low bits of binary index numbers are 1, and D1^D3^D5^D7 is a first check code generation expression of the low bits;

    where C1 represents a result of performing an exclusive-or operation on all data bits for which second low bits of binary index numbers are 1, and D2^D3^D6^D7 is a first check code generation expression of the second low bits;

    where C2 represents a result of performing an exclusive-or operation on all data bits for which high bits of binary index numbers are 1, and D4^D5^D6^D7 is a first check code generation expression of the high bits;
    furthermore, a first total check code may be set for the first check code, and specifically, as shown in Formula (4):

    where Ca represents a result of performing an exclusive-or operation on all data bits and is a first total check code, and D0^D1^D2^D3^D4^D5^D6^D7 is a first total check code generation expression; and

    where C represents a first check code, C0 represents a result of performing an exclusive-or operation on all data bits for which low bits of binary index numbers are 1, C1 represents a result of performing an exclusive-or operation on all data bits for which second low bits of binary index numbers are 1, and C2 represents a result of performing an exclusive-or operation on all data bits for which high bits of binary index numbers are 1.

    [0032] Specifically, as shown in Formula (5), after the first check code generation expression of each index number bit is obtained, a result of the first check code generation expression of each index number bit is taken as a corresponding bit of the first check code. That is, the result C0 of the first check code generation expression D1^D3^D5^D7 of the low bit is taken as a low bit of the first check code; the result C1 of the first check code generation expression D2^D3^D6^D7 of the second low bit is taken as a second low bit of the first check code; the result C2 of the first check code generation expression D4^D5^D6^D7 of the high bit is taken as a high bit of the first check code; and in such a way, each check bit of the first check code is obtained.

    [0033] Step 102: A second check code is generated according to the first check code, the first check code is compared with the second check code to determine an erroneous data bit, and the erroneous data bit is corrected.

    [0034] In this step, during data reading or data writing, the second check code is generated by means of an algorithm similar to an algorithm for generating the first check code, correspondingly, the second check code may also be represented by 3-bit binary number, and the second check code represented by 3-bit binary number is composed of a high bit C'2, second low bit C'1 and low bit C'0 of the second check code from left to right in sequence.

    [0035] Specifically, for the binary index numbers for the respective data bits of the input data, an exclusive-or operation is performed on data bits of input data, for which corresponding bits of respective binary index numbers are 1 or 0, and a second check code generation expression of each index number bit is obtained. For example, an exclusive-or operation is performed on data bits for which high bits, second low bits and low bits of respective index numbers are 1, the second check code generation expression of each index number bit is obtained, and a specific operation process is shown in the following formulae:

    where C'0 represents a result of performing an exclusive-or operation on all data bits for which low bits of binary index numbers of the input data are 1, and D'1^D'3^D5'^D'7, is a second check code generation expression of the low bits;

    where C'1 represents a result of performing an exclusive-or operation on all data bits for which second low bits of binary index numbers of the input data are 1, and D'2^D'3^D'6^D'7, is a second check code generation expression of the second low bits;

    where C'2 represents a result of performing an exclusive-or operation on all data bits for which high bits of binary index numbers of the input data are 1, and D'4^D'5^D'6^D'7 is a second check code generation expression of the high bits;
    furthermore, a second total check code may be set for the second check code, and specifically, as shown in Formula (9):

    where C'a represents a result of performing an exclusive-or operation on all data bits of the input data and is a second total check code, and D'0^D'1^D'2^D'3^D'4^D'5^D'6^D'7 is a second total check code generation expression; and

    where C' represents a second check code, C'0 represents a result of performing an exclusive-or operation on all data bits of input data, for which low bits of binary index numbers are 1, C'1 represents a result of performing an exclusive-or operation on all data bits of input data, for which second low bits of binary index numbers are 1, and C'2 represents a result of performing an exclusive-or operation on all data bits of input data, for which high bits of binary index numbers are 1.

    [0036] Specifically, as shown in Formula (10), after the second check code generation expression of each index number bit of the input data is obtained, a result of the second check code generation expression of each index number bit of the input data is taken as a corresponding bit of the second check code. That is, the result C'0 of the second check code generation expression D'1^D'3^D'5^D'7 of the low bit is taken as a low bit of the second check code; the result C'1 of the second check code generation expression D'2^D'3^D'6^D'7 of the second low bit is taken as a second low bit of the second check code; the result C'2 of the second check code generation expression D'4^D'5^D'6^D'7 of the high bit is taken as a high bit of the second check code; and in such a way, each check bit of the second check code is obtained.

    [0037] It is not needed to perform an error correcting operation during data writing, and therefore written data is directly output after the first check code and the second check code are obtained; during data reading, if a certain data bit is erroneous, a corresponding bit in the second check code will change; and the erroneous data bit may be determined by comparing the first check code with the second check code. Here, during data reading, it is assumed that errors only occur on a data bit instead of a first check bit.

    [0038] Specifically, during data reading, an exclusive-or operation is performed on corresponding bits of the first check code and the second check code to obtain respective bits of a third check code, and a specific operation process is shown in the following formulae:

    where S0 represents a result of performing an exclusive-or operation on a low bit of a first check code and a low bit of a second check code, and C0^C'0 is a third check code generation expression of a low bit;

    where S1 represents a result of performing an exclusive-or operation on a second low bit of a first check code and a second low bit of a second check code, and C1^C'1 is a third check code generation expression of a second low bit;

    where S2 represents a result of performing an exclusive-or operation on a high bit of a first check code and a high bit of a second check code, and C2^C'2 is a third check code generation expression of a high bit;
    furthermore, a third total check code may be set for the third check code, and specifically, as shown in Formula (14):

    where Sa represents a result of performing an exclusive-or operation on a first total check code and a second total check code, and Ca^C'a is a third total check code generation expression; and

    where S represents a third check code, S0 represents a result of performing an exclusive-or operation on a low bit of a first check code and a low bit of a second check code, S1 represents a result of performing an exclusive-or operation on a second low bit of a first check code and a second low bit of a second check code, and S2 represents a result of performing an exclusive-or operation on a high bit of a first check code and a high bit of a second check code.

    [0039] During data reading, if a certain bit among S2, S1 and S0 is 1, it is represented that the C2 bit of the first check code and the C'2 bit of the second check code, or the C1 bit of the first check code and the C'1 bit of the second check code or the C0 bit of the first check code and the C'0 bit of the second check code, corresponding to each other, are inconsistent. Here, the situation that the Sa bit is 1 is omitted, and only the situation that the S2, S1 or S0 bits are 1 is considered. That is, only the situation that a certain data bit corresponding to C2, C1 and C0 is erroneous in a data reading process is considered.

    [0040] Specifically, during data reading, if the S0 bit is 1 and the S2 and S1 bits are 0, it is represented that the C0 bit of the first check code and the C'0 bit of the second check code are inconsistent, the C1 bit of the first check code and the C'1 bit of the second check code are consistent and the C2 bit of the first check code and the C'2 bit of the second check code are consistent, and according to a first check code generation expression of the C0 bit, it can be seen that a certain data bit among D1, D3, D5 and D7 is erroneous during data reading. That is, one of all data bits for which low bits of binary index numbers are 1 is erroneous.

    [0041] Similarly, if the S1 bit is 1 and the S0 and S2 bits are 0, it is represented that the C1 bit of the first check code and the C'1 bit of the second check code are inconsistent, the C0 bit of the first check code and the C'0 bit of the second check code are consistent and the C2 bit of the first check code and the C'2 bit of the second check code are consistent, and according to a first check code generation expression of the C1 bit, it can be seen that a certain data bit among D2, D3, D6 and D7 is erroneous during data reading. That is, one of all data bits for which second low bits of binary index numbers are 1 is erroneous.

    [0042] If the S2 bit is 1 and the S0 and S1 bits are 0, it is represented that the C2 bit of the first check code and the C'2 bit of the second check code are inconsistent, the C0 bit of the first check code and the C'0 bit of the second check code are consistent and the C1 bit of the first check code and the C'1 bit of the second check code are consistent, and according to a first check code generation expression of the C2 bit, it can be seen that a certain data bit among D4, D5, D6 and D7 is erroneous during data reading. That is, one of all data bits for which high bits of binary index numbers are 1 is erroneous. Then, a range of erroneous data bits is concluded according to the corresponding first check code generation expressions.

    [0043] For example, if S=001, it is represented that the C0 bit of the first check code and the C'0 bit of the second check code are inconsistent. That is, in the data reading process, a certain data bit among D1, D3, D5 and D7 is erroneous; and D1 only exists in the first check code generation expression of the C0 bit, and according to the condition that data bits corresponding to the C1 bit and data bits corresponding to the C2 bit are not erroneous, it can be seen that data bits D3, D5 and D7 are not erroneous, so that it may be judged that the D1 bit is erroneous in the data reading process.

    [0044] In addition, from S=001, it can be seen that in the data reading process, a certain data bit corresponding to the C0 bit is erroneous and data bits corresponding to the C1 bit and data bits corresponding to the C2 bit are not erroneous; and according to a relationship between the C0, C1 and C2 bits and a binary index number, it can be seen that a low bit of the binary index number corresponding to the erroneous data bit is 1, and a second low bit and a high bit are 0, so it is determined that the binary index number corresponding to the erroneous data bit is a 3-bit binary number 3'b001, and the 3-bit binary number is converted to a decimal number 3'd1. Thus, it may be directly judged that the D1 bit corresponding to a decimal index number 1 is erroneous in the data reading process.

    [0045] If S=101, it is represented that the C0 bit of the first check code and the C2 bit of the second check code are inconsistent. That is, a certain data bit among D1, D3, D4, D5, D6 and D7 is erroneous in the data reading process, and data bits corresponding to C1 are not erroneous in the data reading process; and only D5 exists in the first check code generation expressions of the C0 bit and the C2 bit simultaneously and does not exist in the first check code generation expression of the C1 bit, and therefore it may be judged that the D5 bit is erroneous in the data reading process.

    [0046] In addition, from S=101, it can be seen that in the data reading process, a certain data bit of data bits corresponding to the C0 bit and data bits corresponding to the C2 bit is erroneous and data bits corresponding to the C1 bit are not erroneous in the data reading process; and according to a relationship between the C0, C1 and C2 bits and a binary index number, it can be seen that a low bit of the binary index number corresponding to the erroneous data bit is 1, a second low bit is 0, and a high bit is 1, so it is determined that the binary index number corresponding to the erroneous data bit is a 3-bit binary number 3'b101, and the 3-bit binary number is converted to a decimal number 3'd5. Thus, it may be directly judged that the D5 bit corresponding to a decimal index number 5 is erroneous in the data reading process.

    [0047] Furthermore, in view of that a decimal index number corresponding to the D0 bit is 0, a binary index number is 000 and the D0 bit is the only data bit which does not exist in the first check code generation expressions of the C2, C1 and C0 bits, if all of the C2, C1 and C0 bits in S are 0 and Sa is 1, it is represented that the D0 bit is erroneous during data reading; if not all of the C2, C1 and C0 bits in S are 0 and Sa is 0, it is represented that two bits are erroneous during data reading; and in this case, it is beyond an error correcting capability, it is directly reported, to an operating system, that errors cannot be corrected, and the operating system decides whether it is needed to discard the data and to re-read data.

    [0048] According to the first check code generation expression of the C2 bit, it can be seen that only D4, D5, D6 and D7 participate in the first check code generation expression of the C2; in this way, if it is needed to apply the method to the situation that a data bit width is 4 bits, the C2 bit may be omitted; and due to the fact that the D4, D5, D6 and D7 bits do not exist in four-bit data, by filling corresponding data bits in the first check code generation expressions and the second check code generation expressions with 0 or 1, a final result of a third check code may not be influenced, so the method may be simply reused to an application where the data bit width is 4 bits. Thus, by means of a similar method, the embodiments of the disclosure may be promoted to an application where a data bit width is 32 bits, 64 bits, 128 bits or higher bits.

    [0049] In practical application, since the first check code is probably erroneous in an access process, an inspection check code may be further set, and it is judged whether the first check code is erroneous in the access process by means of the change of the inspection check code. Specifically, as shown in Formula (16):

    where Cc represents an inspection check code, C2 represents a result of performing an exclusive-or operation on all data bits for which high bits of binary index numbers are 1, C1 represents a result of performing an exclusive-or operation on all data bits for which second low bits of binary index numbers are 1, C0 represents a result of performing an exclusive-or operation on all data bits for which low bits of binary index numbers are 1, and Ca represents a result of performing an exclusive-or operation on all data bits.

    [0050] In practical application, a user only concerns valid data, so if errors occur in a first check code, it is not needed to perform an error correcting operation, and it is directly reported, to an operating system, that the first check code is erroneous.

    [0051] Here, after an erroneous data bit is determined, the erroneous data bit is corrected. A specific correcting process is the traditional art, which will not be elaborated herein.

    [0052] According to an embodiment of the disclosure, a data error correcting apparatus is provided. Data input may be data writing or data reading, and a reading/writing selection signal determines whether data reading or data writing is performed currently. That is, the reading/writing selection signal controls an entire circuit to perform an error correcting operation or an operation of generating a first check code and a second check code. Fig. 4 is a schematic diagram of a composition structure of a data error correcting apparatus embodiment of the disclosure. Fig. 5 is a schematic diagram of a circuit framework of a data error correcting apparatus embodiment of the disclosure. As shown in Fig. 4 and Fig. 5, the apparatus includes: a setting module 43, a first check code generation module 44, a second check code generation module 45 and a data processing module 46, wherein
    the setting module 43 is configured to set an index number for each data bit; and
    specifically, the setting module 43 is configured to set a binary index number for each data bit in an order of data bits.

    [0053] The first check code generation module 44 is configured to generate a first check code according to the index numbers.

    [0054] Specifically, during data reading or data writing, the first check code generation module 44 is configured to perform an exclusive-or operation on data bits for which corresponding bits of respective binary index numbers are 1 or 0, for the binary index numbers for the respective data bits, and obtain a first check code generation expression of each index number bit and take a result of the first check code generation expression of each index number bit as a corresponding bit of the first check code.

    [0055] The first check code generation module 44 is further configured to obtain a first total check code by performing an exclusive-or operation on all data bits.

    [0056] For an application where it is needed to performa reading operation and a writing operation simultaneously, a data reading first check code generation module and a data writing first check code generation module may be provided separately, and the data reading first check code generation module and the data writing first check code generation module generate respective first check codes independently; and for an application where it is not needed to perform the reading operation and the writing operation simultaneously, only one first check code generation module may be provided so as to reduce the scale of hardware logics.

    [0057] The second check code generation module 45 is configured to generate a second check code according to the first check code.

    [0058] Specifically, during data reading or data writing, the second check code generation module 45 is configured to perform an exclusive-or operation on data bits of input data, for which corresponding bits of respective binary index numbers are 1 or 0 for the binary index numbers for the respective data bits of the input data, and obtain a second check code generation expression of each index number bit and take a result of the second check code generation expression of each index number bit as a corresponding bit of the second check code.

    [0059] For an application where it is needed to perform the reading operation and the writing operation simultaneously, a data reading second check code generation module and a data writing second check code generation module may be provided separately, and the data reading second check code generation module and the data writing second check code generation module generate respective second check codes independently; and for an application where it is not needed to perform the reading operation and the writing operation simultaneously, only one second check code generation module may be provided so as to reduce the scale of hardware logics.

    [0060] The second check code generation module 45 is further configured to obtain a second total check code by performing an exclusive-or operation on all data bits of the input data.

    [0061] The data processing module 46 is configured to compare the first check code with the second check code to determine an erroneous data bit, and correct the erroneous data bit.

    [0062] Specifically, during data reading, the data processing module 46 is configured to perform an exclusive-or operation on each bit of the first check code and a responding bit of the second check code to obtain a corresponding bit of a third check code, determine, when it is determined that the corresponding bits of the first check code and the second check code are inconsistent according to the third check code, an erroneous data bit according to the first check code generation expressions of the corresponding bits of the first check code, correct the erroneous data bit, and then output the corrected data; and since it is not needed to perform an error correcting operation during data writing, the data processing module 46 directly outputs the written data.

    [0063] In addition, since it is not needed to perform the error correcting operation during data writing, the reading operation and the writing operation may share a data processing module.

    [0064] Furthermore, the apparatus may include: a data reading/writing module 41 and a multiplex transmission module 42, wherein
    the data reading/writing module 41 is configured to transmit data in a reading operation or a writing operation; and
    for an application where it is needed to perform the reading operation and the writing operation simultaneously, a data reading module and a data writing module may be provided separately, and the data reading module and the data writing module transmit the data in the reading operation or the writing operation independently.

    [0065] The multiplex transmission module 42 is configured to transmit the data of the data reading/writing module.

    [0066] Specifically, when it is needed to perform data writing, a reading/writing selection signal enables the writing operation, the multiplex transmission module 42 selects the data of the data reading/writing module to be input to the setting module 43; and when it is needed to perform data reading, the reading/writing selection signal enables the reading operation, the multiplex transmission module 42 selects the data of the data reading/writing module to be input to the setting module 43.

    [0067] In practical application, the multiplex transmission module 42 may be implemented by a multiplexer; the data reading/writing module 41, the setting module 43, the first check code generation module 44, the second check code generation module 45 and the data processing module 46 may be implemented by a Central Processing Unit (CPU), a Digital Signal Processor (DSP) or a Field Programmable Gate Array (FPGA).

    [0068] According to an embodiment of the disclosure, a computer storage medium is also provided. Computer executable instructions are stored in the computer storage medium and are configured to perform the method according to the embodiment of the disclosure.

    [0069] If the data error correcting method in the embodiment of the disclosure is implemented in a form of a software function module and is sold or used as an independent product, the product may also be stored in a computer readable storage medium. Based on this understanding, those skilled in the art shall understand that the embodiments of the disclosure may be provided as a method, a system or a computer program product. Thus, forms of hardware embodiments, software embodiments or embodiments combining software and hardware may be adopted in the disclosure. Moreover, a form of computer program product implemented on one or more computer available storage media containing computer available program codes may be adopted in the disclosure. The storage media include, but are not limited to, a U disk, a mobile hard disk, a Read-Only Memory (ROM), a magnetic disk memory, a CD-ROM, an optical memory and the like.

    [0070] The disclosure is described with reference to flowcharts and/or block diagrams of a method, an apparatus and a computer program product according to the embodiments of the disclosure. It will be appreciated that each flow and/or block in the flowcharts and/or the block diagrams and the combination of the flows and/or the blocks in the flowcharts and/or the block diagrams may be implemented by computer program instructions. These computer program instructions may be provided for a general purpose computer, a dedicated computer, an embedded processor or processors of other programmable data processing devices to generate a machine, such that an apparatus for achieving functions designated in one or more flows of the flowcharts and/or one or more blocks of the block diagrams is generated via instructions executed by the processors of the computers or the other programmable data processing devices.

    [0071] These computer program instructions may also be stored in a computer readable memory capable of guiding the computers or the other programmable data processing devices to work in a specific mode, such that a manufactured product including an instruction apparatus is generated via the instructions stored in the computer readable memory, and the instruction apparatus achieves the functions designated in one or more flows of the flowcharts and/or one or more blocks of the block diagrams.

    [0072] These computer program instructions may also be loaded onto the computers or the other programmable data processing devices, such that processing implemented by the computers is generated by performing a series of operation steps on the computers or the other programmable devices, and therefore the instructions performed on the computers or the other programmable devices provide a step of achieving the functions designated in one or more flows of the flowcharts and/or one or more blocks of the block diagrams.

    [0073] Correspondingly, according to an embodiment of the disclosure, a computer storage medium is also provided. Computer programs are stored therein and are configured to perform the method for correcting the data error according to the method embodiment of the disclosure.

    [0074] The above is only the preferred embodiments of the disclosure and is not intended to limit the protective scope of the disclosure.


    Claims

    1. A method for correcting a data error in data having 2n data bits where n>2, the method comprising:

    setting (101), for each data bit, n-bit binary index numbers corresponding to the decimal index numbers 0, ..., 2n-1 of the data bits;

    obtaining n first check code generation expressions according to the binary index numbers, and generating a first check code according to the n first check code generation expressions; and

    obtaining n second check code generation expressions according to the binary index numbers, and generating the second check code according to the n second check code generation expressions; and

    comparing (102) the first check code with the second check code to determine an erroneous data bit, and correcting the erroneous data bit:

    characterized in that the step of obtaining the n first check code generation expressions according to the n-bit binary index numbers and generating the n first check code according to the n first check code generation expressions comprises:

    performing, for each bit of the n binary index number bits, an exclusive-or operation only on data bits of the data for which corresponding bits of respective binary index numbers is 1, or performing, for each bit of the n binary index number bits, an exclusive-or operation only on data bits of the data for which corresponding bits of respective binary index numbers is 0, in order to obtain one of the n first check code generation expressions; and

    determining a result of each of the n first check code generation expressions and taking the result as a corresponding bit of the first check code;

    and in that the method further comprises the step of:
    generating a total check code by performing an exclusive-or operation on all the data bits of the data.


     
    2. The method according to claim 1, wherein the step of obtaining the n second check code generation expressions according to the binary index numbers and generating the second check code according to the n second check code generation expressions comprises:

    performing, for each bit of the n binary index number bits, an exclusive-or operation on data bits of the data for which corresponding bit of the respective binary index numbers is 1, or performing, for each bit of the n binary index number bits, an exclusive-or operation on data bits of the data for which corresponding bit of the respective binary index numbers is 0, in order to obtain one of the n second check code generation expressions; and

    determining a result of each of the n second check code generation expressions and taking the result as a corresponding bit of the second check code.


     
    3. The method according to claim 1 or 2, wherein the step of comparing the first check code with the second check code to determine an erroneous data bit and correcting the erroneous data bit comprises:
    performing an exclusive-or operation on each bit of the first check code and a corresponding bit of the second check code to obtain a corresponding bit of a third check code, when it is determined that the corresponding bits of the first check code and the second check code are inconsistent according to the third check code, determining an erroneous data bit according to the first check code generation expressions of the corresponding bits of the first check code, and correcting the erroneous data bit.
     
    4. An apparatus for correcting a data error in data having 2n data bits where n>2, the apparatus comprising: a setting module (43), a first check code generation module (44), a second check code generation module (45) and a data processing module (46), wherein the setting module (43) is configured to set, for each data bit, n-bit binary index numbers corresponding to the decimal index number 0, ..., 2n-1 of the data bits;
    the first check code generation module (44) is configured to obtain n first check code generation expressions according to the binary index numbers, and to generate a first check code according to the n first check code generation expressions;
    the second check code generation module (45) is configured to obtain n second check code generation expressions according to the binary index numbers, and to generate a second check code according to the n second check code generation expressions; and
    the data processing module (46) is configured to compare the first check code with the second check code to determine an erroneous data bit, and correct the erroneous data bit;
    characterized in that the first check code generation module (44) is configured to:

    perform, for each bit of the n binary index number bits, an exclusive-or operation only on data bits for which the corresponding bit of respective binary index numbers is 1, or to perform, for each bit of the n binary index number bits, an exclusive-or operation only on data bits for which the corresponding bit of respective binary index numbers is 0, in order to obtain one of the n first check code generation expressions; and

    determine a result of each of the n first check code generation expressions and to take the result as a corresponding bit of the first check code;

    and in that the apparatus further comprises a total check code generation module configured to generate a total check code by performing an exclusive-or operation on all the data bits of the data.
     
    5. The apparatus according to claim 4, wherein the second check code generation module (45) is configured to:

    perform, for each bit of the n binary index number bits, an exclusive-or operation on data bits of the data for which the corresponding bit of respective binary index number is 1 or to perform, for each bit of the n binary index number bits, an exclusive-or operation on data bits of the data for which the corresponding bit of respective binary index number is 0, in order to obtain one of the n second check code generation expressions; and

    determine a result of each of the n second check code generation expressions and to take the result as a corresponding bit of the second check code.


     
    6. The apparatus according to claim 4 or 5, wherein the data processing module is configured to perform an exclusive-or operation on each bit of the first check code and a corresponding bit of the second check code to obtain a corresponding bit of a third check code, determine, when it is determined that the corresponding bits of the first check code and the second check code are inconsistent according to the third check code, an erroneous data bit according to the first check code generation expressions of the corresponding bits of the first check code, and correct the erroneous data bit.
     
    7. A computer storage medium storing therein computer executable instructions for performing the method according to any one of claims 1 to 3.
     


    Ansprüche

    1. Verfahren zur Korrektur eines Datenfehlers in Daten, die 2n Datenbits aufweisen, wo n>2 ist, wobei das Verfahren umfasst:

    - Einstellen (101), für jedes Datenbit, von n-Bit binären Indexnummern, entsprechend der dezimalen Indexnummern 0, ..., 2n-1 der Datenbits;

    - Erhalten von n ersten Prüfcodeerzeugungsausdrücken gemäß den binären Indexnummern und Erzeugen eines ersten Prüfcodes gemäß den n ersten Prüfcodeerzeugungsausdrücken; und

    - Erhalten von n zweiten Prüfcodeerzeugungsausdrücken gemäß der binären Indexnummern und Erzeugen des zweiten Prüfcodes gemäß den n zweiten Prüfcodeerzeugungsausdrücken; und

    - Vergleichen (102) des ersten Prüfcodes mit dem zweiten Prüfcode, um ein fehlerhaftes Datenbit zu ermitteln, und Korrigieren des fehlerhaften Datenbits:

    - dadurch gekennzeichnet, dass der Schritt zum Erhalten der n ersten Prüfcodeerzeugungsausdrücke gemäß den n-Bit binären Indexnummern und Erzeugen des n ersten Prüfcodes gemäß den n ersten Prüfcodeerzeugungsausdrücken umfasst:

    - Durchführen, für jedes Bit der n binären Indexnummernbits, einer Exklusiv-Oder-Operation nur an Datenbits der Daten, für die entsprechende Bits jeweiliger binärer Indexnummern 1 sind, oder Durchführen, für jedes Bit der n binären Indexnummernbits, einer Exklusiv-Oder-Operation nur an Datenbits der Daten, für die entsprechende Bits jeweiliger binärer Indexnummern 0 sind, um einen der n ersten Prüfcodeerzeugungsausdrücke zu erhalten; und

    - Ermitteln eines Ergebnisses von jedem der n ersten Prüfcodeerzeugungsausdrücke und Heranziehen des Ergebnisses als ein entsprechendes Bit des ersten Prüfcodes;

    - und dadurch, dass das Verfahren weiter den Schritt umfasst:

    - Erzeugen eines gesamten Prüfcodes, indem eine Exklusiv-Oder-Operation an allen Datenbits der Daten durchgeführt wird.


     
    2. Verfahren nach Anspruch 1, wobei der Schritt zum Erhalten der n zweiten Prüfcodeerzeugungsausdrücke gemäß den binären Indexnummern und Erzeugen des zweiten Prüfcodes gemäß den n zweiten Prüfcodeerzeugungsausdrücken umfasst:

    - Durchführen, für jedes Bit der n binären Indexnummernbits, einer Exklusiv-Oder-Operation an Datenbits der Daten, für welche ein entsprechendes Bit der jeweiligen binären Indexnummern 1 ist, oder Durchführen, für jedes Bit der n binären Indexnummernbits, einer Exklusiv-Oder-Operation an Datenbits der Daten, für die ein entsprechendes Bit der jeweiligen binären Indexnummern 0 ist, um einen der n zweiten Prüfcodeerzeugungsausdrücke zu erhalten; und
    Ermitteln eines Ergebnisses von jedem der n zweiten Prüfcodeerzeugungsausdrücke und Heranziehen des Ergebnisses als ein entsprechendes Bit des zweiten Prüfcodes.


     
    3. Verfahren nach Anspruch 1 oder 2, wobei der Schritt zum Vergleichen des ersten Prüfcodes mit dem zweiten Prüfcode, um ein fehlerhaftes Datenbit zu ermitteln, und zum Korrigieren des fehlerhaften Datenbits umfasst:

    - Durchführen einer Exklusiv-Oder-Operation an jedem Bit des ersten Prüfcodes und einem entsprechenden Bit des zweiten Prüfcodes, um ein entsprechendes Bit eines dritten Prüfcodes zu erhalten, wenn ermittelt wird, dass die entsprechenden Bits des ersten Prüfcodes und des zweiten Prüfcodes gemäß dem dritten Prüfcode inkonsistent sind, Ermitteln eines fehlerhaften Datenbits gemäß den ersten Prüfcodeerzeugungsausdrücken der entsprechenden Bits des ersten Prüfcodes und Korrigieren des fehlerhaften Datenbits.


     
    4. Einrichtung zum Korrigieren eines Datenfehlers in Daten, die 2n Datenbits aufweisen, wo n>2 ist, wobei die Einrichtung umfasst: ein Einstellungsmodul (43), ein erstes Prüfcodeerzeugungsmodul (44), ein zweites Prüfcodeerzeugungsmodul (45) und ein Datenverarbeitungsmodul (46), wobei das Einstellungsmodul (43) konfiguriert ist, für jedes Datenbit n-Bit binäre Indexnummern entsprechend der dezimalen Indexnummer 0, ..., 2n-1 der Datenbits einzustellen;

    - das erste Prüfcodeerzeugungsmodul (44) konfiguriert ist, n erste Prüfcodeerzeugungsausdrücke gemäß den binären Indexnummern zu erhalten und einen ersten Prüfcode gemäß den n ersten Prüfcodeerzeugungsausdrücken zu erzeugen;

    - das zweite Prüfcodeerzeugungsmodul (45) konfiguriert ist, n zweite Prüfcodeerzeugungsausdrücke gemäß den binären Indexnummern zu erhalten und einen zweiten Prüfcode gemäß den n zweiten Prüfcodeerzeugungsausdrücken zu erzeugen; und

    - das Datenverarbeitungsmodul (46) konfiguriert ist, den ersten Prüfcode mit dem zweiten Prüfcode zu vergleichen, um ein fehlerhaftes Datenbit zu ermitteln, und das fehlerhafte Datenbit zu korrigieren;

    - dadurch gekennzeichnet, dass das erste Prüfcodeerzeugungsmodul (44) konfiguriert ist zum:

    - Durchführen, für jedes Bit der n binären Indexnummernbits, einer Exklusiv-Oder-Operation nur an Datenbits, für die das entsprechende Bit jeweiliger binärer Indexnummern 1 ist, oder Durchführen, für jedes Bit der n binären Indexnummernbits, einer Exklusiv-Oder-Operation nur an Datenbits, für die das entsprechende Bit jeweiliger binärer Indexnummern 0 ist, um einen der n ersten Prüfcodeerzeugungsausdrücke zu erhalten; und

    - Ermitteln eines Ergebnisses von jedem der n ersten Prüfcodeerzeugungsausdrücke und Heranziehen des Ergebnisses als ein entsprechendes Bit des ersten Prüfcodes;

    - und dadurch, dass die Einrichtung weiter ein gesamtes Codeerzeugungsmodul umfasst, das konfiguriert ist, einen gesamten Prüfcode zu erzeugen, indem eine Exklusiv-Oder-Operation an allen Datenbits der Daten durchgeführt wird.


     
    5. Einrichtung nach Anspruch 4, wobei das zweite Prüfcodeerzeugungsmodul (45) konfiguriert ist zum:

    - Durchführen, für jedes Bit der n binären Indexnummernbits, einer Exklusiv-Oder-Operation an Datenbits der Daten, für die das entsprechende Bit einer jeweiligen binären Indexnummer 1 ist, oder Durchführen, für jedes Bit der n binären Indexnummernbits, einer Exklusiv-Oder-Operation an Datenbits der Daten, für die das entsprechende Bit einer jeweiligen binären Indexnummer 0 ist, um einen der n zweiten Prüfcodeerzeugungsausdrücke zu erhalten; und

    - Ermitteln eines Ergebnisses von jedem der n zweiten Prüfcodeerzeugungsausdrücke und Heranziehen des Ergebnisses als ein entsprechendes Bit des zweiten Prüfcodes.


     
    6. Einrichtung nach Anspruch 4 oder 5, wobei das Datenverarbeitungsmodul konfiguriert ist, eine Exklusiv-Oder-Operation an jedem Bit des ersten Prüfcodes und einem entsprechenden Bit des zweiten Prüfcodes durchzuführen, um ein entsprechendes Bit eines dritten Prüfcodes zu erhalten, wenn ermittelt ist, dass die entsprechenden Bits des ersten Prüfcodes und des zweiten Prüfcodes gemäß dem dritten Prüfcodes inkonsistent sind, ein fehlerhaftes Datenbit gemäß den ersten Prüfcodeerzeugungsausdrücken der entsprechenden Bits des ersten Prüfcodes zu ermitteln und das fehlerhafte Datenbit zu korrigieren.
     
    7. Computerspeichermedium, das computerausführbare Anweisungen zum Durchführen des Verfahrens nach einem der Ansprüche 1 bis 3 darin speichert.
     


    Revendications

    1. Procédé de correction d'une erreur de données dans des données ayant 2n bits de données, où n>2, le procédé comprenant les étapes de :

    réglage (101), pour chaque bit de données, de numéros d'index binaires de n bits correspondant aux numéros d'index décimaux 0, ..., 2n-1 des bits de données ;

    obtention de n expressions de génération de premier code de vérification conformément aux numéros d'index binaires, et génération d'un premier code de vérification conformément aux n expressions de génération de premier code de vérification ; et

    obtention de n expressions de génération de deuxième code de vérification conformément aux numéros d'index binaires, et génération du deuxième code de vérification conformément aux n expressions de génération de deuxième code de vérification ; et

    comparaison (102) du premier code de vérification et du deuxième code de vérification pour déterminer un bit de données erroné, et correction du bit de données erroné :
    caractérisé en ce que l'étape d'obtention des n expressions de génération de premier code de vérification conformément aux numéros d'index binaires de n bits et de génération du premier code de vérification conformément aux n expressions de génération de premier code de vérification comprend les étapes de :

    réalisation, pour chaque bit des n bits de numéros d'index binaires, d'une opération OU exclusif uniquement sur des bits de données des données pour lesquelles des bits correspondants de numéros d'index binaires respectifs est de 1, ou réalisation, pour chaque bit des n bits de numéros d'index binaires, d'une opération OU exclusif uniquement sur des bits de données des données pour lesquelles un bit correspondant de numéros d'index binaires respectifs est de 0, afin d'obtenir l'une des n expressions de génération de premier code de vérification ; et

    détermination d'un résultat de chacune des n expressions de génération de premier code de vérification et considération du résultat en tant que bit correspondant du premier code de vérification ; et

    en ce que le procédé comprend en outre l'étape de :
    génération d'un code de vérification total en effectuant une opération OU exclusif sur tous les bits de données des données.


     
    2. Procédé selon la revendication 1, dans lequel l'étape d'obtention des n expressions de génération de deuxième code de vérification conformément aux numéros d'index binaires et de génération de deuxième code de vérification conformément aux n expressions de génération de deuxième code de vérification comprend les étapes de :

    réalisation, pour chaque bit des n bits de numéros d'index binaires, d'une opération OU exclusif sur des bits de données des données pour lesquelles un bit correspondant des numéros d'index binaires respectifs est de 1, ou réalisation, pour chaque bit des n bits de numéros d'index binaires, d'une opération OU exclusif sur des bits de données des données pour lesquelles un bit correspondant des numéros d'index binaires respectifs est de 0, afin d'obtenir l'une des n expressions de génération de deuxième code de vérification ; et

    détermination d'un résultat de chacune des n expressions de génération de deuxième code de vérification et considération du résultat en tant que bit correspondant du deuxième code de vérification.


     
    3. Procédé selon la revendication 1 ou 2, dans lequel l'étape de comparaison du premier code de vérification avec le deuxième code de vérification pour déterminer un bit de données erroné et corriger le bit de données erroné comprend les étapes de :
    réalisation d'une opération OU exclusif sur chaque bit du premier code de vérification et un bit correspondant du deuxième code de vérification pour obtenir un bit correspondant d'un troisième code de vérification, lorsqu'il est déterminé que les bits correspondants du premier code de vérification et du deuxième code de vérification sont incompatibles conformément au troisième code de vérification, détermination d'un bit de données erroné conformément aux expressions de génération de premier code de vérification des bits correspondants du premier code de vérification, et correction du bit de données erroné.
     
    4. Appareil de correction d'une erreur de données dans des données ayant 2n bits de données, où n>2, l'appareil comprenant : un module de réglage (43), un module de génération de premier code de vérification (44), un module de génération de deuxième code de vérification (45) et un module de traitement de données (46), dans lequel le module de réglage (43) est configuré pour régler, pour chaque bit de données, des numéros d'index binaires de n bits correspondant aux numéros d'index décimaux 0, ..., 2n-1 des bits de données ;
    le module de génération de premier code de vérification (44) est configuré pour obtenir n expressions de génération de premier code de vérification conformément aux numéros d'index binaires, et générer un premier code de vérification conformément aux n expressions de génération de premier code de vérification ;
    le module de génération de deuxième code de vérification (45) est configuré pour obtenir n expressions de génération de deuxième code de vérification conformément aux numéros d'index binaires, et générer un deuxième code de vérification conformément aux n expressions de génération de deuxième code de vérification ; et
    le module de traitement de données (46) est configuré pour comparer le premier code de vérification au deuxième code de vérification pour déterminer un bit de données erroné, et corriger le bit de données erroné ;
    caractérisé en ce que le module de génération de premier code de vérification (44) est configuré pour :

    réaliser, pour chaque bit des n bits de numéros d'index binaires, une opération OU exclusif uniquement sur des bits de données des données pour lesquelles le bit correspondant de numéros d'index binaires respectifs est de 1, ou réaliser, pour chaque bit des n bits de numéros d'index binaires, une opération OU exclusif uniquement sur des bits de données des données pour lesquelles le bit correspondant de numéros d'index binaires respectifs est de 0, afin d'obtenir l'une des n expressions de génération de premier code de vérification ; et

    déterminer un résultat de chacune des n expressions de génération de premier code de vérification et considérer le résultat en tant que bit correspondant du premier code de vérification ; et

    en ce que l'appareil comprend en outre un module de génération de code de vérification total configuré pour générer un code de vérification total en effectuant une opération OU exclusif sur tous les bits de données des données.


     
    5. Appareil selon la revendication 4, dans lequel le module de génération de deuxième code de vérification (45) est configuré pour :

    réaliser, pour chaque bit des n bits de numéros d'index binaires, une opération OU exclusif sur des bits de données des données pour lesquelles le bit correspondant de numéros d'index binaires respectifs est de 1 ou réaliser, pour chaque bit des n bits de numéros d'index binaires, une opération OU exclusif sur des bits de données des données pour lesquelles le bit correspondant de numéros d'index binaires respectifs est de 0, afin d'obtenir l'une des n expressions de génération de deuxième code de vérification ; et

    déterminer un résultat de chacune des n expressions de génération de deuxième code de vérification et considérer le résultat en tant que bit correspondant du deuxième code de vérification.


     
    6. Appareil selon la revendication 4 ou 5, dans lequel le module de traitement de données est configuré pour effectuer une opération OU exclusif sur chaque bit du premier code de vérification et sur un bit correspondant du deuxième code de vérification pour obtenir un bit correspondant d'un troisième code de vérification, déterminer, lorsqu'il est déterminé que les bits correspondants du premier code de vérification et du deuxième code de vérification sont incompatibles conformément au troisième code de vérification, un bit de données erroné conformément aux expressions de génération de premier code de vérification des bits correspondants du premier code de vérification, et corriger le bit de données erroné.
     
    7. Support de stockage d'ordinateur stockant des instructions exécutables par ordinateur pour effectuer le procédé selon l'une quelconque des revendications 1 à 3.
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description