(19)
(11)EP 3 089 562 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
13.07.2022 Bulletin 2022/28

(21)Application number: 14875182.9

(22)Date of filing:  21.05.2014
(51)International Patent Classification (IPC): 
H05K 3/46(2006.01)
H05K 1/11(2006.01)
H05K 3/42(2006.01)
(52)Cooperative Patent Classification (CPC):
H05K 3/429; H05K 2201/10303; H05K 3/4623; H05K 2203/0207; H05K 1/115
(86)International application number:
PCT/CN2014/078052
(87)International publication number:
WO 2015/096365 (02.07.2015 Gazette  2015/26)

(54)

PCB PROCESSING METHOD AND PCB

VERARBEITUNGSVERFAHREN FÜR LEITERPLATTE UND LEITERPLATTE

PROCÉDÉ DE TRAITEMENT DE PCB ET PCB


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 27.12.2013 CN 201310739302

(43)Date of publication of application:
02.11.2016 Bulletin 2016/44

(73)Proprietor: ZTE Corporation
Shenzhen, Guangdong 518057 (CN)

(72)Inventors:
  • YI, Bi
    Shenzhen Guangdong 518057 (CN)
  • MA, Fengchao
    Shenzhen Guangdong 518057 (CN)
  • REN, Yonghui
    Shenzhen Guangdong 518057 (CN)
  • XIONG, Wang
    Shenzhen Guangdong 518057 (CN)
  • WANG, Yingxin
    Shenzhen Guangdong 518057 (CN)

(74)Representative: Regimbeau 
20, rue de Chazelles
75847 Paris Cedex 17
75847 Paris Cedex 17 (FR)


(56)References cited: : 
CN-A- 101 695 224
JP-A- 2012 138 262
US-A1- 2009 166 080
CN-A- 102 316 682
US-A1- 2004 144 564
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    TECHNICAL FIELD



    [0001] The present disclosure relates to the field of PCB technologies, and in particular, to a PCB processing method and a PCB.

    BACKGROUND



    [0002] With the increasing of a user data traffic volume, assembling printed circuit boards (abbreviated as PCB) and connectors is widely used in a communication system to implement the transmission of inter-board signals. The capacity of a typical switching system reaches 10T, and up to hundreds of connectors are used. Very high requirements for the density of the connectors and the rate of single channels are proposed because very high communication capacity needs to be met and so many single boards and connectors need to be installed in a cabinet having a limited space. Currently, the single channel rate of the connectors has been raised more than 25Gbps, and the minimum distance between connector wafers is only 1.85mm. The density of the connectors has to be reduced to further improve the single channel rate of the connectors. The density and rate of the connectors are actually contradictory. Connector manufacturers make great efforts in the design of high-rate and high-density connectors. At present, a through hole is generally designed on a PCB for crimping the connectors. As a result, the wiring space of the PCB is limited by the space between wafers. During the research of the present disclosure, inventors found that the existing art at least has the following problems. After a connector type is determined, the space for layout between wafers on the PCB is limited. Due to through hole crimping, the deeper the backdrilling is, the larger the depth tolerance of a backdrilled hole is, and the poorer the control of a stub is. Further relevant technologies are also known from US 2004/0144564 A1 (HOFFMANN HANS [DE]) 29 July 2004 (2004-07-29) which relates to a multi-layer back-plane, JP 2012 138262 A (HITACHI LTD) 19 July 2012 (2012-07-19) which relates to a substrate mounting structure for mounting a component, and US 2009/166080 A1 (MATSUI AKIKO [JP]) 2 July 2009 (2009-07-02) which relates to a multilayer wiring board and method of manufacturing the same.

    SUMMARY



    [0003] The present disclosure provides a PCB processing method, including: respectively carrying out lamination processing on a plurality of PCB daughter boards constituting a PCB , and drilling and electroplating a top-most PCB daughter board of the PCB to form at least one via hole; laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the at least one via hole after laminating the plurality of PCB daughter boards together to form the PCB, after drilling and electroplating the top-most PCB daughter board of the PCB to form at least one via hole, the method further includes: backdrilling the at least one via hole from a side which is the side on which the other daughter boards of the PCB are to be laminated afterwards.

    [0004] The blind hole has a metallized part after backdrilling.

    [0005] Optionally, drilling and electroplating the formed PCB to form a through hole for mounting the connector includes: drilling and electroplating the formed PCB at preset intervals to form multiple through holes for mounting connectors.

    [0006] Optionally, after drilling and electroplating the formed PCB to form a through hole for mounting the connector, the method further includes: backdrilling at least one through hole.

    [0007] Optionally, the method further includes: determining a position of the through hole and of the blind hole according to wiring pattern of the PCB.

    [0008] Optionally, the top-most PCB daughter board is formed by laminating a core board and a dielectric.

    [0009] Optionally, the bottom-most PCB daughter board of the plurality of PCB daughter boards constituting the PCB is formed by directly processing a core board or is formed by the core board and a dielectric.

    [0010] The present disclosure further provides a PCB fabricated by the foregoing printed circuit board PCB processing method, the PCB is formed by laminating multilayer PCB daughter boards, and the PCB is provided with a blind hole and a through hole for mounting a connector, the at least one blind hole is backdrilled and the at least one through hole is backdrilled.

    [0011] In the case where the density of the connector is constant, the blind hole is formed by twice or more laminations, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.

    [0012] The foregoing description is merely a summarization of the technical schemes of the present disclosure, and may be implemented in accordance with the contents of the specification to more clearly understand the technological means of the present disclosure. The embodiments of the present invention are given to make the foregoing and other objectives, features and advantages of the present disclosure more apparent.

    BRIEF DESCRIPTION OF DRAWINGS



    [0013] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the following optional embodiments. The drawings are merely intended for showing optional embodiments, but are not deemed to limit the present disclosure. Furthermore, in the whole drawings, the same reference marks denote the same parts. In the figures:

    FIG. 1 is a flowchart of a PCB processing method

    FIG. 2 is a schematic assembly diagram without backdrilling

    FIG. 3 is a schematic assembly diagram with backdrilling according to the embodiments of the present disclosure;

    FIG. 4 is a schematic diagram of PCB daughter board of upper layer and PCB daughter board of lower layer according to the embodiments of the present disclosure;

    FIG. 5 is a schematic diagram of drilling and electroplating the PCB daughter board of upper layer according to the embodiments of the present disclosure;

    FIG. 6 is a schematic diagram of backdrilling the PCB daughter board of upper layer according to the embodiments of the present disclosure;

    FIG. 7 is a schematic diagram of laminating the PCB daughter board of upper layer and PCB daughter board of lower layer according to the embodiments of the present disclosure;

    FIG. 8 is a schematic diagram of drilling the PCB daughter board of upper layer and PCB daughter board of lower layer after laminating according to the embodiments of the present disclosure; and

    FIG. 9 is a schematic diagram of backdrilling the PCB daughter board of upper layer and PCB daughter board of lower layer after laminating according to the embodiments of the present disclosure.


    DETAILED DESCRIPTION



    [0014] The following will describe in more detail the exemplary embodiments of the present disclosure with reference to the drawings. Although the drawings display the exemplary embodiments of the present disclosure, it should be understood that the present disclosure may be implemented in various forms but not limited by the embodiments set forth herein. Instead, these embodiments are provided to more thoroughly understand the present disclosure, and completely convey the scope of the present disclosure to those skilled in the art.

    [0015] As mentioned above, in the existing art, connectors are mounted by crimping, and all crimping holes are designed as through holes. This manner has a disadvantage that the distance between two wafers of the connector is quite small so that the space for layout of the connector is very small. The density of the connectors has to be reduced if the space for layout is increased. In order to solve the aforementioned problem, the embodiments of the present invention provide a printed circuit board PCB processing method and a PCB, which may enable the space for layout between wafers to be doubled without reducing the density of the connector. Furthermore, the stub in the crimping of the blind hole may be effectively reduced by adopting multiple backdrilling before crimping. The following further describes in detail the present disclosure with reference to the drawings and the embodiments. It should be understood that the embodiments described herein are merely used to explain the present disclosure, and are not intended to limit the present disclosure.

    Method Embodiments



    [0016] According to the embodiments of the present invention, a PCB processing method is provided. FIG. 1 is a flowchart of a PCB processing method. As shown in FIG. 1, the PCB processing method includes processing in the following Step 101 to Step 102.

    [0017] Step 101: lamination processing is respectively carried out on a plurality of PCB daughter boards constituting a PCB according to PCB design requirements, and a top-most PCB daughter board of the PCB is drilled and electroplated to form a via hole, where the top-most PCB daughter board is formed by laminating a core board and a dielectric. A bottom-most PCB daughter board of the plurality of PCB daughter boards constituting the PCB is formed by directly processing a core board or is formed by laminating the core board and a dielectric.

    [0018] After the via hole is formed by drilling and electroplating the top-most PCB daughter board of the PCB, the via hole is backdrilled in accordance with the invention as claimed. The blind hole has a metallized part after backdrilling, and a length of the metallized part is greater than or equal to that of the signal pin of the connector.

    [0019] Step 102: the plurality of PCB daughter boards are laminated together to form the PCB, and the formed PCB is drilled and electroplated to form a through hole for mounting the connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to a length of the signal pin of the connector.

    [0020] In Step 102, the formed PCB may be drilled and electroplated at preset intervals to form multiple through holes for mounting connectors. And the through hole that needs to be backdrilled may be backdrilled.

    [0021] In this embodiment of the present invention, a position of the through hole and of the blind hole may be determined according to the wiring pattern of the PCB. For example, Optionally, in this embodiment of the present invention, the connector may be crimped by using the blind hole every other wafer.

    [0022] As mentioned above, the embodiments of the present invention propose a PCB processing method for connector crimping. The blind hole is formed by twice or more laminations. And where in terms of design and processing, it is needed to guarantee that the depth of the blind hole is greater than the length of the signal pin of the connector, so as to guarantee that the connector may be inserted from the blind hole by crimping. A schematic assembly diagram without backdrilling, thus not according to the invention as claimed, is as shown in FIG. 2. In a PCB design, if both a PCB of upper layer and a PCB of lower layer need to be backdrilled, the backdrilling of the PCB of upper layer needs to be carried out before laminating in accordance with the invention as claimed, The blind hole has a metallized part after backdrilling, and a length of the metallized part is greater than that of the signal pin of the connector, which guarantees that the connector may be inserted from the blind hole by crimping. The backdrilling of the lower layer of PCB is carried out upon completion of laminating of the PCB of upper layer and PCB of lower layer. To such a design, the schematic assembly diagram with backdrilling in accordance with the invention as claimed is as shown in FIG. 3. If the wiring space needs to be further increased, one through hole may be formed every other two rows, or the position of the through hole and of the blind hole may be freely deployed according to the wiring pattern to achieve the optimum wiring effect.

    [0023] The following makes a detailed description of the specific processing method of the embodiments of the present invention with reference to drawings and by taking two PCB daughter boards, i.e. a PCB daughter board of a upper layer and a PCB daughter board of a lower layer, as an example:
    Step 201: the PCB daughter board of upper layer is processed first according to requirements, the PCB daughter board of lower layer part is processed by directly using a core board, or is processed by multilayer core boards and prepreg PP, where core boards are formed by laminating copper foils the dielectric (PP), as shown in FIG. 4.

    [0024] Step 202: the PCB daughter board of upper layer is drilled and electroplated, as shown in FIG. 5.

    [0025] Step 203: the via hole needed in the PCB daughter board of upper layer is backdrilled, as shown in FIG. 6.

    [0026] Step 204: the PCB daughter board of upper layer and PCB daughter board of lower layer are laminated together, as shown in FIG. 7.

    [0027] Step 205: the position of the crimping hole of the connector is drilled and electroplated, as shown in FIG. 8.

    [0028] Step 206: at least one through hole is backdrilled, as shown in FIG. 9. This step can be omitted if no through hole is designed to be backdrilled.

    [0029] After the foregoing processing, the connector may be assembled, and the schematic diagram after assembly is as shown in FIG. 2 and FIG. 3.

    [0030] In conclusion, through the technical schemes of the embodiments of the present invention, in the case where the density of the connector is constant, wafers between lower layer of PCB may be doubled via reasonably designing the crimping of PCB and connectors, namely by means of twice or more laminations, so that the wiring space between wafers may be doubled. In addition, according to the technical schemes of the embodiments of the present invention, the blind hole is backdrilled before multiple laminating, which may effectively reduce the length of the stub.

    Device Embodiments



    [0031] According to the embodiments of the present invention, there is provided a PCB fabricated by the foregoing PCB processing method, as shown in FIG. 3, the PCB according to the embodiments of the present invention is formed by laminating multilayer PCB daughter boards, and the PCB is provided with a blind hole and a through hole for mounting a connector. The blind hole and the through hole are backdrilled.

    [0032] In conclusion, through the technical schemes of the embodiments of the present invention, in the case where the density of the connector is constant, wafers between lower layer of PCB may be doubled via considerable designing the crimping of PCB and connectors, namely by means of twice or more laminations, so that the wiring space between wafers may be doubled. In addition, according to the technical schemes of the embodiments of the present invention, the blind hole is backdrilled before multiple laminating, which may effectively reduce the length of the stub.


    Claims

    1. A printed circuit board PCB processing method, comprising:

    respectively carrying out (101) lamination processing on a plurality of PCB daughter boards constituting a PCB, and drilling and electroplating a top-most PCB daughter board of the PCB to form at least one via hole; and

    laminating (102) the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the at least one via hole after laminating the plurality of PCB daughter boards together to form the PCB,

    characterized in that after drilling and electroplating the top-most PCB daughter board of the PCB to form at least one via hole, the method further comprising:

    backdrilling the at least one via hole from a side which is the side on which the other daughter boards of the PCB are to be laminated afterwards.


     
    2. The method of claim 1, wherein the blind hole has a metallized part after backdrilling.
     
    3. The method of claim 1, wherein drilling and electroplating the formed PCB to form a through hole for mounting the connector comprises:
    drilling and electroplating the formed PCB at preset intervals to form multiple through holes for mounting connectors.
     
    4. The method of claim 1 or 3, after drilling and electroplating the formed PCB to form a through hole for mounting the connector, the method further comprising:
    backdrilling at least one through hole.
     
    5. The method of claim 1, further comprising:
    determining a position of the through hole and of the blind hole according to a wiring pattern of the PCB.
     
    6. The method of claim 1, wherein the top-most PCB daughter board is formed by laminating a core board and a dielectric.
     
    7. The method of claim 1, wherein a bottom-most PCB daughter board of the PCB is formed by directly processing a core board or is formed by laminating the core board and a dielectric.
     
    8. A printed circuit board PCB fabricated by the printed circuit board PCB processing method according to any one of claims 1-7, comprising:

    a plurality of PCB daughter boards laminated together,

    at least one blind hole, and

    at least one through hole;

    wherein the blind hole is formed by a through hole in at least one of the PCB daughter boards,

    wherein the at least one blind hole is backdrilled and the at least one through hole is backdrilled.


     


    Ansprüche

    1. Verarbeitungsverfahren für eine gedruckten Leiterplatte PCB, umfassend:

    jeweils Durchführen (101) eines Laminierungsprozesses auf einer Vielzahl von PCB-Tochterplatten, die ein PCB bilden, und Bohren und Galvanisieren einer obersten PCB-Tochterplatte der PCB zum Bilden wenigstens eines Durchgangslochs; und

    Laminieren (102) der Vielzahl von PCB-Tochterplatten zusammen zum Bilden der PCB und Bohren und Galvanisieren der gebildeten PCB zum Bilden einer Durchbrechung zum Montieren eines Anschlusses, wobei ein Blindloch zum Bilden eines Anschlusses durch das wenigstens eine Durchgangsloch nach dem Laminieren der Vielzahl von PCB-Tochterplatten zusammen zum Bilden der PCB gebildet wird,

    dadurch gekennzeichnet, dass

    das Verfahren nach dem Bohren und Galvanisieren der obersten PCB-Tochterplatte der PCB zum Bilden wenigstens einer Durchgangsbohrung weiterhin umfasst:
    Hinterbohren des wenigstens einen Durchgangslochs von einer Seite, die die Seite ist, auf der die Tochterplatten der PCB danach laminiert werden sollen.


     
    2. Verfahren gemäß Anspruch 1, bei dem das Blindloch nach dem Hinterbohren einen metallisierten Teil aufweist.
     
    3. Verfahren gemäß Anspruch 1, wobei das Bohren und Galvanisieren der gebildeten PCB zum Bilden einer Durchbrechung zum Montieren des Anschlusses umfass:
    Bohren und Galvanisieren der gebildeten PCB in voreingestellten Intervallen zum Bilden von zahlreichen Durchbrechungen zum Montieren von Anschlüssen.
     
    4. Verfahren gemäß Anspruch 1 oder 3, wobei das Verfahren nach dem Bohren und Galvanisieren der gebildeten PCB zum Bilden einer Durchbrechung zum Montieren des Anschlusses weiterhin umfasst:
    Hinterbohren wenigstens einer Durchbrechung.
     
    5. Verfahren gemäß Anspruch 1, weiterhin umfassend:
    Bestimmen einer Position der Durchbrechung und des Blindlochs gemäß einem Verdrahtungsmuster der PCB.
     
    6. Verfahren gemäß Anspruch 1, bei dem oberste PCB-Tochterplatte durch Laminieren einer Kernplatte und eines Dielektrikums gebildet wird.
     
    7. Verfahren gemäß Anspruch 1, bei dem eine unterste PCB-Tochterplatte der PCB durch direktes Verarbeiten einer Kernplatte gebildet wird oder durch Laminieren der Kernplatte und eines Dielektrikums gebildet wird.
     
    8. Gedruckte Leiterplatte PCB, die durch ein Verarbeitungsverfahren für eine Leiterplatte PCB gemäß irgendeinem der Ansprüche 1 - 7 hergestellt wird, umfassend:

    eine Vielzahl von von zusammen laminierten PCB-Tochterplatten

    wenigstens ein Blindloch und

    wenigstens eine Durchbrechung;

    wobei das Blindloch durch eine Durchbrechung in wenigstens einer der PCB-Tochterplatten gebildet ist,

    wobei das wenigstens eine Blindloch hinterbohrt ist und die wenigsten eine Durchbrechung hinterbohrt ist.


     


    Revendications

    1. Procédé de traitement de carte de circuit imprimé PCB, comprenant :

    effectuer respectivement un traitement de stratification (101) sur une pluralité de cartes filles de PCB constituant un PCB, et percer et galvaniser une carte fille de PCB la plus haute du PCB pour former au moins un trou d'interconnexion ; et

    laminer (102) la pluralité de cartes filles de PCB ensemble pour former le PCB, et percer et électroplaquer le PCB formé pour former un trou traversant pour monter un connecteur, dans lequel un trou borgne pour monter un connecteur est formé par le au moins un trou traversant après avoir laminé la pluralité de cartes filles de PCB ensemble pour former le PCB, caractérisé en ce que

    après le perçage et l'électroplacage de la carte fille de PCB la plus élevée du PCB pour former au moins un trou d'interconnexion, le procédé comprend en outre les étapes suivantes

    perçage en arrière de l'au moins un trou d'interconnexion à partir d'un côté qui est le côté sur lequel les autres cartes filles du PCB doivent être stratifiées par la suite.


     
    2. Procédé de la revendication 1, dans lequel le trou borgne présente une partie métallisée après le perçage en arrière.
     
    3. Procédé de la revendication 1, dans lequel le perçage et l'électroplacage du PCB formé pour former un trou traversant pour le montage du connecteur comprennent:
    le perçage et l'électroplacage du circuit imprimé formé à des intervalles prédéfinis pour former de multiples trous traversants pour le montage de connecteurs.
     
    4. Procédé de la revendication 1 ou 3, après le perçage et l'électroplacage de la carte de circuit imprimé formée pour former un trou traversant pour le montage du connecteur, le procédé comprenant en outre :
    le perçage en arrière d'au moins un trou traversant.
     
    5. Procédé de la revendication 1, comprenant en outre :
    déterminer une position du trou traversant et du trou borgne en fonction d'un schéma de câblage du PCB.
     
    6. Procédé de la revendication 1, dans lequel la carte fille de PCB la plus haute est formée en stratifiant une carte centrale et un diélectrique.
     
    7. Procédé de la revendication 1, dans lequel une carte fille de PCB la plus basse du PCB est formée en traitant directement une carte de noyau ou est formée en stratifiant la carte de noyau et un diélectrique.
     
    8. Carte de circuit imprimé PCB fabriquée par le procédé de traitement de carte de circuit imprimé PCB selon l'une quelconque des revendications 1 à 7, comprenant :

    une pluralité de cartes filles PCB laminées ensemble,

    au moins un trou borgne, et

    au moins un trou traversant ;

    dans lequel le trou borgne est formé par un trou traversant dans au moins une des cartes filles de PCB,

    dans lequel le au moins un trou borgne est percé en arrière et le au moins un trou traversant est percé en arrière.


     




    Drawing




















    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description