(19)
(11)EP 3 120 674 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
29.07.2020 Bulletin 2020/31

(21)Application number: 15711626.0

(22)Date of filing:  11.03.2015
(51)International Patent Classification (IPC): 
H05K 1/02(2006.01)
H05K 3/36(2006.01)
H01L 27/01(2006.01)
H01L 23/64(2006.01)
H05K 1/16(2006.01)
H05K 1/14(2006.01)
H01L 23/48(2006.01)
H01L 23/538(2006.01)
H05K 3/34(2006.01)
(86)International application number:
PCT/US2015/020021
(87)International publication number:
WO 2015/142591 (24.09.2015 Gazette  2015/38)

(54)

FACE-UP SUBSTRATE INTEGRATION WITH SOLDER BALL CONNECTION IN SEMICONDUCTOR PACKAGE

INTEGRATION EINES NACH OBEN GERICHTETEN SUBSTRATS MIT LÖTKUGELVERBINDUNG IN EINEM HALBLEITERGEHÄUSE

INTÉGRATION DE SUBSTRAT FACE VERS LE HAUT AVEC CONNEXION PAR BILLE DE SOUDURE DANS UN BOÎTIER DE SEMI-CONDUCTEUR


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 20.03.2014 US 201414220913

(43)Date of publication of application:
25.01.2017 Bulletin 2017/04

(73)Proprietor: Qualcomm Incorporated
San Diego, CA 92121-1714 (US)

(72)Inventors:
  • KIM, Daeik Daniel
    San Diego, California 92121-1714 (US)
  • KIM, Jonghae
    San Diego, California 92121-1714 (US)
  • ZUO, Chengjie
    San Diego, California 92121-1714 (US)
  • YUN, Changhan Hobie
    San Diego, California 92121-1714 (US)
  • VELEZ, Mario Francisco
    San Diego, California 92121-1714 (US)
  • MIKULKA, Robert Paul
    San Diego, California 92121-1714 (US)

(74)Representative: Dunlop, Hugh Christopher et al
Maucher Jenkins 26 Caxton Street
London SW1H 0RJ
London SW1H 0RJ (GB)


(56)References cited: : 
US-A1- 2005 200 003
US-A1- 2010 148 302
US-A1- 2013 105 966
US-A1- 2008 023 814
US-A1- 2012 199 949
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    Field of Disclosure



    [0001] Disclosed embodiments are directed to semiconductor packages with attachment of flipped substrates using solder balls. More specifically, exemplary embodiments are directed to attachment of a flipped or face-up 2D package-on-glass (POG) structure to a laminate substrate using solder balls and attaching the laminate substrate to a printed circuit board (PCB) to reduce inductance build-up and Q-factor degradation.

    Background



    [0002] Semiconductor packages typically involve one or more semiconductor dies integrated on a substrate, such as, a glass substrate. The substrate is then attached to a package base, such as, a printed circuit board (PCB). Passive components such as capacitors and inductors are usually formed on one side, such as, a bottom side, of the substrate. The substrate may be attached to the PCB, face down, such that the bottom side comprising the passive components is closest to the PCB. Ball grid arrays (BGAs) including solder balls may be utilized for forming the connections and attachment between the substrate and the PCB. Electrical connections between the PCB and the substrate may be formed with wire bonds and pads as known in the art.

    [0003] For example, with reference to FIG. 1, a side view of a conventional semiconductor package 100 is illustrated. Package 100 includes glass substrate 102 with a passive component, inductor 104 attached on a bottom surface of glass substrate 102. The combination of glass substrate with inductor 104 is referred to as a two dimensional (2D) passive-on-glass (POG). The 2D POG comprising glass substrate 102 and inductor 104 is attached in a conventional face down configuration, as illustrated, to PCB 108 using solder balls which form BGA 106. In this configuration, an undesirably high inductance is formed between the inductor and PCB 108. Specifically, the separation 112 between inductor 104 and ground plane 110 of PCB 108 relates to significantly high inductance interference formed. Ground plane 110 is an electrically conductive surface connected to an electrical ground. For example, ground plane 110 may be a large area of copper foil which is connected to the ground terminal (not illustrated) of PCB 108, and serves as a ground or return path for current from the various components integrated on PCB 108.

    [0004] To minimize the undesirable inductance interference and accompanying Q-factor degradation it is necessary to maintain separation 112 at as high a distance as possible. The conventional approaches for forming package 100 rely on BGA 106 to provide the necessary separation 112. However, BGA 106 is not well suited to meet such needs. It is difficult to achieve consistent and desired height among the various solder balls which form BGA 106. The solder balls also tend to be highly susceptible to reflow degradation. Furthermore, over the course of operation, the degeneration of the solder balls may lead to collapse of the 2D POG on PCB 108, due to high heat and stress which is common in semiconductor packages.

    [0005] Even if the inductors and passive components are placed on the opposite side of the semiconductor substrate, in a flipped (or flip-chip or face-up) configuration (not illustrated, with inductor 104, for example, formed on the top side of glass substrate 102) wire bonds are conventionally utilized for forming electrical connections. Wire bonds introduce high resistance, particularly, as the complexity of the semiconductor dies increases. Wire bonds also tend to be expensive and unstable.

    [0006] Accordingly, there is a need in the art for efficient and reliable integration of semiconductor packages, such as, 2D POG structures, which avoid the aforementioned problems.

    [0007] US 2008/023814 A1 describes a stacked ball grid array semiconductor package. The stacked ball grid array semiconductor package includes: a single semiconductor package having landings provided in depressed grooves of both sides thereof, wherein the landings include a conductive material, and a substrate having a semiconductor chip disposed on the substrate; another semiconductor package formed above the single semiconductor package and having landing pads formed in a lower surface of the substrate thereof; and solder balls connecting the landing pads to the landings.

    [0008] US 2010/148302 A1 describes a capacitor-equipped semiconductor device including a semiconductor chip having a plurality of electrode terminals; a sheet-like substrate at least having a film capacitor; and a mounting substrate. The mounting substrate is provided on one side thereof with chip connection terminals and ground terminals. The chip connection terminals are disposed to correspond to the electrode terminals of the semiconductor chip. The ground terminals are disposed to correspond to the one electrode terminals of the film capacitor of the sheet-like substrate. The mounting substrate is provided on the other side thereof with external connection terminals connected to the chip connection terminals and the ground terminals and used to mount the mounting substrate on an external substrate.

    [0009] US 2005/200003 A1 describes a multi-chip package including a substrate on which multiple substrate bonding pads may be formed and under which multiple terminals may be formed, first and second semiconductor chips, which may be deposited on the substrate, and a spacer, which may be formed between the first and second semiconductor chips to have at least power and ground pads.

    [0010] US 2013/105966 A1 describes an integrated circuit device that includes a semiconductor substrate and a die attached to the semiconductor substrate. A conductive pillar is connected to at least one of the semiconductor substrate or the die. An overmold is molded onto the semiconductor substrate over the die, and the conductive pillar extends through the overmold.

    [0011] US 2012/199949 A1 describes forming isotropic ball shapes in trenches on a semiconductor die. The concave surfaces are fabricated by depositing bilayers of amorphous-silicon and silicon oxide. Openings are patterned in a silicon oxide hard mask for trenches. The openings are transferred to the amorphous-silicon layers through isotropic etching to form concave surfaces. Conducting, insulating, and conducting layers are deposited on the concave surfaces of the trenches by atomic layer deposition.

    SUMMARY



    [0012] In accordance with the invention, a semiconductor package and a method of forming a semiconductor package are provided as set forth in the claims.

    [0013] Exemplary embodiments are directed to semiconductor packages with attachment of flipped substrates using solder balls. More specifically, exemplary embodiments are directed to attachment of a flipped or face-up first substrate, such as, a 2D package-on-glass (POG) structure to a second substrate, such as, a laminate substrate, using solder balls and attaching the second/laminate substrate to a printed circuit board (PCB) to reduce inductance build-up and Q-factor degradation.

    [0014] For example, an exemplary embodiment is directed to a semiconductor package comprising: a 2D passive-on-glass (POG) structure with a passive component and a first set of one or more package pads formed on a face of a glass substrate, a laminate substrate with a second set of one or more package pads formed on a face of the laminate substrate, and solder balls configured to contact the first set of one or more package pads with the second set of one or more package pads, wherein the 2D POG structure is placed face-up on the face of the laminate substrate.

    [0015] Another exemplary embodiment is directed to a method of forming a semiconductor package, the method comprising: forming a 2D passive-on-glass (POG) structure with a passive component integrated on a face of a glass substrate; forming a first set of one or more package pads on the face of a glass substrate; forming a laminate substrate with a second set of one or more package pads on a face of the laminate substrate; placing the 2D POG structure face-up on the laminate substrate; and contacting the first set of one or more package pads with the second set of one or more package pads with solder balls.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0016] The accompanying drawings are presented to aid in the description of embodiments of the various embodiments and are provided solely for illustration of the embodiments and not limitation thereof.

    FIG. 1 illustrates a conventional face-down semiconductor package comprising a 2D POG structure formed on a PCB.

    FIGS. 2A-C illustrate exemplary semiconductor packages with flipped or face-up 2D POG structures attached to a laminate substrate using solder balls.

    FIG. 3 illustrates a flow-chart of a method of forming an exemplary semiconductor package with a flipped or face-up 2D POG structure attached to a laminate substrate using solder balls.


    DETAILED DESCRIPTION



    [0017] Aspects of the various embodiments are disclosed in the following description and related drawings directed to specific embodiments. Alternate embodiments may be devised without departing from the scope of the invention. Additionally, well-known elements of the various embodiments will not be described in detail or will be omitted so as not to obscure the relevant details of the various embodiments.

    [0018] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term "embodiments" does not require that all embodiments include the discussed feature, advantage or mode of operation.

    [0019] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising,", "includes" and/or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

    [0020] Exemplary embodiments include package structures which overcome aforementioned deficiencies of conventional packages. In general, exemplary aspects are directed to systems and methods of connecting two semiconductor substrates. For example, a first substrate and a second substrate may be stacked in a flipped arrangement, with both substrates face-up. The first substrate may comprise one or more semiconductor dies and/or passive components, formed on a first side (also referred to as a face or top side) of the first substrate. Pads, such as, BGA pads may be formed on the face of the first substrate. Particularly, a first set of pads may be formed at lateral edges or boundaries of the face of the first substrate. Electrical connections to components on the face of the first substrate can be established through the first set of pads.

    [0021] The second substrate is of larger lateral area than the first substrate. The first substrate is stacked on the second substrate, such that the first substrate covers an inner area on a face of the second substrate while leaving lateral edges or an outside boundary of the face of the second substrate free from coverage. A second set of pads are formed on the outside boundary or lateral edges of the second substrate.

    [0022] Solder balls are dropped on outside edges of the first substrate such that the solder balls contact both the first set of pads and the second set of pads. These solder balls are not only used for attachment, but also for forming electrical connections between the first and second substrates, through the first and second sets of pads respectively. In some cases, vias such as, through-silicon-vias or through-glass-vias, based on whether the second substrate is made of silicon or glass respectively, may be formed to connect the second set of pads to a third set of pads on an opposite, second or bottom surface of the second substrate. The third set of pads may connect to any suitable external semiconductor package element, such as, a PCB. Thus, aspects of exemplary embodiments may be directed to providing electrical and mechanical connections through solder balls in a face-up stacked configuration between two semiconductor substrates. Accordingly, exemplary embodiments may avoid wire bonds and related drawbacks discussed previously.

    [0023] Furthermore, in these exemplary aspects, the face of the first substrate is separated from the second substrate by at least the material and thickness of the first substrate. Thus, passive components formed on the face of the first substrate are sufficiently insulated and separated from the face of the second substrate, and other components such as a PCB attached to the opposite side of the second substrate, thus avoiding or mitigating inductance interference and Q-factor degradation.

    [0024] According to the invention, a 2D POG is formed from the first substrate discussed in the above aspects, and the second substrate is formed as a laminate substrate. These exemplary embodiments are discussed below with reference to FIGS. 2A-C, wherein side views related to step-by-step formation of package structure 200 is illustrated.

    [0025] Initially with reference to FIG. 2A, a first substrate is illustrated. The first substrate is shown to include a 2D integrated passive device (IPD) POG, with glass substrate 202 and inductor 204 on a face (or top side or first side) of glass substrate 202. Due to exemplary configurations, glass substrate 202 need not be formed of increased thickness to avoid inductance effects, but can be thinned down to about 50-100um. POG pads 203 are formed on lateral edges of the face of glass substrate 202.

    [0026] With continuing reference to FIG. 2A, a second substrate may be provided as a laminate substrate 207. A lateral area of laminate substrate 207 is larger than a lateral area of glass substrate 202. Package pads 205 can be provided on lateral or outer edges of a first side (or top side or face) of laminate substrate 2067. Package pads 205 may be BGA pads. Land grid array (LGA) package pads or LGA pads 211 may be formed on corresponding outer edges of an opposite side (or bottom side or second side) of laminate substrate 207. Through vias 209 may be formed within laminate substrate 207 to connect package pads 205 and LGA pads 211. In some aspects, through vias 209 may be through-glass-vias (TGVs).

    [0027] With reference now to FIG. 2B, glass substrate 202 with inductor 204 is placed face-up or in a flipped configuration within a central or inner area on the face of laminate substrate 207, such that package pads 205 surround or flank glass substrate 202. Solder balls 206, of sufficient size, are dropped or formed, such that solder balls 206 contact BGA pads 203 on the face of glass substrate 202, as well as, package pads 205 on the face of laminate substrate 207. In this manner, solder balls 206 provide electrical connection between package pads 205 and BGA pads 203. Solder balls 206 also provide mechanical connection or a means for attachment of glass substrate 202 on laminate substrate 207. As will be appreciated, the exemplary solder ball structures for solder balls 206 avoid the need for undesirable, expensive, and often unstable wire bonds which are conventionally used for forming electrical connections in flipped package designs. The exemplary configuration with solder ball connections or solder ball attachments also enables laminate substrate 207, so as to provide quick adaptability to different pin configurations, which may not be possible using wire bonds.

    [0028] With reference to FIG. 2C, package structure 200 is shown to be integrated on PCB 208. Specifically, laminate substrate 207 with glass substrate 202 attached via solder balls 206 is attached to PCB 208. Pads 213 may be provided at outer edges on a face (or first side or top side) of PCB 208, and aligned with LGA pads 211 on the opposite side of laminate substrate 207. Attachment of laminate surface 207 with PCB 208 may be enabled by contacting LGA pads 211 with pads 213. As will be appreciated, ground plane 210 of PCB is separated from inductor 204 on the face of glass substrate 202 by separation 212, which is significantly larger than the separation 112 observed in conventional package structure 100 described with reference to FIG. 1. Thus, effect of inductance build up between the face of PCB 208 and inductor 204 and related Q factor degradation of package structure 200 is significantly minimized.

    [0029] Yet another beneficial aspect of package structure 200 is derived from the exemplary face-up configuration, wherein inductor 204 is exposed to air, or is free from obstructing structures (such as PCB 108 in the case of inductor 104 of FIG. 1). Such a 2D POG configuration of inductor 204 on glass substrate 202 benefits from a high quality magnetic medium, air, while the inductor's magnetic field is not blocked at the top side or first side.

    [0030] While in some cases it is possible that the opposite side or bottom side of laminate substrate 207 may cause mild inductance, the radio frequency (RF) properties of laminate substrates are known to be superior to the RF properties of face-down or flipped package structures. Therefore, the presence of laminate substrate 207 in exemplary package structure 200 of FIGS. 2A-C is seen to mitigate inductance interference and Q-factor degradation. In some cases, exemplary package structure 200 can achieve performance levels which are comparable to those of expensive three dimensional (3D) package structures known in the art, but at a significantly lower cost.

    [0031] Although not explicitly illustrated, it is possible to provide a mold in some exemplary embodiments, in order to cover the passive components on face of exemplary 2D POG 2D POG structures. Such a mold will serve several functions, including, protection of the passive components as well as the 2D POG structures, as well as, enabling laser markings on the exemplary package structures. Such laser markings may be used for identification and binning purposes, as known in the art.

    [0032] It will be appreciated that embodiments include various methods for performing the processes, functions and/or algorithms disclosed herein. For example, as illustrated in FIG. 4, an embodiment can include a method of forming a semiconductor package (e.g., package structure 200), the method comprising: forming a 2D passive-on-glass (POG) structure with a passive component (e.g., inductor 204) integrated on a face of a glass substrate (e.g., glass substrate 202) - Block 302; forming a first set of one or more package pads (e.g., POG pads 203) on the face of a glass substrate - Block 304; forming a laminate substrate (e.g., laminate substrate 207) with a second set of one or more package pads (e.g., package pads 205) on a face of the laminate substrate - Block 306; placing the 2D POG structure face-up on the laminate substrate - Block 308; and contacting the first set of one or more package pads with the second set of one or more package pads with solder balls (e.g., solder balls 206) - Block 310.

    [0033] Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

    [0034] Further, those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application.

    [0035] The methods, sequences and/or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.

    [0036] While the foregoing disclosure shows illustrative embodiments of the invention, it should be noted that various changes and modifications could be made herein without departing from the scope of protection defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the embodiments of the invention described herein need not be performed in any particular order. Furthermore, although elements of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.


    Claims

    1. A semiconductor package comprising:

    a 2D passive-on-glass, POG, structure with a passive component (204) and a first set of one or more package pads (203) formed on a face of a glass substrate (202);

    a laminate substrate (207) with a second set of one or more package pads (205) formed on a face of the laminate substrate (207); and

    means for contacting (206) the first set of one or more package pads (203) with the second set of one or more package pads (205), wherein the 2D POG structure is placed face-up on the face of the laminate substrate (207).


     
    2. The semiconductor package of claim 1 further comprising a printed circuit board, PCB, (208) wherein the PCB (208) is coupled to a bottom side of the laminate substrate (207).
     
    3. The semiconductor package of claim 2, wherein the PCB (208) is coupled to the bottom side of the laminate substrate (207) through land grid array, LGA, package pads (211) formed on the bottom side of the laminate substrate (207).
     
    4. The semiconductor package of claim 3, wherein the passive component (204) is separated from a ground plane (210) of the PCB (208) by the laminate substrate (207) and the glass substrate (202).
     
    5. The semiconductor package of claim 3, wherein the LGA package pads (211) on the bottom side of the laminate substrate (207) are coupled to the second set of one or more package pads (205) formed on the face of the laminate substrate (207) through vias (209).
     
    6. The semiconductor package of claim 1, further comprising a mold formed over the passive component (204), wherein the mold is configured to protect the passive component (204) and enable laser marking.
     
    7. The semiconductor package of claim 1, wherein the passive component (204) is an inductor (204).
     
    8. The semiconductor package of any one of claims 1 to 7, wherein the means for contacting (206) comprises at least one solder ball.
     
    9. A method of forming a semiconductor package, the method comprising:

    forming a 2D passive-on-glass, POG, structure with a passive component (204) integrated on a face of a glass substrate (202);

    forming a first set of one or more package pads (203) on the face of a glass substrate (202);

    forming a laminate substrate (207) with a second set of one or more package pads (205) on a face of the laminate substrate (207);

    placing the 2D POG structure face-up on the laminate substrate (207); and

    contacting the first set of one or more package pads (203) with the second set of one or more package pads (205) with solder balls (206).


     
    10. The method of claim 9 further comprising attaching a printed circuit board, PCB, (208) to a bottom side of the laminate substrate (207) through land grid array, LGA, package pads (211) on a bottom side of the laminate substrate (207).
     
    11. The method of claim 10, further comprising connecting the LGA package pads (211) on the bottom side of the laminate substrate (207) to the second set of one or more package pads (205) formed on the face of the laminate substrate (207) through vias (209).
     
    12. The method of claim 9, further comprising forming a mold over the passive component (204) for protect the passive component (204) and enabling laser marking.
     
    13. The method of claim 9, wherein the passive component (204) is an inductor (204).
     


    Ansprüche

    1. Ein Halbleitergehäuse bzw. Halbleiter-Package, das Folgendes aufweist:

    eine 2D-POG-Struktur (POG = passive-on-glass) mit einer passiven Komponente (204) und einem ersten Satz von einem oder mehreren Package-Kontakten bzw. Package-Pads (203), die auf einer Fläche eines Glassubstrats (202) ausgebildet sind;

    ein Laminatsubstrat (207) mit einem zweiten Satz von einem oder mehreren Package-Pads (205), die auf einer Fläche des Laminatsubstrats (207) ausgebildet sind; und

    Mittel zum Kontaktieren (206) des ersten Satzes von einem oder mehreren Package-Pads (203) mit den zweiten Satz von einem oder mehreren Package-Pads (205), wobei die 2D-POG-Struktur nach oben weisend auf der Fläche des Laminatsubstrats (207) platziert ist.


     
    2. Halbleiter-Package nach Anspruch 1, das weiter eine gedruckte Leiterplatte bzw. PCB (PCB = printed circuit board) (208) aufweist, wobei das PCB (208) an eine Unterseite des Laminatsubstrats (207) gekoppelt ist.
     
    3. Halbleiter-Package nach Anspruch 2, wobei das PCB (208) an die Unterseite des Laminatsubstrats (207) durch LGA-Package-Pads (LGA = land grid array) (211) gekoppelt ist, die auf der Unterseite des Laminatsubstrats (207) ausgebildet sind.
     
    4. Halbleiter-Package nach Anspruch 3, wobei die passive Komponente (204) von einer Masseebene (210) das PCB (208) durch das Laminatsubstrat (207) und das Glassubstrat (202) getrennt ist.
     
    5. Halbleiter-Package nach Anspruch 3, wobei die LGA-Package-Pads (211) auf der Unterseite des Laminatsubstrats (207) an den zweiten Satz von einem oder mehreren Package-Pads (205) gekoppelt sind, der auf der Fläche des Laminatsubstrats (207) ausgebildet ist, und zwar durch Vias bzw. Durchkontaktierungen (209).
     
    6. Halbleiter-Package nach Anspruch 1, das weiter eine Form aufweist, die über der passiven Komponente (204) ausgebildet ist, wobei die Form konfiguriert ist zum Schützen der passiven Komponente (204) und zum Ermöglichen einer Lasermarkierung.
     
    7. Halbleiter-Package nach Anspruch 1, wobei die passive Komponente (204) eine Induktivität (204) ist.
     
    8. Halbleiter-Package nach einem der Ansprüche 1 bis 7, wobei die Mittel zum Kontaktieren (206) wenigstens eine Lotkugel aufweisen.
     
    9. Ein Verfahren zum Bilden eines Halbleitergehäuses bzw. eines Halbleiter-Packages, wobei das Verfahren Folgendes aufweist:

    Ausbilden einer 2D-POG-Struktur (POG = passive-on-glass) mit einer passiven Komponente (204), die auf einer Fläche eines Glassubstrats (202) integriert ist;

    Ausbilden eines ersten Satzes von einem oder mehreren Package-Kontakten bzw. Package-Pads (203) auf der Fläche eines Glassubstrats (202);

    Ausbilden eines Laminatsubstrats (207) mit einem zweiten Satz von einem oder mehreren Package-Pads (205) auf einer Fläche des Laminatsubstrats (207);

    Platzieren der 2D-POG-Struktur nach oben weisend auf dem Laminatsubstrat (207); und

    Kontaktieren des ersten Satzes von einem oder mehreren Package-Pads (203) mit dem zweiten Satz von einem oder mehreren Package-Pads (205) mit Lotkugeln (206).


     
    10. Verfahren nach Anspruch 9, das weiter Anbringen einer gedruckte Leiterplatte bzw. PCB (PCB = printed circuit board) (208) an eine Unterseite des Laminatsubstrats (207) durch LGA-Package-Pads (LGA = land grid array) (211) auf einer Unterseite des Laminatsubstrats (207) aufweist.
     
    11. Verfahren nach Anspruch 10, das weiter Verbinden der LGA-Package-Pads (211) auf der Unterseite des Laminatsubstrats (207) mit dem zweiten Satz von einem oder mehreren Package-Pads (205) aufweist, die auf der Oberfläche des Laminatsubstrats (207) durch Vias (209) ausgebildet sind.
     
    12. Verfahren nach Anspruch 9, das weiter Ausbilden einer Form über der passiven Komponente (204) aufweist, um die passive Komponente (204) zu schützen und eine Lasermarkierung zu ermöglichen.
     
    13. Verfahren nach Anspruch 9, wobei die passive Komponente (204) eine Induktivität (204) ist.
     


    Revendications

    1. Boîtier semi-conducteur comprenant :

    une structure 2D passive sur verre, POG, dotée d'un composant passif (204) et d'un premier ensemble d'une ou plusieurs pastilles de boîtier (203) formées sur une face d'un substrat de verre (202) ;

    un substrat stratifié (207) doté d'un second ensemble d'une ou plusieurs pastilles de boîtier (205) formées sur une face du substrat stratifié (207) ; et

    un moyen de mise en contact (206) du premier ensemble d'une ou plusieurs pastilles de boîtier (203) avec le second ensemble d'une ou plusieurs pastilles de boîtier (205), la structure 2D POG étant placée face vers le haut sur la face du substrat stratifié (207).


     
    2. Boîtier semi-conducteur selon la revendication 1 comprenant en outre une carte de circuit imprimé, PCB, (208) la PCB (208) étant couplée à un côté inférieur du substrat stratifié (207).
     
    3. Boîtier semi-conducteur selon la revendication 2, la PCB (208) étant couplée au côté inférieur du substrat stratifié (207) par l'intermédiaire de pastilles de boîtier à matrice de plots, LGA, (211) formées sur le côté inférieur du substrat stratifié (207).
     
    4. Boîtier semi-conducteur selon la revendication 3, le composant passif (204) étant séparé d'un plan de masse (210) de la PCB (208) par le substrat stratifié (207) et le substrat de verre (202).
     
    5. Boîtier semi-conducteur selon la revendication 3, les pastilles de boîtier LGA (211) sur le côté inférieur du substrat stratifié (207) étant couplées au second ensemble d'une ou plusieurs pastilles de boîtier (205) formées sur la face du substrat stratifié (207) par l'intermédiaire de trous d'interconnexion (209).
     
    6. Boîtier semi-conducteur selon la revendication 1, comprenant en outre un moule formé sur le composant passif (204), le moule étant conçu pour protéger le composant passif (204) et permettre un marquage laser.
     
    7. Boîtier semi-conducteur selon la revendication 1, le composant passif (204) étant un inducteur (204).
     
    8. Boîtier semi-conducteur selon l'une quelconque des revendications 1 à 7, le moyen de mise en contact (206) comprenant au moins une bille de soudure.
     
    9. Procédé de formation d'un boîtier semi-conducteur, le procédé comprenant les étapes consistant à :

    former une structure 2D passive sur verre, POG, dotée d'un composant passif (204) intégré sur une face d'un substrat de verre (202) ;

    former un premier ensemble d'une ou plusieurs pastilles de boîtier (203) sur la face d'un substrat de verre (202) ;

    former un substrat stratifié (207) doté d'un second ensemble d'une ou plusieurs pastilles de boîtier (205) sur une face du substrat stratifié (207) ;

    placer la structure 2D POG face vers le haut sur le substrat stratifié (207) ; et

    mettre en contact le premier ensemble d'une ou plusieurs pastilles de boîtier (203) avec le second ensemble d'une ou plusieurs pastilles de boîtier (205) à l'aide de billes de soudure (206).


     
    10. Procédé selon la revendication 9, comprenant en outre l'étape consistant à fixer une carte de circuit imprimé, PCB, (208) sur un côté inférieur du substrat stratifié (207) par l'intermédiaire de pastilles de boîtier à matrice de plots, LGA, (211) sur un côté inférieur du substrat stratifié (207).
     
    11. Procédé selon la revendication 10, comprenant en outre l'étape consistant à relier les pastilles de boîtier LGA (211) sur le côté inférieur du substrat stratifié (207) au second ensemble d'une ou plusieurs pastilles de boîtier (205) formées sur la face du substrat stratifié (207) par l'intermédiaire de trous d'interconnexion (209).
     
    12. Procédé selon la revendication 9, comprenant en outre l'étape consistant à former un moule sur le composant passif (204) pour protéger le composant passif (204) et permettre un marquage laser.
     
    13. Procédé selon la revendication 9, le composant passif (204) étant un inducteur (204).
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description