(19)
(11)EP 3 130 119 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
22.07.2020 Bulletin 2020/30

(21)Application number: 15720827.3

(22)Date of filing:  07.04.2015
(51)International Patent Classification (IPC): 
H04L 25/02(2006.01)
(86)International application number:
PCT/US2015/024726
(87)International publication number:
WO 2015/157293 (15.10.2015 Gazette  2015/41)

(54)

SPARSE ORDERED ITERATIVE GROUP MULTI-ANTENNA CHANNEL ESTIMATION

SPÄRLICHE GEORDNETE ITERATIVE GRUPPENKANALSCHÄTZUNG MIT MEHREREN ANTENNEN

ESTIMATION DE CANAL MULTI-ANTENNE PAR GROUPES ITÉRATIFS ORDONNÉS ÉPARS


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 09.04.2014 US 201414248958

(43)Date of publication of application:
15.02.2017 Bulletin 2017/07

(73)Proprietor: Altiostar Networks, Inc.
Tewksbury, MA 01876 (US)

(72)Inventor:
  • ANNAVAJJALA, Ramesh
    Tewksbury, MA 01876 (US)

(74)Representative: Gill Jennings & Every LLP 
The Broadgate Tower 20 Primrose Street
London EC2A 2ES
London EC2A 2ES (GB)


(56)References cited: : 
GB-A- 2 428 934
US-A1- 2006 062 322
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    TECHNICAL FIELD



    [0001] The subject matter described herein relates to estimation of channel parameters for orthogonal frequency-division multiplexing (OFDM) and single-carrier frequency-domain multiplexing (SC-FDMA) based air interface technologies with one or more antennas at the transmitter and multiple antennas at the receiver.

    BACKGROUND



    [0002] Wireless communication standards such as 2nd generation Global System for Mobile Communications (GSM) based on time-division multiple access (TDMA) and/or frequency-division multiple access (FDMA), 3rd generation systems based on wideband code-division multiple access (WCDMA), and emerging 3rd Generation Partnership Program (3GPP) Long Term Evolution (LTE) systems based on orthogonal frequency-division multiplexing (OFDM) (in the downlink) and single-carrier FDMA (in the uplink), all employ multiple antennas to increase signal reception quality, and to enhance the system coverage. Although GSM systems primarily use multiple receiver antennas for link quality enhancement, 3 G- WCDMA and LTE systems use multiple antennas both at the transmitter and the receiver.

    [0003] Due to constructive and destructive addition of radio waves traveling over the air, the wireless channel between a transmitter antenna and a receiver antenna can be described as a frequency-selective and a time-varying random propagation medium. The frequency-selective nature of the channel produces multiple overlapping signals at the receiver, where each copy of the transmitted signal is attenuated by a random channel gain and delayed by a random time offset. A cyclic-prefix (CP) can be introduced to limit inter-symbol interference caused by channel frequency-selectivity. If CP length is larger than a channel's maximum delay spread, inter-symbol interference can be avoided. Additionally, relative motion between the transmitter and the receiver can introduce Doppler spread to the transmitted signal. For OFDM systems, inter-carrier interference can be avoided if the Doppler spread is smaller than the sub-carrier spacing.

    [0004] Traditionally, channel estimation for multiple-antennas with OFDM modulation can be performed in two steps. In a first step, using pilot tones, a frequency- domain channel is estimated. In a second step, the frequency-domain channel is interpolated over the pilot tones of interest. This approach is known to yield satisfactory performance if the pilot density is high. With low pilot density, this approach suffers from interpolation errors (e.g., for tones between two given frequency tones), and extrapolation errors (e.g., for data tones beyond the vicinity of the pilot tones).

    [0005] US-2006/062322-A1 discloses channel estimation using pilot tones to obtain the corresponding channel values in frequency, and transform it to the values in the time domain in a matrix F of complex exponentials with values according to the locations of the tones, to obtain a first channel impulse response estimate.

    [0006] The present invention addresses the problem of increasing the accuracy in the provision of channel impulse response estimates.

    SUMMARY



    [0007] The scope of the invention is defined by the appended independent claims. The present invention provides a method for providing data characterising a final estimated channel impulse response, as defined in claim 1.

    [0008] In an aspect, data can be received characterizing a first signal transmitted in an orthogonal frequency-division multiplexing (OFDM) system by a transmitter with one or more transmit antennas through a wireless channel and received by a receiver with a plurality of receive antennas, the first signal including a plurality of pilot pulses. A final estimated channel impulse response of the wireless channel can be determined for each pair of transmitter and receiver antennas by iteratively finding delay taps of an intermediate channel impulse response estimate and adding the found delay taps to an error of the intermediate channel impulse response estimate. Data characterizing the final estimated channel impulse response can be provided.

    [0009] One or more of the following features can be included. For example, the one or more significant delay taps can be non-zero entries of the intermediate channel impulse response estimate. An estimate of a channel frequency response can be determined for a plurality of sub-carriers. An estimate of a length of a channel impulse response of the wireless channel can be determined. One or more of a maximum delay spread of the wireless channel, a minimum delay spread of the wireless channel, an average delay spread of the wireless channel, and a root-mean-square delay of the wireless channel can be determined for each of the one or more transmit antennas. An estimate of a channel coherence bandwidth can be determined for each of the one or more transmit antennas. Iteratively finding significant delay taps of the intermediate channel impulse response estimate and adding the one or more significant delay taps to the error of the intermediate channel impulse response estimate can be performed according to

    where M is a number of receive antennas; and G, Niter, NCP, and µ are predetermined.

    [0010] A second aspect of the invention provides a data carrier carrying machine-readable instructions that, when performed, cause one or more machines (e.g., computers, etc.) to perform the method of claim 1. Similarly, a third aspect provides a computer system including a processor and a memory storing instructions that cause the processor to perform the method defined in claim 1. Additionally, computer systems may include additional specialized processing units that are able to apply a single instruction to multiple data points in parallel. Such units include but are not limited to so-called "Graphics Processing Units (GPU)."

    [0011] The details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be apparent from the description and drawings, and from the claims.

    DESCRIPTION OF DRAWINGS



    [0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, show certain aspects of the subject matter disclosed herein and, together with the description, help explain some of the principles associated with the disclosed implementations. In the drawings,

    FIG. 1 is a system diagram illustrating an example Multi-User Equipment Multi-stream spatial-division multiple access system with a receiver with Sparse Ordered Iterative Multi Antenna Channel Estimation (SOI-MA-CE) located at a base station;

    FIG. 2 is a system diagram illustrating a base station transmitter and a User Equipment (UE) with a receiver with SOI-MA-CE;

    FIG. 3 is a functional block diagram of an example uplink transmitter signal chain within a UE for a single data stream;

    FIG. 4 is a functional system diagram of components of an example receiver with SOI-MA-CE;

    FIG. 5 is a functional block diagram illustrating an iterative SOI-MA-CE process to estimate a channel impulse response;

    FIG. 6 describes the symbol and slot structure for the Physical Uplink Shared Channel of the 3GPP LTE system with normal cyclic-prefix (CP) mode;

    FIG. 7 describes the symbol and slot structure for the Physical Uplink Shared Channel of the 3GPP LTE system with extended cyclic-prefix mode;

    FIG. 8 describes the symbol and slot structure for the Physical Uplink Control Channel, Formats 1, 1a and 1b, of the 3GPP LTE system with normal cyclic-prefix mode;

    FIG. 9 describes the symbol and slot structure for the Physical Uplink Control Channel, Formats 1a and 1b, of the 3GPP LTE system with normal cyclic-prefix mode, and sounding reference symbol;

    FIG. 10 describes the symbol and slot structure for the Physical Uplink Control Channel, formats 1, 1a and 1b, of the 3GPP LTE system with extended cyclic-prefix mode;

    FIG. 11 describes the symbol and slot structure for the Physical Uplink Control Channel, Formats 2, 2a and 2b, of the 3GPP LTE system with normal cyclic-prefix mode;

    FIG. 12 describes the symbol and slot structure for the Physical Uplink Control Channel, Format 2, of the 3GPP LTE system with extended cyclic-prefix mode;

    FIG. 13 describes the symbol and slot structure for the Physical Uplink Shared Channel of the 3GPP LTE system with normal cyclic-prefix mode, and sounding reference symbol;

    FIG. 14 describes the symbol and slot structure for the Physical Uplink Shared Channel of the 3GPP LTE system with extended cyclic-prefix mode, and sounding reference symbol;

    FIG. 15 describes the reference symbol locations for normal cyclic-prefix with one antenna port for the downlink of 3GPP LTE system; and

    FIG. 16 is a system diagram illustrating an example implementation of a computing system.



    [0013] Like reference symbols in the various drawings indicate like elements.

    DETAILED DESCRIPTION



    [0014] A Sparse Ordered Iterative Group Multi-Antenna Channel Estimation (SOI-MA-CE) scheme is described, which can be used to estimate channel characteristics (e.g., a channel response) between a transmitter with one or more antennas and a receiver equipped with multiple receiver antennas. SOI-MA-CE can iteratively estimate channel characteristics by, for example, iteratively finding significant (e.g., non-zero) delay taps of a channel estimate and adding the significant delay taps to an error measure of the channel estimate to form a sparse ordered channel estimate. The SOI-MA-CE scheme can iteratively process the sparse ordered channel estimate by finding significant delay taps until a predetermined number of iterations have occurred or another stopping criterion is satisfied.

    [0015] SOI-MA-CE can be implemented in a number of systems including at a base station or at user equipment (UE). For example, FIG. 1 is a system diagram illustrating an example Multi-UE Multi-stream spatial-division multiple access (SDMA) system 100 (or MU-MIMO) with a receiver with SOI-MA-CE 130 located at a base station 120. The system 100 includes multiple UEs (1051, 1052, ..., 105k), each having multiple transmit antennas (1101,1, 1101,2, ..., 1101,v), which communicate with the base station 120 having multiple receive antennas (1251, 1252, ..., 125k) via the wireless channel 140 (also denoted as H(n)). While FIG. 1 illustrates that the number of antennas on each UE 105 and the number of the antennas on the base station 120 are equal, the number of antennas on either the UE 105 and/or base station 120 can vary. In some example implementations, the number of streams per UE does not exceed the number of transmit antennas at that UE, and the total number of streams (summed across all the UEs) does not exceed the number of receive antennas at the base station.

    [0016] As a second example, FIG. 2 is a system diagram illustrating a base station 120 transmitter and a UE 105 with a receiver with SOI-MA-CE 130. As described herein, the receiver with SOI-MA-CE 130 can operate either in the uplink or downlink.

    [0017] FIG. 3 is a functional block diagram of an example uplink transmitter signal chain 300 within a UE 105 for a single data stream (e.g., a single data stream of the system configured as shown in FIG. 1). An information bit stream 305 can be passed through an encoder block 310. The coded bit stream at the output of the encoder can be scrambled at 315, and the scrambled sequence can be modulation mapped at 320 using a constellation such as BPSK, QPSK, or any higher order constellation. To maintain low peak-to-average power ratio, the modulation symbols can be DFT precoded at 325. The precoded complex-valued symbols can be mapped to a set of resource elements (REs) at 330. One RE can be a frequency tone associated with an OFDM symbol (when DFT precoding is applied, the symbol can also be referred to as an SC-FDMA symbol). Separately, a pilot sequence can generated at 335 using pilot sequence parameters 340. Pilot symbols of the generated pilot sequence can be multiplexed with modulation symbols in the Resource Mapper 330 before applying an inverse FFT (IFFT) at 345 to convert the frequency-domain symbols into a time-domain symbol stream 355. To minimize the inter-symbol interference (ISI) caused by the channel frequency-selectivity, a cyclic prefix can be added to the OFDM/SC-FDMA symbol at 350. The length of CP can be larger than the maximum expected channel delay to reduce or eliminate the ISI completely. The time-domain symbol stream 355 can be further processed and transmitted over the wireless channel (H(n)) 140 to the base station 120.

    [0018] FIG. 4 is a functional system diagram 400 of components of an example receiver with SOI-MA-CE 130 (e.g., in a system configured as shown in FIG. 1) for initial physical layer processing including channel estimation and channel equalization. A transmitted signal, having traveled through the wireless channel 140 is received by one or more receive antennas (1251, ..., 125K).

    [0019] With a single receiver antenna 1251, the time-varying and frequency-selective channel between the transmitter and the receiver can be described as

    where the variable t corresponds to time variations, the variable τ corresponds to the delay-domain, and the actual delay is denoted by τl(t). The delays are varying with time, therefore τl is a function of t. The number of paths, L(t), and the channel gains, hl(t), are also time-varying. Channel coherence in time-domain can be defined as the time duration during which the delays τl(t), the number of paths L(t), and the channel gains hl(t) do not change with time. If TC denotes the channel coherence, then for all tTC,



    [0020] Assuming sampling of the continuous received signal is at a rate of 1/TS, then the sample-spaced impulse response can be given by

    where N is the number of samples, and h(n) now is the n-th sample of the impulse response with a delay of nTS. However, since the channel length cannot be more than the length of cyclic prefix, NCP, there is effectively up to NCP non-zero samples of the channel h(n).

    [0021] At the example receiver with SOI-MA-CE 130, for each receiver antenna 125i (where i = 1, 2, ..., K), after performing down-conversion processing, automatic gain control (AGC) can be performed at 405i, CP removal can be performed at 410i leaving OFDM or SC-FDMA symbols, which can be processed using an FFT at 415i into the frequency domain. The effect of CP removal 410i, and FFT 415i is that the linear convolution, in time-domain, of the transmitted signal with the channel response becomes frequency-domain multiplication of the transmitted signal with the channel response.

    [0022] The pilot symbols, having been previously multiplexed with modulation symbols in the Resource Mapper 330, as shown in FIG. 3, can be de-multiplexed from the frequency domain data at 420i. The pilot pulses and de-multiplexed data can be provided for channel estimation at 425i, which will estimate the channel response 140. Once the channel estimation at 425i is complete, channel equalization for each receive data stream can be performed at 430.

    [0023] Regarding channel estimation at 425i, the frequency-domain version of the sample-spaced impulse response can denoted by H(f), and can be given by



    [0024] With pilot symbols inserted at frequency tones f1, f2, ...,fP, where P is the number of pilot tones, the received frequency-domain signal can be given by

    p = 1,2,...,P where Sp the p -th pilot symbol, and Wp is frequency-domain noise added on the p -th pilot symbol.

    [0025] The frequency-domain least-squares channel estimate (FDLSCE) on the p -th pilot symbol can given by

    where



    [0026] For convenience, the FDLSCE can be written compactly in the matrix-vector form as

    where F is the matrix of complex exponentials, h is the vector of unknown channel impulse response, and V is a noise vector. Given the number of pilot tones P, the pilot tone locations f1, f2, ..., fP, the sampling rate 1/TS, and the cyclic-prefix length, in some implementations, the matrix F can be pre-computed and stored.

    [0027] FIG. 5 is a functional block diagram illustrating an iterative SOI-MA-CE process 500 to estimate the channel response 140 (H(n)). More specifically, in this example implementation, the estimate is of the time domain channel denoted by hNiter. Initialization of the processing can occur at 505. An initial channel estimate 0 can provided at 505 and can be computed as

    where Herm is the Hermitian operator (i.e., conjugate the entries of the matrix first, and then the matrix transpose). Additionally, an initial error ε can be provided at 505 and can be computed as

    where G can be computed as G = FHerm F.

    [0028] At 510, an intermediate channel estimate k can be computed by adding the prior computed channel estimate k-1 to the error ε. The error ε can be scaled by a factor µ. In some implementations, k can be computed according to

    Where µ is non-negative and can be obtained from link-level or system-level simulations. Additionally, K can be initialized to 1.

    [0029] At 515, significant delay taps can be determined from k. Delay taps can be significant when they are non-zero, or when they are above a predetermined threshold. For example, finding significant delay taps can be performed by finding the nonzero entries of (|k (0)|, ..., |k (NCP)|). The significant delay taps can form the non-zero entries in a sparse vector describing the channel estimate k.

    [0030] At 520, variable K can be incremented (e.g., k = k+1) and at 525 it can be determined whether Niter iterations have completed. Niter can be a predetermined or predefined number of iterations for processing the sparse ordered channel estimate k.

    [0031] If the processing is to continue (e.g., there have not be Niter iterations completed), then at 530, the error ε between the initial estimate 0 and the most recent estimate k-1 can be computed according to



    [0032] The process can iterate (e.g., through 510, 515, 520, 525, and 530) until a predetermined number of iterations has completed (e.g., Niter), or until another stopping criterion is reached. Other stopping criterion can include, for example, when k includes a predetermined number of non-zero delay taps.

    [0033] Once the iteration is complete, a final channel response estimate (denoted by Niter) can, at 535, be used to compute channel delay spread and channel coherence bandwidth. The maximum and minimum delay spreads can be determined by max(I1, I2,..., IQ)and min(I1,I2,...,IQ), respectively, where the locations of non-zero entries in Niter are denoted by (I1,I2,...,IQ), and where Q is the number of non-zero taps. The average delay spread can be given by

    where c is the channel estimate index within the coherence window of NC symbols.

    [0034] The Root Mean Squared (RMS) delay-spread can be given by



    [0035] The frequency-domain channel estimate on a given frequency tone can be obtained as



    [0036] The channel coherence is inversely proportional to the channel delay spread. A typical coherence bandwidth measure, based on the RMS delay spread, with 90% correlation in frequency domain can be given by



    [0037] With 50% correlation in frequency domain, the coherence bandwidth is given by



    [0038] The following is an algorithm for an example implementation of a receiver with SOI-MA-CE 130.
    1. 1. Obtain the initial channel estimate as 0 = FHermY
    2. 2. Perform the following computations for each of the Niter iterations

    3. 3. The final estimate of the time-domain channel is given by Niter. The number of non-zero positions in the above vector is the length of the channel response in time, and the locations of non-zero values are the sample-spaced tap delays.
    4. 4. Compute the maximum, minimum, average and RMS delay spread and channel coherence bandwidth.


    [0039] The following extends the above-described SOI-MA-CE scheme to multiple receiver antennas.

    [0040] With M receiver antennas, the sample-spaced time-domain channel from the transmitter antennas to the mth receiver antenna is given by

    And the FDLSCE on mth receiver antenna can be described as



    [0041] Upon stacking Y(1),Y(2),...,Y(M) in columns for all the receiver antennas, Y can be described as



    [0042] The following is an algorithm for an example implementation of a receiver with SOI-MA-CE 130 having multiple receiver antennas.
    1. 1. Obtain the initial channel estimate as 0 = FHermY
    2. 2. Perform the following computations for each of the Niter iterations

    3. 3. The final estimate of the time-domain channel is given by Niter. The number of non-zero positions in the above vector is the length of the channel response in time, and the locations of non-zero values are the sample-spaced tap delays.
    4. 4. Compute the maximum, minimum, average and RMS delay spread and channel coherence bandwidth.


    [0043] Delay spread and channel coherence bandwidth for multiple receive antennas can be computed as follows. The maximum and minimum delay spreads for receive antenna m can be determined by Dmax,m = max(I1,m,I2,m,...,IQm,m) and Dmin,m = min(I1,m,I2,m,...,IQm,m), respectively, where the location ofnon-zero entries in Niter (:, m) are denoted by (I1,m,I2,m,...,IQm,m), and where Qm is the number of non-zero taps and is a function of receiver antenna index. The average delay spread can be given by

    where c is the channel estimate index within the coherence window of NC symbols.

    [0044] The Root Mean Squared (RMS) delay-spread can be given by



    [0045] Aggregate delay statistics across all the receiver antennas can be determined by using total channel power across the receiver antennas. The frequency-domain channel estimate on a given frequency tone, and on a given receiver antenna, can be obtained as



    [0046] The channel coherence is inversely proportional to the channel delay spread. A typical coherence bandwidth measure, based on the RMS delay spread, with 90% correlation in frequency domain can be given by



    [0047] The subject matter described herein provides many advantages. For example, the current subject matter does not require channel statistics, and in fact estimates the channel statistics (such as the delay spread, the number of taps) along with estimation of both time-domain and frequency-domain channels. Traditional channel estimation schemes often employ both time- and frequency-domain filtering to smooth the channel variations across time and frequency. However, designing optimal time- and frequency-domain filters require the knowledge of the channel second order statistics.

    [0048] Additionally, the current subject matter may not require either interpolation or extrapolation, thereby improving the quality of the estimate channel. Implementation of traditional channel estimation algorithms can involve, along with frequency-domain least squares channel estimation, interpolation and extrapolation. Both interpolation and extrapolation approaches introduce additional noise, which reduce the channel estimation reconstruction quality.

    [0049] Furthermore, the current subject matter can require very few frequency-domain signal samples relative to traditional channel estimation techniques. Once the time-domain channel taps are estimated, the current subject matter can allow for the flexibility of estimating the channel response over a selected sub-set of available frequency tones, which can apply to resource allocation in frequency-domain in multi-user OFDMA/SC-FDMA systems. With multiple users trying to access the same set of frequency resources, the current subject matter can first estimate the frequency-domain channel over the tones in a given allocation for all the users that compete for that allocation. The user that has the best channel quality (e.g., by estimating the channel power) can be given access to that allocation.

    [0050] As yet another non-limiting example advantage, the current subject matter can provide an estimate of the channel coherence bandwidth. Since channel coherence bandwidth is a measure of channel selectivity in frequency domain, knowledge of the channel coherence bandwidth can enable a scheduler (or resource allocation unit) to make allocations that are diversity in frequency-domain. Frequency-diversity resource allocations provide multi-user frequency-selective scheduling gains.

    [0051] By way of illustration and as an example of pilot pulse configurations, the LTE data channel (PUSCH) has a single demodulation reference symbol (DMRS) within a slot of seven symbols for normal CP (or six symbols for extended CP), as shown in FIGS. 6 and 7. If the channel bandwidth is 20 MHz, and if the PUSCH allocation size is one resource block (RB), which corresponds to 12 consecutive sub-carriers on the DRMS, then the channel estimation task is to obtain the channel estimate on the 1200 useful data tones (in LTE with 20 MHz channel bandwidth, the maximum number of resource blocks is 100, or the maximum number of data tones is 1200 sub-carriers), which is a difficult task with an allocation size of one RB. As a second example, the symbol and slot structure for various uplink control channel (PUCCH) formats are depicted in FIGS. 8 through 12. Here, the PUCCH allocations are made towards the edges of the RB allocations, and estimation of the overall frequency domain channel using traditional approaches can be prone to extrapolation errors. In a similar manner, in FIG. 15 the downlink reference signal structure is detailed for normal CP with one antenna port. Here, in each slot of seven OFDM symbols, there are only four reference signals available for channel estimation. Estimation of the channel on 12 subcarriers across seven OFDM symbols using four reference symbols can be a difficult task with conventional channel estimation algorithms as they incur both interpolation and extrapolation errors, along with errors due to channel variation across 12 subcarriers over seven OFDM symbols.

    [0052] In some implementations, the current subject matter can be configured to be implemented in a system 1600, as shown in FIG. 16. The system 1600 can include one or more of a processor 1610, a memory 1620, a storage device 1630, and an input/output device 1640. Each of the components 1610, 1620, 1630 and 1640 can be interconnected using a system bus 1650. The processor 1610 can be configured to process instructions for execution within the system 600. In some implementations, the processor 1610 can be a single-threaded processor. In alternate implementations, the processor 1610 can be a multi-threaded processor. The processor 1610 can be further configured to process instructions stored in the memory 1620 or on the storage device 1630, including receiving or sending information through the input/output device 1640. The memory 1620 can store information within the system 1600. In some implementations, the memory 1620 can be a computer-readable medium. In alternate implementations, the memory 1620 can be a volatile memory unit. In yet some implementations, the memory 1620 can be a non-volatile memory unit. The storage device 1630 can be capable of providing mass storage for the system 1600. In some implementations, the storage device 1630 can be a computer-readable medium. In alternate implementations, the storage device 1630 can be a floppy disk device, a hard disk device, an optical disk device, a tape device, non-volatile solid state memory, or any other type of storage device. The input/output device 1640 can be configured to provide input/output operations for the system 1600. In some implementations, the input/output device 1640 can include a keyboard and/or pointing device. In alternate implementations, the input/output device 1640 can include a display unit for displaying graphical user interfaces.

    [0053] The systems and methods disclosed herein can be embodied in various forms including, for example, a data processor, such as a computer that also includes a database, digital electronic circuitry, firmware, software, or in combinations of them. Moreover, the above-noted features and other aspects and principles of the present disclosed implementations can be implemented in various environments. Such environments and related applications can be specially constructed for performing the various processes and operations according to the disclosed implementations or they can include a general-purpose computer or computing platform selectively activated or reconfigured by code to provide the necessary functionality. The processes disclosed herein are not inherently related to any particular computer, network, architecture, environment, or other apparatus, and can be implemented by a suitable combination of hardware, software, and/or firmware. For example, various general-purpose machines can be used with programs written in accordance with teachings of the disclosed implementations, or it can be more convenient to construct a specialized apparatus or system to perform the required methods and techniques.

    [0054] The systems and methods disclosed herein can be implemented as a computer program product, i.e., a computer program tangibly embodied in an information carrier, e.g., in a machine readable storage device or in a propagated signal, for execution by, or to control the operation of, data processing apparatus, e.g., a programmable processor, a computer, or multiple computers. A computer program can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program can be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a communication network.

    [0055] As used herein, the term "user" can refer to any entity including a person or a computer.

    [0056] Although ordinal numbers such as first, second, and the like can, in some situations, relate to an order; as used in this document ordinal numbers do not necessarily imply an order. For example, ordinal numbers can be merely used to distinguish one item from another. For example, to distinguish a first event from a second event, but need not imply any chronological ordering or a fixed reference system (such that a first event in one paragraph of the description can be different from a first event in another paragraph of the description).

    [0057] The foregoing description is intended to illustrate but not to limit the scope of the invention, which is defined by the scope of the appended claims. Other implementations are within the scope of the following claims.

    [0058] These computer programs, which can also be referred to programs, software, software applications, applications, components, or code, include machine instructions for a programmable processor, and can be implemented in a high-level procedural and/or object-oriented programming language, and/or in assembly/machine language. As used herein, the term "machine-readable medium" refers to any computer program product, apparatus and/or device, such as for example magnetic discs, optical disks, memory, and Programmable Logic Devices (PLDs), used to provide machine instructions and/or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal used to provide machine instructions and/or data to a programmable processor. The machine-readable medium can store such machine instructions non-transitorily, such as for example as would a non-transient solid state memory or a magnetic hard drive or any equivalent storage medium. The machine-readable medium can alternatively or additionally store such machine instructions in a transient manner, such as for example as would a processor cache or other random access memory associated with one or more physical processor cores.

    [0059] To provide for interaction with a user, the subject matter described herein can be implemented on a computer having a display device, such as for example a cathode ray tube (CRT) or a liquid crystal display (LCD) monitor for displaying information to the user and a keyboard and a pointing device, such as for example a mouse or a trackball, by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well. For example, feedback provided to the user can be any form of sensory feedback, such as for example visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including, but not limited to, acoustic, speech, or tactile input.

    [0060] The subject matter described herein can be implemented in a computing system that includes a back-end component, such as for example one or more data servers, or that includes a middleware component, such as for example one or more application servers, or that includes a front-end component, such as for example one or more client computers having a graphical user interface or a Web browser through which a user can interact with an implementation of the subject matter described herein, or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, such as for example a communication network. Examples of communication networks include, but are not limited to, a local area network ("LAN"), a wide area network ("WAN"), and the Internet.

    [0061] The computing system can include clients and servers. A client and server are generally, but not exclusively, remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

    [0062] The implementations set forth in the foregoing description do not represent all implementations consistent with the subject matter described herein. Instead, they are merely some examples consistent with aspects related to the described subject matter. Although a few variations have been described in detail above, other modifications or additions are possible. In particular, further features and/or variations can be provided in addition to those set forth herein. For example, the implementations described above can be directed to various combinations and sub-combinations of the disclosed features and/or combinations and sub-combinations of several further features disclosed above. In addition, the logic flows depicted in the accompanying figures and/or described herein do not necessarily require the particular order shown, or sequential order, to achieve desirable results. Other implementations can be within the scope of the following claims.


    Claims

    1. A processor-implemented method for providing a final estimated channel impulse response, implementable by one or more data processors forming part of at least one computing system, the method comprising:

    receiving, by at least one data processor (130), a first signal transmitted in an orthogonal frequency-division multiplexing OFDM system by a transmitter (105) with one or more transmit antennas (110) through a wireless channel (140) and received by a receiver (120) with a plurality of receive antennas (125), the first signal comprising a plurality of pilot pulses;
    the method characterised by

    determining, using at least one data processor (130) and the first signal, a final estimated time-domain channel impulse response of the wireless channel for each pair of transmitter and receiver antennas by:

    computing a frequency-domain least-squares channel estimate Y(fp) for each pilot tone fp and expressing the frequency-domain least-squares channel estimate in compact matrix-vector form Y as a matrix product Fh + V where F is a matrix of complex exponentials, h is a vector of unknown channel impulse response, and V is a noise vector;

    computing an initial channel estimate 0 as a matrix product FHermY where FHerm is a Hermitian of the matrix of complex exponentials F,

    computing an initial error ε as 0 - (FHermF)0;

    computing an intermediate channel estimate k by adding the initial error ε to 0;

    determining non-zero delay taps from the intermediate channel

    estimate k by comparing a plurality of entries in the intermediate channel impulse response estimate to a threshold;

    adding the determined non-zero delay taps to the error ε;

    computing an error between the initial channel estimate 0 and a most recent channel estimate k - 1 as 0 - (FHermF)k - 1;

    computing a second intermediate channel estimate k + 1 as 0 - (FHermF)k + k;

    computing an error between the initial estimate 0 and the second intermediate channel estimate k + 1 as ε + 0 - (FHermF)k;

    repeating the steps of computing intermediate channel estimates and errors until a stopping criterion is reached; and

    providing, using at least one data processor (130), a last computed intermediate channel estimate as the final estimated channel impulse response.


     
    2. The method of claim 1, wherein the one or more found delay taps are non-zero entries of the intermediate channel estimate.
     
    3. The method of claim 1 or claim 2, further comprising determining an estimate of a channel frequency response for a plurality of sub-carriers.
     
    4. The method of any of the preceding claims, further comprising determining an estimate of a length of a channel impulse response of the wireless channel.
     
    5. The method of any of the preceding claims, further comprising determining, for each of the one or more transmit antennas (110), one or more of a maximum delay spread of the wireless channel, a minimum delay spread of the wireless channel, an average delay spread of the wireless channel, and a root-mean-square delay of the wireless channel.
     
    6. The method of any of the preceding claims, further comprising determining for each of the one or more transmit antennas (110), an estimate of a channel coherence bandwidth.
     
    7. A non-transitory computer program product storing instructions, which when executed by at least one data processor of at least one computing system, implement a method according to any of the preceding claims.
     
    8. A system comprising:

    at least one data processor (130);

    memory storing instructions which, when executed by the at least one data processor (130), causes the at least one data processor to implement a method according to any of claims 1 to 6.


     


    Ansprüche

    1. Prozessorimplementiertes Verfahren zum Bereitstellen einer endgültigen geschätzten Kanalimpulsantwort, das von einem oder mehreren Datenprozessoren implementiert werden kann, die Teil mindestens eines Computersystems sind, wobei das Verfahren umfasst:

    Empfangen eines ersten Signals, das in einem orthogonalen Frequenzmultiplex-OFDM-System von einem Sender (105) mit einer oder mehreren Sendeantennen (110) über einen Funkkanal (140) gesendet wird, von mindestens einem Datenprozessor (130) und das von einem Empfänger (120) mit mehreren Empfangsantennen (125) empfangen wird, wobei das erste Signal mehrere Steuerimpulse umfasst;

    wobei das Verfahren dadurch gekennzeichnet ist, dass unter Verwendung mindestens eines Datenprozessors (130) und des ersten Signals eine endgültige geschätzte Zeitbereichs-Kanalimpulsantwort des Funkkanals für jedes Paar von Sende- und Empfängerantennen bestimmt wird durch:

    Berechnen einer Frequenzbereich-Kanalschätzung der kleinsten Fehlerquadrate Y(fp) für jeden Kontrollton fp und Ausdrücken der Frequenzbereich-Kanalschätzung der kleinsten Fehlerquadrate in kompakter Matrix-Vektor-Form Y als Matrixprodukt Fh + V, wobei F eine Matrix komplexer Exponentiale ist, h ein Vektor einer unbekannten Kanalimpulsantwort ist und V ein Rauschvektor ist;

    Berechnen einer anfänglichen Kanalschätzung 0 als Matrixprodukt FHermY, wobei FHerm ein Hermitescher Operator der Matrix komplexer Exponentiale F ist, Berechnen eines anfänglichen Fehlers ε als 0 - (FHermF) 0;

    Berechnen einer Zwischenkanalschätzung k durch Addieren des Anfangsfehlers ε zu 0;

    Bestimmen von Nicht-Null-Verzögerungsabgriffen aus der Zwischenkanalschätzung k durch Vergleichen mehrerer Einträge in der Zwischenkanalimpulsantwortschätzung mit einem Schwellenwert;

    Addieren der bestimmten Nicht-Null-Verzögerungsabgriffe zum Fehler ε;

    Berechnen eines Fehlers zwischen der anfänglichen Kanalschätzung 0 und einer letzten Kanalschätzung -h̃k-1 als 0 (FHermF) k - 1;

    Berechnen einer zweiten Zwischenkanalschätzung k + 1 als 0-(FHermF) k + k;

    Berechnen eines Fehlers zwischen der anfänglichen Schätzung 0 und der zweiten Zwischenkanalschätzung k+1 als ε + 0-(FHermF) ĥk;

    Wiederholen der Schritte zum Berechnen von Zwischenkanalschätzungen und -fehlern, bis ein Stoppkriterium erreicht ist; und

    Bereitstellen einer zuletzt berechneten Zwischenkanalschätzung unter Verwendung mindestens eines Datenprozessors (130) als endgültige geschätzte Kanalimpulsantwort.


     
    2. Verfahren nach Anspruch 1, wobei der eine oder die mehreren gefundenen Verzögerungsabgriffe Nicht-Null-Einträge der Zwischenkanalschätzung sind.
     
    3. Verfahren nach Anspruch 1 oder Anspruch 2, ferner umfassend das Bestimmen einer Schätzung einer Kanalfrequenzantwort für mehrere Subträger.
     
    4. Verfahren nach einem der vorhergehenden Ansprüche, ferner umfassend das Bestimmen einer Schätzung einer Länge einer Kanalimpulsantwort des Funkkanals.
     
    5. Verfahren nach einem der vorhergehenden Ansprüche, ferner umfassend das Bestimmen einer oder mehrerer von einer maximalen Verzögerungsaufspreizung des drahtlosen Kanals, einer minimalen Verzögerungsaufspreizung des Funkkanals, einer durchschnittlichen Verzögerungsaufspreizung des Funkkanals und einer quadratischen mittleren Verzögerung des Funkkanals für jede der einen oder mehreren Sendeantennen (110).
     
    6. Verfahren nach einem der vorhergehenden Ansprüche, ferner umfassend das Bestimmen einer Schätzung einer Kanalkohärenzbandbreite für jede der einen oder mehreren Sendeantennen (110).
     
    7. Nicht flüchtiges Computerprogrammprodukt, das Anweisungen speichert, welche, wenn sie durch mindestens einen Datenprozessor mindestens eines Computersystems ausgeführt werden, das Verfahren nach einem der vorhergehenden Ansprüche implementieren.
     
    8. System, Folgendes umfassend:

    mindestens einen Datenprozessor (130);

    Speicherungsanweisungen, welche, wenn sie durch den mindestens einen Datenprozessor (130) ausgeführt werden, den mindestens einen Datenprozessor veranlassen, ein Verfahren nach einem der Ansprüche 1 bis 6 durchzuführen.


     


    Revendications

    1. Procédé mis en œuvre par un processeur pour fournir une réponse impulsionnelle de canal estimée finale, pouvant être mis en œuvre par un ou plusieurs processeurs de données faisant partie d'au moins un système informatique, le procédé comprenant :

    la réception, par au moins un processeur de données (130), d'un premier signal transmis dans un système OFDM de multiplexage par répartition en fréquence orthogonal par un émetteur (105) comportant une ou plusieurs antennes d'émission (110) par l'intermédiaire d'un canal sans fil (140) et reçu par un récepteur (120) comportant une pluralité d'antennes de réception (125), le premier signal comprenant une pluralité d'impulsions pilotes ;

    le procédé étant caractérisé par la détermination, en utilisant au moins un processeur de données (130) et le premier signal, d'une réponse impulsionnelle de canal de domaine temporel estimée finale du canal sans fil pour chaque paire d'antennes d'émetteur et de récepteur par :

    le calcul d'une estimation du canal par moindres carrés de domaine fréquentiel Y(fp) pour chaque tonalité pilote fp et l'expression de l'estimation de canal par moindres carrés de domaine fréquentiel sous forme de vecteur matriciel compact Y comme un produit matriciel Fh + VF représente une matrice d'exponentielles complexes, h représente un vecteur de réponse impulsionnelle de canal inconnue, et V est un vecteur de bruit ;

    le calcul d'une estimation de canal initiale 0 comme un produit matriciel FHerm Y où FHerm représente un Hermitien de la matrice d'exponentielles complexes F, le calcul d'une erreur initiale ε comme 0- (FHermF) 0 ;

    le calcul d'une estimation de canal intermédiaire k par l'ajout de l'erreur initiale ε à 0 ;

    la détermination des prises de retard non nulles à partir de l'estimation de canal intermédiaire k par la comparaison d'une pluralité d'entrées dans l'estimation de réponse impulsionnelle de canal intermédiaire à un seuil ;

    l'ajout des prises de retard non nulles déterminées à l'erreur ε ;

    le calcul d'une erreur entre l'estimation de canal initiale 0 et une estimation de canal la plus récente -ĥk -1 comme h̃0 (FHermF) h̃k - 1 ;

    le calcul d'une seconde estimation de canal intermédiaire k +1 comme 0-(FHermF) ĥk + k;

    le calcul d'une erreur entre l'estimation initiale 0 et la seconde estimation de canal intermédiaire k+1 comme ε + 0 -(FHermF) ĥk;

    la répétion des étapes de calcul des estimations et erreurs de canal intermédiaire jusqu'à ce qu'un critère d'arrêt soit atteint ; et

    la fourniture, en utilisant au moins un processeur de données (130), d'une dernière estimation de canal intermédiaire calculée comme la réponse impulsionnelle de canal estimée finale.


     
    2. Procédé selon la revendication 1, dans lequel les une ou plusieurs prises de retard trouvées sont des entrées non nulles de l'estimation de canal intermédiaire.
     
    3. Procédé selon la revendication 1 ou 2, comprenant en outre la détermination d'une estimation d'une réponse fréquentielle de canal pour une pluralité de sous-porteuses.
     
    4. Procédé selon l'une quelconque des revendications précédentes, comprenant en outre la détermination d'une estimation d'une longueur d'une réponse impulsionnelle de canal du canal sans fil.
     
    5. Procédé selon l'une quelconque des revendications précédentes, comprenant en outre la détermination, pour chacune des une ou plusieurs antennes d'émission (110), d'une ou de plusieurs d'une propagation à retard maximum du canal sans fil, d'une propagation à retard minimum du canal sans fil, d'une propagation de retard moyenne du canal sans fil et d'un retard quadratique moyen du canal sans fil.
     
    6. Procédé selon l'une quelconque des revendications précédentes, comprenant en outre la détermination pour chacune des une ou plusieurs antennes d'émission (110), d'une estimation d'une bande passante de cohérence de canal.
     
    7. Produit informatique non transitoire stockant des instructions qui, lorsqu'elles sont exécutées par au moins un processeur de données d'au moins un système informatique, mettent en œuvre un procédé selon l'une quelconque des revendications précédentes.
     
    8. Système comprenant :

    au moins un processeur de données (130) ;

    des instructions de stockage de mémoire qui, lorsqu'elles sont exécutées par l'au moins un processeur de données (130), amènent l'au moins un processeur de données à mettre en œuvre le procédé selon l'une quelconque des revendications 1 à 6.


     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description