(19)
(11)EP 3 147 942 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
09.09.2020 Bulletin 2020/37

(21)Application number: 16175721.6

(22)Date of filing:  22.06.2016
(51)International Patent Classification (IPC): 
H01L 25/065(2006.01)
H01L 25/16(2006.01)
H01L 23/00(2006.01)
H01L 23/31(2006.01)
H01L 23/50(2006.01)
H01L 23/538(2006.01)
H01L 25/10(2006.01)
H01L 21/56(2006.01)
H01L 23/14(2006.01)
H01L 23/498(2006.01)
H01L 21/48(2006.01)

(54)

SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE USING THE SAME AND MANUFACTURING METHOD THEREOF

HALBLEITERGEHÄUSE, HALBLEITERBAUELEMENT DAMIT UND HERSTELLUNGSVERFAHREN DAFÜR

BOÎTIER DE SEMI-CONDUCTEUR, DISPOSITIF À SEMI-CONDUCTEURS L'UTILISANT ET SON PROCÉDÉ DE FABRICATION


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 21.09.2015 US 201562221262 P
24.05.2016 US 201615162760

(43)Date of publication of application:
29.03.2017 Bulletin 2017/13

(73)Proprietor: MediaTek Inc.
Hsin-Chu 300 (TW)

(72)Inventors:
  • Hsu, Wen-Sung
    302 Zhubei City, Hsinchu County (TW)
  • Lin, Shih-Chin
    335 Taoyuan City (TW)
  • Cheng, Tao
    302 Zhubei City, Hsinchu County (TW)
  • Chang, Andrew C.
    300 Hsinchu City (TW)

(74)Representative: Krauns, Christian 
Wallinger Ricker Schlotter Tostmann Patent- und Rechtsanwälte Partnerschaft mbB Zweibrückenstraße 5-7
80331 München
80331 München (DE)


(56)References cited: : 
US-A1- 2011 140 259
US-A1- 2014 252 646
US-A1- 2012 061 814
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    FIELD OF THE INVENTION



    [0001] The invention relates to a semiconductor package, a semiconductor device using the same and a manufacturing method thereof, and more particularly to a thin semiconductor package, a semiconductor device using the same and a manufacturing method thereof.

    BACKGROUND OF THE INVENTION



    [0002] In the electronics industry, high integration and multiple functions with high performance become essential for new products. And meanwhile, high integration may cause higher manufacturing cost, since the manufacturing cost is in proportional to its size. Therefore, demanding on miniaturization of integrated circuit (IC) packages has become more and more critical.

    [0003] Package-on-package (PoP) is now the fastest growing semiconductor package technology since it is a cost-effective solution to high-density system integration in a single package. In a PoP structure, various packages are integrated in a single semiconductor package to reduce the size. Accordingly, there exists a need to provide a semiconductor package to overcomes, or at least reduces the above-mentioned problems. The US 2012/061814 A1 discloses a semiconductor device having a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die is mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads. The US 2011/140259 A1 discloses a manufacturing method of an integrated circuit packaging system. The method include fabricating a base package substrate, coupling a conductive column lead frame to the base package substrate by providing a lead frame support, patterning a conductive material on the lead frame support including forming an interconnect securing structure, and coupling the conductive material to the base package substrate, forming a base package body between the base package substrate and the conductive column lead frame, and removing the lead frame support from the conductive column lead frame for exposing the interconnect securing structure from the base package body.

    [0004] Therefore, it is important to increase the performance of the 3D graphic processing circuit while reducing the consumption of the electric power and extending the operating time of the mobile device.

    SUMMARY OF THE INVENTION



    [0005] The problems of the present invention are solved by a semiconductor package according to the independent claim 1 and a manufacturing method according to the independent claim 13. The dependent claims refer to further advantageous developments of the present invention. In one embodiment of the invention, a semiconductor package is provided. The semiconductor package includes a package substrate, a first electronic component and a second package body. The package substrate includes a first conductive layer, a first pillar layer, a first package body and a second conductive layer, wherein the first pillar layer is formed on the first conductive layer, the first package body encapsulates the first conductive layer and the first pillar layer, and the second conductive layer electrically connects to the first pillar layer. The first electronic component is disposed above the second conductive layer of the package substrate. The second package body encapsulates the first electronic component and the second conductive layer.

    [0006] In another embodiment of the invention, a semiconductor device is provided. The semiconductor device includes a semiconductor package, a second pillar layer and a third electronic component. The semiconductor package includes a package substrate, a first electronic component and a second package body. The package substrate includes a first conductive layer, a first pillar layer, a first package body and a second conductive layer, wherein the first pillar layer is formed on the first conductive layer, the first package body encapsulates the first conductive layer and the first pillar layer, and the second conductive layer electrically connects to the first pillar layer. The first electronic component is disposed above the second conductive layer of the package substrate. The second package body encapsulates the first electronic component and the second conductive layer. The second pillar layer is formed on the second conductive layer of the semiconductor package. The third electronic component is disposed above the second package body and electrically connects to the package substrate through the second pillar layer. The second package body further encapsulates the second pillar layer.

    [0007] In another embodiment of the invention, a manufacturing method of a semiconductor package is provided. The manufacturing method includes the following steps. A carrier is provided; a package body is formed and includes the steps of forming a first conductive layer on the carrier, forming a first pillar layer on the first conductive layer, forming a first package body encapsulating the first conductive layer and the first pillar layer, and forming a second conductive layer on the first pillar layer; a first electronic component is disposed above the second conductive layer of the package substrate; a second package body encapsulating the first electronic component and the second conductive layer is formed, and the carrier is removed.

    [0008] In another embodiment of the invention, a manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A carrier is provided; a package body is formed and includes the steps of forming a first conductive layer on the carrier, forming a first pillar layer on the first conductive layer, forming a first package body encapsulating the first conductive layer and the first pillar layer, and forming a second conductive layer on the first pillar layer; a first electronic component is disposed above the second conductive layer of the package substrate; a second package body encapsulating the first electronic component, the second conductive layer and the second pillar layer is formed, and the carrier is removed.

    [0009] Numerous objects, features and advantages of the invention will be readily apparent upon a reading of the following detailed description of embodiments of the invention when taken in conjunction with the accompanying drawings. However, the drawings employed herein are for the purpose of descriptions and should not be regarded as limiting.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0010] The above objects and advantages of the invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

    FIG. 1 illustrates a diagram of a semiconductor package according to an embodiment of the invention;

    FIG. 2 illustrates a diagram of a semiconductor package according to another embodiment of the invention;

    FIG. 3 illustrates a diagram of a semiconductor package according to another embodiment of the invention;

    FIG. 4 illustrates a diagram of a semiconductor package according to another embodiment of the invention;

    FIG. 5 illustrates a diagram of a semiconductor package according to another embodiment of the invention;

    FIG. 6 illustrates a diagram of a semiconductor device according to one embodiment of the invention;

    FIG. 7 illustrates a diagram of a semiconductor device according to another embodiment of the invention;

    FIGS. 8A to 8H illustrate manufacturing processes of the semiconductor package of FIG. 1;

    FIGS. 9A to 9B illustrate manufacturing processes of the semiconductor package of FIG. 2;

    FIGS. 10A to 10C illustrate manufacturing processes of the semiconductor package of FIG. 3;

    FIGS. 11A to 11H illustrate manufacturing processes of the semiconductor package of FIG. 4; and

    FIGS. 12A to 12C illustrate manufacturing processes of the semiconductor package of FIG. 5.


    DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS



    [0011] FIG. 1 illustrates a diagram of a semiconductor package 100 according to an embodiment of the invention. The semiconductor package 100 includes a package substrate 110, a first electronic component 120, a second package body 130, a second electronic component 140 and at least one conductive contact 150.

    [0012] The package substrate 110 includes a first conductive layer 111, a first pillar layer 112, a first package body 113 and a second conductive layer 114.

    [0013] The first conductive layer 111 includes a plurality of elements 1111, such as pads, traces or combination thereof. Each element 1111 has a first lower surface 1111b and a first lateral surface 1111s, and the first package body 113 has a second lower surface 113b. The first lower surface 1111b is exposed from the second lower surface 113b, and the first lower surface 1111b is aligned with the second lower surface 113b. Each element 1111 may be a multi-layered structure or single-layered structure. For example, each element 1111 includes nickel layer, gold layer, palladium layer, copper layer or combination thereof.

    [0014] The first pillar layer 112 connects the first conductive layer 111 to the second conductive layer 114. In the present embodiment, the first pillar layer 112 includes a plurality of pillars 1121. The pillars 1121 are made of a material such as copper. Each pillar 1121 has a first upper surface 1121u, and the first package body 113 has a second upper surface 113u, wherein the first upper surface 1121u is exposed from the second upper surface 113u and aligned with the second upper surface 113u.

    [0015] The first package body 113 encapsulates the first conductive layer 111 and the first pillar layer 112. For example, the first package body 113 encapsulates the first lateral surface 1111s of the first conductive layer 111 and the lateral surface of each pillar 1121.

    [0016] The first package body 113 may be a molding compound which is made of a material including, for example, a Novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant. Suitable fillers also can be included, such as powdered SiO2.

    [0017] Since the first package body 113 is the molding compound, the package substrate 110 has thin thickness t1. Compared to the silicon substrate, the thickness t1 of the package substrate 110 is much smaller. In general, the silicon substrate has a thickness larger than 100 micrometers. In the present embodiment, the thickness t1 of the package substrate 110 is smaller, and accordingly the thickness t2 of the semiconductor package 100 may be reduced.

    [0018] The second conductive layer 114 includes a plurality of elements 1141, such as pads, traces or combination thereof. Each element 1141 may be a multi-layered structure or single-layered structure. For example, the element 1141 may be nickel layer, gold layer, copper layer, palladium layer or combination thereof.

    [0019] In the present embodiment, the first electronic component 120 is coupled to the second conductive layer 114 of the package substrate 110 in a "face-down" orientation and electrically connected to the second conductive layer 114 via a plurality of conductive contacts 121. This configuration is sometimes referred to as "flip-chip". The conductive contact 121 may be solder ball, conductive pillar, etc.

    [0020] In other embodiments, the first electronic component 120 may be coupled to the package substrate 110 in a "face-up" orientation, and electrically connected to the package substrate 110 via a plurality of conductive bond wires (not shown). The first electronic component 120 may be an active chip or a passive component, such as a resistor, an inductor or a capacitor. In another embodiment, the number of the first electronic component 120 may be several. In addition, the first electronic component 120 may be, for example, a chip, a passive component, etc.

    [0021] The second package body 130 formed on the second upper surface 113u of the package substrate 110 encapsulates the second conductive layer 114 and the first electronic component 120. The second package body 130 may be made of a material which is the same as that of the first package body 113.

    [0022] The second electronic component 140 is disposed on the first lower surface 1111b of the first substrate 110 and electrically connects to the first conductive layer 111. In one embodiment, the second electronic component 140 is, for example, passive component, such as a resistor, an inductor or a capacitor.

    [0023] The conductive contacts 150 are disposed on the first lower surface 1111b of the first substrate 110. The semiconductor package 100 is disposed on and electrically connected to an exterior circuit, such as a circuit board, through the conductive contacts 150. The conductive contacts 150 may be solder ball, conductive pillar, etc.

    [0024] FIG. 2 illustrates a diagram of a semiconductor package 200 according to another embodiment of the invention. The semiconductor package 200 includes the package substrate 110, the first electronic component 120, the second package body 130, the second electronic component 140, at least one conductive contact 150, a second pillar layer 260 and an interposer 270.

    [0025] The second package body 130 further encapsulates the second pillar layer 260. The second pillar layer 260 includes a plurality of pillars 261 connecting the second conductive layer 114 to the interposer 270.

    [0026] The interposer 270 is disposed on the second package body 130 and electrically connects to the package substrate 110 through the second pillar layer 260 encapsulated within second package body 130. The interposer 270 may be electrically connected to the first electronic component 120 through the second pillar layer 260 and the package substrate 110.

    [0027] Each pillar 261 has a third upper surface 261u, and the second package body 130 has a fourth upper surface 130u, wherein the third upper surface 261u is exposed from the fourth upper surface 130u and aligned with the fourth upper surface 130u.

    [0028] FIG. 3 illustrates a diagram of a semiconductor package 300 according to another embodiment of the invention. The semiconductor package 300 includes the package substrate 110, the first electronic component 120, the second package body 130, the second electronic component 140, at least one conductive contact 150, the second pillar layer 260 and a fourth conductive layer 370.

    [0029] The second package body 130 encapsulates the second conductive layer 114, the second pillar layer 260 and the fourth conductive layer 370.

    [0030] The second pillar layer 260 electrically connects the second conductive layer 114 to the fourth conductive layer 370, such that the first electronic component 120 may electrically connect the fourth conductive layer 370 through the package substrate 110 and the second pillar layer 260.

    [0031] The fourth conductive layer 370 includes a plurality of elements 371, such as pads, traces or combination thereof. Each element 371 has a fifth upper surface 371u, and the second package body 130 has the fourth upper surface 130u, wherein the fifth upper surface 371u is exposed from the fourth upper surface 130u and aligned with the fourth upper surface 130u.

    [0032] Each element 371 may be a multi-layered structure or single-layered structure. For example, the each element 371 includes nickel layer, gold layer, palladium layer, copper layer or combination thereof.

    [0033] The fourth conductive layer 370 is embedded in the second package body 130. For example, each element 371 (trace or pad) has a second lateral surface 371s which is encapsulated by the second package body 130. Since the fourth conductive layer 370 is embedded in the second package body 130, the second package body 130 has a thin thickness t3.

    [0034] FIG. 4 illustrates a diagram of a semiconductor package 400 according to another embodiment of the invention. The semiconductor package 400 includes a package substrate 410, the first electronic component 120, the second package body 130, the second electronic component 140, at least one conductive contact 150, the second pillar layer 260 and the interposer 270.

    [0035] In the present embodiment, the package substrate 410 is multi-layered package structure. For example, the package substrate 410 includes the first conductive layer 111, the first pillar layer 112, the first package body 113, the second conductive layer 114, a third conductive layer 411, a third pillar layer 412 and a third package body 413. The first conductive layer 111, the first pillar layer 112 and the first package body 113 together form a first single-layered package structure, and the third conductive layer 411, the third pillar layer 412 and the third package body 413 form a second single-layered package structure. In another embodiment, the number of the layers of the package substrate 410 may be more than two.

    [0036] The third conductive layer 411 is formed on the second upper surface 113u of the first package body 113 and electrical connects to the first pillar layer 112. The third pillar layer 412 connects the third conductive layer 411 to the second conductive layer 114. The third package body 413 encapsulates the third pillar layer 412 and the third conductive layer 411. In the present embodiment, the second conductive layer 114 is formed on a sixth upper surface 413u of the third package body 413 and electrically connects to the first conductive layer 111 through the third conductive layer 411, the third pillar layer 412 and the first pillar layer 112.

    [0037] In addition, the third package body 413 may be made of a material which is the same as that of the first package body 113.

    [0038] Since the first package body 113 and the third package body 413 are the molding compounds, the package substrate 410 has thin thickness t1. Compared to the silicon substrate, the thickness t1 of the package substrate 410 is much smaller. In general, the silicon substrate has the thickness larger than 100 micrometers. In the present embodiment, the thickness t1 of the package substrate 410 is smaller, and accordingly the thickness t2 of the semiconductor package 100 may be reduced.

    [0039] FIG. 5 illustrates a diagram of a semiconductor package 500 according to another embodiment of the invention. The semiconductor package 500 includes the package substrate 410, the first electronic component 120, the second package body 130, the second electronic component 140, at least one conductive contact 150, the second pillar layer 260 and the fourth conductive layer 370.

    [0040] In the present embodiment, since the fourth conductive layer 370 is embedded in the second package body 130, the second package body 130 has the thin thickness t3. The second pillar layer 260 electrically connects the second conductive layer 114 to the fourth conductive layer 370, such that the first electronic component 120 may electrically connect the fourth conductive layer 370 through the package substrate 410 and the second pillar layer 260.

    [0041] FIG. 6 illustrates a diagram of a semiconductor device 10 according to one embodiment of the invention. The semiconductor device 10 includes the semiconductor package 200 and a third electronic component 11. In another embodiment, the third electronic component 11 may be a semiconductor package including a plurality of dies, such as DRAMs stacked to each other.

    [0042] The third electronic component 11 is disposed on the interposer 270 of the semiconductor package 200 in a "face-down" orientation and electrically connected to the interposer 270 via a plurality of conductive contacts 115. The conductive contacts 115 may be solder ball, conductive pillar, etc. In another embodiment, the third electronic component 11 is disposed on the interposer 270 in a "face-up" orientation and electrically connected to the interposer 270 via a plurality of conductive bond wires (not shown). The third electronic component 11 electrically connects to the first electronic component 120 through the interposer 270, the second pillar layer 260 and the package substrate 110. In addition, the third electronic component 11 electrically connects to the conductive contacts 150 through the interposer 270, the second pillar layer 260 and the package substrate 110.

    [0043] FIG. 7 illustrates a diagram of a semiconductor device 20 according to another embodiment of the invention. The semiconductor device 20 includes the semiconductor package 300 and a third electronic component 11.

    [0044] The third electronic component 11 is disposed on the fourth conductive layer 370 of the semiconductor package 300 in a "face-down" orientation or in a "face-up" orientation. The third electronic component 11 electrically connects to the first electronic component 120 through the fourth conductive layer 370, the second pillar layer 260 and the package substrate 110. In addition, the third electronic component 11 electrically connects to the conductive contacts 150 through the fourth conductive layer 370, the second pillar layer 260 and the package substrate 110.

    [0045] In another embodiment, the third electronic component 11 may be disposed on the interposer 270 of the semiconductor package 400 of FIG. 4 to form another semiconductor device. In other embodiment, the third electronic component 11 may be disposed on the fourth conductive layer 370 of the semiconductor package 500 of FIG. 5 to form another semiconductor device.

    [0046] FIGS. 8A to 8H illustrate manufacturing processes of the semiconductor package 100 of FIG. 1.

    [0047] Referring to FIG. 8A, a carrier 180 is provided. The carrier 180 may be formed by a metal plate comprising of copper, iron or steel.

    [0048] Referring to FIG. 8A, the first conductive layer 111 is formed on the carrier 180 using, for example, photolithography, electroless plating, electrolytic plating, printing, sputtering, vacuum deposition, etc.

    [0049] Referring to FIG. 8B, the first pillar layer 112 is formed on the first conductive layer 111 using, for example, photolithography, electroless plating, electrolytic plating, printing, sputtering, vacuum deposition, etc.

    [0050] Referring to FIG. 8C, the first package body 113 encapsulating the first conductive layer 111 and the first pillar layer 112 is formed on an upper surface 180u of the carrier 180. The first package body 113 may be formed by various packaging technologies, such as, for example, compression molding, injection molding, transfer molding or dispensing technology.

    [0051] In the present embodiment, the first package body 113 may be grinded, such that the first upper surface 1121u of each pillar 1121 is exposed from the second upper surface 113u of the first package body 113, wherein the first upper surface 1121u is aligned with the second upper surface 113u.

    [0052] Referring to FIG. 8D, the second conductive layer 114 is formed on the first pillar layer 112 using, for example, photolithography, electroless plating, electrolytic plating, printing, sputtering, vacuum deposition, etc. The first conductive layer 111, the first pillar layer 112, the first package body 113 and the second conductive layer 114 form the package substrate 110.

    [0053] Referring to FIG. 8E, the first electronic component 120 is disposed on second conductive layer 114 of the package substrate 110 through the conductive contacts 121 using, for example, surface mount technology (SMT).

    [0054] Referring to FIG. 8F, the second package body 130 encapsulating the first electronic component 120 and the second conductive layer 114 is formed on the package substrate 110. The second package body 130 may be formed by various packaging technologies, such as, for example, compression molding, injection molding, transfer molding or dispensing technology.

    [0055] Referring to FIG. 8G, the carrier 180 is removed using, for example, etching, peeling, etc. After the carrier 180 is removed, the first lower surface 1111b of the first conductive layer 111 and the second lower surface 113b of the first package body 113 are exposed, wherein the first lower surface 1111b and the second lower surface 113b are aligned with each other. For example, the first lower surface 1111b and the second lower surface 113b are coplanar.

    [0056] Referring to FIG. 8H, the conductive contacts 150 are formed on the first lower surface 1111b of the first conductive layer 111 using, for example, ball mounting technology. In addition, the second electronic component 140 is disposed on the first lower surface 1111b of the first conductive layer 111 using, for example, SMT.

    [0057] FIGS. 9A to 9B illustrate manufacturing processes of the semiconductor package 200 of FIG. 2.

    [0058] Referring to FIG. 9A, the interposer 270 connects to the package substrate 110 through the second pillar layer 260. The interposer 270 may electrically connect to the first electronic component 120 through the second pillar layer 260 and the package substrate 110.

    [0059] Referring to FIG. 9B, the second package body 130 encapsulating the first electronic component 120, the second conductive layer 114 and second pillar layer 260 is formed between the package substrate 110 and the interposer 270. The second package body 130 may be formed by various packaging technologies, such as, for example, compression molding, injection molding, transfer molding or dispensing technology.

    [0060] Then, referring to FIG. 9B, the carrier 180 is removed. After the carrier 180 is removed, the first lower surface 1111b of the first conductive layer 111 and the second lower surface 113b of the first package body 113 are exposed, wherein the first lower surface 1111b and the second lower surface 113b are aligned with each other. For example, the first lower surface 1111b and the second lower surface 113b are coplanar.

    [0061] Then, the conductive contacts 150 and the second electronic component 140 are formed on the first lower surface 1111b of the first conductive layer 111 to form the semiconductor package 200 of FIG. 2.

    [0062] In another embodiment, the third electronic component 11 of FIG. 6 may be disposed on the interposer 270 of FIG. 9B to form the semiconductor device 10 of FIG. 6.

    [0063] FIGS. 10A to 10C illustrate manufacturing processes of the semiconductor package 300 of FIG. 3.

    [0064] Referring to FIG. 10A, the fourth conductive layer 370 formed on a carrier 190 connects to the package substrate 110 through the second pillar layer 260. The fourth conductive layer 370 may electrically connect to the first electronic component 120 through the second pillar layer 260 and the package substrate 110.

    [0065] Referring to FIG. 10B, the second package body 130 encapsulating the first electronic component 120, the second conductive layer 114, the second pillar layer 260 and the fourth conductive layer 370 is formed between the package substrate 110 and the carrier 190. The second package body 130 may be formed by various packaging technologies, such as, for example, compression molding, injection molding, transfer molding or dispensing technology.

    [0066] Referring to FIG. 10C, the carrier 190 is removed to expose the fourth upper surface 130u of the second package body 130 and the fifth upper surface 371u of the fourth conductive layer 370, wherein the fourth upper surface 130u and the fifth upper surface 371u are aligned with each other.

    [0067] Referring to FIG. 10C, the carrier 180 is removed. After the carrier 180 is removed, the first lower surface 1111b of the first conductive layer 111 and the second lower surface 113b of the first package body 113 are exposed, wherein the first lower surface 1111b and the second lower surface 113b are aligned with each other. For example, the first lower surface 1111b and the second lower surface 113b are coplanar.

    [0068] Then, the conductive contacts 150 and the second electronic component 140 are formed on the first lower surface 1111b of the first conductive layer 111 to form the semiconductor package 300 of FIG. 3.

    [0069] In another embodiment, the third electronic component 11 of FIG. 7 may be disposed on the fourth conductive layer 370 of FIG. 10C to form the semiconductor device 20 of FIG. 7.

    [0070] FIGS. 11A to 11H illustrate manufacturing processes of the semiconductor package 400 of FIG. 4.

    [0071] Referring to FIG. 11A, the carrier 180 is provided. The carrier 180 may be formed by a metal plate comprising of copper, iron or steel.

    [0072] Referring to FIG. 11A, the first conductive layer 111, the first pillar layer 112, the first package body 113 are formed on the carrier 180 using the processes, as mentioned above.

    [0073] Referring to FIG. 11B, the third pillar layer 411 is formed on the first pillar layer 112 using, for example, photolithography, electroless plating, electrolytic plating, printing, sputtering, vacuum deposition, etc.

    [0074] Referring to FIG. 11B, the third pillar layer 412 is formed on the third pillar layer 411 using, for example, photolithography, electroless plating, electrolytic plating, printing, sputtering, vacuum deposition, etc.

    [0075] Referring to FIG. 11C, the third package body 413 encapsulating the third conductive layer 411 and the third pillar layer 412 is formed on the second upper surface 113u of the first package body 113. The third package body 413 may be formed by various packaging technologies, such as, for example, compression molding, injection molding, transfer molding or dispensing technology.

    [0076] In the present embodiment, the third package body 413 may be grinded, such that an upper surface 412u of the third pillar layer 412 is exposed from the sixth upper surface 413u of the third package body 413, wherein the upper surface 412u is aligned with the sixth upper surface 413u.

    [0077] Referring to FIG. 11D, the second conductive layer 114 is formed on the third pillar layer 412 using, for example, photolithography, electroless plating, electrolytic plating, printing, sputtering, vacuum deposition, etc. The first conductive layer 111, the first pillar layer 112, the first package body 113, the second conductive layer 114, the third conductive layer 411, the third pillar layer 412 and the third package body 413 form the package substrate 410.

    [0078] Referring to FIG. 11E, the first electronic component 120 is disposed on second conductive layer 114 of the package substrate 410 through the conductive contacts 121 using, for example, surface mount technology (SMT).

    [0079] Referring to FIG. 11F, the interposer 270 connects to the package substrate 410 through the second pillar layer 260. The interposer 270 may electrically connect to the first electronic component 120 through the second pillar layer 260 and the package substrate 410.

    [0080] Referring to FIG. 11G, the second package body 130 encapsulating the first electronic component 120, the second conductive layer 114 and second pillar layer 260 is formed between the package substrate 410 and the interposer 270. The second package body 130 may be formed by various packaging technologies, such as, for example, compression molding, injection molding, transfer molding or dispensing technology.

    [0081] Referring to FIG. 11H, the carrier 180 is removed using, for example, etching, peeling, etc. After the carrier 180 is removed, the first lower surface 1111b of the first conductive layer 111 and the second lower surface 113b of the first package body 113 are exposed, wherein the first lower surface 1111b and the second lower surface 113b are aligned with each other. For example, the first lower surface 1111b and the second lower surface 113b are coplanar.

    [0082] Then, the conductive contacts 150 and the second electronic component 140 are formed on the first lower surface 1111b of the first conductive layer 111 to form the semiconductor package 400 of FIG. 4.

    [0083] In another embodiment, the third electronic component 11 of FIG. 6 may be disposed on the interposer 270 of FIG. 11H to form another semiconductor device.

    [0084] FIGS. 12A to 12C illustrate manufacturing processes of the semiconductor package 500 of FIG. 5.

    [0085] Referring to FIG. 12A, the fourth conductive layer 370 formed on the carrier 190 connects to the package substrate 410 through the second pillar layer 260. The fourth conductive layer 370 may electrically connect to the first electronic component 120 through the second pillar layer 260 and the package substrate 410.

    [0086] Referring to FIG. 12B, the second package body 130 encapsulating the first electronic component 120, the second conductive layer 114, the second pillar layer 260 and the fourth conductive layer 370 is formed between the package substrate 410 and the carrier 190. The second package body 130 may be formed by various packaging technologies, such as, for example, compression molding, injection molding, transfer molding or dispensing technology.

    [0087] Referring to FIG. 12C, the carrier 190 is removed to expose the fourth upper surface 130u of the second package body 130 and the fifth upper surface 371u of the fourth conductive layer 370, wherein the fourth upper surface 130u and the fifth upper surface 371u are aligned with each other.

    [0088] Referring to FIG. 12C, the carrier 180 is removed. After the carrier 180 is removed, the first lower surface 1111b of the first conductive layer 111 and the second lower surface 113b of the first package body 113 are exposed, wherein the first lower surface 1111b and the second lower surface 113b are aligned with each other. For example, the first lower surface 1111b and the second lower surface 113b are coplanar.

    [0089] Then, the conductive contacts 150 and the second electronic component 140 are formed on the first lower surface 1111b of the first conductive layer 111 to form the semiconductor package 500 of FIG. 5.

    [0090] In another embodiment, the third electronic component 11 of FIG. 7 may be disposed on the fourth conductive layer 370 of FIG. 12C to form another semiconductor device.


    Claims

    1. A semiconductor package (100-500), comprising:

    a package substrate (110, 410), which comprises:

    a layer (111) of first conductive elements (1111), in the following called first conductive layer (111);

    a layer (112) of first pillars (1121) formed on the first conductive layer (111), in the following called first pillar layer (112);

    a first package body (113) encapsulating the first conductive layer (111) and the first pillar layer (112);

    a layer (114) of second conductive elements (1141)

    electrically connecting to the first pillar layer (112), in the following called second conductive layer (114);

    a first electronic component (120) disposed above the second conductive layer (114) of the package substrate (110, 410);

    a second package body (130) encapsulating the first electronic component (120) and the second conductive layer (114);

    a layer (260) of second pillars (261) formed on the second conductive layer (114), in the following called second pillar layer (260), and

    an interposer (270) disposed on the second package body (130), electrically connected to the second pillars (261) and covering a top surface of the second package body (130) and a top surface of each second pillar (261) of the second pillar layer (260);

    wherein the second package body (130) further completely encapsulates a lateral
    surface of each second pillar (261) of the second pillar layer (260).


     
    2. The semiconductor package (100-500) as claimed in claim 1, wherein the first package body (113) is a molding compound.
     
    3. The semiconductor package (100-500) as claimed in claim 1 or 2, wherein the package substrate (110, 410) further comprises:

    a layer (411) of third conductive elements formed on the first package body (113), in the following called third conductive layer (411);

    a layer (412) of third pillars connecting the third conductive layer (411) to the second conductive layer (114), in the following called third pillar layer (412); and

    a third package body (413) encapsulating the third pillar layer (412) and the third conductive layer (411);

    wherein the second conductive layer (114) is formed on the third package body (413).


     
    4. The semiconductor package (100-500) as claimed in claim 3, wherein the third package body (413) is a molding compound.
     
    5. The semiconductor package (100-500) as claimed in any one of the claims 1 to 4, wherein the first conductive layer (111) has a first lower surface (1111b), the first package body (113) has a second lower surface (113b), the first lower surface (1111b) is exposed from the second lower surface (113b), and the semiconductor package (100-500) further comprises:
    a second electronic component (140) disposed on the first lower surface (1111b) of the first conductive layer (111).
     
    6. The semiconductor package (100-500) as claimed in any one of the claims 1 to 5, wherein
    the interposer (270) is electrically connected to the package substrate (110, 410) through the second pillar layer (260).
     
    7. The semiconductor package (100-500) as claimed in any one of the claims 1 to 6, wherein the semiconductor package (100-500) further comprises:

    a layer (370) of fourth conductive elements (371), in the following called fourth conductive layer (370);

    wherein the second pillar layer (260) connects the fourth conductive layer (370) to the second conductive layer (114);

    wherein the second package body (130) encapsulates the second pillar layer (260) and the fourth conductive layer (370).


     
    8. The semiconductor package (100-500) as claimed in any one of the claims 1 to 7, wherein the first pillar layer (112) has a first upper surface, the first package body (113) has a second upper surface (113u), and the first upper surface is aligned with the second upper surface (113u).
     
    9. The semiconductor package (100-500) as claimed in any one of the claims 1 to 8, wherein the first conductive layer (111) has a first lower surface (1111b), the first package body (113) has a second lower surface (113b), and the first lower surface (1111b) is aligned with the second lower surface (113b).
     
    10. A semiconductor device (10, 20), comprising:

    a semiconductor package (100-500) as claimed in any of the claims 1 to 9; and

    a third electronic component (11) disposed above the second package body (130) and electrically connecting to the package substrate (110, 410) through the second pillar layer (260);

    wherein the second package body (130) further encapsulates the second pillar layer (260).


     
    11. The semiconductor device (10, 20) as claimed in claim 10, wherein
    the third electronic component (11) is disposed on and electrically to the interposer (270).
     
    12. The semiconductor device (10, 20) as claimed in claim 10 or 11, wherein the semiconductor device (10, 20) further comprises:

    a conductive layer (370) of fourth conductive elements (371), in the following called fourth conductive layer (370); and

    wherein the second pillar layer (260) connects the fourth conductive layer (370) to the second conductive layer (114), the second package body (130) encapsulates the second pillar layer (260) and the fourth conductive layer (370), and the third electronic component (11) is disposed on and electrically to the fourth conductive layer (370).


     
    13. A manufacturing method of a semiconductor package (100-500) according to claim 1, the method
    comprising:
    providing a carrier (180);
    forming a package substrate (110, 410), comprising:

    forming a first conductive layer (111) of first conductive elements (1111) on the carrier (180);

    forming a first pillar layer (112) of first pillars (1121) on the first conductive layer (111);

    forming a first package body (113) encapsulating the first conductive layer (111) and the first pillar layer (112); and

    forming a second conductive layer (114) of second conductive elements (1141) on the first pillar layer (112);

    disposing a first electronic component (120) above the second conductive layer (114) of the package substrate (110, 410);

    forming a second pillar layer (260) of second pillars on the second conductive layer (114);

    disposing an interposer (270) on the second pillar layer (260), wherein the interposer (270) is electrically connected to the second pillars (261) and covers a top surface of each second pillar (261) of the second pillar layer (260);

    forming a second package body (130) encapsulating the first electronic component (120) and the second conductive layer (114), wherein the second package body (130) further completely encapsulates lateral surface of each second pillar (261) of the second pillar layer (260); and

    removing the carrier (180).


     
    14. The manufacturing method of a semiconductor device (10, 20) as claimed in claim 13, the method further comprising:

    connecting the second pillar layer (260) to the package substrate (110, 410); and

    disposing a third electronic component (11) above the second package body (130), wherein the third electronic component (11) electrically connects to the package substrate (110, 410) through the second pillar layer (260).


     


    Ansprüche

    1. Halbleiterbaugruppe (100-500), welche aufweist:
    ein Baugruppensubstrat (110, 410), welches aufweist:

    eine Schicht (111) aus ersten leitenden Elementen (1111), die im Folgenden als eine erste leitende Schicht (111) bezeichnet wird;

    eine Schicht (112) aus ersten Säulen (1121), die auf der ersten leitenden Schicht (111) ausgebildet worden ist und die im Folgenden als eine erste Säulenschicht (112) bezeichnet wird;

    einen ersten Baugruppenkörper (113), der die erste leitende Schicht (111) und die erste Säulenschicht (112) einkapselt und der im Folgenden als ein erster Baugruppenkörper (113) bezeichnet wird;

    eine Schicht (114) aus zweiten leitenden Elementen (1141), die elektrisch mit der ersten Säulenschicht (112) verbunden ist und die im Folgenden als eine zweite leitende Schicht (114) bezeichnet wird;

    eine erste elektronische Komponente (120), die über der zweiten leitenden Schicht (114) des Baugruppensubstrats (110, 410) angeordnet ist;

    einen zweiten Baugruppenkörper (130), der die erste elektronische Komponente (120) und die zweite leitende Schicht (114) einkapselt;

    eine Schicht (260) aus zweiten Säulen (261), die auf der zweiten leitenden Schicht (114) ausgebildet worden ist und die im Folgenden als eine zweite Säulenschicht (260) bezeichnet wird; und

    einen Zwischenelement (270), das auf dem zweiten Baugruppenkörper (130) angeordnet ist und das elektrisch mit den zweiten Säulen (261) verbunden ist und das eine obere Oberfläche des zweiten Baugruppenkörpers (130) und eine obere Oberfläche von jeder zweiten Säule (261) der zweiten Säulenschicht (260) bedeckt;

    wobei der zweite Baugruppenkörper (130) ferner eine seitliche Oberfläche von jeder zweiten Säule (261) der zweiten Säulenschicht (260) vollständig einkapselt.


     
    2. Halbleiterbaugruppe (100-500) nach Anspruch 1, wobei der erste Baugruppenkörper (113) eine Formmasse ist.
     
    3. Halbleiterbaugruppe (100-500) nach Anspruch 1 oder 2, wobei das Gehäusesubstrat (110, 410) ferner aufweist:

    eine Schicht (411) aus dritten leitenden Elementen, die auf dem ersten Baugruppenkörper (113) ausgebildet worden ist und die im Folgenden als eine dritte leitende Schicht (411) bezeichnet wird;

    eine Schicht (412) aus dritten Säulen, die die dritte leitende Schicht (411) mit der zweiten leitenden Schicht (114) verbindet und die im Folgenden als eine dritte Säulenschicht (412) bezeichnet wird; und

    einen dritten Baugruppenkörper (413), der die dritte Säulenschicht (412) und die dritte leitende Schicht (411) einkapselt;

    wobei die zweite leitende Schicht (114) auf dem dritten Baugruppenkörper (413) ausgebildet worden ist.


     
    4. Halbleiterbaugruppe (100-500) nach Anspruch 3, wobei der dritte Baugruppenkörper (413) eine Formmasse ist.
     
    5. Halbleiterbaugruppe (100-500) nach einem der Ansprüche 1 bis 4, wobei die erste leitende Schicht (111) eine erste untere Oberfläche (1111b) aufweist, der erste Baugruppenkörper (113) eine zweite untere Oberfläche (113b) aufweist, die erste untere Oberfläche (1111b) gegenüber der zweiten unteren Oberfläche (113b) freigelegt ist, und die Halbleiterbaugruppe (100-500) ferner aufweist:
    eine zweite elektronische Komponente (140), die auf der ersten unteren Oberfläche (1111b) der ersten leitenden Schicht (111) angeordnet ist.
     
    6. Halbleiterbaugruppe (100-500) nach einem der Ansprüche 1 bis 5, wobei das Zwischenelement (270) über die zweite Säulenschicht (260) elektrisch mit dem Baugruppensubstrat (110, 410) verbunden ist.
     
    7. Halbleiterbaugruppe (100-500) nach einem der Ansprüche 1 bis 6, wobei die Halbleiterbaugruppe (100-500) ferner aufweist:

    eine Schicht (370) aus vierten leitenden Elementen (371), die im Folgenden als eine vierte leitende Schicht (370) bezeichnet wird;

    wobei die zweite Säulenschicht (260) die vierte leitende Schicht (370) mit der zweiten leitenden Schicht (114) verbindet;

    wobei der zweite Baugruppenkörper (130) die zweite Säulenschicht (260) und die vierte leitende Schicht (370) einkapselt.


     
    8. Halbleiterbaugruppe (100-500) nach einem der Ansprüche 1 bis 7, wobei die erste Säulenschicht (112) eine erste obere Oberfläche aufweist, der erste Baugruppenkörper (113) eine zweite obere Oberfläche (113u) aufweist und die erste obere Oberfläche mit der zweiten oberen Oberfläche (113u) ausgerichtet ist.
     
    9. Halbleiterbaugruppe (100-500) nach einem der Ansprüche 1 bis 8, wobei die erste leitende Schicht (111) eine erste untere Oberfläche (1111b) aufweist, der erste Baugruppenkörper (113) eine zweite untere Oberfläche (113b) aufweist und die erste untere Oberfläche (1111b) mit der zweiten unteren Oberfläche (113b) ausgerichtet ist.
     
    10. Halbleitervorrichtung (10, 20), welche aufweist:

    ein Halbleiterbaugruppe (100-500) nach einem der Ansprüche 1 bis 9; und

    eine dritte elektronische Komponente (11), die über dem zweiten Baugruppenkörper (130) angeordnet ist und die über die zweite Säulenschicht (260) elektrisch mit dem Baugruppensubstrat (110, 410) verbunden ist;

    wobei der zweite Baugruppenkörper (130) die zweite Säulenschicht (260) weiter einkapselt.


     
    11. Halbleitervorrichtung (10, 20) nach Anspruch 10, wobei die dritte elektronische Komponente (11) auf dem Zwischenelement (270) angeordnet ist und elektrisch mit diesem verbunden ist.
     
    12. Halbleitervorrichtung (10, 20) nach Anspruch 10 oder 11, wobei die Halbleitervorrichtung (10, 20) ferner aufweist:

    eine Schicht (370) aus vierten leitenden Elementen (371), die im Folgenden als eine vierte leitende Schicht (370) bezeichnet wird; und

    wobei die zweite Säulenschicht (260) die vierte leitende Schicht (370) mit der zweiten leitenden Schicht (114) verbindet, der zweite Gehäusekörper (130) die zweite Säulenschicht (260) und die vierte leitende Schicht (370) einkapselt, und die dritte elektronische Komponente (11) auf der vierten leitenden Schicht (370) angeordnet ist und elektrisch mit dieser verbunden ist.


     
    13. Herstellungsverfahren einer Halbleiterbaugruppe (100-500) nach Anspruch 1, wobei das Verfahren umfasst:

    ein Bereitstellen eines Trägers (180);

    ein Bilden eines Baugruppensubstrats (110, 410), das umfasst:

    ein Bilden einer ersten leitenden Schicht (111) aus ersten leitenden Elementen (1111) auf dem Träger (180);

    ein Bilden einer ersten Säulenschicht (112) aus ersten Säulen (1121) auf der ersten leitenden Schicht (111);

    ein Bilden eines ersten Baugruppenkörpers (113), der die erste leitende Schicht (111) und die erste Säulenschicht (112) einkapselt; und

    ein Bilden einer zweiten leitenden Schicht (114) aus zweiten leitenden Elementen (1141) auf der ersten Säulenschicht (112);

    ein Anordnen einer ersten elektronischen Komponente (120) über der zweiten leitenden Schicht (114) des Baugruppensubstrats (110, 410);

    ein Bilden einer zweiten Säulenschicht (260) aus zweiten Säulen auf der zweiten leitenden Schicht (114);

    ein Anordnen eines Zwischenelements (270) auf der zweiten Säulenschicht (260), wobei das Zwischenelement (270) elektrisch mit den zweiten Säulen (261) verbunden ist und eine obere Oberfläche von jeder zweiten Säule (261) der zweiten Säulenschicht (260) bedeckt;

    ein Bilden eines zweiten Baugruppenkörpers (130), der die erste elektronische Komponente (120) und die zweite leitende Schicht (114) einkapselt, wobei der zweite Baugruppenkörper (130) die seitliche Oberfläche von jeder zweiten Säule (261) der zweiten Säulenschicht (260) ferner vollständig einkapselt; und

    ein Entfernen des Trägers (180).


     
    14. Herstellungsverfahren einer Halbleitervorrichtung (10, 20) nach Anspruch 13, wobei das Verfahren ferner umfasst:

    ein Verbinden der zweiten Säulenschicht (260) mit dem Baugruppensubstrat (110, 410); und

    ein Anordnen einer dritten elektronischen Komponente (11) über dem zweiten Baugruppensubstrat (130), wobei die dritte elektronische Komponente (11) durch die zweite Säulenschicht (260) elektrisch mit dem Baugruppensubstrat (110, 410) verbunden ist.


     


    Revendications

    1. Boîtier de semi-conducteur (100-500), comprenant :
    un substrat de boîtier (110, 410), qui comprend :

    une couche (111) de premiers éléments conducteurs (1111), dans la ci-après dite première couche conductrice (111) ;

    une couche (112) de premiers piliers (1121) formée sur la première couche conductrice (111), dans la ci-après dite première couche de piliers (112) ;

    un premier corps de boîtier (113) encapsulant la première couche conductrice (111) et la première couche de piliers (112) ;

    une couche (114) de deuxièmes éléments conducteurs (1141) se connectant électriquement à la première couche de piliers (112), dans la ci-après dite deuxième couche conductrice (114) ;

    un premier composant électronique (120) disposé au-dessus de la deuxième couche conductrice (114) du substrat de boîtier (110, 410) ;

    un deuxième corps de boîtier (130) encapsulant le premier composant électronique (120) et la deuxième couche conductrice (114) ;

    une couche (260) de deuxièmes piliers (261) formée sur la deuxième couche conductrice (114), dans la ci-après dite deuxième couche de piliers (260), et

    un élément d'interposition (270) disposé dans le deuxième corps de boîtier (130), connecté électriquement aux deuxièmes piliers (261) et couvrant une surface de dessus du deuxième corps de boîtier (130) et une surface de dessus de chaque deuxième pilier (261) de la deuxième couche de piliers (260) ;

    dans lequel le deuxième corps de boîtier (130) encapsule en outre totalement une surface latérale de chaque deuxième pilier (261) sur la deuxième couche de piliers (260).


     
    2. Boîtier de semi-conducteur (100-500) selon la revendication 1, dans lequel le premier corps de boîtier (113) est un composé de moulage.
     
    3. Boîtier de semi-conducteur (100-500) selon la revendication 1 ou 2, dans lequel le substrat de boîtier (110, 410) comprend en outre :

    une couche (411) de troisièmes éléments conducteurs formée sur le premier corps de boîtier (113), dans la ci-après dite troisième couche conductrice (411) ;

    une couche (412) de troisièmes piliers connectant la troisième couche conductrice (411) à la deuxième couche conductrice (114), dans la ci-après dite troisième couche de piliers (412) ; et

    un troisième corps de boîtier (413) encapsulant la troisième couche de piliers (412) et la troisième couche conductrice (411) ;

    dans lequel la deuxième couche conductrice (114) est formée sur le troisième corps de boîtier (413).


     
    4. Boîtier de semi-conducteur (100-500) selon la revendication 3, dans lequel le troisième corps de boîtier (413) est un composé de moulage.
     
    5. Boîtier de semi-conducteur (100-500) selon l'une quelconque des revendications 1 à 4, dans lequel la première couche conductrice (111) a une première surface inférieure (1111b), le premier corps de boîtier (113) a une seconde surface inférieure (113b), la première surface inférieure (1111b) est exposée à partir de la deuxième surface inférieure (113b), et le boîtier de semi-conducteur (100-500) comprend en outre :
    un deuxième composant électronique (140) disposé sur la première surface inférieure (1111b) de la première couche conductrice (111).
     
    6. Boîtier de semi-conducteur (100-500) selon l'une quelconque des revendications 1 à 5, dans lequel
    l'élément d'interposition (270) est connecté électriquement au substrat de boîtier (110, 410) par le biais de la deuxième couche de piliers (260).
     
    7. Boîtier de semi-conducteur (100-500) selon l'une quelconque des revendications 1 à 6, dans lequel le boîtier de semi-conducteur (100-500) comprend en outre :

    une couche (370) de quatrièmes éléments conducteurs (371), dans la ci-après dite quatrième couche conductrice (370) ;

    dans lequel la deuxième couche de piliers (260) connecte la quatrième couche conductrice (370) à la deuxième couche conductrice (114) ;

    dans lequel le deuxième corps de boîtier (130) encapsule la deuxième couche de piliers (260) et la quatrième couche conductrice (370).


     
    8. Boîtier de semi-conducteur (100-500) selon l'une quelconque des revendications 1 à 7, dans lequel la première couche de piliers (112) a une première surface supérieure, le premier corps de boîtier (113) a une seconde surface supérieure (113u), et la première surface supérieure est alignée avec la seconde surface supérieure (113u).
     
    9. Boîtier de semi-conducteur (100-500) selon l'une quelconque des revendications 1 à 8, dans lequel la première couche conductrice (111) a une première surface inférieure (1111b), le premier corps de boîtier (113) a une seconde surface inférieure (113b), et la première surface inférieure (1111b) est alignée avec la seconde surface inférieure (113b).
     
    10. Dispositif à semi-conducteur (10, 20), comprenant :

    un boîtier de semi-conducteur (100-500) selon l'une quelconque des revendications 1 à 9 ; et

    un troisième composant électronique (11) disposé au-dessus du deuxième corps de boîtier (130) et se connectant électriquement au substrat de boîtier (110, 410) par le biais de la deuxième couche de piliers (260) ;

    dans lequel le deuxième corps de boîtier (130) encapsule en outre la deuxième couche de piliers (260).


     
    11. Dispositif à semi-conducteur (10, 20) selon la revendication 10, dans lequel le troisième composant électronique (11) est disposé sur l'élément d'interposition (270) et connecté électriquement à celui-ci.
     
    12. Dispositif à semi-conducteur (10, 20) selon la revendication 10 ou 11, dans lequel le dispositif à semi-conducteur (10, 20) comprend en outre :

    une couche conductrice (370) de quatrièmes éléments conducteurs (371), dans la ci-après dite quatrième couche conductrice (370) ; et

    dans lequel la deuxième couche de piliers (260) connecte la quatrième couche conductrice (370) à la deuxième couche conductrice (114), le deuxième corps de boîtier (130) encapsule la deuxième couche de piliers (260) et la quatrième couche conductrice (370), et le troisième composant électronique (11) est disposé sur la quatrième couche conductrice (370) et connecté électriquement à celle-ci.


     
    13. Procédé de fabrication d'un boîtier de semi-conducteur (100-500) selon la revendication 1, le procédé comprenant :

    la fourniture d'un élément porteur (180) ;

    la formation d'un substrat de boîtier (110, 410), comprenant :

    la formation d'une première couche conductrice (111) de premiers éléments conducteurs (1111) sur l'élément porteur (180) ;

    la formation d'une première couche de piliers (112) de premiers piliers (1121) sur la première couche conductrice (111) ;

    la formation d'un premier corps de boîtier (113) encapsulant la première couche conductrice (111) et la première couche de piliers (112) ; et

    la formation d'une deuxième couche conductrice (114) de deuxièmes éléments conducteurs (1141) sur la première couche de piliers (112) ;

    la disposition d'un premier composant électronique (120) au-dessus de la deuxième couche conductrice (114) du substrat de boîtier (110, 410) ;

    la formation d'une deuxième couche de piliers (260) de deuxièmes piliers sur la deuxième couche conductrice (114) ;

    la disposition d'un élément d'interposition (270) sur la deuxième couche de piliers (260), dans lequel l'élément d'interposition (270) est connecté électriquement aux deuxièmes piliers (261) et couvre une surface de dessus de chaque deuxième pilier (261) dans la deuxième couche de piliers (260) ;

    la formation d'un deuxième corps de boîtier (130) encapsulant le premier composant électronique (120) et la deuxième couche conductrice (114), dans lequel le deuxième corps de boîtier (130) encapsule en outre totalement une surface latérale de chaque deuxième pilier (261) de la deuxième couche de piliers (260) ; et

    le retrait de l'élément porteur (180).


     
    14. Procédé de fabrication d'un dispositif à semi-conducteur (10, 20) selon la revendication 13, le procédé comprenant en outre :

    la connexion de la deuxième couche de piliers (260) au substrat de boîtier (110, 410) ; et

    la disposition d'un troisième composant électronique (11) au-dessus du deuxième corps de boîtier (130), dans lequel le troisième composant électronique (11) se connecte électriquement au substrat de boîtier (110, 410) par le biais de la deuxième couche de piliers (260).


     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description