(19)
(11)EP 3 156 994 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
06.05.2020 Bulletin 2020/19

(21)Application number: 14866804.9

(22)Date of filing:  26.09.2014
(51)Int. Cl.: 
G09G 3/32  (2016.01)
(86)International application number:
PCT/CN2014/087600
(87)International publication number:
WO 2015/188520 (17.12.2015 Gazette  2015/50)

(54)

PIXEL DRIVER CIRCUIT, DRIVING METHOD, ARRAY SUBSTRATE, AND DISPLAY DEVICE

PIXELTREIBERSCHALTUNG, ANSTEUERUNGSVERFAHREN, ARRAYSUBSTRAT UND ANZEIGEVORRICHTUNG

CIRCUIT DE COMMANDE DE PIXEL, PROCÉDÉ DE COMMANDE, SUBSTRAT MATRICIEL ET DISPOSITIF D'AFFICHAGE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 13.06.2014 CN 201410265310

(43)Date of publication of application:
19.04.2017 Bulletin 2017/16

(73)Proprietor: BOE Technology Group Co., Ltd.
Beijing 100015 (CN)

(72)Inventors:
  • WANG, Ying
    Beijing 100176 (CN)
  • YIN, Xinshe
    Beijing 100176 (CN)
  • LI, Guang
    Beijing 100176 (CN)
  • SUN, Liang
    Beijing 100176 (CN)

(74)Representative: Brötz, Helmut et al
Rieder & Partner mbB Patentanwälte - Rechtsanwalt Corneliusstrasse 45
42329 Wuppertal
42329 Wuppertal (DE)


(56)References cited: : 
CN-A- 102 402 940
CN-A- 103 000 126
CN-U- 203 433 775
KR-A- 20120 043 300
US-A1- 2011 193 856
CN-A- 102 930 824
CN-A- 103 474 025
KR-A- 20100 045 578
US-A1- 2009 121 981
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    TECHNICAL FIELD OF THE DISCLOSURE



    [0001] The present disclosure relates to a field of display technique, and particularly to a pixel driving circuit, a driving method, an array substrate and a display apparatus.

    BACKGROUND



    [0002] As a current type light emitting device, an Organic Light emitting Diode (OLED) is increasingly applied to a high performance Active Matrix Organic Light Emitting Device Display (AMOLED). With an increasing in the display size of a conventional Passive Matrix OLED (PMOLED), the conventional PMOLED requires a shorter single pixel driving time for displaying, and thus a transient current is needed to be increased, which renders an increasing in power consumption. Meanwhile, an application of the large current causes a voltage drop of the Indium Tin Oxide (ITO) line to decrease too much, rendering the operation voltage of OLED too high and in turn an efficiency of OLED is lower. An Active Matrix OLED (AMOLED) inputs an OLED current via switching transistors by progressive scanning for display, which can solve the above problems very well.

    [0003] In designing of a pixel circuit of the AMOLED, a problem mainly to be solved is non-uniformity in luminance of OLED devices driven by pixel driving units in AMOLED.

    [0004] Firstly, in AMOLED, a pixel driving unit is constituted by thin film transistors (TFTs) to supply a corresponding driving circuit to a light emitting device. As the inventor noticed, low temperature poly-Si Thin Film Transistors (LTPS TFTs) or Oxide TFTs are mostly adopted. As compared to the conventional amorphous-si TFT, LTPS TFT and Oxide TFT have a higher mobility and more stable characteristics, and thus are more suitable to be used in an AMOLED display. However, due to limitations of a crystallization process, LTPS TFTs, which are manufactured on a glass substrate with a large area, have non-uniformity in electrical parameters such as a threshold voltage, the mobility, etc, and such non-uniformity may result in variances in driving currents and luminances among OLEDs which can be perceived by human eyes, i.e., Mura phenomenon. Although a process for the Oxide TFTs shows a better uniformity, similar to a-Si TFTs, the threshold voltage of the Oxide TFT may drift under a high temperature or under a case that the Oxide TFT is supplied a voltage for a long time. Due to different display pictures, drifts of threshold voltages of TFTs in respective areas on a panel may be different from each other, which may cause variances in display luminance. Such variances in display luminance often render an image sticking phenomenon since such display luminance difference has a relation to a previously displayed image.

    [0005] Since the OLED light emitting device is a device driven by a current (current-driven device), the threshold characteristic of the driving transistor in a pixel driving unit for driving the light emitting device to emit light has a great effect on the driving current and the ultimate display luminance. The threshold voltage of the driving transistor will drift under a voltage stress or light illumination, which causes the non-uniformity in the luminance of the resulted display.

    [0006] In addition, in order to remove the effect caused by the variances in threshold voltages of the driving transistors, the existing pixel circuits are commonly designed to have a complex structure, which may render a low good manufacturing production rate of pixel circuits of AMOLED.
    KR 20100045578A discloses an organic electroluminescent display device provided to minimize the electrical characteristic deviation of a driving thin film transistor by removing a threshold voltage of a thin film transistor. CONSTITUTION: An organic electroluminescent display device (OLED) receives a driving voltage or a GND. The first switching thin film transistor receives data voltage. A first switching thin film transistor outputs the data voltage. The first switching thin film transistor (S1) is switch-controlled by a scan signal. A capacitor is connected to the output terminal of the first switching thin film transistor. A driving thin-film transistor (DR) supplies a driving current to the organic electro luminescence device. A second switching thin film transistor (S2) is switch-controlled by the current supply signal.; The second switching thin film transistor controls the driving current traffic to flow through the driving thin-film transistor. A third switching thin film transistor (S3) outputs a reference voltage to the output terminal of the first switching thin film transistor.
    KR 2012 0043300A discloses an organic light emitting diode display apparatus and a driving method thereof provided to accurately detect threshold voltage of a drive switching device by securing time for accurately sensing the threshold voltage. CONSTITUTION: A first switching device(T1) supplies data voltage to a first node. A second switching device(T2) supplies first power source voltage to the first node. A third switching device(T3) supplies reference voltage to a second node. A drive switching device(DT) controls a current amount supplied to an organic light emitting diode. A fourth switching device(T4) supplies the reference voltage to the first node. A fifth switching device(T5) connects a second node and a drain electrode of the drive switching device. A sixth switching device(T6) connects an anode electrode of the organic light emitting diode and the drain electrode of the drive switching device.

    [0007] Therefore, in order to solve the above problem, there is a need for providing a pixel driving unit, a driving method and a pixel circuit in embodiments of the present disclosure.

    SUMMARY


    Technical problem to be solved



    [0008] A technical problem to be solved by the embodiments of the present disclosure is how to implement an AMOLED pixel driving circuit possessing capability of compensating and removing display non-uniformity caused by variances in threshold voltage among driving transistors.

    Technical solution



    [0009] To solve the above technical problem, Embodiments of the present disclosure provide a pixel driving circuit comprising a data line for supplying a data voltage, a gate line for supplying a scan voltage, a first power supply line for supplying a first power supply voltage, a second power supply line for supplying a second power supply voltage, a reference signal line for supplying a reference voltage, a light emitting device, a driving transistor, a storage capacitor, a reset unit, a data writing unit, a compensating unit and a light emitting control unit.

    [0010] The reset unit is connected to the reference signal line and the storage capacitor, and is configured to reset a voltage across the storage capacitor to a predefined signal voltage.

    [0011] The data writing unit is connected to the gate line, the data line and a second terminal of the storage capacitor, and is configured to write information including a data voltage into the second terminal of the storage capacitor.

    [0012] The compensating unit is connected the gate line, a first terminal of the storage capacitor and the driving transistor, and is configured to write information including a threshold voltage of the driving transistor and an information of the first power supply voltage into the first terminal of the storage capacitor.

    [0013] The light emitting control unit is connected to the reference signal line, the second terminal of the storage capacitor, the driving transistor and the light emitting device, and is configured to write the reference voltage into the second terminal of the storage capacitor and control the driving transistor to drive the light emitting device to emit light.

    [0014] The first terminal of the storage capacitor is connected to a gate of the driving transistor, and the storage capacitor is configured to transfer the information including the data voltage into the gate of the driving transistor.

    [0015] The driving transistor is connected to the first power supply line, the light emitting device is connected to the second power supply line, and the driving transistor is configured to control an amplitude of a current flowing through the light emitting device according to the information including the data voltage, the threshold voltage of the driving transistor, the reference voltage and the first power supply voltage under the control of the light emitting control unit.

    [0016] The reset unit comprises a reset control line, a reset signal line, a first transistor and a second transistor, the first transistor has a gate connected to the reset control line, a source connected the reset signal line and a drain connected to the first terminal of the storage capacitor, and is configured to write a voltage on the reset signal line into the first terminal of the storage capacitor; the second transistor has a gate connected to the reset control line, a source connected the reference signal line and a drain connected to the second terminal of the storage capacitor, and is configured to write the reference voltage into the second terminal of the storage capacitor. The reference signal line is separate from the first power supply line. The light emitting control unit comprises a light emitting control line, a fifth transistor and a sixth transistor, wherein the fifth transistor has a gate connected to the light emitting control line, a source connected to the reference signal line and the source of the second transistor, and a drain connected to the second terminal of the storage capacitor, and is configured to write the reference voltage supplied by the reference signal line into the second terminal of the storage capacitor such that the storage capacitor transfers the reference voltage to the gate of the driving transistor, and the sixth transistor has a gate connected to the light emitting control line), a source connected to a first terminal of the light emitting device and a drain connected to the drain of the driving transistor, and is configured to control the light emitting device to emit light, the driving transistor is configured to control the amplitude of the current flowing through the light emitting device according to the information including the data voltage, the threshold voltage of the driving transistor, the first power supply voltage and the reference voltage under the control of the light emitting control unit, and wherein the reference voltage is a high level voltage such that the light emitting control unit writes the high level voltage into the second terminal of the storage capacitor during a light emitting period.

    [0017] In an example, the first and second transistors are P type transistors.

    [0018] In an example, the data writing unit comprises a fourth transistor, the fourth transistor has a gate connected to the gate line, a source connected the data line and a drain connected to the second terminal of the storage capacitor, and is configured to write the data voltage into the second terminal of the storage capacitor.

    [0019] In an example, the fourth transistor is a P type transistor.

    [0020] In an example, the compensating unit comprises a third transistor, the third transistor has a gate connected to the gate line, a source connected to the first terminal of the storage capacitor and a drain connected to the drain of the driving transistor, and is configured to write the information including the threshold voltage of the driving transistor and the first power supply voltage into the first terminal of the storage capacitor.

    [0021] In an example, the third transistor is a P type transistor.

    [0022] In an example, the fifth and sixth transistors are P type transistors.

    [0023] In an example, the driving transistor is a P type transistor.

    [0024] In the embodiments of the present disclosure, there is further provided a driving method for any one of the above described pixel driving circuit. The driving method comprises following steps:

    [0025] during a resetting period, resetting the voltage across the storage capacitor to a predefined voltage by the reset unit;

    [0026] during a data voltage writing period, writing the data voltage into the second terminal of the storage capacitor by the data writing unit, and writing the information including the threshold voltage of the driving transistor and the first power supply voltage into the first terminal of the storage capacitor by the compensating unit;

    [0027] during a light emitting period, writing the reference voltage into the second terminal of the storage capacitor by the light emitting control unit, transferring the information including the data voltage and the reference voltage to the gate of the driving transistor by the storage capacitor, and controlling the amplitude of the current flowing through the light emitting device according to the information including the data voltage, the threshold voltage of the driving transistor, the reference voltage and the first power supply voltage to drive the light emitting device to emit light by the driving transistor under the control of the light emitting control unit.

    [0028] During the resetting period, the reset unit resets voltages at the two terminals of the storage capacitor to the voltage on the rest signal line and the reference voltage, respectively.

    [0029] In the embodiments of the present disclosure, there is further provided an array substrate comprising any one of the above described pixel driving circuit.

    [0030] In the embodiments of the present disclosure, there is further provided a display apparatus comprising the above described array substrate.

    Advantageous Effect



    [0031] In the pixel driving unit according to the embodiments of the present disclosure, the first power supply voltage and the threshold voltage of the driving transistor are loaded together to the first terminal of the storage capacitor through the drain of the driving transistor by aid of a structure in which the gate and the drain of the driving transistor of the driving transistor are connected to each other (the gate and drain of the driving transistor are connected with each other through the third switch transistor when a gate control signal is ON), such that the threshold voltage of the driving transistor is compensated; the non-uniformity in display luminance caused by variances in threshold voltages of the driving transistors and the image sticking phenomenon caused by the threshold voltage drifts can be effectively removed during the process for driving the light emitting device. The problem of non-uniformity in display luminance among the light emitting devices in different pixel driving units of the AMOLED caused by variances in the threshold voltages of the driving transistors corresponding to the light emitting devices can be avoided in the AMOLED. Therefore, a driving effect of the pixel driving unit on the light emitting device is improved, and a quality of the AMOLED is further improved.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0032] 

    Fig.1 is a diagram of a pixel driving circuit according to embodiments of the present disclosure;

    Fig.2 is a structural diagram of a pixel according to the embodiments of the present disclosure; and

    Fig.3 is a timing diagram of the pixel driving circuit shown in Fig.1.


    DETAILED DESCRIPTION



    [0033] Descriptions will be given to particular implementations of the present disclosure below, taken in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the following embodiments are only illustrative for the embodiments of the present disclosure, but not intended to limit the scope of the present disclosure.

    [0034] It should be explained that a gate of a transistor as defined in the embodiments of the present disclosure is a terminal for controlling the transistor to be turned on, and a source and a drain are two terminals other than the gate of the transistor. The source and the drain are only descriptive for connection relationship of the transistor, but not limitative on current direction. Those skilled in the art can clearly know its operational principle and stage according to the type of the transistor, the signal connection manner, and etc.

    [0035] As shown in Fig.1, a pixel driving circuit of the embodiments of the present disclosure comprises a data line Data, a gate line Gate, a first power supply line ELVDD, a second power supply line ELVSS, a reference signal line ref, a light emitting device D, a driving transistor T7, a storage capacitor C1, a reset unit, a data writing unit, a compensating unit and a light emitting control unit. The data line Data is configured to supply a data voltage, the gate line Gate is configured to supply a scan voltage, the first power supply line ELVDD is configured to supply a first power supply voltage, the second power supply line ELVSS is configured to supply a second power supply voltage, and the reference signal line ref is configured to supply a reference voltage.

    [0036] The light emitting device D may be an organic light emitting diode. The driving transistor T7 has a gate connected to a first terminal N1 of the storage capacitor C1, a source connected to the first power supply line ELVDD and a drain connected to the light emitting control unit.

    [0037] The reset unit is connected to the reference signal line ref and the storage capacitor C1, and is configured to reset a voltage across the storage capacitor C1 to a predefined voltage.

    [0038] The data writing unit is connected to the gate line Gate, the data line Data and a second terminal N2 of the storage capacitor C1, and is configured to write information including a data voltage into the second terminal N2 of the storage capacitor C1.

    [0039] The compensating unit is connected the gate line Gate, the first terminal N1 of the storage capacitor C1 and the driving transistor T7, and is configured to write information including a threshold voltage of the driving transistor and the first power supply voltage into the first terminal N1 of the storage capacitor C1.

    [0040] The light emitting control unit is connected to the reference signal line ref, the second terminal N2 of the storage capacitor C1, the driving transistor T7 and the light emitting device D, and is configured to write the reference voltage into the second terminal N2 of the storage capacitor C1 and control the driving transistor T7 to drive the light emitting device D to emit light.

    [0041] The first terminal N1 of the storage capacitor C1 is connected to the gate of the driving transistor T7, and the storage capacitor C1 is configured to transfer the information including the data voltage into the gate of the driving transistor T7.

    [0042] The driving transistor T7 is connected to the first power supply line ELVDD, the light emitting device D is connected to the second power supply line ELVSS, and the driving transistor T7 is configured to control an amplitude of a current flowing through the light emitting device D according to the information including the data voltage, the threshold voltage of the driving transistor T7, the reference voltage and the first power supply voltage under the control of the light emitting control unit.

    [0043] In the driving circuit according to the present embodiment, the threshold voltage of the driving transistor T7 can be compensated during the process for driving the light emitting device by extracting the threshold voltage of the driving transistor through the compensating unit, such that the non-uniformity in display luminance caused by variances in threshold voltages of the driving transistors and the image sticking phenomenon caused by the threshold voltage drifts can be effectively removed , and the problem of non-uniformity in display luminance among the light emitting devices in different pixel driving units of the AMOLED caused by variances in the threshold voltages of the driving transistors corresponding to the light emitting devices can be avoided.

    [0044] In addition, the light emitting control unit writes the reference voltage into the second terminal N2 of the storage capacitor C1. As shown in Fig.2, the reference voltage is transmitted through the reference signal line ref which is separate from the first power supply line ELVDD. During the process for driving, a current flowing through the reference signal line ref is small, and a voltage drop in the reference signal line is also small. The storage capacitor is connected to the gate of the driving transistor. Since the reference voltage is more stable relative to the first power supply voltage, the voltage at the gate of the driving transistor is more stable, and thus the problem of uniformity in luminance among different pixels caused by the effect of the drop of the first power supply voltage on the current can be avoided.

    [0045] In addition, such pixel structure can reduce the effect on the display uniformity caused by the variance in the DC voltage on the reference signal line ref to the greatest extent, and can achieve a purpose that adjacent pixels share the reference signal line ref, reduce the area occupied by the pixel driving circuit to the greatest extent so as to increase an aperture ratio.

    [0046] It should be explained that Fig.2 is only illustrative for the pixel structure but not limitative for the pixel structure, and other arrangement can be adopted in actual design.

    [0047] In the present embodiment, the reset unit comprises a reset control line Reset, a reset signal line ini, a first transistor T1 and a second transistor T2. The first transistor T1 has a gate connected to the reset control line Reset, a source connected the reset signal line ini and a drain connected to the first terminal of the storage capacitor C1, and is configured to write a voltage Vini on the reset signal line ini into the first terminal of the storage capacitor C1. The second transistor T2 has a gate connected to the reset control line Reset, a source connected the reference signal line ref and a drain connected to the second terminal of the storage capacitor C1, and is configured to write the reference voltage Vref into the second terminal of the storage capacitor C1. That is, voltages at the two terminals of C1 are reset to Vini and Vref respectively.

    [0048] The data writing unit comprises a fourth transistor T4. The fourth transistor T4 has a gate connected to the gate line Gate, a source connected the data line Gate and a drain connected to the second terminal of the storage capacitor C1, and is configured to write the data voltage Vdata into the second terminal of the storage capacitor. That is, the voltage at the point N2 is set to Vdata.

    [0049] The compensating unit comprises a third transistor T3. The third transistor T3 has a gate connected to the gate line Gate, a source connected to the first terminal of the storage capacitor C1 and a drain connected to the drain of the driving transistor T7, and is configured to write the information including the threshold voltage Vth of the driving transistor T7 and the first power supply voltage into the first terminal of the storage capacitor C1. That is, the voltage at the point N1 is Vdd-Vth, where Vdd is the first power supply voltage on the first power supply line ELVDD, and Vth is the threshold voltage of the driving transistor T7.

    [0050] The light emitting control unit comprises a light emitting control line EM, a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 has a gate connected to the light emitting control line EM, a source connected to the reference signal line ref and a drain connected to the second terminal of the storage capacitor C1, and is configured to write the reference voltage Vref into the second terminal of the storage capacitor C1 such that the storage capacitor C1 transfers the reference voltage Vref to the gate of the driving transistor T7. The sixth transistor T6 has a gate connected to the light emitting control line EM, a source connected to a first terminal of the light emitting device D and a drain connected to the drain of the driving transistor T7, and is configured to control the light emitting device D to emit light, that is, the driving transistor T7 can drive a current to flow through the light emitting device D only when T6 is turned on. The driving transistor T7 is configured to control the amplitude of the current flowing through the light emitting device D according to the information including the data voltage Vdata, the threshold voltage Vth of the driving transistor, the first power supply voltage Vdd and the reference voltage Vref under the control of the light emitting control unit.

    [0051] As shown in Fig.3, there are three periods when the circuit structure according to the present embodiment.

    [0052] During a first period t1, a signal on the reset control line Reset is valid, T1 and T2 are turned on to reset the two terminals of the storage capacitor C1. At this time, the voltage Vini on the reset signal line ini is written to the point N1, and the point N2 is at the reference voltage Vref.

    [0053] During a second period t2, a signal on the gate line is valid, T3 and T4 are turned on, Vdata is written into the point N2, Vdd-Vth is written into the point N1, and the voltage stored by the storage capacitor C1 is Vdd-Vth-Vdata at this time. During this period, T3 writes the information including the first power supply voltage and the threshold voltage of the driving transistor into the first terminal of the storage capacitor C1.

    [0054] During a third period t3, a signal on the light emitting control line EM is valid, T5 and T6 are turned on, T5 is connected to the reference signal line ref, the voltage at the point N2 is Vref, the voltage at the point N1 is Vdd-Vth-Vdata+Vref which is the voltage at the gate of the driving transistor, the voltage at the source of the driving transistor is Vdd, a gate-source voltage Vgs of the driving transistor is Vdd-Vth-Vdata+Vref-Vdd, the current flowing through the light emitting device is I = ½µCox(W/L) (Vgs-Vth)2 = ½µCox(W/L) (Vref-Vdata)2, where µ is a carrier mobility, Cox is capacitance of a gate oxide layer, W/L is a width-length ratio of the driving transistor.

    [0055] It can be seen from the above equation of the current flowing through the light emitting device that the current I is irrelevant to the threshold voltage Vth of the driving transistor, and thus the problem of non-uniformity in display luminance among the different pixels of the AMOLED caused by variances in the threshold voltages of the driving transistors in the pixels can be avoided. Furthermore, the current I is irrelevant to Vdd, Vref is only used to charge the storage capacitor, the current flowing through the corresponding lines is small and the corresponding voltage drop is also small. The storage capacitor is connected to the gate of the driving transistor. Since Vref is more stable relative to Vdd, the voltage at the gate of the driving transistor is more stable, and thus the problem of uniformity in luminance among different pixels caused by the effect of the drop of Vdd on the current can be avoided.

    [0056] In the driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor in the above embodiment are all P type transistors. Of course, they may also be N type transistor, or a combination of P type transistors and N type transistors with different valid signals on gate control signal lines.

    [0057] In the embodiments of the present disclosure, there is further provided a driving method for any one of the above described pixel driving circuit. The driving method comprises following process.

    [0058] During a resetting period, the reset unit resets the voltage across the storage capacitor to a predefined voltage.

    [0059] During a data voltage writing period, the data writing unit writes the data voltage into the second terminal of the storage capacitor, and the compensating unit writes the information including the threshold voltage of the driving transistor and the first power supply voltage into the first terminal of the storage capacitor.

    [0060] During a light emitting period, the light emitting control unit writes the reference voltage into the second terminal of the storage capacitor, the storage capacitor transfers the information including the data voltage and the reference voltage to the gate of the driving transistor, and the driving transistor controls the amplitude of the current flowing through the light emitting device according to the information including the data voltage, the threshold voltage of the driving transistor, the reference voltage and the first power supply voltage to drive the light emitting device to emit light under the control of the light emitting control unit.

    [0061] During the resetting period, the reset unit resets the voltages at the two terminals of the storage capacitor to the voltage on the rest signal line and the reference voltage, respectively.

    [0062] For particular driving steps, we can refer to the descriptions for the three operational periods in the above embodiment, and repeated descriptions are omitted herein.

    [0063] In the embodiments of the present disclosure, there is further provided an array substrate comprising the pixel driving circuit according to the above embodiment.

    [0064] In the embodiments of the present disclosure, there is further provided a display apparatus comprising the above described array substrate. The display apparatus may be any product or component having display function comprising AMOLED panel, television, digital frame, cell phone, tablet computer and so on.

    [0065] The above descriptions are only for illustrating the embodiments of the present disclosure, and in no way limit the scope of the present disclosure.


    Claims

    1. A pixel driving circuit, comprising: a data line (Data) for supplying a data voltage, a gate line (Gate) for supplying a scan voltage, a first power supply line (ELVDD) for supplying a first power supply voltage, a second power supply line (ELVSS) for supplying a second power supply voltage, a reference signal line (ref) for supplying a reference voltage, a light emitting device (D), a driving transistor (T7), a storage capacitor (C1), a reset unit, a data writing unit, a compensating unit and a light emitting control unit;
    the reset unit is connected to the reference signal line (ref) and the storage capacitor (C1), and is configured to reset a voltage across the storage capacitor (C1) to a predefined signal voltage,
    the data writing unit is connected to the gate line (Gate), the data line (Data) and a second terminal (N2) of the storage capacitor (C1), and is configured to write information including a data voltage into the second terminal (N2) of the storage capacitor (C1),
    the compensating unit is connected to the gate line (Gate), a first terminal (N1) of the storage capacitor (C1) and the drain of the driving transistor (T7), and is configured to write information including a threshold voltage of the driving transistor (T7) and an information of the first power supply voltage into the first terminal (N1) of the storage capacitor (C1),
    the light emitting control unit is connected to the reference signal line (ref), the second terminal (N2) of the storage capacitor (C1), the driving transistor (T7) and the light emitting device (D), and is configured to write the reference voltage into the second terminal (N2) of the storage capacitor (C1) and control the driving transistor (T7) to drive the light emitting device (D) to emit light,
    the first terminal (N1) of the storage capacitor (C1) is connected to a gate of the driving transistor (T7), and the storage capacitor (C1) is configured to transfer the information including the data voltage into the gate of the driving transistor (T7), and
    the driving transistor (T7) is connected to the first power supply line (ELVDD), a first terminal of the light emitting device (D) is connected to the second power supply line (ELVSS), and the driving transistor (T7) is configured to control an amplitude of a current flowing through the light emitting device (D) according to the information including the data voltage, the threshold voltage of the driving transistor (T7), the reference voltage and the first power supply voltage under the control of the light emitting control unit,
    wherein, the reset unit comprises a reset control line (Reset), a reset signal line (ini), a first transistor (T1) and a second transistor (T2), the first transistor (T1) has a gate connected to the reset control line (Reset) and a source connected to the reset signal line (ini); the second transistor (T2) has a gate connected to the reset control line (Reset) and a source connected the reference signal line (ref),
    wherein, the first transistor (T1) has a drain connected to the first terminal (N1) of the storage capacitor (C1), and is configured to write a voltage on the reset signal line (ini) into the first terminal (N1) of the storage capacitor (C1),
    the second transistor (T2) has a drain connected to the second terminal (N2) of the storage capacitor (C1), and is configured to write the reference voltage into the second terminal (N2) of the storage capacitor (C1),
    the reference signal line (ref) is separate from the first power supply line (ELVDD),
    the light emitting control unit comprises a light emitting control line (EM), a fifth transistor (T5) and a sixth transistor (T6), wherein the fifth transistor (T5) has a gate connected to the light emitting control line (EM), a source connected to the reference signal line (ref) and the source of the second transistor (T2), and a drain connected to the second terminal (N2) of the storage capacitor (C1), and is configured to write the reference voltage supplied by the reference signal line (ref) into the second terminal (N2) of the storage capacitor (C1) such that the storage capacitor (C1) transfers the reference voltage to the gate of the driving transistor (T7), and the sixth transistor (T6) has a gate connected to the light emitting control line (EM), a source connected to the drain of the driving transistor (T7) and a drain connected to the second terminal of the light emitting device (D) and is configured to control the light emitting device (D) to emit light, the driving transistor (T7) is configured to control the amplitude of the current flowing through the light emitting device (D) according to the information including the data voltage, the threshold voltage of the driving transistor (T7), the first power supply voltage and the reference voltage under the control of the light emitting control unit, and wherein the reference voltage is a high level voltage and the voltage on the reset signal line is a low level (Vint) such that the light emitting control unit writes the high level voltage into the second terminal (N2) of the storage capacitor (C1) during a light emitting period.
     
    2. The pixel driving circuit of claim 1, characterized in that the first and second transistors (T1, T2) are P type transistors.
     
    3. The pixel driving circuit of claim 1, characterized in that the data writing unit comprises a fourth transistor (T4),
    the fourth transistor (T4) has a gate connected to the gate line (Gate), a source connected the data line (Data) and a drain connected to the second terminal (N2) of the storage capacitor (C1), and is configured to write the data voltage into the second terminal (N2) of the storage capacitor (C1).
     
    4. The pixel driving circuit of claim 3, characterized in that the fourth transistor (T4) is a P type transistor.
     
    5. The pixel driving circuit of claim 1, characterized in that the compensating unit comprises a third transistor (T3),
    the third transistor (T3) has a gate connected to the gate line (Gate), a source connected to the first terminal (N1) of the storage capacitor (C1) and a drain connected to the drain of the driving transistor (T7), and is configured to write the information including the threshold voltage of the driving transistor (T7) and the first power supply voltage into the first terminal (N1) of the storage capacitor (C1).
     
    6. The pixel driving circuit of claim 5, characterized in that the third transistor (T3) is a P type transistor.
     
    7. The pixel driving circuit of claim 1, wherein the driving transistor (T7), the fifth and sixth transistors (T5, T6) are P type transistors.
     
    8. A driving method for the pixel driving circuit of any one of claims 1-7, characterized in that comprising following steps:

    during a resetting period, resetting the voltage across the storage capacitor (C1) to a predefined voltage by the reset unit;

    during a data voltage writing period, writing the data voltage into the second terminal (N2) of the storage capacitor (C1) by the data writing unit, and writing the information including the threshold voltage of the driving transistor (T7) and the first power supply voltage into the first terminal (N1) of the storage capacitor (C1) by the compensating unit; and

    during a light emitting period, writing the reference voltage into the second terminal (N2) of the storage capacitor (C1) by the light emitting control unit, transferring the information including the data voltage and the reference voltage to the gate of the driving transistor (T7) by the storage capacitor (C1), and controlling the amplitude of the current flowing through the light emitting device (D) according to the information including the data voltage, the threshold voltage of the driving transistor (T7), the reference voltage and the first power supply voltage to drive the light emitting device (D) to emit light by the driving transistor (T7) under the control of the light emitting control unit.


     
    9. The driving method of claim 8, characterized in that
    during the resetting period, the reset unit resets voltages at the two terminals of the storage capacitor (C1) to the voltage on the reset signal line (ini) and the reference voltage, respectively.
     
    10. An array substrate, characterized in that comprising the pixel driving circuit of any one of claims 1-7.
     
    11. A display apparatus, characterized in that comprising the array substrate of claim 10.
     


    Ansprüche

    1. Pixelansteuerungsschaltung, umfassend: eine Datenleitung (Data) zum Zuführen einer Datenspannung, eine Gate-Leitung (Gate) zum Zuführen einer Abtastspannung, eine erste Energiezufuhrleitung (ELVDD) zum Zuführen einer ersten Energiezufuhrspannung, eine zweite Energiezufuhrleitung (ELVSS) zum Zuführen einer zweiten Energiezufuhrspannung, eine Referenzsignalleitung (ref) zum Zuführen einer Referenzspannung, eine Licht emittierende Vorrichtung (D), einen Ansteuerungstransistor (T7), einen Speicherkondensator (C1), eine Rücksetzeinheit, eine Datenschreibeinheit, eine Kompensationseinheit und eine Lichtemittierungs-Steuereinheit;

    wobei die Rücksetzeinheit an die Referenzsignalleitung (ref) und den Speicherkondensator (C1) angeschlossen ist und konfiguriert ist, um eine Spannung über den Speicherkondensator (C1) auf eine vordefinierte Signalspannung zurückzusetzen,

    wobei die Datenschreibeinheit an die Gate-Leitung (Gate), die Datenleitung (Data) und einen zweiten Anschluss (N2) des Speicherkondensators (C1) angeschlossen ist und konfiguriert ist, um Information, beinhaltend eine Datenspannung in dem zweiten Anschluss (N2) des Speicherkondensators (C1), zu schreiben,

    wobei die Kompensationseinheit an die Gate-Leitung (Gate), einen ersten Anschluss (N1) des Speicherkondensators (C1) und den Drain des Ansteuerungstransistors (T7) angeschlossen ist und konfiguriert ist, um Information, beinhaltend eine Schwellenspannung des Ansteuerungstransistors (T7), und eine Information der ersten Energiezufuhrspannung in dem ersten Anschluss (N1) des Speicherkondensators (C1), zu schreiben,

    wobei die Lichtemittierungs-Steuereinheit an die Referenzsignalleitung (ref), den zweiten Anschluss (N2) des Speicherkondensators (C1), den Ansteuerungskondensator (T7) und die Licht emittierende Vorrichtung (D) angeschlossen ist und konfiguriert ist, um die Referenzspannung in dem zweiten Anschluss (N2) des Speicherkondensators (C1) zu schreiben und um den Ansteuerungstransistor (T7) zu steuern, um die Licht emittierende Vorrichtung (D) anzusteuern, um Licht zu emittieren,

    wobei der erste Anschluss (N1) des Speicherkondensators (C1) an ein Gate des Ansteuerungstransistors (T7) angeschlossen ist, und wobei der Speicherkondensator (C1) konfiguriert ist, um die Information, die die Datenspannung in dem Gate des Ansteuerungstransistors (T7) beinhaltet, zu übertragen, und

    wobei der Ansteuerungstransistor (T7) an die erste Energiezufuhrleitung (ELVDD) angeschlossen ist, wobei ein erster Anschluss der Licht emittierenden Vorrichtung (D) an die zweite Energiezufuhrleitung (ELVSS) angeschlossen ist, und wobei der Ansteuerungstransistor (T7) konfiguriert ist, um eine Amplitude eines durch die Licht emittierende Vorrichtung (D) fließenden Stromes gemäß der Information, welche die Datenspannung, die Schwellenspannung des Ansteuerungstransistors (T7), die Referenzspannung und die erste Energiezufuhrspannung beinhaltet, unter der Steuerung der Lichtemittierungs-Steuereinheit zu steuern,

    wobei die Rücksetzeinheit eine Rücksetzsteuerleitung (Reset), eine Rücksetzsignalleitung (ini), einen ersten Transistor (T1) und einen zweiten Transistor (T2) umfasst, wobei der erste Transistor (T1) ein Gate aufweist, das an die Rücksetzsteuerleitung (Reset) angeschlossen ist, und eine Source, die an die Rücksetzsignalleitung (ini) angeschlossen ist; wobei der zweite Transistor (T2) ein Gate aufweist, das an die Rücksetzsteuerleitung (Reset) angeschlossen ist und eine Source, die an die Referenzsignalleitung (ref) angeschlossen ist,

    wobei der erste Transistor (T1) einen Drain aufweist, der an den ersten Anschluss (N1) des Speicherkondensators (C1) angeschlossen ist, und konfiguriert ist, um eine Spannung auf der Rücksetzsignalleitung (ini) in den ersten Anschluss (N1) des Speicherkondensators (C1) zu schreiben,

    wobei der zweite Transistor (T2) einen Drain aufweist, der an den zweiten Anschluss (N2) des Speicherkondensators (C1) angeschlossen ist und konfiguriert ist, um die Referenzspannung in den zweiten Anschluss (N2) des Speicherkondensators (C1) zu schreiben,

    wobei die Referenzsignalleitung (ref) getrennt ist von der ersten Energiezufuhrleitung (ELVDD),

    wobei die Lichtemittierungs-Steuereinheit eine Lichtemittierungs-Steuerleitung (EM), einen fünften Transistor (T5) und einen sechsten Transistor (T6) umfasst, wobei der fünfte Transistor (T5) ein Gate aufweist, das an die Lichtemittierungs-Steuerleitung (EM) angeschlossen ist, eine Source, die an die Referenzsignalleitung (ref) und die Source des zweiten Transistors (T2) angeschlossen ist, und einen Drain, der an den zweiten Anschluss (N2) des Speicherkondensators (C1) angeschlossen ist, und konfiguriert ist, um die Referenzspannung, die mittels der Referenzsignalleitung (ref) zugeführt wird, in den zweiten Anschluss (N2) des Speicherkondensators (C1) zu schreiben, so dass der Speicherkondensator (C1) die Referenzspannung an das Gate des Ansteuerungstransistors (T7) überträgt, und wobei der sechste Transistor (T6) ein Gate aufweist, das an die Lichtemittierungs-Steuerleitung (EM) angeschlossen ist, eine Source, die an den Drain des Ansteuerungstransistors (T7) angeschlossen ist, und einen Drain, der an den zweiten Anschluss der Licht emittierenden Vorrichtung (D) angeschlossen ist, und konfiguriert ist, um die Licht emittierende Vorrichtung (D) anzusteuern, um Licht zu emittieren, wobei der Ansteuerungstransistor (T7) konfiguriert ist, um die Amplitude des durch die Licht emittierende Vorrichtung (D) fließenden Stromes zu steuern gemäß der Information, die die Datenspannung, die Schwellenspannung des Ansteuerungstransistors (T7), die erste Energiezufuhrspannung und die Referenzspannung beinhaltet, unter der Steuerung der Lichtemittierungs-Steuereinheit, und wobei die Referenzspannung eine Hochpegelspannung ist, und wobei die Spannung auf der Rücksetzsignalleitung ein Niedrigpegel (Vint) ist, so dass die Lichtemittierungs-Steuereinheit die Hochpegelspannung in den zweiten Anschluss des Speicherkondensators (C1) während einer Lichtemittierungsperiode schreibt.


     
    2. Pixelansteuerungsschaltung gemäß Anspruch 1, dadurch gekennzeichnet, dass die ersten und zweiten Transistoren (T1, T2) P-Typ-Transistoren sind.
     
    3. Pixelansteuerungsschaltung gemäß Anspruch 1, dadurch gekennzeichnet, dass die Datenschreibeinheit einen vierten Transistor (T4) umfasst,
    wobei der vierte Transistor (T4) ein Gate aufweist, das an die Gate-Leitung (Gate) angeschlossen ist, eine Source, die an die Datenleitung (Data) angeschlossen ist, und einen Drain, der an den zweiten Anschluss (N2) des Speicherkondensators (C1) angeschlossen ist, und konfiguriert ist, um die Datenspannung in den zweiten Anschluss (N2) des Speicherkondensators (C1) zu schreiben.
     
    4. Pixelansteuerungsschaltung gemäß Anspruch 3, dadurch gekennzeichnet, dass der vierte Transistor (T4) ein P-Typ-Transistor ist.
     
    5. Pixelansteuerungsschaltung gemäß Anspruch 1, dadurch gekennzeichnet, dass die Kompensationseinheit einen dritten Transistor (T3) umfasst,
    wobei der dritte Transistor (T3) ein Gate aufweist, dass an die Gate-Leitung (Gate) angeschlossen ist, eine Source, die an den ersten Anschluss (N1) des Speicherkondensators (C1) angeschlossen ist und einen Drain, der an den Drain des Ansteuerungstransistors (T7) angeschlossen ist, und konfiguriert ist, um die Information, die die Schwellenspannung des Ansteuerungstransistors (T7) und die erste Energiezufuhrspannung beinhaltet, in den ersten Anschluss (N1) des Speichertransistors (C1) zu schreiben.
     
    6. Pixelansteuerungsschaltung gemäß Anspruch 5, dadurch gekennzeichnet, dass der dritte Transistor (T3) ein P-Typ-Transistor ist.
     
    7. Pixelansteuerungsschaltung gemäß Anspruch 1, wobei der Ansteuerungstransistor (T7), die fünften und sechsten Transistoren (T5, T6) P-Typ-Transistoren sind.
     
    8. Ansteuerungsverfahren für die Pixelansteuerungsschaltung gemäß einem der Ansprüche 1-7, dadurch gekennzeichnet, dass es die folgenden Schritte umfasst:

    während einer Rücksetzperiode, Rücksetzen der Spannung über den Speicherkondensator (C1) auf eine vordefinierte Spannung mittels der Rücksetzeinheit;

    während einer Datenspannungsschreibperiode, Schreiben der Datenspannung in den zweiten Anschluss (N2) des Speicherkondensators (C1) mittels der Datenschreibeinheit, und Schreiben der Information, die die Schwellenspannung des Ansteuerungstransistors (T7) und die erste Energiezufuhrspannung beinhaltet, in den ersten Anschluss (N1) des Speicherkondensators (C1) mittels der Kompensationseinheit; und

    während einer Lichtemittierungs-Periode, Schreiben der Referenzspannung in den zweiten Anschluss (N2) des Speicherkondensators (C1) mittels der Lichtemittierungs-Steuereinheit, Übertragen der Information, die die Datenspannung und die Referenzspannung beinhaltet, an das Gate des Ansteuerungstransistors (T7) mittels des Speicherkondensators (C1), und Steuern der Amplitude des durch die Licht emittierende Vorrichtung (D) fließenden Stromes gemäß der Information, die die Datenspannung, die Schwellenspannung des Ansteuerungstransistors (T7), die Referenzspannung und die erste Energiezufuhrspannung beinhaltet, um die Licht emittierende Vorrichtung (D) anzusteuern, um Licht zu emittieren, mittels des Ansteuerungstransistors (T7) unter der Steuerung der Lichtemittierungs-Steuereinheit.


     
    9. Ansteuerungsverfahren gemäß Anspruch 8, dadurch gekennzeichnet, dass
    während der Rücksetzperiode die Rücksetzeinheit Spannungen an den zwei Anschlüssen des Speicherkondensators (C1) auf die Spannung an der Rücksetzsignalleitung (ini) bzw. die Referenzspannung zurücksetzt.
     
    10. Array-Substrat, dadurch gekennzeichnet, dass es die Pixelansteuerungsschaltung gemäß einem der Ansprüche 1-7 umfasst.
     
    11. Anzeigevorrichtung, dadurch gekennzeichnet, dass sie das Array-Substrat gemäß Anspruch 10 umfasst.
     


    Revendications

    1. Un circuit de commande de pixel, comprenant : une ligne de données (Data) pour fournir une tension de données, une ligne de grille (Gate) pour fournir une tension de balayage, une première ligne d'alimentation (ELVDD) pour fournir une première tension d'alimentation, une deuxième ligne d'alimentation (ELVSS) pour fournir une deuxième tension d'alimentation, une ligne de signal de référence (ref) pour fournir une tension de référence, un dispositif d'émission de lumière (D), un transistor de commande (T7), un condensateur de stockage (C1), une unité de réinitialisation, une unité d'écriture de données, une unité de compensation et une unité de commande d'émission de lumière ;

    l'unité de réinitialisation est reliée à la ligne de signal de référence (ref) et au condensateur de stockage (C1), et est configurée pour réinitialiser une tension aux bornes du condensateur de stockage (C1) à une tension de signal prédéfinie,

    l'unité d'écriture de données est reliée à la ligne de grille (Gate), à la ligne de données (Data) et à une deuxième borne (N2) du condensateur de stockage (C1), et est configurée pour écrire une/des information(s) comprenant une tension de données dans la deuxième borne (N2) du condensateur de stockage (C1),

    l'unité de compensation est reliée à la ligne de grille (Gate), à une première borne (N1) du condensateur de stockage (C1) et au drain du transistor de commande (T7), et est configurée pour écrire des informations comprenant une tension de seuil du transistor de commande (T7) et une information de la première tension d'alimentation dans la première borne (N1) du condensateur de stockage (C1),

    l'unité de commande d'émission de lumière est reliée à la ligne de signal de référence (ref), à la deuxième borne (N2) du condensateur de stockage (C1), au transistor de commande (T7) et au dispositif d'émission de lumière (D), et est configurée pour écrire la tension de référence dans la deuxième borne (N2) du condensateur de stockage (C1) et pour commander le transistor de commande (T7) pour amener le dispositif d'émission de lumière (D) à émettre de la lumière,

    la première borne (N1) du condensateur de stockage (Cl) est reliée à une grille du transistor de commande (T7), et le condensateur de stockage (C1) est configuré pour transférer la/les information(s) comprenant la tension de données, dans la grille du transistor de commande (T7), et

    le transistor de commande (T7) est relié à la première ligne d'alimentation (ELVDD), une première borne du dispositif d'émission de lumière (D) est relié à la deuxième ligne d'alimentation (ELVSS), et le transistor de commande (T7) est configuré pour commander une amplitude d'un courant circulant à travers le dispositif d'émission de lumière (D) en fonction des informations comprenant la tension de données, la tension de seuil du transistor de commande (T7), la tension de référence et la première tension d'alimentation sous la commande de l'unité de commande d'émission de lumière,

    dans lequel l'unité de réinitialisation comprend une ligne de commande de réinitialisation (Reset), une ligne de signal de réinitialisation (ini), un premier transistor (T1) et un deuxième transistor (T2), le premier transistor (T1) a une grille reliée à la ligne de commande de réinitialisation (Reset) et une source reliée à la ligne de signal de réinitialisation (ini) ; le deuxième transistor (T2) a une grille reliée à la ligne de commande de réinitialisation (Reset) et une source reliée à la ligne de signal de référence (ref),

    dans lequel :

    le premier transistor (T1) a un drain relié à la première borne (N1) du condensateur de stockage (C1), et est configuré pour écrire une tension sur la ligne de signal de réinitialisation (ini) dans la première borne (N1) du condensateur de stockage (C1),

    le deuxième transistor (T2) a un drain relié à la deuxième borne (N2) du condensateur de stockage (C1), et est configuré pour écrire la tension de référence dans la deuxième borne (N2) du condensateur de stockage (C1),

    la ligne de signal de référence (ref) est séparée de la première ligne d'alimentation (ELVDD),

    l'unité de commande d'émission de lumière comprend une ligne de commande d'émission de lumière (EM), un cinquième transistor (T5) et un sixième transistor (T6), dans lequel le cinquième transistor (T5) a une grille reliée à la ligne de commande d'émission de lumière (EM), une source reliée à la ligne de signal de référence (ref) et à la source du deuxième transistor (T2), et un drain relié à la deuxième borne (N2) du condensateur de stockage (C1), et est configuré pour écrire la tension de référence fournie par la ligne de signal de référence (ref) dans la deuxième borne (N2) du condensateur de stockage (Cl) de sorte que le condensateur de stockage (C1) transfère la tension de référence à la grille du transistor de commande (T7), et le sixième transistor (T6) a une grille reliée à la ligne de commande d'émission de lumière (EM), une source reliée au drain du transistor de commande (T7) et un drain relié à la deuxième borne du dispositif d'émission de lumière (D) et est configuré pour commander le dispositif d'émission de lumière (D) pour émettre de la lumière, le transistor de commande (T7) est configuré pour commander l'amplitude du courant circulant à travers le dispositif d'émission de lumière (D) en fonction des informations comprenant la tension de données, la tension de seuil du transistor de commande (T7), la première tension d'alimentation et la tension de référence sous la commande de l'unité de commande d'émission de lumière, et dans lequel la tension de référence est une tension de niveau haut et la tension sur la ligne de signal de réinitialisation est un niveau bas (Vint) de telle sorte que l'unité de commande d'émission de lumière écrit la tension de niveau haut dans la deuxième borne (N2) du condensateur de stockage (C1) pendant une période d'émission de lumière.


     
    2. Le circuit de commande de pixel de la revendication 1, caractérisé en ce que les premiers et deuxièmes transistors (T1, T2) sont des transistors de type P.
     
    3. Le circuit de commande de pixel de la revendication 1, caractérisé en ce que l'unité d'écriture de données comprend un quatrième transistor (T4),
    le quatrième transistor (T4) a une grille reliée à la ligne de grille (Gâte), une source reliée à la ligne de données (Data) et un drain relié à la deuxième borne (N2) du condensateur de stockage (C1), et est configuré pour écrire la tension de données dans la deuxième borne (N2) du condensateur de stockage (C1).
     
    4. Le circuit de commande de pixel de la revendication 3, caractérisé en ce que le quatrième transistor (T4) est un transistor de type P.
     
    5. Le circuit de commande de pixel de la revendication 1, caractérisé en ce que l'unité de compensation comprend un troisième transistor (T3),
    le troisième transistor (T3) a une grille reliée à la ligne de grille (Gate), une source reliée à la première borne (N1) du condensateur de stockage (C1) et un drain relié au drain du transistor de commande (T7), et est configuré pour écrire les informations comprenant la tension de seuil du transistor de commande (T7) et la première tension d'alimentation dans la première borne (N1) du condensateur de stockage (C1).
     
    6. Le circuit de commande de pixel de la revendication 5, caractérisé en ce que le troisième transistor (T3) est un transistor de type P.
     
    7. Le circuit de commande de pixel de la revendication 1, dans lequel le transistor de commande (T7), les cinquième et sixième transistors (T5, T6) sont des transistors de type P.
     
    8. Un procédé de commande pour le circuit de commande de pixel de l'une quelconque des revendications 1 à 7, caractérisé en ce qu'il comprend les étapes suivantes :

    pendant une période de réinitialisation, réinitialisation de la tension aux bornes du condensateur de stockage (Cl) à une tension prédéfinie par l'unité de réinitialisation ;

    pendant une période d'écriture de tension de données, écriture de la tension de données dans la deuxième borne (N2) du condensateur de stockage (C1) par l'unité d'écriture de données, et écriture des informations comprenant la tension de seuil du transistor de commande (T7) et la première tension d'alimentation dans la première borne (N1) du condensateur de stockage (C1) par l'unité de compensation ; et

    pendant une période d'émission de lumière, écriture de la tension de référence dans la deuxième borne (N2) du condensateur de stockage (Cl) par l'unité de commande d'émission de lumière, transfert des informations, y compris la tension de données et la tension de référence, sur la grille du transistor de commande (T7) par le condensateur de stockage (C1), et commande de l'amplitude du courant traversant le dispositif d'émission de lumière (D) en fonction des informations comprenant la tension de données, la tension de seuil du transistor de commande (T7), la tension de référence et la première tension d'alimentation pour amener le dispositif d'émission de lumière (D) à émettre de la lumière grâce au transistor de commande (T7) sous la commande de l'unité de commande d'émission de lumière.


     
    9. Le procédé de commande de la revendication 8, caractérisé en ce que
    pendant la période de réinitialisation, l'unité de réinitialisation réinitialise des tensions aux deux bornes du condensateur de stockage (C1) à la tension sur la ligne de signal de réinitialisation (ini) et à la tension de référence, respectivement.
     
    10. Un substrat de réseau, caractérisé en ce qu'il comprend le circuit de commande de pixel de l'une quelconque des revendications 1 à 7.
     
    11. Un appareil d'affichage, caractérisé en ce qu'il comprend le substrat de réseau de la revendication 10.
     




    Drawing












    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description