(19)
(11)EP 3 163 616 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
04.12.2019 Bulletin 2019/49

(21)Application number: 16192005.3

(22)Date of filing:  03.10.2016
(51)Int. Cl.: 
H01L 25/16  (2006.01)
H03H 7/06  (2006.01)
H01L 23/64  (2006.01)
H03K 5/1252  (2006.01)

(54)

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

VORRICHTUNG MIT EINER INTEGRIERTEN HALBLEITERSCHALTUNG

CIRCUIT INTÉGRÉ À SEMI-CONDUCTEUR


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 14.10.2015 US 201562241240 P
23.09.2016 US 201615274473

(43)Date of publication of application:
03.05.2017 Bulletin 2017/18

(73)Proprietor: MediaTek Inc.
Hsin-Chu 300 (TW)

(72)Inventors:
  • LIAO, Chun-Neng
    New Taipei City 234 (TW)
  • CHIANG, Meng-Hsin
    Zhubei City 302 (TW)
  • CHANG, Chun-Wei
    Taipei City 104 (TW)
  • UNG, Chee-Kong
    Hsinchu City 300 (TW)
  • LI, Ching-Chih
    New Taipei City 231 (TW)

(74)Representative: Goddar, Heinz J. 
Boehmert & Boehmert Anwaltspartnerschaft mbB Pettenkoferstrasse 22
80336 München
80336 München (DE)


(56)References cited: : 
JP-A- S6 175 558
US-A1- 2007 279 882
US-A1- 2012 081 193
US-A1- 2006 139 123
US-A1- 2011 180 898
US-A1- 2015 207 485
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    BACKGROUND OF THE INVENTION


    Field of the Invention



    [0001] The invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device with a tunable external decoupling capacitor for anti-resonance suppression.

    Description of the Related Art



    [0002] Anti-resonance is a pronounced minimum in the amplitude of a circuit at a particular frequency, accompanied by a large shift in its oscillation phase. Such a frequency is known as the system's anti-resonant frequency, and at this frequency, the amplitude of a signal can drop to almost zero.

    [0003] FIG. 1 is a diagram showing an exemplary impedance profile of a system. The curve 101 represents a first capacitive impedance of a component, such as a printed circuit board (PCB), in the system. The curve 102 represents a second capacitive impedance of a component, such as a die, in the system. The curve 103 represents a first inductive impedance of a component, such as the PCB, in the system. The curve 104 represents a second inductive impedance of a component, such as the die, in the system.

    [0004] When two curves intersect at a particular frequency, such as the frequency f1 shown in FIG. 1, the anti-resonance phenomenon occurs at the particular frequency and a shoulder 105 in the impedance profile is generated. Because the impedance increases enormously at the anti-resonant frequency f1, an undesired amplitude drop in the signal oscillating at the anti-resonant frequency f1 will occur and cause the performance of the system to suffer.

    [0005] US 2012/081193 A1 describes a band elimination filter provided as a closed circuit connected between a starter solenoid and a starter motor. The closed circuit comprises two capacitors having a respective equivalent series inductance and a respective equivalent series resistance. A resistor is connected in series to one of the capacitors for damping the parallel resonance of the closed circuit.

    [0006] US 2007/279882 A1 describes an integrated circuit package to be connected to a power wiring network. A shunt network is provided having a series resonant frequency at or near the parallel resonant frequency of the power wiring network. In particular, the ratio of the inductive reactance to the resistive impedance at the respective pole or zero, i.e. the Q factor, is 1.4 or less.

    [0007] US 2006/139123 A1 describes embodiments of resistive capacitor structures comprising a decoupling capacitor for filtering power and ground noise signals and a series resistance element conductively coupled in series to a plate of the capacitor.

    [0008] US 2015/207485 A1 describes a RC network with a variable resistor and a variable capacitor for damping and phase shift capabilities. The RC network comprises multiple capacitors and resistor assemblies. Each resistor assembly comprises at least one PDR layer, at least one NDR layer and at least one ZDR layer laid upon each other.

    [0009] US 2011/180898 A1 describes a semiconductor device having one or more capacitance chips disposed on a semiconductor chip. JP S61 75558 A describes a semiconductor structure with a semiconductor pellet arranged on the opposite side of a thick film substrate to a chip capacitor and semiconductor.

    [0010] To suppress the undesired anti-resonance, a novel design for a semiconductor integrated circuit device is required.

    BRIEF SUMMARY OF THE INVENTION



    [0011] Semiconductor integrated circuit devices are provided in accordance with the features of independent claim 1. An exemplary embodiment of a semiconductor integrated circuit device comprises a chip main circuit, a damper and a passive component. The chip main circuit is coupled to a power source and performs a predetermined function. The damper is coupled to an output terminal of the chip main circuit. The passive component is coupled to the chip main circuit via the damper.

    [0012] An exemplary embodiment of a semiconductor integrated circuit device comprises a chip main circuit and a damper. The chip main circuit is coupled to a power source and performs a predetermined function. The damper is coupled to an output terminal of the chip main circuit. The damper is coupled between the chip main circuit and a passive component for suppressing anti-resonance of the semiconductor integrated circuit device.

    [0013] A detailed description is given in the following embodiments with reference to the accompanying drawings.

    BRIEF DESCRIPTION OF DRAWINGS



    [0014] The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

    FIG. 1 is a diagram showing an exemplary impedance profile of a system;

    FIG. 2 shows an exemplary block diagram of a semiconductor integrated circuit device according to an embodiment of the invention;

    FIG. 3 is an equivalent circuit diagram of an electronic system comprising the semiconductor integrated circuit device according to an embodiment of the invention;

    FIG. 4 is a diagram showing an exemplary impedance profiles of the electronic system according to an embodiment of the invention;

    FIG. 5A shows an exemplary circuit diagram of a semiconductor integrated circuit device according to an embodiment of the invention;

    FIG. 5B shows an exemplary circuit diagram of a variable resistor according to an embodiment of the invention;

    FIG. 6 is a flow chart of a method for determining the optimal resistance of the damper according to an embodiment of the invention;

    FIG. 7 shows an exemplary lateral view of an electronic system according to an embodiment of the invention;

    FIG. 8 shows an exemplary lateral view of an electronic system according to another embodiment of the invention; and

    FIG. 9 shows an exemplary lateral view of an electronic system according to another embodiment of the invention.


    DETAILED DESCRIPTION OF THE INVENTION



    [0015] The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

    [0016] FIG. 2 shows an exemplary block diagram of a semiconductor integrated circuit device according to an embodiment of the invention. The semiconductor integrated circuit device 200 may at least comprise a chip main circuit 210 and a damper 220. The chip main circuit 210 is coupled to a power source 240 and performs a predetermined function. For example, the chip main circuit 210 may perform a modem (that is, modulation and demodulation) function for wired/wireless communication, a signal processing function for wired/wireless communication, a digital signal processing function, an analog signal processing function, etc.

    [0017] For providing the predetermined function, the chip main circuit 210 may be integrated in a chip such as a modem chip, a baseband signal processing chip, an RF signal processing chip, a digital signal processing chip, an analog signal processing chip, etc. The power source 240 may be configured inside or outside of the chip. In addition, the power source 240 may be configured inside or outside of the chip main circuit 210.

    [0018] The damper 220 is coupled to an output terminal OUT of the chip main circuit 210.

    [0019] The semiconductor integrated circuit device 200 may further comprise a passive component 230. The damper 220 is coupled between the chip main circuit 210 and the passive component 230. In other words, in an embodiment of the invention, the passive component 230 is coupled to the chip main circuit 210 via the damper 220.

    [0020] According to an embodiment of the invention, the passive component 230 is in an independent path that is not directly connected to the power source 240, regardless of whether the power source 240 is configured inside or outside of the chip main circuit 210 or the chip.

    [0021] In addition, according to an embodiment of the invention, the damper 220 is coupled between the chip main circuit 210 and the passive component 220 for suppressing anti-resonance of the semiconductor integrated circuit device 200.

    [0022] In addition, in the embodiments of the invention, the damper 220 and the passive component 230 are the circuit components external to the chip main circuit 210, as shown in FIG. 2. In other words, the predetermined function performed by the chip main circuit 210 is not affected by the damper 220 and the passive component 230. The chip main circuit 210 can perform the predetermined function even if the damper 220 and the passive component 230 are not coupled thereto or do not even exist in the semiconductor integrated circuit device 200. The damper 220 and the passive component 230 are introduced to decrease the impedance and suppress anti-resonance of the semiconductor integrated circuit device 200.

    [0023] According to an embodiment of the invention, the chip main circuit 210, the damper 220 and the passive component 230 may be packed in a package and/or mounted on a printed circuit board (PCB). Therefore, in some embodiments of the invention, the semiconductor integrated circuit device 200 may further comprise a package and/or a PCB.

    [0024] FIG. 3 is an equivalent circuit diagram of an electronic system comprising the semiconductor integrated circuit device according to an embodiment of the invention. The capacitor Cpcb represents the equivalent capacitor of the PCB. The inductor Lpcb represents the equivalent inductor of the PCB. The resistor Rpkg represents the equivalent resistor of the package. The inductor Lpkg represents the equivalent inductor of the package. The resistor Rdie represents the equivalent resistor of a chip with the chip main circuit 210 integrated therein. The capacitor Cdie represents the equivalent capacitor of the chip with the chip main circuit 210 integrated therein.

    [0025] The capacitor Cext represents the equivalent capacitor of the passive component 230. The inductor Lext represents the parasitic inductor of the passive component 230. The resistor Rext represents the parasitic resistor of the passive component 230. The resistor Rvar represents the equivalent resistor of the damper 220.

    [0026] The capacitor Cext, the inductor Lext and the resistor Rext may be as a whole regarded as the overall impedance contributed by the passive component 230. According to an embodiment of the invention, the damper 220 and the passive component 230 are coupled in serial.

    [0027] As shown in FIG. 3, the passive component 230 is not directly connected to the power source Vsys of the electronic system and is coupled to the chip (that is, the chip main circuit 210) via the damper 220.

    [0028] According to an embodiment of the invention, the resistance of the damper 220 may be adjustable, so as to be adjusted to an optimal value for suppressing anti-resonance of the semiconductor integrated circuit device 200.

    [0029] FIG. 4 is a diagram showing exemplary impedance profiles of the electronic system according to an embodiment of the invention. FIG. 4 shows the impedance profiles of the shoulder generated when anti-resonance occurs. The curve 401 represents the impedance profile of the shoulder when the damper 220 is not added. The curve 402 represents the impedance profile of the shoulder when the damper 220 is added to the electronic system as shown in FIG. 2 and FIG. 3. As shown in FIG. 4, when the damper 220 is added, the shoulder becomes wider and the peak amplitude of the shoulder is decreased.

    [0030] According to an embodiment of the invention, the damper 220 is a variable resistor. The resistance of the resistor may be adjusted to an optimal value for suppressing anti-resonance of the semiconductor integrated circuit device 200.

    [0031] According to an embodiment of the invention, the passive component 230 is a capacitor.

    [0032] FIG. 5A shows an exemplary circuit diagram of a semiconductor integrated circuit device according to an embodiment of the invention. The variable resistor 520 is coupled between the chip main circuit 510 and the capacitor 530. The capacitor 530 may be regarded as an external decoupling capacitor of the chip main circuit 510. The semiconductor integrated circuit device 500 may further comprise a control circuit 550 generating a multi-bit control signal Control_Bit for controlling the resistance of the variable resistor 520 (that is, the damper). Note that in some embodiments, the control circuit 550 may also be integrated in the chip main circuit 510, or may be implemented by any device in the chip main circuit 510. Therefore, the invention should not be limited to the architecture shown in FIG. 5A.

    [0033] In the embodiment, the variable resistor 520 may be implemented by a plurality of transistors coupled in parallel. For example, as an exemplary circuit diagram shown in FIG. 5B, the variable resistor may be implemented by four transistors with a first electrode coupled to the terminal X, a second electrode coupled to the terminal Y and a control electrode receiving the corresponding control signal B1~B4 carried in the multi-bit control signal Control_Bit. When the transistor is turned on in response to the corresponding control signal, the transistor is equivalent to a resistor or resistive device. For example, the multi-bit control signal [0000] may correspond to the minimum resistance provided by the variable resistor 520, and the multi-bit control signal [1110] may correspond to the maximum resistance provided by the variable resistor 520.

    [0034] Note that, although there are four transistors or resistive devices shown in FIG. 5B to implement the variable resistor, the invention should not be limited thereto. The variable resistor may also be implemented by less than or more than four transistors, resistive devices, resistors, or inductors.

    [0035] According to an embodiment of the invention, the chip main circuit 510 may comprise a processor 511. The processor 511 may determine the optimal resistance of the variable resistor 520 (that is, the damper) by searching for the minimum system voltage provided by the power source (such as the power source 240 or Vsys) of the electronic system for the chip main circuit 510, the semiconductor integrated circuit device, or even the electronic system being able to function without crashing, and generate a control signal for controlling the resistance of the variable resistor 520 (that is, the damper) according to the optimal resistance. The control signal may be provide to the control circuit 550 and the control circuit 550 generates the multi-bit control signal Control_Bit according to the control signal as shown in FIG. 5, or may be directly provided to the variable resistor 520 for controlling the resistance thereof.

    [0036] For example, in an embodiment of the invention, suppose that there are n values of resistance R1-Rn that can be provided by the variable resistor 520. For each resistance, the processor 511 may first search for a corresponding minimum system voltage, such as Vmin_R1, Vmin_R2...Vmin_Rn, provided by the power source of the electronic system for the chip main circuit 510, the semiconductor integrated circuit device, or even the electronic system to be able to function without crashing, and then compare the minimum system voltages Vmin_R1, Vmin_R2... Vmin_Rn to obtain the smallest one among them. The resistance corresponding to the smallest one may be determined to be the optimal resistance.

    [0037] FIG. 6 is a flow chart of a method for determining the optimal resistance of the damper according to an embodiment of the invention. When the electronic system powers on (that is, when the power source supplies power) (Step S602), the chip main circuit boots up and the processor generates control signals to control the resistance of the damper (for example, the variable resistor). The system voltage provided by the power source is adjusted to multiple levels as well for every possible resistance supported by the damper, to test whether the electronic system can function normally or not under each level of system voltage, and obtain the minimum system voltage that the electronic system is able to function on without crashing, corresponding to each resistance supported by the damper (Step S604). Next, the processor obtains the smallest of the minimum system voltages corresponding to the supported resistance (Step S606). The resistance corresponding to the smallest one is determined to be the optimal resistance. Next, the processor generates a control signal for setting the resistance of the damper to the optimal resistance (Step S608).

    [0038] According to an embodiment of the invention, the chip main circuit, the damper and the passive component may be integrated in a chip.

    [0039] FIG. 7 shows an exemplary lateral view of an electronic system according to an embodiment of the invention. In this embodiment, the chip main circuit, the damper (for example, a variable resistor) and the passive component (for example, an external decoupling capacitor) may be integrated in a chip 700. The chip 700 may be packed in the substrate as shown.

    [0040] According to another embodiment of the invention, the chip main circuit and the damper may be integrated in a chip, and the passive component may be configured outside of the chip.

    [0041] FIG. 8 shows an exemplary lateral view of an electronic system according to another embodiment of the invention. In this embodiment, the chip main circuit and the damper (for example, a variable resistor) may be integrated in a chip 800, and the passive component (for example, an external decoupling capacitor) may be configured outside of the chip 800. The chip 800 may be packed in the substrate as shown, and the passive component may be coupled to the damper via a trace.

    [0042] According to yet another embodiment of the invention, the chip main circuit may be integrated in a chip, and the damper and the passive component may be configured outside of the chip.

    [0043] FIG. 9 shows an exemplary lateral view of an electronic system according to another embodiment of the invention. In this embodiment, the chip main circuit may be integrated in a chip 900, and the damper (for example, a variable resistor) and the passive component (for example, an external decoupling capacitor) may be configured outside of the chip 900. The chip 900 may be packed in the substrate as shown, and the damper and the passive component may be coupled to the damper via a trace.

    [0044] Note that, in some embodiments of the invention, the damper and the passive component may also be integrated as one device, and the invention should not be limited to the embodiments as illustrated above. For example, the damper (for example, a variable resistor) may be implemented in the passive component (for example, an external decoupling capacitor).

    [0045] As described above, in the embodiments of the invention, with the damper 220 and the passive component 230, the impedance and the anti-resonance of the semiconductor integrated circuit device or the electronic system can be effectively decreased and suppressed.


    Claims

    1. A semiconductor integrated circuit device (200), comprising:

    a chip main circuit (210), coupled to a power source (240) and performing a predetermined function;

    a damper (220), coupled to an output terminal of the chip main circuit (210), wherein the damper (220) is a variable resistor; and

    a passive component (230), wherein the passive component (230) is a capacitor;

    wherein the damper (220) is coupled between the chip main circuit (210) and the passive component (230) for suppressing anti-resonance of the semiconductor integrated circuit device (200),

    wherein the power source (240) is configured to provide a minimum system voltage for the semiconductor integrated circuit device (200) to be able to function without crashing,

    wherein the chip main circuit (210) comprises a processor (511) configured to determine an optimal resistance of the damper (220) by searching for the minimum system voltage, and configured to generate a control signal for controlling resistance of the damper (220) according to the optimal resistance.


     
    2. The semiconductor integrated circuit device of claim 1, further comprising: a control circuit configured to generate the control signal for controlling resistance of the damper.
     
    3. The semiconductor integrated circuit device of claim 1 or 2, further comprising a chip (700), wherein the chip main circuit (210), the damper (220), and the passive component (230) are integrated in the chip (700).
     
    4. The semiconductor integrated circuit device of claim 1 or 2, further comprising a chip (800), wherein the chip main circuit (210) and the damper (220) are integrated in the chip (800), and the passive component (230) is configured outside of the chip (800).
     
    5. The semiconductor integrated circuit device of claim 1 or 2, further comprising a chip (900), wherein the chip main circuit (210) is integrated in the chip (900), and the damper (220) and the passive component (230) are configured outside of the chip (900).
     
    6. A method for determining an optimal resistance of a damper (220) configured in a semiconductor integrated circuit device (200), wherein the damper (220) is a variable resistor, wherein the damper (220) is coupled between a chip main circuit (210) and a passive component (230) for suppressing anti-resonance of the semiconductor integrated circuit device (200), wherein the passive component (230) is a capacitor, comprising:

    providing a system voltage by a power source (240) with different levels to obtain (S604) a minimum system voltage corresponding to each resistance supported by the damper (220);

    determining an optimal resistance of the damper (220) by searching for a minimum system voltage provided by the power source (240) for the semiconductor integrated circuit device (200) to be able to function without crashing;

    obtaining (S606) the smallest of the minimum system voltages corresponding to the supported resistance as the optimal resistance of the damper (220); and

    generating a control signal for controlling resistance of the damper (220) according to the optimal resistance

    setting (S608) the resistance of the damper (220) to the optimal resistance.


     


    Ansprüche

    1. Integrierte Halbleiterschaltungsvorrichtung (200), aufweisend:

    eine Chip-Hauptschaltung (210), die mit einer Energiequelle (240) gekoppelt ist und eine vorbestimmte Funktion ausführt;

    einen Dämpfer (220), der mit einem Ausgangsanschluss der Chip-Hauptschaltung (210) gekoppelt ist, wobei der Dämpfer (220) ein variabler Widerstand ist; und

    eine passive Komponente (230), wobei die passive Komponente (230) ein Kondensator ist;

    wobei der Dämpfer (220) zwischen der Chip-Hauptschaltung (210) und der passiven Komponente (230) zum Unterdrücken von Antiresonanz der integrierten Halbleiterschaltungsvorrichtung (200) gekoppelt ist,

    wobei die Energiequelle (240) dazu ausgebildet ist, eine Mindestsystemspannung bereitzustellen, damit die integrierte Halbleiterschaltungsvorrichtung (200) in der Lage ist, ohne Absturz zu funktionieren,

    wobei die Chip-Hauptschaltung (210) einen Prozessor (511) aufweist, der dazu ausgebildet ist, einen optimalen Widerstand des Dämpfers (220) durch Suchen nach der Mindestsystemspannung zu bestimmen, und dazu ausgebildet ist, ein Steuersignal zum Steuern des Widerstands des Dämpfers (220) gemäß dem optimalen Widerstand zu erzeugen.


     
    2. Integrierte Halbleiterschaltungsvorrichtung nach Anspruch 1, ferner aufweisend:
    eine Steuerschaltung, die dazu ausgebildet ist, das Steuersignal zum Steuern des Widerstands des Dämpfers zu erzeugen.
     
    3. Integrierte Halbleiterschaltungsvorrichtung nach Anspruch 1 oder 2, ferner aufweisend einen Chip (700), wobei die Chip-Hauptschaltung (210), der Dämpfer (220) und die passive Komponente (230) in dem Chip (700) integriert sind.
     
    4. Integrierte Halbleiterschaltungsvorrichtung nach Anspruch 1 oder 2, ferner aufweisend einen Chip (800), wobei die Chip-Hauptschaltung (210) und der Dämpfer (220) in dem Chip (800) integriert sind und die passive Komponente (230) außerhalb des Chips (800) ausgebildet ist.
     
    5. Integrierte Halbleiterschaltungsvorrichtung nach Anspruch 1 oder 2, ferner aufweisend einen Chip (900), wobei die Chip-Hauptschaltung (210) in dem Chip (900) integriert ist und der Dämpfer (220) und die passive Komponente (230) außerhalb des Chips (900) ausgebildet sind.
     
    6. Verfahren zum Bestimmen eines optimalen Widerstands eines Dämpfers (220), der in einer integrierten Halbleiterschaltungsvorrichtung (200) ausgebildet ist, wobei der Dämpfer (220) ein variabler Widerstand ist, wobei der Dämpfer (220) zwischen einer Chip-Hauptschaltung (210) und einer passiven Komponente (230) zum Unterdrücken von Antiresonanz der integrierten Halbleiterschaltungsvorrichtung (200) gekoppelt ist, wobei die passive Komponente (230) ein Kondensator ist, umfassend:

    Bereitstellen einer Systemspannung durch eine Energiequelle (240) mit verschiedenen Pegeln, um eine Mindestsystemspannung, die jedem durch den Dämpfer (220) unterstützten Widerstand entspricht, zu erhalten (S604);

    Bestimmen eines optimalen Widerstands des Dämpfers (220) durch Suchen nach einer Mindestsystemspannung, die durch die Energiequelle (240) bereitgestellt wird, damit die integrierte Halbleiterschaltungsvorrichtung (200) in der Lage ist, ohne Absturz zu funktionieren;

    Erhalten (S606) der kleinsten der Mindestsystemspannungen, die dem unterstützten Widerstand als optimalem Widerstand des Dämpfers (220) entspricht; und

    Erzeugen eines Steuersignals zum Steuern des Widerstands des Dämpfers (220) gemäß dem optimalen Widerstand,

    Einstellen (S608) des Widerstands des Dämpfers (220) auf den optimalen Widerstand.


     


    Revendications

    1. Circuit intégré à semi-conducteur (200), comprenant :

    un circuit principal à puce (210), relié à une source d'alimentation électrique (240) et qui exécute une fonction prédéterminée ;

    un régulateur (220), relié à une borne de sortie du circuit principal à puce (210),
    dans lequel le régulateur (220) est une résistance variable ; et

    un composant passif (230), dans lequel le composant passif (230) est un condensateur ;

    dans lequel le régulateur (220) est relié entre le circuit principal à puce (210) et le composant passif (230) afin de supprimer l'antirésonance du circuit intégré à semi-conducteur (200),

    dans lequel la source d'alimentation électrique (240) est configurée pour fournir une tension système minimum pour le circuit intégré à semi-conducteur (200) afin qu'il puisse fonctionner sans tomber en panne,

    dans lequel le circuit principal à puce (210) comprend un processeur (511) configuré pour déterminer une résistance optimale du régulateur (220) en recherchant la tension système minimum, et configuré pour générer un signal de commande destiné à contrôler la résistance du régulateur (220) selon la résistance optimale.


     
    2. Circuit intégré à semi-conducteur selon la revendication 1, comprenant en outre :
    un circuit de commande configuré pour générer le signal de commande destiné à contrôler la résistance du régulateur.
     
    3. Circuit intégré à semi-conducteur selon la revendication 1 ou 2, comprenant en outre une puce (700), dans lequel le circuit principal à puce (210), le régulateur (220) et le composant passif (230) sont intégrés à la puce (700).
     
    4. Circuit intégré à semi-conducteur selon la revendication 1 ou 2, comprenant en outre une puce (800), dans lequel le circuit principal à puce (210) et le régulateur (220) sont intégrés à la puce (800), et le composant passif (230) est configuré à l'extérieur de la puce (800).
     
    5. Circuit intégré à semi-conducteur selon la revendication 1 ou 2, comprenant en outre une puce (900), dans lequel le circuit principal à puce (210) est intégré à la puce (900), et le régulateur (220) et le composant passif (230) sont configurés à l'extérieur de la puce (900).
     
    6. Procédé de détermination d'une résistance optimale d'un régulateur (220) configuré dans un circuit intégré à semi-conducteur (200), dans lequel le régulateur (220) est une résistance variable, dans lequel le régulateur (220) est relié entre un circuit principal à puce (210) et un composant passif (230) afin de supprimer l'antirésonance du circuit intégré à semi-conducteur (200), dans lequel le composant passif (230) est un condensateur, comprenant :

    la fourniture d'une tension système par une source d'alimentation électrique (240) avec différents niveaux afin d'obtenir (S604) une tension système minimum correspondant à chaque résistance supportée par le régulateur (220) ;

    la détermination d'une résistance optimale du régulateur (220) en recherchant une tension système minimum fournie par la source d'alimentation électrique (240) pour le circuit intégré à semi-conducteur (200) afin qu'il puisse fonctionner sans tomber en panne ;

    l'obtention (S606) de la plus faible des tensions système minimum correspondant à la résistance supportée en guise de résistance optimale du régulateur (220) ; et

    la génération d'un signal de commande destiné à contrôler la résistance du régulateur (220) selon la résistance optimale,

    le réglage (S608) de la résistance du régulateur (220) sur la résistance optimale.


     




    Drawing






























    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description