(19)
(11)EP 3 188 235 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
06.05.2020 Bulletin 2020/19

(21)Application number: 14891131.6

(22)Date of filing:  19.11.2014
(51)Int. Cl.: 
G02F 1/1362  (2006.01)
(86)International application number:
PCT/CN2014/091555
(87)International publication number:
WO 2016/029564 (03.03.2016 Gazette  2016/09)

(54)

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE

ARRAYSUBSTRAT UND HERSTELLUNGSVERFAHREN DAFÜR, ANZEIGETAFEL UND ANZEIGEVORRICHTUNG

SUBSTRAT MATRICIEL ET SON PROCÉDÉ DE FABRICATION, ÉCRAN D'AFFICHAGE ET DISPOSITIF D'AFFICHAGE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 29.08.2014 CN 201410438637

(43)Date of publication of application:
05.07.2017 Bulletin 2017/27

(73)Proprietors:
  • BOE Technology Group Co., Ltd.
    Beijing 100015 (CN)
  • Beijing BOE Display Technology Co., Ltd.
    Beijing 100176 (CN)

(72)Inventor:
  • ZHAN, Hongming
    Beijing 100176 (CN)

(74)Representative: Brötz, Helmut et al
Rieder & Partner mbB Patentanwälte - Rechtsanwalt Corneliusstrasse 45
42329 Wuppertal
42329 Wuppertal (DE)


(56)References cited: : 
CN-A- 102 981 335
CN-A- 103 309 108
CN-U- 202 948 925
US-A1- 2007 284 627
CN-A- 103 208 491
CN-A- 104 037 126
CN-U- 203 117 620
US-A1- 2014 054 581
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    TECHNICAL FIELD



    [0001] Embodiments of the present disclosure relate to an array substrate and a fabricating method thereof, a display panel and a display apparatus.

    BACKGROUND



    [0002] A thin film transistor liquid crystal display (TFT-LCD) is a comparatively ideal display device due to advantages of small size, low power consumption, no radiation and so on. In recent years, the scope of application of TFT-LCDs in the display field is gradually enlarged, and relevant technologies are developed rapidly. Displays of a high aperture ratio Advanced-super Dimensional Switching (HADS) mode have been widely applied to various display products due to advantages of wide viewing angle, low color cast and so on.
    US20140545 81A1 discloses an array substrate, in which a common electrode 8 is connected with a storage capacitance bottom electrode 13 through an insulation layer via hole above the storage capacitance bottom electrode 13; CN 203117620U discloses a manufacturing method of an array substrate, in which the common electrode 8 is connected with the signal line 5 through the passivation layer via hole 10, and the signal line 5 is connected with the gate line 2 through the gate insulating layer via hole 9.

    [0003] As shown in FIG. 1, an array substrate of an HADS technology in the state of art comprises a base substrate 1a, a gate electrode 2a, a common electrode line 3a, a gate insulating layer 4a, an active layer 5a, a pixel electrode 6a, a drain electrode 8a, a source electrode 7a, a data line 9a, a passivation layer 10a, and a common electrode 11a; the common electrode 11a is electrically connected with the common electrode line 3a through a via hole 20a. It can be seen from FIG. 1, the via hole 20a is a via hole penetrating through both the gate insulating layer 4a and the passivation layer 10a. When the array substrate is designed, in order to reduce coupling capacitance between the common electrode 11a and the data line 9a, the passivation layer 10a is required to be made thicker, and therefore, to ensure effectiveness of the via hole 20a, a hole depth of the via hole 20a is enough large and the size of the via hole is relatively large. However, the relatively large hole depth and size of the via hole 20a make the coating process of a subsequent fabricating process be difficultly controlled and easily invoke moires on a coated film layer, thereby affecting the yield of the fabricated array substrates.

    SUMMARY



    [0004] According to a first embodiment of the present invention as recited in appended claim 1, there is provided an array substrate. The array substrate comprises a base substrate and a gate metal layer, a gate insulating layer, an active layer, a source-drain electrode metal layer, a passivation layer and a common electrode layer which are sequentially formed on the base substrate, as well as a pixel electrode layer which is positioned either between the active layer and the source-drain electrode metal layer, or between the source-drain electrode metal layer and the passivation layer; the gate metal layer including a gate electrode and a common electrode line. Either the pixel electrode layer, or the source-drain electrode metal layer includes a connecting electrode, the connecting electrode is electrically connected with the common electrode line through a first via hole in the gate insulating layer, and the connecting electrode is electrically connected with a common electrode of the common electrode layer through a second via hole in the passivation layer. Vertical projections of the first via hole and the second via hole on the base substrate are mutually staggered, and the vertical projections of the first via hole and the second via hole on the base substrate fall within a scope of a vertical projection of the connecting electrode on the base substrate.

    [0005] According to a further embodiment of the present invention as recited in appended claim 2, the connecting electrode may be in direct contact with the gate insulating layer and the passivation layer.

    [0006] According to a further embodiment of the present invention as recited in appended claim 3, the connecting electrode may be positioned in the pixel electrode layer, in which case the connecting electrode is mutually insulated from a pixel electrode of the pixel electrode layer.

    [0007] According to a further embodiment of the present invention as recited in appended claim 4, the connecting electrode may be positioned in the source-drain electrode metal layer, in which case the connecting electrode is mutually insulated from a source electrode, a drain electrode and a data line of the source-drain electrode metal layer.

    [0008] According to a further embodiment of the present invention as recited in appended claim 5, there is provided a display panel. The display panel comprises the array substrate as described above.

    [0009] According to a further embodiment of the present invention as recited in appended claim 6, there is provided a display apparatus. The display apparatus comprises the display panel as described above.

    [0010] According to a further embodiment of the present invention as recited in appended claim 7, there is provided a fabricating method of an array substrate. The fabricating method comprises: sequentially forming a gate metal layer, a gate insulating layer, an active layer, a source-drain electrode metal layer, a passivation layer and a common electrode layer on a substrate, and forming a pixel electrode layer either between the active layer and the source-drain electrode metal layer, or between the source-drain electrode metal layer and the passivation layer, the gate metal layer including a gate electrode and a common electrode line. The fabricating method further comprises: forming a connecting electrode either in the pixel electrode layer, or in the source-drain electrode metal layer, forming a first via hole in the gate insulating layer, and forming a second via hole in the passivation layer, the connecting electrode being electrically connected with the common electrode line through the first via hole in the gate insulating layer, and the connecting electrode being electrically connected with a common electrode of the common electrode layer through the second via hole in the passivation layer. Vertical projections of the first via hole and the second via hole on the base substrate are mutually staggered, and the vertical projections of the first via hole and the second via hole on the base substrate fall within a scope of a vertical projection of the connecting electrode on the base substrate.

    [0011] According to a further embodiment of the present invention as recited in appended claim 8, the fabricating method of the array substrate may comprise: sequentially forming the gate metal layer on the base substrate, the gate metal layer including a gate electrode and the common electrode line; sequentially forming the gate insulating layer and the active layer on the gate metal layer; forming the first via hole in a region of the gate insulating layer outside the active layer, a position of the first via hole corresponding to that of the common electrode line; forming the pixel electrode layer including a pixel electrode and the connecting electrode on the base substrate, the connecting electrode being electrically connected with the common electrode line through the first via hole; forming the source-drain electrode metal layer including a source electrode, a drain electrode and a data line on the base substrate; forming the passivation layer on the base substrate, the passivation layer including the second via hole corresponding to the connecting electrode; forming the common electrode layer including the common electrode on the base substrate, the common electrode being electrically connected with the connecting electrode through the second via hole.

    [0012] According to a further embodiment of the present invention as recited in appended claim 9, the fabricating method of the array substrate may comprise: sequentially forming the gate metal layer on the base substrate, the gate metal layer including a gate electrode and the common electrode line; sequentially forming the gate insulating layer and the active layer on the gate metal layer; forming the first via hole in a region of the gate insulating layer outside the active layer, a position of the first via hole corresponding to that of the common electrode line; forming the source-drain electrode metal layer including a source electrode, a drain electrode, a data line and the connecting electrode on the base substrate, the connecting electrode being electrically connected with the common electrode line through the first via hole; forming the pixel electrode layer including a pixel electrode on the base substrate; forming the passivation layer on the base substrate, the passivation layer including the second via hole corresponding to the connecting electrode; forming the common electrode layer including the common electrode on the base substrate, the common electrode being electrically connected with the connecting electrode through the second via hole.

    [0013] According to a further embodiment of the present invention as recited in appended claim 10, the fabricating method of the array substrate may comprise: sequentially forming the gate metal layer on the base substrate, the gate metal layer including a gate electrode and the common electrode line; forming a gate insulating layer, an active layer and a pixel electrode layer including a pixel electrode on the gate metal layer; forming the first via hole in a region of the gate insulating layer, a position of the first via hole corresponding to that of the common electrode line; forming the source-drain electrode metal layer including a source electrode, a drain electrode, a data line and the connecting electrode on the base substrate, the connecting electrode being electrically connected with the common electrode line through the first via hole; forming a passivation layer on the base substrate, the passivation layer including the second via hole corresponding to the connecting electrode; forming a common electrode layer including the common electrode on the base substrate, the common electrode being electrically connected with the connecting electrode through the second via hole.

    [0014] According to a further embodiment of the present invention as recited in appended claim 11, the fabricating method of the array substrate may comprise: sequentially forming the gate metal layer on the base substrate, the gate metal layer including a gate electrode and the common electrode line; forming the gate insulating layer, the active layer, and the source-drain electrode metal layer including a source electrode, a drain electrode and a data line on the gate metal layer; forming the first via hole in a region of the gate insulating layer outside the active layer and the data line, a position of the first via hole corresponding to that of the common electrode line; forming the pixel electrode layer including a pixel electrode and the connecting electrode on the base substrate, the connecting electrode being electrically connected with the common electrode line through the first via hole; forming the passivation layer on the base substrate, the passivation layer including the second via hole corresponding to the connecting electrode; forming a common electrode layer including the common electrode on the base substrate, the common electrode being electrically connected with the connecting electrode through the second via hole.

    [0015] According to a further embodiment of the present invention as recited in appended claim 12, the connecting electrode may be mutually insulated from the pixel electrode.

    [0016] According to a further embodiment of the present invention as recited in appended claim 13, the connecting electrode may be mutually insulated from the source electrode, the drain electrode and the data line.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0017] In order to more clearly illustrate the technical solution of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described in the following; it is obvious that the described drawings are only related to some embodiments of the present disclosure and thus are not limitative of the present disclosure.

    FIG. 1 is a structural schematic diagram of an array substrate of an HADS mode in the state of art;

    FIG. 2 is a structural schematic diagram of a first array substrate provided in an embodiment of the present disclosure;

    FIG. 3 is a structural schematic diagram of a second array substrate provided in an embodiment of the present disclosure;

    FIG. 4 is a structural schematic diagram of a third array substrate provided in an embodiment of the present disclosure; and

    FIG. 5 is a schematic structural diagram of a fourth array substrate provided in an embodiment of the present disclosure.


    DETAILED DESCRIPTION



    [0018] In order to make objects, technical details and advantages of the embodiments of the present invention apparent, the technical solutions of the embodiments will be described below in a clearly and fully understandable way in connection with the drawings. It is obvious that the described embodiments are just a part but not all of the embodiments of the present invention. Based on the described embodiments of the present invention, those ordinarily skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the protective scope of the present invention as defined by the appended claims.

    [0019] An embodiment of the present disclosure provides an array substrate, which comprises a base substrate and a gate metal layer, a gate insulating layer, an active layer, a source-drain electrode metal layer, a passivation layer, and a common electrode layer which are sequentially formed on the base substrate, as well as a pixel electrode layer which is positioned between the active layer and the source-drain electrode metal layer or between the source-drain electrode metal layer and the passivation layer; the gate metal layer includes a gate electrode and a common electrode line.

    [0020] The pixel electrode layer or the source-drain electrode metal layer includes a connecting electrode, the connecting electrode is electrically connected with the common electrode line through a first via hole in the gate insulating layer, and the connecting electrode is electrically connected with a common electrode of the common electrode layer through a second via hole in the passivation layer.

    [0021] In the embodiment of the present disclosure, with the connecting electrode arranged on the pixel electrode layer or the source-drain electrode metal layer, the connecting electrode is electrically connected with the common electrode line through the first via hole, and the common electrode of the common electrode layer is electrically connected with the connecting electrode through the second via hole, so that an electrical connection between the common electrode and the common electrode line is established. Because the first via hole and the second via hole are electrically connected by the connecting electrode, hole depths and sizes of the first via hole and the second via hole are reduced in comparison with those of a continuous via hole directly penetrating through both the gate insulating layer and the passivation layer, the influence on the coated film layer in the subsequent fabricating process is reduced, and moires are prevented from being produced on the coated film layer.

    [0022] In this embodiment, the connecting electrode is in direct contact with the gate insulating layer and the passivation layer, and is electrically connected with the common electrode line and the common electrode respectively through the first via hole in the gate insulating layer and the second via hole in the passivation layer. For example, vertical projections of the first via hole and the second via hole on the base substrate are mutually staggered, the position of the first via hole corresponds to that of the common electrode line, the position of the second via hole corresponds to that of the common electrode, and the vertical projections of the first via hole and the second via hole on the base substrate fall within the scope of a vertical projection of the connecting electrode on the base substrate. Because the vertical projections of the first via hole and the second via hole are in different positions, they are not mutually influenced.

    [0023] For example, the connecting electrode is positioned in the pixel electrode layer, and the connecting electrode is mutually insulated from the pixel electrode in the pixel electrode layer. Or, the connecting electrode is positioned in the source-drain electrode metal layer, and the connecting electrode is mutually insulated from a source electrode, a drain electrode and a data line in the source-drain electrode metal layer.

    [0024] Hereinafter, the array substrate provided in an embodiment of the present disclosure will be illustrated in more detail with reference to the accompanying drawings.

    [0025] With reference to FIG. 2, an array substrate provided in an embodiment of the present disclosure comprises a base substrate 1, and a gate metal layer, a gate insulating layer 4, an active layer 5, a pixel electrode layer, a source-drain electrode metal layer, a passivation layer 10 and a common electrode layer which are sequentially formed on the base substrate 1; the gate metal layer includes a gate electrode 2 and a common electrode line 3; the pixel electrode layer includes a pixel electrode 6; the source-drain electrode metal layer includes a source electrode 7, a drain electrode 8 and a data line 9; the common electrode layer includes a common electrode 11; and the source electrode 7, the drain electrode 8, the gate electrode 2 and the active layer 5 form a Thin Film Transistor (TFT).

    [0026] The pixel electrode layer further includes a connecting electrode 12, the connecting electrode 12 is electrically connected with the common electrode line 3 through a first via hole 13 in the gate insulating layer, and the connecting electrode 12 is electrically connected with the common electrode 11 of the common electrode layer through a second via hole 14 in the passivation layer. In this embodiment, the connecting electrode 12 and the pixel electrode 6 are arranged in a same layer.

    [0027] According to FIG. 2, the connecting electrode 12 is in direct contact with the gate insulating layer 4 and the passivation layer 10 and is arranged outside a region of the active layer 5 and the pixel electrode 6.

    [0028] Vertical projections (not shown) of the first via hole 13 and the second via hole 14 on the base substrate 1 are mutually staggered, the position of the first via hole 13 corresponds to that of the common electrode line 3, the position of the second via hole corresponds to that of the common electrode 11, and the vertical projections (not shown) of the first via hole 13 and the second via hole 14 on the base substrate 1 fall within a scope of a vertical projection (not shown) of the connecting electrode 12 on the base substrate 1; although each of the above projections is not shown in this embodiment, FIG. 2 visually shows a positional relationship of the first via hole 13, the second via hole 14 and the connecting electrode 12. Because the vertical projections of the first via hole 13 and the second via hole 14 are in different positions, they are not mutually influenced.

    [0029] The connecting electrode 12 is mutually insulated from the pixel electrode 6.

    [0030] In FIG. 2, with the connecting electrode 12 arranged in the pixel electrode layer, the connecting electrode 12 is electrically connected with the common electrode line 3 through the first via hole 13, and the common electrode 11 of the common electrode layer is electrically connected with the connecting electrode 12 through the second via hole 14, so that an electrical connection of the common electrode 11 and the common electrode line 3 is established. Because the first via hole 13 and the second via hole 14 are electrically connected by the connecting electrode 12, hole depths and sizes of the first via hole 13 and the second via hole 14 are reduced in comparison with those of a continuous via hole (via hole 20a as shown in FIG. 1) directly penetrating through both the gate insulating layer 4 and the passivation layer 10, the influence on the coated film layer in the subsequent fabricating process is reduced, and moires are prevented from being produced on the coated film layer, so that the yield of array substrates is increased.

    [0031] With reference to FIG. 3, an array substrate provided in an embodiment of the present disclosure comprises a base substrate 1, and a gate metal layer, a gate insulating layer 4, an active layer 5, a pixel electrode layer, a source-drain electrode metal layer, a passivation layer 10 and a common electrode layer which are sequentially formed on the base substrate 1; the gate metal layer includes a gate electrode 2 and a common electrode line 3; the pixel electrode layer includes a pixel electrode 6; the source-drain electrode metal layer includes a source electrode 7, a drain electrode 8 and a data line 9; the common electrode layer includes a common electrode 11; and the source electrode 7, the drain electrode 8, the gate electrode 2 and the active layer 5 form a TFT.

    [0032] The pixel electrode layer further includes a connecting electrode 12, the connecting electrode 12 is electrically connected with the common electrode line 3 through a first via hole 13 in the gate insulating layer, and the connecting electrode 12 is electrically connected with the common electrode 11 of the common electrode layer through a second via hole 14 in the passivation layer. In this embodiment, the connecting electrode 12 and the source electrode 7, the drain electrode 8 and the data line 9 are arranged in a same layer.

    [0033] According to FIG. 3, the connecting electrode 12 is in direct contact with the gate insulating layer 4 and the passivation layer 10 and is arranged outside a region of the active layer 5 and the pixel electrode 6.

    [0034] Vertical projections (not shown) of the first via hole 13 and the second via hole 14 on the base substrate 1 are mutually staggered, the position of the first via hole 13 corresponds to that of the common electrode line 3, the position of the second via hole corresponds to that of the common electrode 11, the vertical projections (not shown) of the first via hole 13 and the second via hole 14 on the base substrate 1 fall within a scope of a vertical projection (not shown) of the connecting electrode 12 on the base substrate 1; although each of the above projections is not shown in the embodiment, FIG. 3 visually shows a positional relationship of the first via hole 13, the second via hole 14 and the connecting electrode 12. Because the vertical projections of the first via hole 13 and the second via hole 14 are in different positions, they are not mutually influenced.

    [0035] The connecting electrode 12 is mutually insulated from the source electrode 7, the drain electrode 8 and the data line 9.

    [0036] In FIG. 3, with the connecting electrode 12 arranged in the source-drain electrode metal layer, the connecting electrode 12 is electrically connected with the common electrode line 3 through the first via hole 13, and the common electrode 11 of the common electrode layer is electrically connected with the connecting electrode 12 through the second via hole 14, so that an electrical connection of the common electrode 11 and the common electrode line 3 is established. Because the first via hole 13 and the second via hole 14 are electrically connected by the connecting electrode 12, hole depths and sizes of the first via hole 13 and the second via hole 14 are reduced in comparison with those of a continuous via hole (via hole 20a as shown in FIG. 1) directly penetrating through both the gate insulating layer 4 and the passivation layer 10, the influence on the coated film layer in the subsequent fabricating process is reduced, and moires are prevented from being produced on the coated film layer, so that the yield of array substrates is increased.

    [0037] With reference to FIG. 4, an array substrate provided in an embodiment of the present disclosure comprises a base substrate 1, and a gate metal layer, a gate insulating layer 4, an active layer 5, a source-drain electrode metal layer, a pixel electrode layer, a passivation layer 10 and a common electrode layer which are sequentially formed on the base substrate 1; the gate metal layer includes a gate electrode 2 and a common electrode line 3; the source-drain electrode metal layer includes a source electrode 7, a drain electrode 8 and a data line 9; the pixel electrode layer includes a pixel electrode 6; the common electrode layer includes a common electrode 11; and the source electrode 7, the drain electrode 8, the gate electrode 2 and the active layer 5 form a TFT.

    [0038] The source-drain electrode metal layer further includes a connecting electrode 12, the connecting electrode 12 is electrically connected with the common electrode line 3 through a first via hole 13 in the gate insulating layer, and the connecting electrode 12 is electrically connected with the common electrode 11 of the common electrode layer through a second via hole 14 in the passivation layer. In this embodiment, the connecting electrode 12 and the source electrode 7, the drain electrode 8 and the data line 9 are arranged in a same layer.

    [0039] According to FIG. 4, the connecting electrode 12 is in direct contact with the gate insulating layer 4 and the passivation layer 10 and is arranged outside a region of the active layer 5 and the pixel electrode 6.

    [0040] Vertical projections (not shown) of the first via hole 13 and the second via hole 14 on the base substrate 1 are mutually staggered, the position of the first via hole 13 corresponds to that of the common electrode line 3, the position of the second via hole corresponds to that of the common electrode 11, the vertical projections (not shown) of the first via hole 13 and the second via hole 14 on the base substrate 1 fall within a scope of a vertical projection (not shown) of the connecting electrode 12 on the base substrate 1; although each of the above projections is not shown in the embodiment, FIG. 3 visually shows a positional relationship of the first via hole 13, the second via hole 14 and the connecting electrode 12. Because the vertical projections of the first via hole 13 and the second via hole 14 are in different positions, they are not mutually influenced.

    [0041] The connecting electrode 12 is mutually insulated from the source electrode 7, the drain electrode 8 and the data line 9.

    [0042] In FIG. 4, with the connecting electrode 12 arranged in the source-drain electrode metal layer, the connecting electrode 12 is electrically connected with the common electrode line 3 through the first via hole 13, and the common electrode 11 of the common electrode layer is electrically connected with the connecting electrode 12 through the second via hole 14, so that an electrical connection of the common electrode 11 and the common electrode line 3 is established. Because the first via hole 13 and the second via hole 14 are electrically connected by the connecting electrode 12, hole depths and sizes of the first via hole 13 and the second via hole 14 are reduced in comparison with those of a continuous via hole (via hole 20a as shown in FIG. 1) directly penetrating through both the gate insulating layer 4 and the passivation layer 10, the influence on the coated film layer in the subsequent fabricating process is reduced, and moires are prevented from being produced on the coated film layer, so that the yield of array substrates is increased.

    [0043] With reference to FIG. 5, an array substrate provided in an embodiment of the present disclosure comprises a base substrate 1, and a gate metal layer, a gate insulating layer 4, an active layer 5, a source-drain electrode metal layer, a pixel electrode layer, a passivation layer 10 and a common electrode layer which are sequentially formed on the base substrate 1; the gate metal layer includes a gate electrode 2 and a common electrode line 3, the source-drain electrode metal layer includes a source electrode 7, a drain electrode 8 and a data line 9; the pixel electrode layer includes a pixel electrode 6; the common electrode layer includes a common electrode 11; and the source electrode 7, the drain electrode 8, the gate electrode 2 and the active layer 5 form a thin film transistor (TFT).

    [0044] The pixel electrode layer further includes a connecting electrode 12, the connecting electrode 12 is electrically connected with the common electrode line 3 through a first via hole 13 in the gate insulating layer, and the connecting electrode 12 is electrically connected with the common electrode 11 of the common electrode layer through a second via hole 14 in the passivation layer. In this embodiment, the connecting electrode 12 and the pixel electrode 6 are arranged in a same layer.

    [0045] According to FIG. 5, the connecting electrode 12 is in direct contact with the gate insulating layer 4 and the passivation layer 10 and is arranged outside a region of the active layer 5 and the pixel electrode 6.

    [0046] Vertical projections (not shown) of the first via hole 13 and the second via hole 14 on the base substrate 1 are mutually staggered, the position of the first via hole 13 corresponds to that of the common electrode line 3, the position of the second via hole corresponds to that of the common electrode 11, the vertical projections (not shown) of the first via hole 13 and the second via hole 14 on the base substrate 1 fall within a scope of a vertical projection (not shown) of the connecting electrode 12 on the base substrate 1; although each of the above projections is not shown in the embodiment, FIG. 2 visually shows a positional relationship of the first via hole 13, the second via hole 14 and the connecting electrode 12. Because the vertical projections of the first via hole 13 and the second via hole 14 are in different positions, they are not mutually influenced.

    [0047] The connecting electrode 12 is mutually insulated from the pixel electrode 6.

    [0048] In FIG. 5, with the connecting electrode 12 arranged in the pixel electrode layer, the connecting electrode 12 is electrically connected with the common electrode line 3 through the first via hole 13, and the common electrode 11 of the common electrode layer is electrically connected with the connecting electrode 12 through the second via hole 14, so that an electrical connection of the common electrode 11 and the common electrode line 3 is established. Because the first via hole 13 and the second via hole 14 are electrically connected by the connecting electrode 12, hole depths and sizes of the first via hole 13 and the second via hole 14 are reduced in comparison with those of a continuous via hole (via hole 20a as shown in FIG. 1) directly penetrating through both the gate insulating layer 4 and the passivation layer 10, the influence on the coated film layer in the subsequent fabricating process is reduced, and moires are prevented from being produced on the coated film layer, so that the yield of array substrates is increased.

    [0049] An embodiment of the present disclosure further provides a display panel, comprising the array substrate provided by any of the above embodiments. Certainly, the display panel provided by the embodiment of the present disclosure may further comprise a color filter substrate, a liquid crystal, and other commonly used components, which will not be described in detail herein.

    [0050] In the display panel provided by the embodiment of the present disclosure, a pixel electrode layer or a source-drain electrode metal layer is provided with a connecting electrode, the connecting electrode is electrically connected with a common electrode line through a first via hole, and the common electrode is electrically connected with the connecting electrode through a second via hole, so that an electrical connection of the common electrode and the common electrode line is established. Because the first via hole and the second via hole are respectively arranged in different layers and are electrically connected through the connecting electrode, hole depths and sizes of the first via hole and the second via hole are reduced in comparison with those of a continuous via hole directly penetrating through both the gate insulating layer and the passivation layer, the influence on the coated film layer in the subsequent fabricating process is reduced, and moires are prevented from being produced on the coated film layer, so that the yield of array substrates is increased.

    [0051] An embodiment of the present disclosure further provides a display apparatus, comprising the display panel provided by the above embodiment. The display apparatus according to the embodiment of the present disclosure may further comprise a backlight module, a frame, a base and the like, which will not be described in detail herein.

    [0052] In the display apparatus according to the embodiment of the present disclosure, a connecting electrode is arranged between a gate insulating layer and a passivation layer of the array substrate, the connecting electrode is electrically connected with a common electrode line through a first via hole, and the common electrode is electrically connected with the connecting electrode through a second via hole, so that an electrical connection of the common electrode and the common electrode line is established. Because the first via hole and the second via hole are respectively arranged in different layers and are electrically connected through the connecting electrode, the hole depths and the sizes of the first via hole and the second via hole are reduced in comparison with those of a continuous via hole directly penetrating through both the gate insulating layer and the passivation layer, the influence on the coated film layer in the subsequent fabricating process is reduced, and moires are prevented from being produced on the coated film layer, so that the yield of array substrates is increased.

    [0053] An embodiment of the present disclosure further provides a fabricating method of an array substrate. The fabricating method comprises: sequentially forming a gate metal layer, a gate insulating layer, an active layer, a source-drain electrode metal layer, a passivation layer and a common electrode layer on a base substrate, and forming a pixel electrode layer between the active layer and the source-drain electrode metal layer or between the source-drain electrode metal layer and the passivation layer, the gate metal layer including a gate electrode and a common electrode line.

    [0054] Additionally, the fabricating method further comprises: forming a connecting electrode in the pixel electrode layer or the source-drain electrode metal layer, forming a first via hole in the gate insulating layer, and forming a second via hole in the passivation layer, the connecting electrode being electrically connected with the common electrode line through the first via hole in the gate insulating layer, and the connecting electrode being electrically connected with a common electrode of the common electrode layer through the second via hole in the passivation layer.

    [0055] For example, the fabricating method of the array substrate, provided by the embodiment of the present disclosure, comprises following steps:

    601: Sequentially forming a gate metal layer on the base substrate, the gate metal layer including a gate electrode and a common electrode line.

    602: Sequentially forming a gate insulating layer and an active layer on the gate metal layer.

    603: Forming a first via hole in a region of the gate insulating layer outside the active layer, a position of the first via hole corresponding to that of the common electrode line.

    604: Forming a pixel electrode layer including a pixel electrode and a connecting electrode on the base substrate on which the above-described steps have been completed, the connecting electrode being electrically connected with the common electrode line through the first via hole.
    The connecting electrode is mutually insulated from the pixel electrode.

    605: Forming a source-drain electrode metal layer including a source electrode, a drain electrode and a data line on the base substrate on which the above-described steps have been completed.

    606: Forming a passivation layer on the base substrate on which the above-described steps have been completed, the passivation layer including a second via hole corresponding to the connecting electrode.
    Vertical projections of the second via hole and the first via hole on the base substrate are mutually staggered and fall within a scope of a vertical projection of the connecting electrode on the base substrate.

    607: Forming a common electrode layer comprising a common electrode on the base substrate where the above-described steps have been formed, the common electrode being electrically connected with the connecting electrode through the second via hole.



    [0056] The structure of the array substrate fabricated by the steps 601-607 is shown in FIG. 2.

    [0057] In the fabricating method of the array substrate according to the embodiment of the present disclosure, with the connecting electrode arranged in the pixel electrode layer, the connecting electrode is electrically connected with the common electrode line through the first via hole, and the common electrode of the common electrode layer is electrically connected with the connecting electrode through the second via hole, so that an electrical connection of the common electrode and the common electrode line is established. Because the first via hole and the second via hole are electrically connected by the connecting electrode, hole depths and sizes of the first via hole and the second via hole are reduced in comparison with those of a continuous via hole directly penetrating through both the gate insulating layer and the passivation layer, the influence on the coated film layer in the subsequent fabricating process is reduced, and moires are prevented from being produced on the coated film layer, so that the yield of array substrates is increased; further, the connecting electrode and the pixel electrode are in a same layer and are synchronously formed, so that fabricating procedures and material consumption are reduced.

    [0058] For example, the fabricating method of the array substrate, provided by the embodiment of the present disclosure, comprises following steps:

    701: Sequentially forming a gate metal layer on the base substrate, the gate metal layer including a gate electrode and a common electrode line.

    702; Sequentially forming a gate insulating layer and an active layer on the gate metal layer.

    703: Forming a first via hole in a region of the gate insulating layer outside the active layer, a position of the first via hole corresponding to that of the common electrode line.

    704: Forming a source-drain electrode metal layer including a source electrode, a drain electrode, a data line and a connecting electrode on the base substrate on which the above-described steps have been completed, the connecting electrode being electrically connected with the common electrode line through the first via hole.
    The connecting electrode is mutually insulated from the source electrode, the drain electrode and the data line.

    705: Forming a pixel electrode layer including a pixel electrode on the base substrate on which the above-described steps have been completed.

    706: Forming a passivation layer on the base substrate on which the above-described steps have been completed, the passivation layer including a second via hole corresponding to the connecting electrode.

    Vertical projections of the second via hole and the first via hole on the base substrate are mutually staggered, and fall within a scope of a vertical projection of the connecting electrode on the base substrate.

    707: Forming a common electrode layer including a common electrode on the base substrate on which the above-described steps have been completed, the common electrode being electrically connected with the connecting electrode through the second via hole.



    [0059] In the fabricating method of the array substrate according to the embodiment of the present disclosure, with the connecting electrode arranged in the source-drain electrode metal layer, the connecting electrode is electrically connected with the common electrode line through the first via hole, and the common electrode of the common electrode layer is electrically connected with the connecting electrode through the second via hole, so that an electrical connection of the common electrode and the common electrode line is established. Because the first via hole and the second via hole are electrically connected by the connecting electrode, the hole depths and the sizes of the first via hole and the second via hole are reduced in comparison with those of a continuous via hole directly penetrating through both the gate insulating layer and the passivation layer, the influence on the coated film layer in the subsequent fabricating process is reduced, and moires are prevented from being produced on the coated film layer, so that the yield of array substrates is increased; further, the connecting electrode, and the source electrode, the drain electrode and the data line are in a same layer and are synchronously formed, so that fabricating procedures and material consumption are reduced.

    [0060] The structure of the array substrate fabricated by the steps 701-707 is shown in FIG. 4.

    [0061] For example, the fabricating method of the array substrate, provided by the embodiment of the present disclosure, comprises following steps:

    801: Sequentially forming a gate metal layer on the base substrate, the gate metal layer including a gate electrode and a common electrode line.

    802: Forming a gate insulating layer, an active layer, and a pixel electrode layer including a pixel electrode on the gate metal layer.

    803: Forming a first via hole in a region of the gate insulating layer outside the active layer and the pixel electrode, a position of the first via hole corresponding to that of the common electrode line.

    804: Forming a source-drain electrode metal layer including a source electrode, a drain electrode, a data line and a connecting electrode on the base substrate where the above-described steps have been formed, the connecting electrode being electrically connected with the common electrode line through the first via hole.
    The connecting electrode is mutually insulated from the source electrode, the drain electrode and the data line.

    805: Forming a passivation layer on the base substrate on which the above-described steps have been completed, the passivation layer including a second via hole corresponding to the connecting electrode.
    Vertical projections of the second via hole and the first via hole on the base substrate are mutually staggered, and fall within a scope of a vertical projection of the connecting electrode on the base substrate.

    806: Forming a common electrode layer including a common electrode on the base substrate on which the above-described steps have been completed, the common electrode being electrically connected with the connecting electrode through the second via hole.



    [0062] In the fabricating method of the array substrate according to the embodiment of the present disclosure, with the connecting electrode arranged in the source-drain electrode metal layer, the connecting electrode is electrically connected with the common electrode line through the first via hole, and the common electrode of the common electrode layer is electrically connected with the connecting electrode through the second via hole, so that an electrical connection of the common electrode and the common electrode line is established. Because the first via hole and the second via hole are electrically connected by the connecting electrode, the hole depths and the sizes of the first via hole and the second via hole are reduced in comparison with those of a continuous via hole directly penetrating through both the gate insulating layer and the passivation layer, the influence on the coated film layer in the subsequent fabricating process is reduced, and moires are prevented from being produced on the coated film layer, so that the yield of array substrates is increased; further, the connecting electrode and the source electrode, the drain electrode and the data line are in a same layer and are synchronously formed, so that fabricating procedures and material consumption are reduced.

    [0063] The structure of the array substrate fabricated by the steps 801-806 is shown in FIG. 3.

    [0064] For example, the fabricating method of the array substrate, provided by the embodiment of the present disclosure, comprises following steps:

    901: Sequentially forming a gate metal layer on the base substrate, the gate metal layer including a gate electrode and a common electrode line.

    902: Forming a gate insulating layer, an active layer, and a source-drain electrode metal layer including a source electrode, a drain electrode and a data line on the gate metal layer.

    903: Forming a first via hole in a region of the gate insulating layer outside the active layer and the data line.
    The position of the first via hole corresponds to that of the common electrode line.

    904: Forming a pixel electrode layer including a pixel electrode and a connecting electrode on the base substrate on which the above-described steps have been completed, the connecting electrode being electrically connected with the common electrode line through the first via hole.
    The connecting electrode is mutually insulated from the pixel electrode.

    905: Forming a passivation layer on the base substrate on which the above-described steps have been completed, the passivation layer including a second via hole corresponding to the connecting electrode.
    Vertical projections of the second via hole and the first via hole on the base substrate are mutually staggered, and fall within a scope of a vertical projection of the connecting electrode on the base substrate.

    906: Forming a common electrode layer including a common electrode on the base substrate on which the above-described steps have been completed, the common electrode being electrically connected with the connecting electrode through the second via hole.



    [0065] In the fabricating method of the array substrate according to the embodiment of the present disclosure, by the connecting electrode arranged in the pixel electrode layer, the connecting electrode is electrically connected with the common electrode line through the first via hole, and the common electrode of the common electrode layer is electrically connected with the connecting electrode through the second via hole, so that an electrical connection of the common electrode and the common electrode line is established. Because the first via hole and the second via hole are electrically connected by the connecting electrode, the hole depths and the sizes of the first via hole and the second via hole are reduced in comparison with those of a continuous via hole directly penetrating through both the gate insulating layer and the passivation layer, the influence on the coated film layer in the subsequent fabricating process is reduced, and moires are prevented from being produced on the coated film layer, so that the yield of array substrates is increased; further, the connecting electrode and the pixel electrode are in a same layer and are synchronously formed, so that fabricating procedures and material consumption are reduced.

    [0066] The structure of the array substrate fabricated by the steps 901-906 is shown in FIG. 5.

    [0067] It should be noted that, in the fabricating methods of the array substrate according to the embodiments of the present disclosure, the gate insulating layer and the first via hole therein and the passivation layer and the second via hole therein may be formed by processes such as coating and etching, the gate metal layer and the source-drain electrode metal layer may be formed by processes such as sputtering, etching and the like, and the active layer, the pixel electrode layer and the common electrode layer may be formed by processes such as coating, etching and the like, which will not be described in detail herein.

    [0068] The foregoing embodiments merely are exemplary embodiments of the present invention, and not intended to define the protective scope of the present invention, and the protective scope of the present invention is determined by the appended claims.


    Claims

    1. An array substrate, comprising a base substrate (1) and a gate metal layer, a gate insulating layer (4), an active layer (5), a source-drain electrode metal layer, a passivation layer (10) and a common electrode layer which are sequentially formed on the base substrate, as well as a pixel electrode layer which is positioned either between the active layer (5) and the source-drain electrode metal layer, or between the source-drain electrode metal layer and the passivation layer (4); the gate metal layer including a gate electrode (2) and a common electrode line (3); wherein
    either the pixel electrode layer, or the source-drain electrode metal layer comprises a connecting electrode (12), the connecting electrode (12) is electrically connected with the common electrode line (3) through a first via hole (13) in the gate insulating layer (4), and the connecting electrode (12) is electrically connected with a common electrode (11) of the common electrode layer through a second via hole (14) in the passivation layer (10);
    characterized in that vertical projections of the first via hole (13) and the second via hole (14) on the base substrate (1) are mutually staggered, a position of the first via hole (13) corresponds to that of the common electrode line (3), a position of the second via hole (14) corresponds to that of the common electrode (11), and the vertical projections of the first via hole (13) and the second via hole (14) on the base substrate (1) fall within a scope of a vertical projection of the connecting electrode (12) on the base substrate (1).
     
    2. The array substrate according to claim 1, wherein the connecting electrode (12) is in direct contact with the gate insulating layer (4) and the passivation layer (10).
     
    3. The array substrate according to any one of claims 1 to 2, wherein the connecting electrode (12) is positioned in the pixel electrode layer, and the connecting electrode (12) is mutually insulated from a pixel electrode (6) of the pixel electrode layer.
     
    4. The array substrate according to any one of claims 1 to 2, wherein the connecting electrode (12) is positioned in the source-drain electrode metal layer, and the connecting electrode (12) is mutually insulated from a source electrode (7), a drain electrode (8) and a data line (9) in the source-drain electrode metal layer.
     
    5. A display panel, comprising the array substrate according to any one of claims 1 to 4.
     
    6. A display apparatus, comprising the display panel according to claim 5.
     
    7. A fabricating method of an array substrate, comprising: sequentially forming a gate metal layer, a gate insulating layer (4), an active layer (5), a source-drain electrode metal layer, a passivation layer (10) and a common electrode layer on a base substrate (1), and forming a pixel electrode layer either between the active layer (5) and the source-drain electrode metal layer, or between the source-drain electrode metal layer and the passivation layer (10), the gate metal layer comprising a gate electrode (2) and a common electrode line (3), wherein
    the fabricating method further comprises: forming a connecting electrode (12) either in the pixel electrode layer, or the source-drain electrode metal layer, forming a first via hole (13) in the gate insulating layer (4), and forming a second via hole (13) in the passivation layer (10), the connecting electrode (12) being electrically connected with the common electrode line (3) through the first via hole (13) in the gate insulating layer (4), and the connecting electrode (12) being electrically connected with a common electrode (11) of the common electrode layer through the second via hole (14) in the passivation layer (10);
    characterized in that vertical projections of the first via hole (13) and the second via hole (14) on the base substrate (1) are mutually staggered, and the vertical projections of the first via hole (13) and the second via hole (14) on the base substrate (1) fall within a scope of a vertical projection of the connecting electrode (12) on the base substrate (1).
     
    8. The fabricating method of the array substrate according to claim 7, comprising:

    sequentially forming the gate metal layer on the base substrate (1), the gate metal layer comprising a gate electrode (2) and the common electrode line (3);

    sequentially forming the gate insulating layer (4) and the active layer (5) on the gate metal layer;

    forming the first via hole (13) in a region of the gate insulating layer (4) outside the active layer (5), a position of the first via hole (13) corresponding to that of the common electrode line (3);

    forming the pixel electrode layer comprising a pixel electrode (6) and the connecting electrode (12) on the base substrate (1), the connecting electrode (12) being electrically connected with the common electrode line (3) through the first via hole (13);

    forming the source-drain electrode metal layer comprising a source electrode (7), a drain electrode (8) and a data line (9) on the base substrate (1);

    forming the passivation layer (10) on the base substrate (1), the passivation layer (10) comprising the second via hole (14) corresponding to the connecting electrode (12); and

    forming the common electrode layer comprising the common electrode (11) on the base substrate, the common electrode (11) being electrically connected with the connecting electrode (12) through the second via hole (14).


     
    9. The fabricating method of the array substrate according to claim 7, comprising:

    sequentially forming the gate metal layer on the base substrate (1), the gate metal layer comprising a gate electrode (2) and the common electrode line (3);

    sequentially forming the gate insulating layer (4) and the active layer (5) on the gate metal layer;

    forming the first via hole (13) in a region of the gate insulating layer (4) outside the active layer (5), a position of the first via hole (13) corresponding to that of the common electrode line (3);

    forming the source-drain electrode metal layer comprising a source electrode (7), a drain electrode (8), a data line (9) and the connecting electrode (12) on the base substrate (1), the connecting electrode (12) being electrically connected with the common electrode line (3) through the first via hole (13);

    forming the pixel electrode layer comprising a pixel electrode (6) on the base substrate (1);

    forming the passivation layer (10) on the base substrate (1), the passivation layer (10) comprising the second via hole (14) corresponding to the connecting electrode (12); and

    forming the common electrode layer comprising the common electrode (11) on the base substrate (1), the common electrode (11) being electrically connected with the connecting electrode (12) through the second via hole (14).


     
    10. The fabricating method of the array substrate according to claim 7, comprising:

    sequentially forming the gate metal layer on the base substrate (1), the gate metal layer comprising a gate electrode (2) and the common electrode line (3);

    forming the gate insulating layer (4), the active layer (5), and the pixel electrode layer comprising a pixel electrode (6) on the gate metal layer;

    forming the first via hole (13) in a region of the gate insulating layer (4) outside the active layer (5) and the pixel electrode (6), a position of the first via hole (13) corresponding to that of the common electrode line (3);

    forming the source-drain electrode metal layer comprising a source electrode (7), a drain electrode (8), a data line (9) and the connecting electrode (12) on the base substrate (1), the connecting electrode (12) being electrically connected with the common electrode line (3) through the first via hole (13);

    forming the passivation layer (10) on the base substrate (1), the passivation layer (10) comprising the second via hole (14) corresponding to the connecting electrode (12); and

    forming the common electrode layer comprising the common electrode (11) on the base substrate (1), the common electrode (11) being electrically connected with the connecting electrode (12) through the second via hole (14).


     
    11. The fabricating method of the array substrate according to claim 7, comprising:

    sequentially forming the gate metal layer on the base substrate (1), the gate metal layer comprising a gate electrode (2) and the common electrode line (3);

    forming the gate insulating layer (4), the active layer (5), and the source-drain electrode metal layer comprising a source electrode (7), a drain electrode (8) and a data line (9) on the gate metal layer;

    forming the first via hole (13) in a region of the gate insulating layer (4) outside the active layer (5) and the data line (9), a position of the first via hole (13) corresponding to that of the common electrode line (3);

    forming the pixel electrode layer comprising a pixel electrode (6) and the connecting electrode (12) on the base substrate (1), the connecting electrode (12) being electrically connected with the common electrode line (3) through the first via hole (13);

    forming the passivation layer on the base substrate (1), the passivation layer comprising the second via hole (14) corresponding to the connecting electrode (12); and

    forming the common electrode layer comprising the common electrode (11) on the base substrate (1), the common electrode (11) being electrically connected with the connecting electrode (12) through the second via hole (14).


     
    12. The fabricating method of the array substrate according to claim 8 or 11, wherein the connecting electrode (12) is mutually insulated from the pixel electrode (6).
     
    13. The fabricating method of the array substrate according to claim 9 or 10, wherein the connecting electrode (12) is mutually insulated from the source electrode (7), the drain electrode (8) and the data line (9).
     


    Ansprüche

    1. Array-Substrat, umfassend ein Basissubstrat (1) und eine Gate-Metallschicht, eine Gate-Isolierschicht (4), eine aktive Schicht (5), eine Source-Drain-Elektroden-Metallschicht, eine Passivierungsschicht (10) und eine gemeinsame Elektrode-Schicht, die sequentiell auf dem Basissubstrat gebildet sind, sowie eine Pixelelektrodenschicht, die entweder zwischen der aktiven Schicht (5) und der Source-Drain-Elektroden-Metallschicht oder zwischen der Source-Drain-Elektroden-Metallschicht und der Passivierungsschicht (4) ist; wobei die Gate-Metallschicht eine Gate-Elektrode (2) und eine gemeinsame Elektrode-Leitung (3) einschließt; wobei

    entweder die Pixelelektrodenschicht oder die Source-Drain-Elektroden-Metallschicht eine Verbindungselektrode (12) umfasst, wobei die Verbindungselektrode (12) durch eine erste Durchgangsöffnung (13) in der Gate-Isolierschicht (4) mit der gemeinsame Elektrode-Leitung (3) elektrisch verbunden ist, und wobei die Verbindungselektrode (12) mit einer gemeinsamen Elektrode (11) der gemeinsame Elektrode-Schicht durch eine zweite Durchgangsöffnung (14) in der Passivierungsschicht (10) elektrisch verbunden ist;

    dadurch gekennzeichnet, dass vertikale Projektionen der ersten Durchgangsöffnung (13) und der zweiten Durchgangsöffnung (14) auf das Basissubstrat (1) gegenseitig versetzt sind, wobei eine Position der ersten Durchgangsöffnung (13) mit der von der gemeinsame Elektrode-Leitung (3) korrespondiert, wobei eine Position der zweiten Durchgangsöffnung (14) mit der von der gemeinsamen Elektrode (11) korrespondiert, und wobei die vertikalen Projektionen der ersten Durchgangsöffnung (13) und der zweiten Durchgangsöffnung (14) auf das Basissubstrat (1) in einen Bereich einer vertikalen Projektion der Verbindungselektrode (12) auf das Basissubstrat (1) fallen.


     
    2. Array-Substrat gemäß Anspruch 1, wobei die Verbindungselektrode (12) in direktem Kontakt mit der Gate-Isolierschicht (4) und der Passivierungsschicht (10) ist.
     
    3. Array-Substrat gemäß einem der Ansprüche 1 bis 2, wobei die Verbindungselektrode (12) in der Pixelelektrodenschicht positioniert ist und wobei die Verbindungselektrode (12) gegenseitig isoliert ist von einer Pixelelektrode (6) der Pixelelektrodenschicht.
     
    4. Array-Substrat gemäß einem der Ansprüche 1 bis 2, wobei die Verbindungselektrode (12) in der Source-Drain-Elektroden-Metallschicht positioniert ist, und wobei die Verbindungselektrode (12) gegenseitig isoliert von einer Source-Elektrode (7), einer Drain-Elektrode (8) und einer Datenleitung (9) in der Source-Drain-Elektroden-Metallschicht ist.
     
    5. Anzeigepanel, umfassend das Array-Substrat gemäß einem der Ansprüche 1 bis 4.
     
    6. Anzeigevorrichtung, umfassend das Anzeigepanel gemäß Anspruch 5.
     
    7. Herstellungsverfahren eines Array-Substrats, umfassend: sequentielles Bilden einer Gate-Metallschicht, einer Gate-Isolierschicht (4), einer aktiven Schicht (5), einer Source-Drain-Elektroden-Metallschicht, einer Passivierungsschicht (10) und einer gemeinsame Elektrode-Schicht auf einem Basissubstrat (1), und Bilden einer Pixelelektrodenschicht entweder zwischen der aktiven Schicht (5) und der Source-Drain-Elektroden-Metallschicht oder zwischen der Source-Drain-Elektroden-Metallschicht und der Passivierungsschicht (10), wobei die Gate-Metallschicht eine Gate-Elektrode (2) und eine gemeinsame Elektrode-Leitung (3) umfasst, wobei

    das Herstellungsverfahren außerdem umfasst: Bilden einer Verbindungselektrode (12) entweder in der Pixelelektrodenschicht oder der Source-Drain-Elektroden-Metallschicht, Bilden einer ersten Durchgangsöffnung (13) in der Gate-Isolierschicht (4) und Bilden einer zweiten Durchgangsöffnung (13) in der Passivierungsschicht (10), wobei die Verbindungselektrode (12) mit der gemeinsame Elektrode-Leitung (3) durch die erste Durchgangsöffnung (13) in der Gate-Isolierschicht (4) elektrisch verbunden wird, und wobei die Verbindungselektrode (12) mit einer gemeinsamen Elektrode (11) der gemeinsame Elektrode-Schicht durch die zweite Durchgangsöffnung (14) in der Passivierungsschicht (10) elektrisch verbunden wird;

    dadurch gekennzeichnet, dass vertikale Projektionen der ersten Durchgangsöffnung (13) und der zweiten Durchgangsöffnung (14) auf das Basissubstrat (1) gegenseitig versetzt sind und dass vertikale Projektionen der ersten Durchgangsöffnung (13) und der zweiten Durchgangsöffnung (14) auf das Basissubstrat (1) in einen Bereich einer vertikalen Projektion der Verbindungselektrode (12) auf das Basissubstrat (1) fallen.


     
    8. Herstellungsverfahren des Array-Substrats gemäß Anspruch 7, umfassend: sequentielles Bilden der Gate-Metallschicht auf dem Basissubstrat (1), wobei die Gate-Metallschicht eine Gate-Elektrode (2) und die gemeinsame Elektrode-Leitung (3) umfasst;

    sequentielles Bilden der Gate-Isolierschicht (4) und der aktiven Schicht (5) auf der Gate-Metallschicht;

    Bilden der ersten Durchgangsöffnung (13) in einer Region der Gate-Isolierschicht (4) außerhalb der aktiven Schicht (5), wobei eine Position der ersten Durchgangsöffnung (13) zu der der gemeinsame Elektrode-Leitung (3) korrespondiert;

    Bilden der Pixel-Elektrodenschicht, umfassend eine Pixelelektrode (6), und der Verbindungselektrode (12) auf dem Basissubstrat (1), wobei die Verbindungselektrode (12) durch die erste Durchgangsöffnung (13) mit der gemeinsame Elektrode-Leitung (3) elektrisch verbunden wird;

    Bilden der Source-Drain-Elektroden-Metallschicht, umfassend eine Source-Elektrode (7), eine Drain-Elektrode (8) und eine Datenleitung (9), auf dem Basissubstrat (1);

    Bilden der Passivierungsschicht (10) auf dem Basissubstrat (1), wobei die Passivierungsschicht (10) die zweite Durchgangsöffnung (14) korrespondierend zu der Verbindungselektrode (12) umfasst;

    Bilden der gemeinsame Elektrode-Schicht, umfassend die gemeinsame Elektrode (11), auf dem Basissubstrat, wobei die gemeinsame Elektrode (11) durch die zweite Durchgangsöffnung (14) mit der Verbindungselektrode (12) elektrisch verbunden wird.


     
    9. Herstellungsverfahren des Array-Substrats gemäß Anspruch 7, umfassend:

    sequentielles Bilden der Gate-Metallschicht auf dem Basissubstrat (1), wobei die Gate-Metallschicht eine Gate-Elektrode (2) und die gemeinsame Elektrode-Leitung (3) umfasst;

    sequentielles Bilden der Gate-Isolierschicht (4) und der aktiven Schicht (5) auf der Gate-Metallschicht;

    Bilden der ersten Durchgangsöffnung (13) in einer Region der Gate-Isolierschicht (4) außerhalb der aktiven Schicht (5), wobei eine Position der ersten Durchgangsöffnung (13) mit der der gemeinsame Elektrode-Leitung (3) korrespondiert;

    Bilden der Source-Drain-Elektroden-Metallschicht, umfassend eine Source-Elektrode (7), eine Drain-Elektrode (8), eine Datenleitung (9) und die Verbindungselektrode (12) auf dem Basissubstrat (1), wobei die Verbindungselektrode (12) durch die erste Durchgangsöffnung (13) mit der gemeinsame Elektrode-Leitung (3) elektrisch verbunden wird;

    Bilden der Pixelelektrodenschicht, umfassend eine Pixelelektrode (6), auf dem Basissubstrat (1);

    Bilden der Passivierungsschicht (10) auf dem Basissubstrat (1), wobei die Passivierungsschicht (10) die zweite Durchgangsöffnung (14) korrespondierend zu der Verbindungselektrode (12) umfasst; und

    Bilden der gemeinsame Elektrode-Schicht, umfassend die gemeinsame Elektrode (11), auf dem Basissubstrat (1), wobei die gemeinsame Elektrode (11) durch die zweite Durchgangsöffnung (14) mit der Verbindungselektrode (12) elektrisch verbunden wird.


     
    10. Herstellungsverfahren des Array-Substrats gemäß Anspruch 7, umfassend:

    sequentielles Bilden der Gate-Metallschicht auf dem Basissubstrat (1), wobei die Gate-Metallschicht eine Gate-Elektrode (2) und die gemeinsame Elektrode-Leitung (3) umfasst;

    Bilden der Gate-Isolierschicht (4), der aktiven Schicht (5) und der Pixelelektrodenschicht, umfassend eine Pixelelektrode (6), auf der Gate-Metallschicht;

    Bilden der ersten Durchgangsöffnung (13) in einer Region der Gate-Isolierschicht (4) außerhalb der aktiven Schicht (5) und der Pixelelektrode (6), wobei eine Position der ersten Durchgangsöffnung (13) mit der der gemeinsame-Elektrode-Leitung (3) korrespondiert;

    Bilden der Source-Drain-Elektroden-Metallschicht, umfassend eine Source-Elektrode (7), eine Drain-Elektrode (8), eine Datenleitung (9) und die Verbindungselektrode (12) auf dem Basissubstrat (1), wobei die Verbindungselektrode (12) durch die erste Durchgangsöffnung (13) mit der gemeinsame Elektrode-Leitung (3) elektrisch verbunden wird;

    Bilden der Passivierungsschicht (10) auf dem Basissubstrat (1), wobei die Passivierungsschicht (10) die zweite Durchgangsöffnung (14) korrespondierend zu der Verbindungselektrode (12) umfasst; und

    Bilden der gemeinsame Elektrode-Schicht, umfassend die gemeinsame Elektrode (11), auf dem Basissubstrat (19, wobei die gemeinsame Elektrode (11) durch die zweite Durchgangsöffnung (14) mit der Verbindungselektrode (12) elektrisch verbunden wird.


     
    11. Herstellungsverfahren des Array-Substrats gemäß Anspruch 7, umfassend:

    sequentielles Bilden der Gate-Metallschicht auf dem Basissubstrat (1), wobei die Gate-Metallschicht eine Gate-Elektrode (2) und die gemeinsame Elektrode-Leitung (3) umfasst;

    Bilden der Gate-Isolierschicht (4), der aktiven Schicht (5) und der Source-Drain-Elektroden-Metallschicht, umfassend eine Source-Elektrode (7), eine Drain-Elektrode (8) und eine Datenleitung (9) auf der Gate-Metallschicht;

    Bilden der ersten Durchgangsöffnung (13) in einer Region der Gate-Isolierschicht (4) außerhalb der aktiven Schicht (5) und der Datenleitung (9), wobei eine Position der ersten Durchgangsöffnung (13) zu der der gemeinsame Elektrode-Leitung (3) korrespondiert;

    Bilden der Pixel-Elektrodenschicht, umfassend eine Pixel-Elektrode (6) und die Verbindungselektrode (12) auf dem Basissubstrat (1), wobei die Verbindungselektrode (12) durch die erste Durchgangsöffnung (13) mit der gemeinsame Elektrode-Leitung (3) elektrisch verbunden wird;

    Bilden der Passivierungsschicht auf dem Basissubstrat (1), wobei die Passivierungsschicht die zweite Durchgangsöffnung (14) korrespondierend zu der Verbindungselektrode (12) umfasst; und

    Bilden der gemeinsame Elektrode-Schicht, umfassend die gemeinsame Elektrode (11), auf dem Basissubstrat (1), wobei die gemeinsame Elektrode (11) durch die zweite Durchgangsöffnung (14) mit der Verbindungselektrode (12) elektrisch verbunden wird.


     
    12. Herstellungsverfahren des Array-Substrats gemäß Anspruch 8 oder 11, wobei die Verbindungselektrode (12) gegenseitig von der Pixelelektrode (6) isoliert ist.
     
    13. Herstellungsverfahren des Array-Substrats gemäß Anspruch 9 oder 10, wobei die Verbindungselektrode (12) gegenseitig von der Source-Elektrode (7), der Drain-Elektrode (8) und der Datenleitung (9) isoliert ist.
     


    Revendications

    1. un substrat de réseau, comprenant un substrat de base (1) et une couche métallique de grille, une couche d'isolation de grille (4), une couche active (5), une couche métallique d'électrodes source-drain, une couche de passivation (10) et une couche d'électrode commune qui sont formées séquentiellement sur le substrat de base, ainsi qu'une couche d'électrode de pixel qui est positionnée soit entre la couche active (5) et la couche métallique d'électrodes source-drain, soit entre la couche métallique d'électrodes source-drain et la couche de passivation (4) ; la couche métallique de grille comprenant une électrode de grille (2) et une ligne d'électrode commune (3) ; dans lequel soit la couche d'électrode de pixel, soit la couche métallique d'électrodes source-drain comprend une électrode de connexion (12), l'électrode de connexion (12) est reliée électriquement à la ligne d'électrode commune (3) à travers un premier trou d'interconnexion (13) dans la couche d'isolation de grille (4), et l'électrode de connexion (12) est reliée électriquement à une électrode commune (11) de la couche d'électrode commune à travers un deuxième trou d'interconnexion (14) dans la couche de passivation (10) ;
    caractérisé en ce que des projections verticales du premier trou d'interconnexion (13) et du deuxième trou d'interconnexion (14) sur le substrat de base (1) sont mutuellement décalées, une position du premier trou d'interconnexion (13) correspond à celle de la ligne d'électrode commune (3), une position du deuxième trou d'interconnexion (14) correspond à celle de l'électrode commune (11), et les projections verticales du premier trou d'interconnexion (13) et du deuxième trou d'interconnexion (14) sur le substrat de base (1) tombent dans l'étendue d'une projection verticale de l'électrode de connexion (12) sur le substrat de base (1).
     
    2. Le substrat de réseau selon la revendication 1, dans lequel l'électrode de connexion (12) est en contact direct avec la couche d'isolation de grille (4) et la couche de passivation (10).
     
    3. Le substrat de réseau selon l'une quelconque des revendications 1 à 2, dans lequel l'électrode de connexion (12) est positionnée dans la couche d'électrode de pixel, et l'électrode de connexion (12) est mutuellement isolée d'une électrode de pixel (6) de la couche d'électrode de pixel.
     
    4. Le substrat de réseau selon l'une quelconque des revendications 1 à 2, dans lequel l'électrode de connexion (12) est positionnée dans la couche métallique d'électrodes source-drain, et l'électrode de connexion (12) est mutuellement isolée d'une électrode de source (7), d'une électrode de drain (8) et d'une ligne de données (9) dans la couche métallique d'électrodes source-drain.
     
    5. Un panneau d'affichage, comprenant le substrat de réseau selon l'une quelconque des revendications 1 à 4.
     
    6. Un appareil d'affichage, comprenant le panneau d'affichage selon la revendication 5.
     
    7. Un procédé de fabrication d'un substrat de réseau, comprenant : la formation séquentielle d'une couche métallique de grille, d'une couche d'isolation de grille (4), d'une couche active (5), d'une couche métallique d'électrodes source-drain, d'une couche de passivation (10) et d'une couche d'électrode commune sur un substrat de base (1), et la formation d'une couche d'électrode de pixel soit entre la couche active (5) et la couche métallique d'électrodes source-drain, soit entre la couche métallique d'électrodes source-drain et la couche de passivation (10), la couche métallique de grille comprenant une électrode de grille (2) et une ligne d'électrode commune (3), dans lequel

    le procédé de fabrication comprend en outre : la formation d'une électrode de connexion (12) soit dans la couche d'électrode de pixel, soit dans la couche métallique d'électrodes source-drain, la formation d'un premier trou d'interconnexion (13) dans la couche d'isolation de grille (4), et la formation d'un deuxième trou d'interconnexion (13) dans la couche de passivation (10), l'électrode de connexion (12) étant reliée électriquement à la ligne d'électrode commune (3) à travers le premier trou d'interconnexion (13) dans la couche d'isolation de grille (4), et l'électrode de connexion (12) étant reliée électriquement à une électrode commune (11) de la couche d'électrode commune à travers le deuxième trou d'interconnexion (14) dans la couche de passivation (10) ;

    caractérisé en ce que des projections verticales du premier trou d'interconnexion (13) et du deuxième trou d'interconnexion (14) sur le substrat de base (1) sont mutuellement décalées, et les projections verticales du premier trou d'interconnexion (13) et du deuxième trou d'interconnexion (14) sur le substrat de base (1) tombent dans l'étendue d'une projection verticale de l'électrode de connexion (12) sur le substrat de base (1).


     
    8. Le procédé de fabrication du substrat de réseau selon la revendication 7, comprenant :

    la formation séquentielle de la couche métallique de grille sur le substrat de base (1), la couche métallique de grille comprenant une électrode de grille (2) et la ligne d'électrode commune (3) ;

    la formation séquentielle de la couche d'isolation de grille (4) et de la couche active (5) sur la couche métallique de grille ;

    la formation du premier trou d'interconnexion (13) dans une région de la couche d'isolation de grille (4) à l'extérieur de la couche active (5), une position du premier trou d'interconnexion (13) correspondant à celle de la ligne d'électrode commune (3) ;

    la formation de la couche d'électrode de pixel comprenant une électrode de pixel (6) et l'électrode de connexion (12) sur le substrat de base (1), l'électrode de connexion (12) étant reliée électriquement à la ligne d'électrode commune (3) à travers le premier trou d'interconnexion (13) ;

    la formation de la couche métallique d'électrodes source-drain comprenant une électrode de source (7), une électrode de drain (8) et une ligne de données (9) sur le substrat de base (1) ;

    la formation de la couche de passivation (10) sur le substrat de base (1), la couche de passivation (10) comprenant le deuxième trou d'interconnexion (14) correspondant à l'électrode de connexion (12) ; et

    la formation de la couche d'électrode commune comprenant l'électrode commune (11) sur le substrat de base, l'électrode commune (11) étant reliée électriquement à l'électrode de connexion (12) à travers le deuxième trou d'interconnexion (14).


     
    9. Le procédé de fabrication du substrat de réseau selon la revendication 7, comprenant :

    la formation séquentielle de la couche métallique de grille sur le substrat de base (1), la couche métallique de grille comprenant une électrode de grille (2) et la ligne d'électrode commune (3) ;

    la formation séquentielle de la couche d'isolation de grille (4) et de la couche active (5) sur la couche métallique de grille ;

    la formation du premier trou d'interconnexion (13) dans une région de la couche d'isolation de grille (4) à l'extérieur de la couche active (5), une position du premier trou d'interconnexion (13) correspondant à celle de la ligne d'électrode commune (3) ;

    la formation de la couche métallique d'électrodes source-drain comprenant une électrode de source (7), une électrode de drain (8), une ligne de données (9) et l'électrode de connexion (12) sur le substrat de base (1), l'électrode de connexion (12) étant reliée électriquement à la ligne d'électrode commune (3) à travers le premier trou d'interconnexion (13) ;

    la formation de la couche d'électrode de pixel comprenant une électrode de pixel (6) sur le substrat de base (1) ;

    la formation de la couche de passivation (10) sur le substrat de base (1), la couche de passivation (10) comprenant le deuxième trou d'interconnexion (14) correspondant à l'électrode de connexion (12) ; et

    la formation de la couche d'électrode commune comprenant l'électrode commune (11) sur le substrat de base (1), l'électrode commune (11) étant reliée électriquement à l'électrode de connexion (12) à travers le deuxième trou d'interconnexion (14).


     
    10. Le procédé de fabrication du substrat de réseau selon la revendication 7, comprenant :

    la formation séquentielle de la couche métallique de grille sur le substrat de base (1), la couche métallique de grille comprenant une électrode de grille (2) et la ligne d'électrode commune (3) ;

    la formation de la couche d'isolation de grille (4), de la couche active (5) et de la couche d'électrode de pixel comprenant une électrode de pixel (6) sur la couche métallique de grille ;

    la formation du premier trou d'interconnexion (13) dans une région de la couche d'isolation de grille (4) à l'extérieur de la couche active (5) et de l'électrode de pixel (6), une position du premier trou d'interconnexion (13) correspondant à celle de la ligne d'électrode commune (3) ;

    la formation de la couche métallique d'électrodes source-drain comprenant une électrode de source (7), une électrode de drain (8), une ligne de données (9) et l'électrode de connexion(12) sur le substrat de base (1), l'électrode de connexion (12) étant reliée électriquement à la ligne d'électrode commune (3) à travers le premier trou d'interconnexion (13) ;

    la formation de la couche de passivation (10) sur le substrat de base (1), la couche de passivation (10) comprenant le deuxième trou d'interconnexion (14) correspondant à l'électrode de connexion (12) ; et

    la formation de la couche d'électrode commune comprenant l'électrode commune (11) sur le substrat de base (1), l'électrode commune (11) étant reliée électriquement à l'électrode de connexion (12) à travers le deuxième trou d'interconnexion (14).


     
    11. Le procédé de fabrication du substrat de réseau selon la revendication 7, comprenant :

    la formation séquentielle de la couche métallique de grille sur le substrat de base (1), la couche métallique de grille comprenant une électrode de grille (2) et la ligne d'électrode commune (3) ;

    la formation de la couche d'isolation de grille (4), de la couche active (5) et de la couche métallique d'électrodes source-drain comprenant une électrode de source (7), une électrode de drain (8) et une ligne de données (9) sur la couche métallique de grille ;

    la formation du premier trou d'interconnexion (13) dans une région de la couche d'isolation de grille (4) à l'extérieur de la couche active (5) et de la ligne de données (9), une position du premier trou d'interconnexion (13) correspondant à celle de la ligne d'électrode commune (3) ;

    la formation de la couche d'électrode de pixel comprenant une électrode de pixel (6) et l'électrode de connexion (12) sur le substrat de base (1), l'électrode de connexion (12) étant reliée électriquement à la ligne d'électrode commune (3) à travers le premier trou d'interconnexion (13) ;

    la formation de la couche de passivation sur le substrat de base (1), la couche de passivation comprenant le deuxième trou d'interconnexion (14) correspondant à l'électrode de connexion (12) ; et

    la formation de la couche d'électrode commune comprenant l'électrode commune (11) sur le substrat de base (1), l'électrode commune (11) étant reliée électriquement à l'électrode de connexion (12) à travers le deuxième trou d'interconnexion (14).


     
    12. Le procédé de fabrication du substrat de réseau selon la revendication 8 ou 11, dans lequel l'électrode de connexion (12) est mutuellement isolée de l'électrode de pixel (6).
     
    13. Le procédé de fabrication du substrat de réseau selon la revendication 9 ou 10, dans lequel l'électrode de connexion (12) est mutuellement isolée de l'électrode de source (7), de l'électrode de drain (8) et de la ligne de données (9).
     




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    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description