(19)
(11)EP 3 188 237 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
29.04.2020 Bulletin 2020/18

(21)Application number: 16197569.3

(22)Date of filing:  30.07.2012
(51)International Patent Classification (IPC): 
H01L 27/14(2006.01)
H01L 33/38(2010.01)
H01L 33/02(2010.01)
H01L 33/00(2010.01)
H01L 31/02(2006.01)
H01L 27/15(2006.01)
H01L 33/32(2010.01)
H01L 31/0304(2006.01)
H01L 33/62(2010.01)

(54)

HIGH-VOLTAGE SOLID-STATE TRANSDUCERS AND ASSOCIATED SYSTEMS AND METHODS

HOCHSPANNUNGSFESTKÖRPERWANDLER SOWIE ZUGEHÖRIGE SYSTEME UND VERFAHREN

TRANSDUCTEURS À SEMI-CONDUCTEURS HAUTE TENSION ET SYSTÈMES ET PROCÉDÉS ASSOCIÉS


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 15.08.2011 US 201113210249

(43)Date of publication of application:
05.07.2017 Bulletin 2017/27

(62)Application number of the earlier application in accordance with Art. 76 EPC:
12823667.6 / 2745323

(73)Proprietor: Micron Technology, Inc.
Boise, ID 83707-0006 (US)

(72)Inventor:
  • SCHUBERT, Martin F.
    Boise, ID 83716 (US)

(74)Representative: Carpmaels & Ransford LLP 
One Southampton Row
London WC1B 5HA
London WC1B 5HA (GB)


(56)References cited: : 
WO-A2-2010/114250
DE-A1-102008 022 942
DE-A1-102008 011 848
KR-B1- 101 039 610
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    TECHNICAL FIELD



    [0001] The present technology is related to solid-state transducers ("SSTs"). In particular, the present technology relates to high-voltage SSTs and associated systems and methods.

    BACKGROUND



    [0002] Mobile phones, personal digital assistants ("PDAs"), digital cameras, MP3 players, and other electronic devices utilize light-emitting diodes ("LEDs"), organic light-emitting diodes ("OLEDs"), polymer light-emitting diodes ("PLEDs"), and other SST devices for backlighting. SST devices are also used for signage, indoor lighting, outdoor lighting, and other types of general illumination. Figure 1A is a cross-sectional view of a conventional LED device 10a with lateral contacts. As shown in Figure 1A, the LED device 10a includes a substrate 20 carrying an LED structure 11 having an active region 14, e.g., containing gallium nitride/indium gallium nitride (GaN/InGaN) multiple quantum wells ("MQWs"), positioned between N-type GaN 15 and P-type GaN 16. The LED device 10a also includes a first contact 17 on the front surface of the P-type GaN 16 and a second contact 19 spaced laterally apart from the first contact 17 on the front surface of the N-type GaN 15. The first contact 17 typically includes a transparent and conductive material (e.g., indium tin oxide ("ITO")) to allow light to escape from the LED structure 11.

    [0003] Figure 1B is a cross-sectional view of another conventional LED device 10b in which the first and second contacts 17 and 19 are opposite each other, e.g., in a vertical rather than lateral configuration. During formation of the LED device 10b, the N-type GaN 15, the active region 14 and the P-type GaN 16 are stacked sequentially on a growth substrate (not shown), similar to the substrate 20 shown in Figure 1A. The first contact 17 is formed on the P-type GaN 16, and a carrier substrate 21 is attached to the first contact 17. The growth substrate is then removed and the second contact 19 is formed on the N-type GaN 15. The structure is then inverted to produce the orientation shown in Figure 1B. The N-type GaN 15 at the front surface of the LED device 10b provides better current spreading than the P-type GaN 16. The vertical LED device 10b also has enhanced light extraction and thermal properties, and accordingly a higher efficiency than the lateral LED device 10a of Figure 1A.

    [0004] Typical LEDs have relatively low forward junction voltages (or built-in voltages) compared to the power supplies with which they are used. For example, gallium nitride/indium gallium nitride (GaN/InGaN) based LED dies typically operate at a forward junction voltage of approximately 3 volts direct current ("DC") and aluminum indium gallium phosphide (AlInGaP) based LED dies typically have a forward junction voltage of approximately 2 volts DC, whereas many power supplies operate at 48 volts alternating current ("AC"), 120 volts AC, 60 volts DC, etc. Therefore, power supplies typically include AC/DC rectifiers, DC/DC converters, power conditioners, drivers, and/or other suitable components to supply power to LED dies at suitable voltage levels. However, power supplies and associated components operate more efficiently when the difference between the output voltage and the input voltage is smaller. Accordingly, high-voltage LEDs (e.g., 24 volts, 60 volts, etc.) are preferred for use with high-voltage power supplies to enhance the overall efficiency of the LED system.

    [0005] Conventional high-voltage LEDs are made by coupling several lateral LED dies (e.g., the lateral LED device 10a of Figure 1A) together in series. For example, twenty lateral LED dies, each having a forward junction voltage of 3 volts, can be serially coupled to operate at a combined forward junction voltage of 60 volts. Lateral LEDs, however, have several performance limitations. For example, referring to Figure 1A, the P-type GaN 16 at the front surface of the lateral LED device 10a does not inherently provide current spreading, and therefore current and light concentrate under the first contact 17. To increase current spreading across the lateral LED device 10, the first contact 17 must be thickened and extend over a larger portion of the P-type GaN 16, which makes the first contact 17 less transparent and decreases the light extraction from the LED device 10a. Additionally, lateral LEDs typically have poor thermal characteristics and low overall efficiency. Accordingly, there is a need for high-voltage LEDs and other high-voltage SSTs with enhanced efficiency and performance. WO 2010/114250 discloses a light emitting device having a plurality of light emitting cells. The light emitting device comprises a substrate; a plurality of light emitting cells positioned on the substrate to be spaced apart from one another, each of the light emitting cells comprising a p-type lower semiconductor layer, an active layer and an n-type upper semiconductor layer; p-electrodes positioned to be spaced apart from one another between the substrate and the light emitting cells, the respective p-electrodes being electrically connected to the corresponding lower semiconductor layers, each of the p-electrodes having an extension extending toward adjacent one of the light emitting cells; n-electrodes disposed on upper surfaces of the respective light emitting cells, wherein a contact surface of each of the n-electrodes electrically contacting with each light emitting cell exists both sides of any straight line that bisects the light emitting cell across the center of the upper surface of the light emitting cell; a side insulating layer for covering sides of the light emitting cells; and wires for connecting the p-electrodes and the n-electrodes, the wires being spaced apart from the sides of the light emitting cells by the side insulating layer. DE 10 2008 011848 discloses an optoelectronic semiconductor body comprising a substantially planar semiconductor layer sequence having a first and a second main side, which has an active layer suitable for generating electromagnetic radiation. Furthermore, the semiconductor body comprises at least one trench that severs the active layer of the semiconductor layer sequence and serves for subdividing the active of the semiconductor layer sequence into at least two electrically insulated active partial layers. A first and second connection layer arranged on a second main side serve for making contact with the active partial layers. In this case, the first and second connection layers for making contact with the at least two active partial layers are electrically conductively connected to one another in such a way that the active partial layers form a series circuit.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0006] Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale.
    Instead, emphasis is placed on illustrating clearly the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views and/or embodiments.

    Figure 1A is a partially schematic, cross-sectional diagram of an LED device configured in accordance with the prior art.

    Figure 1B is a partially schematic, cross-sectional diagram of another LED device configured in accordance with the prior art.

    Figures 2A and 2B are partially schematic top plan and cross-sectional views, respectively, of a multi-junction SST device with buried contacts configured in accordance with an embodiment of the present technology.

    Figures 3A-3C are partially schematic top plan and cross-sectional views of a multi-junction SST device with buried contacts configured in accordance with another embodiment of the present technology.

    Figure 4 is a partially schematic, cross-sectional view of a multi-junction SST device with vertical contacts configured in accordance with an embodiment of the present technology.

    Figure 5 is a partially schematic, cross-sectional view of a multi-junction SST device with vertical contacts configured in accordance with another embodiment of the present technology.

    Figures 6A-6C are partially schematic, cross-sectional views illustrating a process of forming the multi-junction SST device of Figures 2A and 2B in accordance with an embodiment of the present technology.

    Figures 7A and 7B are partially schematic, cross-sectional views illustrating a process of forming the multi-junction SST device of Figure 5 in accordance with an embodiment of the present technology.

    Figure 8 is a schematic view of a system that incorporates an SST device in accordance with embodiments of the present technology.


    DETAILED DESCRIPTION



    [0007] Specific details of several embodiments of high-voltage SSTs and associated systems and methods are described below. The term "SST" generally refers to solid-state transducer devices that include a semiconductor material as the active medium to convert electrical energy into electromagnetic radiation in the visible, ultraviolet, infrared, and/or other spectra. For example, SSTs include solid-state light emitters (e.g., LEDs, laser diodes, etc.) and/or other sources of emission other than electrical filaments, plasmas, or gases. SSTs can also include solid-state devices that convert electromagnetic radiation into electricity. Additionally, as used herein, the phrases "high voltage" and "low voltage" refer to relative voltage levels. Therefore, the same voltage level (e.g., 12 volts) may be considered "high voltage" when it is compared to 6 volts, but may be considered a "low voltage" when it is compared is 24 volts. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference to Figures 2A-8.

    [0008] Figure 2A is a partially schematic top plan view of a multi-junction SST device 200 ("SST device 200") configured in accordance with an embodiment of the present technology, and Figure 2B is a partially schematic cross-sectional view of the SST device 200 taken substantially along line 2B-2B of Figure 2A. Referring first to Figure 2A, the SST device 200 can include a carrier substrate 202 and a plurality of SST dies (identified individually as first through fourth SST dies 204a-d, respectively, and referred to collectively as SST dies 204) electrically coupled together in series between a first terminal 220 and a second terminal 222. Each SST die 204 can include a separate transducer structure (identified individually as first through fourth transducer structures 206a-d, respectively, and referred to collectively as transducer structures 206), a first contact 216 on the backside of the transducer structure 206, and a second contact 218. In various embodiments, the SST device 200 can also include a lens, a mirror, and/or other suitable optical and/or electrical components. In the illustrated embodiment, the SST device 200 includes four SST dies 204a-d. A person of skill in the art, however, will understand that the SST device 200 can include two, three, or more than four SST dies 204.

    [0009] The terms "backside" and "front side" are used herein to refer to relative positions of elements with respect to the emissions from or to the SST device 200. The front side of an element refers to a side or surface facing in the same direction as the emissions, and the backside refers to the side or surface of the element facing away from the direction of the emissions. For example, if the SST device 200 is configured to emit light, the side of the carrier substrate 202 that faces the same direction as light emanating from the SST device 200 is the front side and the opposite side of the carrier substrate 202 is the backside.

    [0010] As shown in Figure 2A, the SST dies 204 can be arranged in an array on the carrier substrate 202 with channels 228 separating adjacent SST dies 204. The channels 228 can connect with or include openings 232 above the first and second contacts 216 and 218 to allow the SST dies 204 to be serially coupled together at interconnect regions (identified individually as first-third interconnect regions 230a-230c, respectively, and referred to collectively as interconnect regions 230) proximate to the backside of the transducer structures 206. The openings 232 can also expose portions of the first and second contacts 216 and 218 at the backside of the transducer structures 206. In the illustrated embodiment, a portion the first contact 216 of the first SST die 204a is connected to the first terminal 220 and a portion of the second contact 218 of the fourth SST die 204d is connected to the second terminal 222. In other embodiments, exposed portions of the first and second contacts 216 and 218 of other SST dies 204 in the array can also be connected to the first and second terminals 220 and 222.

    [0011] Referring now to Figure 2B, each transducer structure 206 can include an active region 214 between a first semiconductor material 208 at a first side 210a of the transducer structure 206 and a second semiconductor material 212 at a second side 210b of the transducer structure 206 opposite the first side 210a. The first and second semiconductor materials 208 and 212 can be doped with impurities to form a p-n junction. For example, the first semiconductor material 208 can be a P-type semiconductor material (e.g., P-type GaN), and the second semiconductor material 212 can be an N-type semiconductor material (e.g., N-type GaN). This configuration is suitable when the transducer structure 206 is formed on a growth substrate (not shown), inverted, and subsequently attached to the carrier substrate 202. In other embodiments, the first and second semiconductor materials 208 and 212 may be reversed.

    [0012] The active region 214 can include a single quantum well ("SQW"), multiple quantum wells ("MQWs"), and/or a bulk semiconductor material. The term "bulk semiconductor material" generally refers to a single grain semiconductor material (e.g., InGaN) with a thickness greater than approximately 10 nanometers and up to approximately 500 nanometers. In other embodiments, the transducer structure 206 can include other suitable semiconductor materials, such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), etc.), and/or other semiconductor materials.

    [0013] As shown in Figure 2B, the first contact 216 can be positioned in a first region 201a and can be electrically coupled to the first semiconductor material 208. As used herein, elements positioned in the first region 201a are positioned in a region bounded internally by the first side 210a of the transducer structure 206, and elements positioned in a second region 201b are positioned in a region bounded internally by the second side 210b of the transducer structure 206. In various embodiments, the first contact 216 can be made from a reflective material, such as nickel (Ni), silver (Ag), copper (Cu), aluminum (Al), tungsten (W), and/or other suitable reflective materials. The reflective first contact 216 can redirect emissions (e.g., light, energy, etc.) back through the transducer structure 206 toward the second side 210b to enhance emissions from the SST die 204. In other embodiments, the first contact 216 can be made from non-reflective materials and/or the SST 204 can include separate reflective elements positioned in the first region 201a.

    [0014] The second contact 218 can be a buried contact that is electrically coupled to the second semiconductor material 212. In the embodiment illustrated in Figure 2B, for example, the second contact 218 extends along the backside of the first contact 216 and projects through the first contact 216 at least to the second semiconductor material 212. In other embodiments, the first contact 216 is spaced laterally apart from the second contact 218 such that the buried second contact 218 projects through a plane containing the first contact 216. For illustrative purposes, each SST die 204 includes one buried second contact 218, but in other embodiments each SST die 204 can include a plurality of buried contact elements extending into the transducer structure 206. The second contact 218 can be made from titanium (Ti), aluminum (Al), nickel (Ni), silver (Ag), and/or other suitable conductive materials.

    [0015] As further shown in Figure 2B, a dielectric material 224 can be positioned between the first and second contacts 216 and 218 to electrically isolate the two from one another. The dielectric material 224 can also extend along a sidewall 226 of the buried second contact 218 to electrically isolate the second contact 218 from the first semiconductor material 208 and the active region 214. The dielectric material 224 can be made from silicon dioxide (SiO2), silicon nitride (SiN), and/or other suitable generally nonconductive materials.

    [0016] In a particular embodiment, the carrier substrate 202 is made from a nonconductive, semiconductive or low conductivity material, such as a ceramic material, silicon, polysilicon, and/or other suitable substrate materials. Accordingly, as shown in Figure 2B, the carrier substrate 202 can be attached to the backside of the SST dies 204 without shorting the dies via the second contacts 218. As explained in further detail below with reference to Figures 3A and 3B, in other embodiments the carrier substrate 202 can be made from a conductive material that serves as a thermal pad to draw heat away from the SST dies 204 and thereby improves the thermal performance of the SST device 200.

    [0017] As further shown in Figure 2B, the opening 232 between the adjacent first and second transducer structures 206a and 206b exposes a portion of the second contact 218 as it extends beyond the backside of the first transducer structure 206a, and exposes a portion of the first contact 216 as it extends beyond the backside of the second transducer structure 206b. This allows the first and second contacts 216 and 218 of the adjacent first and second SST dies 204a and 204b to be serially coupled together in the first region 201a at the first interconnect region 230a. The second and third interconnect regions 230b and 230c can be formed similarly such that the first-fourth SST dies 204a-204d are coupled together in series. Additionally, the openings 232 allow the first and second terminals 220 and 222 to be positioned in the first region 201a and to be electrically accessible from the front side of the SST device 200 via wirebonds 234, solder balls, and/or other suitable electrical connections.

    [0018] The SST device 200 has a total forward junction voltage that is approximately equivalent to the sum of the forward junction voltages of the individual transducer structures 206. For example, if each transducer structure 206 has a forward junction voltage of approximately 4 volts, the four-die SST device 200 of Figures 2A and 2B has a combined forward junction voltage of 16 volts. The SST device 200 can then be coupled to a power supply (not shown) with an output voltage approximately the same as (e.g., 20 volts) the combined forward junction voltage of the SST device 200. Since power supplies and associated components (e.g., drivers) operate more efficiently when the difference between the input voltage and the output voltage is smaller, the increased forward junction voltage of the SST device 200, which correlates to the output voltage of the power supply and/or associated component, can enhance the efficiency of a higher voltage power supply. Additionally, the SST device 200 can be coupled to higher voltage power supplies and operate more efficiently than any one of the SST dies 204 alone. In selected embodiments, the SST device 200 can be configured to have a sufficiently high forward junction voltage such that the SST device 200 can be driven directly by a standard AC power supply (e.g., a 120 volt power supply; not shown), and eliminate the need for a driver. Moreover, the high-voltage SST device 200 can also enhance the conversion efficiency when an AC power supply must be converted to DC.

    [0019] During operation, a voltage can be applied to the first and second terminals 220 and 222. As discussed above, the high-voltage SST device 200 can decrease the difference between the input voltage and the output voltage of the associated power supply, and can therefore improve the efficiency of the overall system. As shown in Figure 2B, the first and second contacts 216 and 218 and the first and second terminals 220 and 222 can be positioned in the first region 201a such that neither blocks emissions from or to the second side 210b of the transducer structure 206. The reflective characteristics of the first contact 216 can further enhance emissions through the second side 210b of the transducer structure 206. Additionally, the configuration of the SST dies 204 allow N-type GaN to be used as the second semiconductor material 212 positioned at the second side 210b of the transducer structure 206. N-type GaN, unlike P-type GaN, inherently spreads current across the transducer structure 206, and therefore provides improved current spreading and uniformity across the SST device 200. N-type GaN also facilitates surface roughening, and can therefore be used as the second semiconductor material 212 to increase extraction efficiency of the SST device 200. Accordingly, the SST device 200 can have increased emission extraction, enhanced current uniformity, and/or higher overall efficiency than conventional high-voltage SST devices with lateral SST dies.

    [0020] Figure 3A is a partially schematic top plan view of a multi-junction SST device 300 configured in accordance with another embodiment of the present technology, and Figures 3B and 3C are partially schematic cross-sectional views taken substantially along lines 3B-3B and 3C-3C of Figure 3A, respectively. The SST device 300 can include features generally similar to those of the SST device 200 described above with reference to Figures 2A and 2B. For example, as shown in Figures 3A-3C, the SST device 300 can include a plurality of SST dies 204 with backside first contacts 216 and buried second contacts 218 coupled together in series at a plurality of interconnect regions 230. In the embodiment illustrated in Figures 3A-3C, the SST dies 204 are carried by a conductive, rather than a nonconductive, carrier substrate 302. The conductive carrier substrate 302 can be made from a metal, a metal alloy, a doped silicon, and/or other electrically conductive substrate materials. For example, in various embodiments, the substrate 302 can include copper, aluminum, and/or other suitable metals.

    [0021] Referring to Figure 3B, the SST device 300 further includes a second dielectric material 324 positioned between the second contact 218 and the conductive carrier substrate 302 to electrically isolate the two from one another. The second dielectric material 324 can be made from materials similar to those described above with reference to the dielectric material 224 positioned between the first and second contacts 216 and 218. For example, the second dielectric material 324 can be made from silicon oxide (SiO2), silicon nitride (Si3N4), and/or other suitable generally nonconductive materials.

    [0022] As shown in Figure 3C, a portion of the second contact 218 of the fourth SST die 204d can be exposed through the second dielectric material 324 such that it electrically couples to the conductive carrier substrate 302 and thereby forms a backside second terminal 322. Accordingly, the second terminal 322 is electrically accessible from a backside of the SST device 300 (e.g., from the backside of the conductive carrier substrate 302) and facilitates a wirebond-free electrical connection.

    [0023] Similar to the SST device 200 described above with reference to Figures 2A and 2B, the SST device 300 of Figures 3A-3C can provide a high forward junction voltage with enhanced current spreading, emission extraction, and overall efficiency. The backside second terminal 322 does not block or interfere with emissions (e.g., light energy) from or to the front side of the SST device 300 (e.g., the second side 210b of the transducer structure 206) and allows the second semiconductor material 212 to span a greater surface area across the fourth SST die 204d (Figure 3A), thereby further enhancing extraction efficiency. Additionally, the conductive carrier substrate 302 can function as a heat sink to draw heat away from the SST dies 204 during operation. This decreases the operating temperature of the SST device 300 and enhances the overall thermal performance of the device.

    [0024] Figure 4 is a partially schematic, cross-sectional views of multi-junction SST device 400 ("SST device 400") configured in accordance with a further embodiment of the present technology. The SST device 400 includes features generally similar to the features of the SST devices 200 and 300 described above with reference to Figures 2A-3C. For example, the SST device 400 includes SST dies (identified individually as a first SST die 404a and a second SST die 404b, and referred to collectively as SST dies 404) serially coupled together at the interconnect region 230. For illustrative purposes, Figure 4 shows the SST device 400 having two SST dies 404, but in other embodiments the SST device 400 can include additional SST dies 404 to obtain a desired forward junction voltage.

    [0025] Rather than buried second contacts 218 (as described above with reference to Figures 2B, 3B and 3C), the SST dies 404 shown in Figure 4 each have a second contact 418 in the second region 201b spaced vertically apart from the first contact 216 in the first region 201a. For example, as shown in Figure 4, the second contact 418 of the second SST die 404b can extend from the backside first contact 216 of the adjacent first SST die 404a, along a sidewall 438 of the second transducer structure 206b, and onto the second side 210b where it is electrically coupled to the second semiconductor material 212. An underlying dielectric material 424 can extend between the sidewall 438 and the second contact 418 to electrically isolate the second contact 418 from the first contact 216, the first semiconductor material 208 and the active region 214. The dielectric material 424 can be made from materials generally similar to the dielectric materials described above, such as silicon oxide (SiO2), silicon nitride (Si3N4), and/or other suitable generally nonconductive materials. The vertical SST dies 404, like the SST dies 202 of Figures 2A-3C, allow N-type GaN to be positioned at the front side of the SST device 400, and therefore the SST device 400 can have enhanced current spreading and emission extraction compared to conventional high-voltage SST devices with lateral SST dies. Also similar to the SST devices 200 and 300 described above, the SST device 400 of Figure 4 can enhance efficiency of the system due to the high combined forward junction voltage of the SST dies 404.

    [0026] As further shown in Figure 4, in various embodiments, the vertical SST dies 404 can be positioned on a generally nonconductive carrier substrate 402. The carrier substrate 402 can be made from materials similar to those of the generally nonconductive substrate 202 described above with reference to Figures 2A and 2B, such as ceramic, silicon, polysilicon, and/or other generally nonconductive substrate materials. Accordingly, the SST device 400 includes first and second terminals 420 and 422 that are electrically accessible from a front side of the SST device 400 on a surface facing away from the carrier substrate 402. For example, in the embodiment illustrated in Figure 4, the first terminal 420 is exposed through one of the openings 232 and positioned in the first region 201a, and the second terminal 422 is positioned on the second side 210b of the first transducer structure 206a in the second region 201b. Wirebonds 234 and/or other suitable electrical connectors can be used to couple the first and second terminals 420 and 422 to a power supply (not shown).

    [0027] Figure 5 is a partially schematic, cross-sectional view of a multi-junction SST device 500 ("SST device 500") configured in accordance with another embodiment of the present technology. The SST device 500 includes features generally similar to the features of the SST device 400 described above with reference to Figure 4. For example, the SST device 500 includes vertical SST dies 404 serially coupled together at the interconnect region 230. However, the SST device 500 shown in Figure 5 includes a conductive carrier substrate 502 made from metals, metal alloys, doped semiconductor materials, and/or other suitable conductive substrate materials. The SST device 500 can therefore include a first terminal 520 electrically coupled to the conductive carrier substrate 502 and electrically accessible from the backside of the SST device 500 to facilitate wirebond-free connections. A second terminal 522 can be positioned in the second region 201b and can be electrically accessible from the front side of the SST device 500. The conductive carrier substrate 502 can draw heat from the SST dies 404 during operation and thereby enhance the thermal performance of the SST device 500.

    [0028] Figures 6A-6C are partially schematic, cross-sectional views illustrating a process for forming the SST device 200 of Figures 2A and 2B in accordance with an embodiment of the present technology. Figure 6A, for example, illustrates the SST device 200 at a stage of the process after the transducer structure 206 has been formed on a growth substrate 640. The transducer structure 206 can be formed via metal organic chemical vapor deposition ("MOCVD"), molecular beam epitaxy ("MBE"), liquid phase epitaxy ("LPE"), and/or hydride vapor phase epitaxy ("HVPE"). In other embodiments, at least a portion of the transducer structure 206 may be formed using other suitable epitaxial growth techniques.

    [0029] As further shown in Figure 6A, the first contact 216 can be formed in the first region 201a (e.g., on the first side 210a of the transducer structure 206) and a plurality of vias 642 can be formed through the first contact 216. The first contact 216 can be formed using chemical vapor deposition ("CVD"), physical vapor deposition ("PVD"), atomic layer deposition ("ALD"), spin coating, patterning, and/or other suitable techniques known in the semiconductor fabrication arts. The vias 642 can be formed by positioning a mask (not shown) over the first contact 216 and etching (e.g., by wet etch, dry etch, and/or other suitable process) through the exposed portions of the first contact 216 and the transducer structure 206. In other embodiments, the vias 642 can be formed using other suitable removal methods. In further embodiments, the vias 642 can be formed before the formation of the first contact 216 such that the first contact 216 is subsequently deposited, etched, and/or otherwise formed in the first region 201a without obstructing the vias 632. Each via 642 can extend to or into the second semiconductor material 212 to define the dimensions of the subsequently formed buried second contact 218 (Figure 6B).

    [0030] Figure 6B shows a later stage in the process after the buried second contacts 218 have been formed at the backside of the SST device 200. The dielectric material 224 can first be disposed over the first contact 216 and along the sidewalls 226 of the vias 642. A portion of the second semiconductor material 212 in the via 642 is not covered by the dielectric material 224 to provide access for subsequent electrical connections. For example, in various embodiments, the dielectric material 224 can be formed along the sidewalls 226 of the vias 642 using spacer etching. In other embodiments, the dielectric material 224 can be formed using CVD, PVD, ALD, patterning, selective etching, and/or other suitable formation processes.

    [0031] As further shown in Figure 6B, an isolating protrusion 625 made from the dielectric material 224 and/or other generally nonconductive material can be formed between portions of the second contact 218. The isolating protrusions can define the lateral bounds of individual SST dies 204 (Figure 6C) and electrically isolate individual second contacts 218 from one another. In various embodiments, the isolating protrusion 625 can be formed by selectively etching a notch into the second contact 218 and selectively depositing the isolating protrusion 225 therein. In other embodiments, isolating protrusions 625 can be formed using other suitable methods known in the semiconductor fabrication arts. In further embodiments, individual second contacts 218 can be electrically isolated from one another during subsequent processing stages.

    [0032] Figure 6C illustrates a further stage in the process after the growth substrate 640 has been removed, the SST device 200 has been inverted, and the carrier substrate 202 has been positioned in the first region 201a on the second contacts 218. The growth substrate 640 can be removed from the second side 210b of the transducer structure 206 by backgrinding, etching (e.g., wet etching, dry etching, etc.), and/or otherwise removing the growth substrate 640 from the second semiconductor material 212. The carrier substrate 202 can be attached to the backside of the SST dies 204 using temporary and/or permanent bonding materials (e.g., WaferBOND™ HT-10.10 from Brewer Science, Inc. of Rolla, MO). In other embodiments, the carrier substrate 202 can be formed or attached to the SST dies 204 using other suitable methods known in the semiconductor fabrication arts.

    [0033] As shown in Figure 6C, portions of the transducer structure 206 have been removed to form the opening 232 and to separate the transducer structure 206 into separate transducer structures 206a and 206b with isolated p-n junctions. The opening 232 can also expose portions of the second contact 218 of the first SST die 204a and the first contact 216 of the adjacent second SST die 204b such that the first and second SST dies 204a and 204b are electrically isolated from one another. The transducer structure 206, the first contact 216, and the dielectric material 224 can be removed by positioning a mask over the front side of the SST device 200 and selectively etching away the various materials. In other embodiments, the transducer structure 206, the first contact 216, the second contact 218, the dielectric material 224, and/or other portions of the SST device 200 can be removed using other methods known in the semiconductor fabrication arts.

    [0034] After electrically isolating the SST dies 204, an electrically conductive material 617 (shown in broken lines), such as the material used for the first and/or second contacts 216 and 218, can be deposited at the interconnect region 230 to serially couple the first contact 216 and the second contact 218 of adjacent SST dies 204. A portion of the first contact 216 of the first SST die 204a can be exposed to define the first terminal 220, and a portion of the second contact 218 of the last SST die 204 in the series (e.g., the fourth SST die 204d shown in Figure 2A) can be exposed to define the second terminal 222, or vice versa. The first and second terminals 220 and 222 can then be electrically coupled to a power supply 650 via wirebonds 234 and/or other electrical connectors to drive the SST device 200. In various embodiments, the process can further include roughening the second semiconductor material 212 (e.g., N-type GaN) to enhance light extraction from the SST device 200.

    [0035] The SST device 300 of Figures 3A-3C can be formed using methods generally similar to the methods discussed above with reference to Figures 6A-6C. However, forming the SST device 300 can further include forming the second dielectric material 324 on the second contact 218 before the conductive carrier substrate 302 is positioned thereon. Additionally, at least a portion of one of the second contacts 218 can be exposed through the second dielectric material 324 and coupled to the conductive carrier substrate 302 to form the backside second terminal 322.

    [0036] Figures 7A and 7B are partially schematic, cross-sectional views illustrating a process for forming the SST device 500 of Figure 5 in accordance with an embodiment of the present technology. Figure 7A, for example, illustrates the SST device 500 at a stage of the process after the transducer structure 206 has been formed on a growth substrate 740 using MOCVD, MBE, LPE, HVPE, and/or other suitable epitaxial growth techniques. The first contact 216 and the dielectric material 424 can then be formed sequentially in the first region 201a (e.g., on the first side 210a of the transducer structure 206) using CVD, PVD, ALD, patterning, and/or other suitable formation techniques. As shown in Figure 7A, the dielectric material 424 can extend into a notch 752 between portions of the first contact 216 to demarcate the lateral bounds of the subsequently formed individual SST dies 404 (Figure 7B). The notch 752 can be formed by selectively etching and/or otherwise removing portions of the first contact 216, or the first contact 216 can be selectively formed to include the notch 752. As further shown in Figure 7A, a portion of the first contact 216 can remain exposed through the dielectric material 424 (e.g., using selective etching or deposition), and additional conductive material can be formed thereon to define the backside first terminal 520.

    [0037] Figure 7B shows a further stage in the process after the growth substrate 740 has been removed from the second side 210b of the transducer structure 206, the SST device 500 has been inverted, and the conductive carrier substrate 502 has been positioned on the backside of the SST device 500. When the carrier substrate 502 is attached, the exposed backside first terminal 520 can electrically coupled thereto to provide electrical access to the backside of the SST device 500. Portions of the transducer structure 206 can then be removed between the SST dies 404 to form a plurality of separate transducer structures 206 with isolated p-n junctions that can be subsequently coupled together in series. These steps can be performed using generally similar methods as those described above with reference to Figure 6C.

    [0038] Once the individual SST dies 404 have been formed, a dielectric material 436 and the second contact 418 (both shown in broken lines) can then be sequentially formed along the sidewall 438 of the transducer structure 206 to connect the SST dies 404 in series. The dielectric material 436 and the second contact 418 can be formed using CVD, PVD, ALD, and/or other suitable formation techniques. The second terminal 522 can be formed independently of or in conjunction with the second contact(s) 418 on the second side 210b of the one of the transducer structure 206 using CVD, PVD, ALD, and/or other suitable formation techniques. The first and second terminals 520 and 522 can then be connected to a power supply 750 that can drive the multi-junction SST device 500.

    [0039] Any of the high-voltage SST devices described above with reference to Figures 2A-7B can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system 800 shown schematically in Figure 8. The system 800 can include an SST device 810, a power supply 820, a driver 830, a processor 840, and/or other subsystems or components 850. As discussed above, the SST device 810 can decrease the difference between the input and the output voltage of the power supply 820 and/or the driver 830, and thereby increase the efficiency of the system 800. In various embodiments, the SST device 810 can have a sufficiently high voltage such that the driver 830 can be eliminated from the system 800. The resulting system 800 can perform any of a wide variety of functions, such as backlighting, general illumination, power generation, sensors, and/or other functions. Accordingly, representative systems 800 can include, without limitation, hand-held devices (e.g., cellular or mobile phones, tablets, digital readers, and digital audio players), lasers, photovoltaic cells, remote controls, computers, and appliances (e.g., refrigerators). Components of the system 800 may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the system 800 can also include local and/or remote memory storage devices, and any of a wide variety of computer-readable media.

    [0040] From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. For example, the SST devices 200 and 300 shown in Figures 2A-3C include 2x2 arrays of SST dies 204. However, in other embodiments, SST devices 200 and 300 can include two, three, or more than four SST dies 204 arranged in arrays having a variety of configurations, such as linear arrays, circular arrays, etc. Certain aspects of the new technology described in the context of particular embodiments may be combined or eliminated in other embodiments. For example, the SST dies 204 with buried contacts 218 shown in Figures 2A-3C can be serially coupled with the vertical SST dies 404 of Figures 4 and 5.


    Claims

    1. A method for operating a solid-state transducer (SST) device, comprising:

    providing an SST device comprising:

    a carrier substrate (202);

    a first terminal (220);

    a second terminal (222); and

    a plurality of SST dies (204) electrically coupled together in series between the first and second terminals, wherein the plurality of SST dies includes a first SST die (204a) adjacent to a second SST die (204b), and wherein the individual SST dies comprise-

    a transducer structure having an active region (214) between a first semiconductor material (208) at a first side of the transducer structure and a second semiconductor material (212) at a second side of the transducer structure opposite the first side, wherein the first and second semiconductor materials are doped with impurities to form a p-n junction;

    a first contact (216) on a backside of the transducer structure and electrically coupled to the first semiconductor material; and

    a second contact (218) electrically coupled to the second semiconductor material, wherein the second contact is a buried contact; and wherein the second contact extends along a backside of the first contact and projects through the first contact at least to the second semiconductor material; and

    an opening (232) between the transducer structures of the adjacent first and second SST dies, wherein the opening exposes a portion of the second contact as it extends beyond the backside of the transducer structure of the first SST die and exposes a portion of the first contact as it extends beyond the backside of the transducer structure of the second SST die, and wherein the first and second contacts of the adjacent first and second SST dies are serially coupled together at a first interconnect region proximate to the backside of the transducer structures; and

    applying a voltage to the first terminal and the second terminal.


     
    2. The method of claim 1, wherein the SST device has a total forward junction voltage that is approximately equivalent to the sum of the forward junction voltages of the individual transducer structures, and wherein the applied voltage is approximately the same as the combined forward junction voltage of the SST device.
     
    3. The method of claim 1 or claim 2, wherein the first and second terminals are positioned to couple to a power supply having an output voltage.
     
    4. The method of any preceding claim, wherein a dielectric material is positioned between the first and second contacts to electrically isolate the two from one another.
     
    5. The method of any preceding claim, wherein the SST device emits electromagnetic radiation in at least one of the ultraviolet spectrum, the visible spectrum, and the infrared spectrum.
     
    6. The method of any preceding claim, wherein the first semiconductor material comprises a P-type GaN semiconductor material, the second semiconductor material comprises an N-type GaN semiconductor material, and the active region comprises InGaN.
     
    7. The method of any preceding claim, wherein the carrier substrate comprises a nonconductive, semiconductive or low conductivity material.
     
    8. The method of any of claims 1 to 6, wherein the carrier substrate comprises a conductive material.
     
    9. The method of any of claims 1 to 8, wherein the second contact is spaced vertically apart from the first contact.
     
    10. The method of any preceding claim, wherein at least a portion of the carrier substrate defines the second terminal.
     
    11. The method of claim 1, wherein:

    the carrier substrate comprises a generally nonconductive material;

    the first semiconductor material comprises P-type gallium nitride (P-type GaN) facing toward a first region;

    the second semiconductor material comprises N-type gallium nitride (N-type GaN) facing toward a second region;

    the active region comprises indium gallium nitride (InGaN); and

    the first and second terminals are electrically accessible from the first region.


     
    12. The method of claim 1 wherein:

    the carrier substrate comprises a conductive material;

    the first semiconductor material includes P-type GaN facing toward a first region;

    the second semiconductor material includes N-type GaN facing toward a second region;

    the active region includes InGaN;

    the second contact is electrically isolated from the carrier substrate;

    the first terminal is electrically accessible from the first region; and

    the second terminal is electrically coupled to the carrier substrate.


     
    13. The method of claim 1 wherein:

    the carrier substrate comprises a generally nonconductive material; and

    the first and second terminals are electrically accessible from a surface facing away from the carrier substrate.


     
    14. The method of claim 1 wherein:

    the carrier substrate comprises a conductive material;

    the first terminal is electrically accessible from a surface facing away from the carrier substrate; and

    the second terminal is electrically coupled to the carrier substrate.


     


    Ansprüche

    1. Verfahren zum Betreiben einer Festkörperwandler-Vorrichtung (SST-Vorrichtung), das Folgendes umfasst:

    Bereitstellen einer SST-Vorrichtung, die Folgendes umfasst:

    ein Trägersubstrat (202);

    einen ersten Anschluss (220);

    einen zweiten Anschluss (222); und

    mehrere SST-Dies (204), die zwischen dem ersten und dem zweiten Anschluss elektrisch miteinander in Reihe gekoppelt sind, wobei die mehreren SST-Dies einen ersten SST-Die (204a), der einem zweiten SST-Die (204b) benachbart ist, enthalten, und wobei die einzelnen SST-Dies Folgendes umfassen:

    eine Wandlerstruktur mit einem aktiven Bereich (214) zwischen einem ersten Halbleitermaterial (208) an einer ersten Seite der Wandlerstruktur und einem zweiten Halbleitermaterial (212) an einer zweiten Seite der Wandlerstruktur gegenüber der ersten Seite, wobei das erste und das zweite Halbleitermaterial mit Fremdstoffen dotiert sind, um einen p-n-Übergang zu bilden;

    einen ersten Kontakt (216) auf einer Rückseite der Wandlerstruktur, der mit dem ersten Halbleitermaterial elektrisch gekoppelt ist; und

    einen zweiten Kontakt (218), der mit dem zweiten Halbleitermaterial elektrisch gekoppelt ist, wobei der zweite Kontakt ein vergrabener Kontakt ist; und wobei sich der zweite Kontakt entlang einer Rückseite des ersten Kontakts erstreckt und durch den ersten Kontakt wenigstens bis zu dem zweiten Halbleitermaterial vorsteht; und

    eine Öffnung (232) zwischen den Wandlerstrukturen der benachbarten ersten und zweiten SST-Dies, wobei die Öffnung einen Abschnitt des zweiten Kontakts freilegt, während er sich über die Rückseite der Wandlerstruktur des ersten SST-Dies hinaus erstreckt, und einen Abschnitt des ersten Kontakts freilegt, während er sich über die Rückseite der Wandlerstruktur des zweiten SST-Dies hinaus erstreckt, und wobei der erste und zweite Kontakt der benachbarten ersten und zweiten SST-Dies an einem ersten Zusammenschaltungsbereich in der Nähe der Rückseite der Wandlerstrukturen miteinander in Reihe gekoppelt sind; und

    Anlegen einer Spannung an den ersten Anschluss und den zweiten Anschluss.


     
    2. Verfahren nach Anspruch 1, wobei die SST-Vorrichtung eine Gesamtdurchlassspannung aufweist, die etwa gleich der Summe der Durchlassspannungen der einzelnen Wandlerstrukturen ist, und wobei die angelegte Spannung etwa die gleiche ist wie die kombinierte Durchlassspannung der SST-Vorrichtung.
     
    3. Verfahren nach Anspruch 1 oder Anspruch 2, wobei der erste und der zweite Anschluss positioniert sind, um an eine Leistungsversorgung, die eine Ausgangsspannung aufweist, gekoppelt zu sein.
     
    4. Verfahren nach einem vorhergehenden Anspruch, wobei ein dielektrisches Material zwischen dem ersten und zweiten Kontakt positioniert ist, um beide voneinander zu isolieren.
     
    5. Verfahren nach einem vorhergehenden Anspruch, wobei die SST-Vorrichtung elektromagnetische Strahlung im ultravioletten Spektrum und/oder im sichtbaren Spektrum und/oder im Infrarotspektrum emittiert.
     
    6. Verfahren nach einem vorhergehenden Anspruch, wobei das erste Halbleitermaterial ein P-Typ-GaN-Halbleitermaterial umfasst, das zweite Halbleitermaterial ein N-Typ-GaN-Halbleitermaterial umfasst und der aktive Bereich InGaN umfasst.
     
    7. Verfahren nach einem vorhergehenden Anspruch, wobei das Trägersubstrat ein nichtleitfähiges Material, ein halbleitfähiges Material oder ein Material mit geringer Leitfähigkeit umfasst.
     
    8. Verfahren nach einem der Ansprüche 1 bis 6, wobei das Trägersubstrat ein leitfähiges Material umfasst.
     
    9. Verfahren nach einem der Ansprüche 1 bis 8, wobei der zweite Kontakt vertikal von dem ersten Kontakt beabstandet ist.
     
    10. Verfahren nach einem vorhergehenden Anspruch, wobei wenigstens ein Abschnitt des Trägersubstrats den zweiten Anschluss definiert.
     
    11. Verfahren nach Anspruch 1, wobei:

    das Trägersubstrat ein allgemein nichtleitfähiges Material umfasst;

    das erste Halbleitermaterial P-Typ-Galliumnitrid (P-Typ-GaN) umfasst, das einem ersten Bereich zugewandt ist;

    das zweite Halbleitermaterial N-Typ-Galliumnitrid (N-Typ-GaN) umfasst, das einem zweiten Bereich zugewandt ist;

    der aktive Bereich Indiumgalliumnitrid (InGaN) umfasst;

    und

    der erste und der zweite Anschluss von dem ersten Bereich elektrisch zugänglich sind.


     
    12. Verfahren nach Anspruch 1, wobei:

    das Trägersubstrat ein leitfähiges Material umfasst;

    das erste Halbleitermaterial P-Typ-GaN enthält, das einem ersten Bereich zugewandt ist;

    das zweite Halbleitermaterial N-Typ-GaN enthält, das einem zweiten Bereich zugewandt ist;

    der aktive Bereich InGaN enthält;

    der zweite Kontakt von dem Trägersubstrat elektrisch isoliert ist;

    der erste Anschluss von dem ersten Bereich elektrisch zugänglich ist; und

    der zweite Anschluss mit dem Trägersubstrat elektrisch gekoppelt ist.


     
    13. Verfahren nach Anspruch 1, wobei:

    das Trägersubstrat ein allgemein nichtleitfähiges Material umfasst; und

    der erste und der zweite Anschluss von einer Oberfläche, die von dem Trägersubstrat abgewandt ist, elektrisch zugänglich sind.


     
    14. Verfahren nach Anspruch 1, wobei:

    das Trägersubstrat ein leitfähiges Material umfasst;

    der erste Anschluss von einer Oberfläche, die von dem Trägersubstrat abgewandt ist, elektrisch zugänglich ist; und

    der zweite Anschluss mit dem Trägersubstrat elektrisch gekoppelt ist.


     


    Revendications

    1. Procédé d'exploitation d'un dispositif transducteur à semi-conducteur (SST), comprenant :

    la fourniture d'un dispositif SST, comprenant :

    un substrat de support (202) ;

    une première borne (220) ;

    une deuxième borne (222) ; et

    une pluralité de matrices de SST (204) électriquement couplées ensemble en série entre les première et deuxième bornes, la pluralité de matrices de SST comprenant une première matrice de SST (204a) adjacente à une deuxième matrice de SST (204b), et les matrices de SST individuelles comprenant

    une structure de transducteur ayant une région active (214) entre un premier matériau semi-conducteur (208) sur un premier côté de la structure de transducteur et un deuxième matériau semi-conducteur (212) sur un deuxième côté de la structure de transducteur à l'opposé du premier côté, les premier et deuxième matériaux semi-conducteurs étant dopés avec des impuretés pour former une jonction p-n ;

    un premier contact (216) sur une face arrière de la structure de transducteur et électriquement couplé au premier matériau semi-conducteur ; et

    un deuxième contact (218) électriquement couplé au deuxième matériau semi-conducteur, le deuxième contact étant un contact enfoui ; et le deuxième contact s'étendant le long d'une face arrière du premier contact et faisant saillie à travers le premier contact au moins jusqu'au deuxième matériau semi-conducteur ; et

    une ouverture (232) entre les structures de transducteur des première et deuxième matrices de SST adjacentes, l'ouverture exposant une partie du deuxième contact lorsqu'il s'étend au-delà de la face arrière de la structure de transducteur de la première matrice de SST et exposant une partie du premier contact lorsqu'il s'étend au-delà de la face arrière de la structure de transducteur de la deuxième matrice de SST, et les premier et deuxième contacts des première et deuxième matrices de SST adjacentes étant couplées ensemble en série au niveau d'une première région d'interconnexion proche de la face arrière des structures de transducteur ; et

    l'application d'une tension à la première borne et à la deuxième borne.


     
    2. Procédé selon la revendication 1, dans lequel le dispositif SST présente une tension de jonction directe totale qui est approximativement équivalente à la somme des tensions de jonction directes des structures de transducteur individuelles, et la tension appliquée étant approximativement la même que la tension de jonction avant combinée du dispositif SST.
     
    3. Procédé selon la revendication 1 ou 2, dans lequel les première et deuxième bornes sont positionnées pour être couplées à une alimentation électrique ayant une tension de sortie.
     
    4. Procédé selon l'une quelconque des revendications précédentes, dans lequel un matériau diélectrique est positionné entre les premier et deuxième contacts pour isoler électriquement les deux l'un de l'autre.
     
    5. Procédé selon l'une quelconque des revendications précédentes, dans lequel le dispositif SST émet un rayonnement électromagnétique dans au moins l'un parmi le spectre ultraviolet, le spectre visible et le spectre infrarouge.
     
    6. Procédé selon l'une quelconque des revendications précédentes, dans lequel le premier matériau semi-conducteur comprend un matériau semi-conducteur GaN de type P, le deuxième matériau semi-conducteur comprend un matériau semi-conducteur GaN de type N, et la région active comprend de l'InGaN.
     
    7. Procédé selon l'une quelconque des revendications précédentes, dans lequel le substrat de support comprend un matériau non conducteur, semi-conducteur ou à faible conductivité.
     
    8. Procédé selon l'une quelconque des revendications 1 à 6, dans lequel le substrat de support comprend un matériau conducteur.
     
    9. Procédé selon l'une quelconque des revendications 1 à 8, dans lequel le deuxième contact est espacé verticalement du premier contact.
     
    10. Procédé selon l'une quelconque des revendications précédentes, dans lequel au moins une partie du substrat de support définit la deuxième borne.
     
    11. Procédé selon la revendication 1, dans lequel :

    le substrat de support comprend un matériau généralement non conducteur ;

    le premier matériau semi-conducteur comprend du nitrure de gallium de type P (GaN de type P) faisant face à une première région ;

    le deuxième matériau semi-conducteur comprend du nitrure de gallium de type N (GaN de type N) faisant face à une deuxième région ;

    la région active comprend du nitrure de gallium-indium (InGaN) ; et

    les première et deuxième bornes sont électriquement accessibles depuis la première région.


     
    12. Procédé selon la revendication 1, dans lequel :

    le substrat de support comprend un matériau conducteur ;

    le premier matériau semi-conducteur comprend du GaN de type P faisant face à une première région ;

    le deuxième matériau semi-conducteur comprend du GaN de type N faisant face à une deuxième région ;

    la région active comprend de l'InGaN ;

    le deuxième contact est électriquement isolé du substrat de support ;

    la première borne est électriquement accessible depuis la première région ; et

    la deuxième borne est électriquement couplée au substrat de support.


     
    13. Procédé selon la revendication 1, dans lequel :

    le substrat de support comprend un matériau généralement non conducteur ; et

    les première et deuxième bornes sont électriquement accessibles depuis une surface détournée du substrat de support.


     
    14. Procédé selon la revendication 1, dans lequel :

    le substrat de support comprend un matériau conducteur ;

    la première borne est électriquement accessible depuis une surface détournée du substrat de support ; et

    la deuxième borne est électriquement couplée au substrat de support.


     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description