(19)
(11)EP 3 196 887 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
04.12.2019 Bulletin 2019/49

(21)Application number: 16192219.0

(22)Date of filing:  04.10.2016
(51)International Patent Classification (IPC): 
G11C 17/16(2006.01)
G11C 7/24(2006.01)
H01L 27/112(2006.01)
H04L 9/32(2006.01)
G11C 17/18(2006.01)
G06F 21/73(2013.01)
G11C 16/22(2006.01)

(54)

ONE TIME PROGRAMMING MEMORY CELL AND MEMORY ARRAY FOR PHYSICALLY UNCLONABLE FUNCTION TECHNOLOGY AND ASSOCIATED RANDOM CODE GENERATING METHOD

SPEICHERZELLE UND SPEICHERARRAY MIT EINMALIGER PROGRAMMIERUNG FÜR PHYSIKALISCH UNKLONBARE FUNKTIONSTECHNOLOGIE UND ZUGEHÖRIGES ZUFALLSCODEERZEUGUNGSVERFAHREN

CELLULE DE MÉMOIRE À PROGRAMMATION UNIQUE ET RÉSEAU DE MÉMOIRE POUR UNE TECHNOLOGIE DE FONCTION PHYSIQUEMENT NON CLONABLE ET PROCÉDÉ DE GÉNÉRATION DE CODE ALÉATOIRE ASSOCIÉ


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 19.01.2016 US 201662280137 P

(43)Date of publication of application:
26.07.2017 Bulletin 2017/30

(60)Divisional application:
19203016.1

(73)Proprietor: eMemory Technology Inc.
Hsin-Chu 30075 (TW)

(72)Inventors:
  • Wong, Wei-Zhe
    Zhubei City 302 (TW)
  • Chen, Hsin-Ming
    Hsinchu City 300 (TW)
  • Wu, Meng-Yi
    Zhubei City 302 (TW)

(74)Representative: dompatent von Kreisler Selting Werner - Partnerschaft von Patent- und Rechtsanwälten mbB 
Deichmannhaus am Dom Bahnhofsvorplatz 1
50667 Köln
50667 Köln (DE)


(56)References cited: : 
CN-A- 103 730 164
US-A1- 2006 291 267
US-A1- 2011 044 107
US-A- 5 847 987
US-A1- 2008 074 915
US-A1- 2015 312 036
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    FIELD OF THE INVENTION



    [0001] The present invention relates to a memory cell and a memory array, and more particularly to a one time programming memory cell and a memory array for a physically unclonable function (PUF) technology and associated random code generating method.

    BACKGROUND OF THE INVENTION



    [0002] A physically unclonable function (PUF) technology is a novel method for protecting the data of a semiconductor chip. That is, the use of the PUF technology can prevent the data of the semiconductor chip from being stolen. In accordance with the PUF technology, the semiconductor chip is capable of providing a random code. This random code is used as a unique identity code (ID code) of the semiconductor chip to achieve the protecting function.

    [0003] Generally, the PUF technology acquires the random code of the semiconductor chip according to the manufacturing variation of the semiconductor chip. This manufacturing variation includes semiconductor process variation. That is, even if the PUF semiconductor chip is produced by a precise fabricating process, the random code cannot be duplicated. Consequently, the PUF semiconductor chip is suitably used in the applications with high security requirements.

    [0004] US 2008/0074915 discloses a one-time-programmable memory cell using two complementary antifuses. Because the two complementary antifuses in the one-time-programmable memory cell are directly connected with each other, there is no way to isolate the two complementary antifuses.

    [0005] US 2015/0312036 discloses a generation and a management of multiple base keys based on a device generated key. The key deriver of the device may include an OTP memory capable of generating a device generation key.

    SUMMARY OF THE INVENTION



    [0006] The present invention provides a one time programming memory cell and a memory array for a physically unclonable function (PUF) technology. The one time programming memory cell and the memory array capable of generating random codes are designed. After the program cycle, the random codes corresponding to the one time programming memory cell and a memory array are determined.

    [0007] An embodiment of the present invention provides a memory array. The memory array is connected with a first bit line (BL), a first inverted bit line (/BL), a first word line (WL), a first isolation line (IG), a first antifuse control line (AF1) and a second antifuse control line (AF2). The memory array comprises a first one time programming memory cell. The first one time programming memory cell comprises: a first selecting circuit (910) connected with the first bit line (BL), the first inverted bit line (/BL)and the first word line (WL); a first isolation circuit (916) connected with the first isolation control line (IG); a first antifuse storing circuit (912) connected with the first antifuse control line (AF1), the first isolation circuit (916) and the first selecting circuit (910); and a second antifuse storing circuit (914) connected with the second antifuse control line (AF2), the first isolation circuit (916) and the first selecting circuit (910), wherein during a program cycle, a select voltage is provided to the first word line (WL), a ground voltage is provided to the first bit line (BL) and the first inverted bit line (/BL), an on voltage is provided to the first isolation control line (IG), and a program voltage is provided to the first antifuse control line (AF1) and the second antifuse control line (AF2), wherein the first isolation circuit (916) is connected with the first antifuse storing circuit (912) and the second antifuse storing circuit (914), the first selecting circuit (910) provides the ground voltage to the first antifuse storing circuit (912) and the second antifuse storing circuit (914), and the program voltage is applied to both of the first antifuse storing circuit (912) and the second antifuse storing circuit (914), so that a storing state of the first antifuse storing circuit (912) or the second antifuse storing circuit (914) is changed, wherein during a read cycle, the select voltage is provided to the first word line (WL), the ground voltage is provided to the first bit line (BL) and the first inverted bit line (/BL), a read voltage is provided to the first antifuse control line (AF1) and the second antifuse storing circuit (AF2), and an off voltage is provided to the first isolation control line (IG), so that the first antifuse storing circuit (912) generates a first read current to the first bit line (BL) and the second antifuse storing circuit (914) generates a second read current to the first inverted bit line (/BL), wherein one bit of a random code for a physically unclonable function technology is realized according to the first read current of the first antifuse storing circuit (912).

    [0008] Numerous objects, features and advantages of the present invention will be readily apparent upon a reading of the following detailed description of embodiments of the present invention when taken in conjunction with the accompanying drawings. However, the drawings employed herein are for the purpose of descriptions and should not be regarded as limiting.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0009] The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

    FIG. 1A is a schematic top view of a one time programming memory cell according to a first embodiment of the present invention;

    FIG. 1B is a schematic equivalent circuit diagram of the one time programming memory cell according to the first embodiment of the present invention;

    FIGS. 2A∼2B schematically illustrate associated voltage signals for programming and reading the memory array for the PUF technology according to the first embodiment of the present invention;

    FIG. 3A is a schematic equivalent circuit diagram illustrating a memory array of OTP memory cells according to the first embodiment of the present invention;

    FIGS. 3B∼3C schematically illustrate associated voltage signals for programming and reading the memory array for the PUF technology according to the first embodiment of the present invention;

    FIG. 4A is a schematic top view of a one time programming memory cell according to a second embodiment of the present invention;

    FIG. 4B is a schematic cross-sectional view of the antifuse-type one time programming memory cell of FIG. 4A and taken along a line AA';

    FIG. 4C is a schematic equivalent circuit diagram of the one time programming memory cell according to the second embodiment of the present invention;

    FIGS. 5A∼5C schematically illustrate associated voltage signals for programming and reading the OTP memory cell for the PUF technology according to the second embodiment of the present invention;

    FIG. 6A is a schematic equivalent circuit diagram illustrating a memory array of OTP memory cells according to the second embodiment of the present invention;

    FIGS. 6B∼6D schematically illustrate associated voltage signals for programming and reading the memory array for the PUF technology according to the second embodiment of the present invention;

    FIG. 7A is a schematic top view of a one time programming memory cell according to a third embodiment of the present invention;

    FIG. 7B is a schematic equivalent circuit diagram of the one time programming memory cell according to the third embodiment of the present invention;

    FIGS. 8A∼8B schematically illustrate associated voltage signals for programming and reading the memory array for the PUF technology according to the third embodiment of the present invention;

    FIG. 9A is a schematic equivalent circuit diagram illustrating a memory array of OTP memory cells according to the third embodiment of the present invention;

    FIGS. 9B∼9C schematically illustrate associated voltage signals for programming and reading the memory array for the PUF technology according to the third embodiment of the present invention;

    FIG. 10A is a schematic top view of a one time programming memory cell according to a fourth embodiment of the present invention;

    FIG. 10B is a schematic equivalent circuit diagram of the one time programming memory cell according to the fourth embodiment of the present invention;

    FIGS. 11A∼11B schematically illustrate associated voltage signals for programming and reading the memory array for the PUF technology according to the fourth embodiment of the present invention;

    FIG. 12A is a schematic equivalent circuit diagram illustrating a memory array of OTP memory cells according to the fourth embodiment of the present invention;

    FIGS. 12B∼12C schematically illustrate associated voltage signals for programming and reading the memory array for the PUF technology according to the fourth embodiment of the present invention; and

    FIG. 13 is a schematic functional diagram illustrating the first type OTP memory cell of the present invention.


    DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS



    [0010] As is well known, a non-volatile memory is able to continuously retain data after the supplied power is interrupted. A one time programming memory (also referred as an OTP memory) is one kind of non-volatile memory. The OTP memory can be programmed once. After the OTP memory is programmed, the stored data fails to be modified.

    [0011] Moreover, depending on the characteristics, the OTP memories may be classified into two types, i.e., a fuse-type OTP memory and an antifuse-type OTP memory. Before a memory cell of the antifuse-type OTP memory is programmed, the memory cell has a high-resistance storage state. After the memory cell of the antifuse-type OTP memory is programmed, the memory cell has a low-resistance storage state. The present invention related to a novel antifuse-type OTP memory. Some examples of the antifuse-type OTP memory will be illustrated as follows.

    [0012] FIG. 1A is a schematic top view of a one time programming memory cell according to a first embodiment of the present invention. FIG. 1B is a schematic equivalent circuit diagram of the one time programming memory cell according to the first embodiment of the present invention. In comparison with the first embodiment, the OTP memory cell of this embodiment is a differential memory cell.

    [0013] As shown in FIG. 1A, the OTP memory cell c1 comprises a first doped region 210, a second doped region 220, a third doped region 230, a fourth doped region 240, a fifth doped region 250 and a sixth doped region 260. A first gate 215 is formed on a gate oxide layer (not shown) and spanned over the first doped region 210 and the second doped region 220. Moreover, the first gate 215 is connected with a word line WL of the memory cell c1. A second gate 225 is formed on the gate oxide layer and spanned over the second doped region 220 and the third doped region 230. Moreover, the second gate 225 is connected with a first antifuse control line AF1 of the memory cell c1. A third gate 235 is formed on the gate oxide layer and spanned over the third doped region 230 and the fourth doped region 240. Moreover, the third gate 235 is connected with an isolation control line IG of the memory cell c1. A fourth gate 245 is formed on the gate oxide layer and spanned over the fourth doped region 240 and the fourth doped region 250. Moreover, the fourth gate 245 is connected with a second antifuse control line AF2 of the memory cell c1. A fifth gate 255 is formed on the gate oxide layer and spanned over the fifth doped region 250 and the sixth doped region 260. Moreover, the fifth gate 255 is connected with the word line WL of the memory cell c1. In this embodiment, the five gates 215, 225, 235, 245 and 255 are polysilicon gates or metal gates.

    [0014] A first metal layer 272 is connected with the first doped region 210 through a via. Moreover, first metal layer 272 is used as a bit line BL of the memory cell c1. A second metal layer 274 is connected with the sixth doped region 260 through another via. Moreover, the second metal layer 274 is used as an inverted bit line BL of the memory cell c1. A third metal layer 270 is connected with the first gate 215 and the fifth gate 255.

    [0015] Please refer to FIG. 1B. The first doped region 210, the second doped region 220 and the first gate 215 are collaboratively formed as a first select transistor S1. The second doped region 220, the third doped region 230 and the second gate 225 are collaboratively formed as a first antifuse transistor A1. The third doped region 230, the fourth doped region 240 and the third gate 235 are collaboratively formed as an isolation transistor O. The fourth doped region 240, the fifth doped region 250 and the fourth gate 245 are collaboratively formed as a second antifuse transistor A2. The fifth doped region 250, the sixth doped region 260 and the fifth gate 255 are collaboratively formed as a second select transistor S2.

    [0016] The first select transistor S1, the first antifuse transistor A1, the isolation transistor O, the second antifuse transistor A2 and the second select transistor S2 are serially connected between the bit line BL and the inverted bit line BL. The gate terminal of the first select transistor S1 is connected with the word line WL. The gate terminal of the first antifuse transistor A1 is connected with a first antifuse control line AF1. The gate terminal of the isolation transistor O is connected with an isolation control line IG. The gate terminal of the second antifuse transistor A2 is connected with a second antifuse control line AF2. The gate terminal of the second select transistor S2 is connected with the word line WL.

    [0017] In accordance with the first embodiment, the OTP memory cell c1 comprises two storing circuits. That is, the first antifuse transistor A1 is a first storing circuit, and the second antifuse transistor A2 is a second storing circuit. During the program cycle of the OTP memory cell c1, the high voltage stress is applied to both of the first antifuse transistor A1 and the second antifuse transistor A2. Under this circumstance, the gate oxide layer of one of the first antifuse transistor A1 and the second antifuse transistor A2 is ruptured. Consequently, the storing state of the first antifuse transistor A1 or the second antifuse transistor A2 is changed. During the read cycle of the OTP memory cell c1, the storing states of the first antifuse transistor A1 and the second antifuse transistor A2 are directly read, and the storing states thereof are used as the random code of the PUF technology. It is noted that the storing state is capable of indicating the ruptured condition of the antifuse transistor. For example, a first storing state means the gate oxide layer of the antifuse transistor is ruptured, and a second storing state means the gate oxide layer of the antifuse transistor is not ruptured.

    [0018] FIGS. 2A∼2B schematically illustrate associated voltage signals for programming and reading the memory array for the PUF technology according to the first embodiment of the present invention. Please refer to FIG. 2A. For programming the selected OTP memory cell c1, a ground voltage (0V) is provided to the bit line BL and the inverted bit line BL, a select voltage Vdd is provided to the word line WL, a program voltage Vpp is provided to the first antifuse control line AF1 and the second antifuse control line AF2, and a second voltage V2 is provided to the isolation line IG. In an embodiment, the select voltage Vdd is in the range between 0.75V and 3.6V, and the program voltage Vpp is in the range between 3.6V and 11V. Moreover, the second voltage V2 is larger than or equal to the select voltage Vdd and smaller than three-fourths of the program voltage Vpp (i.e., Vdd ≤ V2 < 3Vpp/4).

    [0019] During the program cycle, the third doped region 230 and the fourth doped region 240 are connected to each other by turning on the isolation transistor O. Consequently, a bias voltage Vpp is applied to the gate oxide layer of the first antifuse transistor A1 and the gate oxide layer of the second antifuse transistor A2. Since the program voltage Vpp is beyond the withstanding voltage range of the gate oxide layer, the gate oxide layer of one of the first antifuse transistor A1 and the second antifuse transistor A2 is ruptured. The ruptured gate oxide layer may be considered as a resistor with a low resistance value.

    [0020] Due to the manufacturing variation of the OTP memory cell c1, the gate oxide layer of which antifuse transistor is ruptured during the program cycle cannot be realized. Consequently, the OTP memory cell c1 can utilize the PUF technology. Take the OTP memory cell c1 of FIG. 2A as an example. During the program cycle, the gate oxide layer of the first antifuse transistor A1 is not ruptured, but the gate oxide layer of the second antifuse transistor A2 is ruptured.

    [0021] After the OTP memory cell c1 is programmed, one read action is performed to judge the storing states of the two storing circuits. Please refer to FIG. 2B. During the read cycle of the OTP memory cell c1, the ground voltage (0V) is provided to the bit line BL and the inverted bit line BL, the select voltage Vdd is provided to the word line WL, a read voltage Vr is provided to the first antifuse control line AF1 and the second antifuse control line AF2, and the ground voltage (0V) is provided to the isolation control line IG. In an embodiment, the read voltage Vr is in the range between 0.75V and 3.6V.

    [0022] Since the third doped region 230 and the fourth doped region 240 are isolated by turning off the isolation transistor O, a first read current Ir1 having a small value (i.e., nearly zero) is provided from the first antifuse transistor A1 to the bit line BL, and a second read current Ir2 having a higher value is provided from the second antifuse transistor A2 to the inverted bit line BL. According to the first read current Ir1 and the second read current Ir2, the first antifuse transistor A1 (i.e., the first storing circuit) is verified to have a second storing state corresponding to the high resistance value, and the second antifuse transistor A2 (i.e., the second storing circuit) is verified to have a first storing state corresponding to the low resistance value.

    [0023] Then, according to the storing states of the first antifuse transistor A1 (i.e., the first storing circuit) and the second antifuse transistor A2 (i.e., the second storing circuit), one bit of the random code is determined and applied to the PUF technology.

    [0024] Alternatively, one bit of the random code can be determined by using a differential sensing operation. For example, if the first read current Ir1 is larger than the second read current Ir2, the OTP memory cell c1 is defined as a first storing state; and if the first read current Ir1 is smaller than the second read current Ir2, the OTP memory cell c1 is defined as a second storing state.

    [0025] FIG. 3A is a schematic equivalent circuit diagram illustrating a memory array of OTP memory cells according to the first embodiment of the present invention. As shown in FIG. 3A, the memory array comprises OTP memory cells c11∼c22 in a 2×2 array. The structure of each of the OTP memory cells c11∼c22 is similar to the structure of the OTP memory cell as shown in FIG. 2A. In this embodiment, each of the OTP memory cells c11∼c22 comprises a first select transistor S1, a second select transistor S2, a first antifuse transistor A1, a second antifuse transistor A2 and an isolation transistor O.

    [0026] FIGS. 3B∼3C schematically illustrate associated voltage signals for programming and reading the memory array for the PUF technology according to the first embodiment of the present invention. For example, the OTP memory cell c22 is a selected memory cell.

    [0027] Please refer to FIG. 3B. For programming the selected OTP memory cell c22, a ground voltage (0V) is provided to a second bit line BL2 and a second inverted bit line BL2, a select voltage Vdd is provided to a second word line WL2, a program voltage Vpp is provided to a third antifuse control line AF3 and a fourth antifuse control line AF4, and a second voltage V2 is provided to a second isolation control line IG2. In an embodiment, the select voltage Vdd is in the range between 0.75V and 3.6V, and the program voltage Vpp is in the range between 3.6V and 11V. Moreover, the second voltage V2 is larger than or equal to the select voltage Vdd and smaller than three-fourths of the program voltage Vpp (i.e., Vdd ≤ V2 < 3Vpp/4).

    [0028] The memory cells c12, c21 and c22 are unselected memory cells. For these unselected memory cells, a first voltage V1 is provided to a first bit line BL1 and a first inverted bit line BL1, the ground voltage (0V) is provided to a first word line WL1, and the ground voltage (0V) is provided to a first antifuse control line AF1, a second antifuse control line AF2 and a first isolation control line IG1. In an embodiment, the first voltage V1 is equal to or larger than the select voltage Vdd, and the first voltage V1 is smaller than a half of the program voltage Vpp (i.e., Vdd≤V1<Vpp/2).

    [0029] Please refer to FIG. 3B again. Since the memory cell c22 is the selected memory cell, the bias voltage Vpp is applied to the gate oxide layer of the first antifuse transistor A1 and the gate oxide layer of the second antifuse transistor A2. Consequently, the gate oxide layer of one of the first antifuse transistor A1 and the second antifuse transistor A2 is ruptured. The ruptured gate oxide layer may be considered as a resistor with a low resistance value. For example, in the memory cell c22 as shown in FIG. 3B, the gate oxide layer of the first antifuse transistor A1 is not ruptured, but the gate oxide layer of the second antifuse transistor A2 is ruptured.

    [0030] In case that the OTP memory cell c11, c12 or c21 is the selected memory cell, the bias voltages for performing the programming process are similar to those for the memory cell c22. The detailed description thereof is not redundantly described herein.

    [0031] After the memory cell c22 is completely programmed, one read action is performed to confirm the storing states of the two storing circuits of the memory cell c22. Please refer to FIG. 3C. During the read cycle of the selected memory cell c22, a ground voltage (0V) is provided to the second bit line BL2 and the second inverted bit line BL2, the select voltage Vdd is provided to a second word line WL2, a read voltage Vr is provided to the first antifuse control line AF1 and the second antifuse control line AF2, and the ground voltage (0V) is provided to a second isolation control line IG2. In an embodiment, the read voltage Vr is in the range between 0.75V and 3.6V.

    [0032] For the unselected memory cells c11, c12 and c21, the first bit line BL1 and the first inverted bit line BL1 are in a floating state, the ground voltage (0V) is provided to the first word line WL1, and the ground voltage (0V) is provided to the first antifuse control line AF1, the second antifuse control line AF2 and the first isolation control line IG1.

    [0033] In the selected memory cell c22, since the gate oxide layer of the first antifuse transistor A1 is not ruptured, a first read current Ir1 flowing through the second bit line BL2 has a small value (i.e., nearly zero) and a second read current Ir2 flowing through the second inverted bit line BL2 has a higher value. According to the first read current Ir1 and the second read current Ir2, the first antifuse transistor A1 (i.e., the first storing circuit) is verified to have a second storing state corresponding to the high resistance value, and the second antifuse transistor A2 (i.e., the second storing circuit) is verified to have a first storing state corresponding to the low resistance value.

    [0034] From the above descriptions, one read action is performed to confirm the storing states of the two storing circuits and determine one bit of the random code.

    [0035] Moreover, after the program actions and the read actions of the four memory cells c11∼c22 are performed, a four-bit random code for the PUF technology is generated.

    [0036] FIG. 4A is a schematic top view of a one time programming memory cell according to a second embodiment of the present invention. FIG. 4B is a schematic cross-sectional view of the antifuse-type one time programming memory cell of FIG. 4A and taken along a line AA'. FIG. 4C is a schematic equivalent circuit diagram of the one time programming memory cell according to the second embodiment of the present invention.

    [0037] As shown in FIGS. 4A and 4B, the OTP memory cell c1 is constructed in a P-well region PW. A gate oxide layer 352 covers the top surface of the P-well region PW. After a first etching process to thin out the gate oxide layer 352 and a second etching process to form openings, a first doped region 310, a second doped region 320 and a third doped region 330 are formed under a top surface of the P-well region PW. In this embodiment, the gate oxide layer 352 has a thinner part 352a. Moreover, the first doped region 310, the second doped region 320 and the third doped region 330 are N-type doped regions.

    [0038] A first gate 315 is formed on the gate oxide layer 352 and spanned over the first doped region 310 and the second doped region 320. Moreover, the first gate 315 is connected with a first antifuse control line AF1 of the memory cell c1. A second gate 325 is formed on the gate oxide layer 352 and spanned over the second doped region 320 and the third doped region 330. Moreover, the second gate 325 is connected with a second antifuse control line AF2 of the memory cell c1. In this embodiment, the two gates 315 and 325 are polysilicon gates or metal gates.

    [0039] A metal layer 360 is disposed over the two gates 315 and 325. Moreover, the metal layer 360 is connected with the first doped region 310 and the third doped region 330 through two vias. The metal layer 360 is used as a bit line BL of the memory cell c1.

    [0040] Please refer to FIG. 4C. The first doped region 310, the second doped region 320 and the first gate 315 are collaboratively formed as a first antifuse transistor A1. The second doped region 320, the third doped region 330 and the second gate 325 are collaboratively formed as a second antifuse transistor A2. The gate oxide layer 352 comprises a first part and a second part. The second part is the thinner part 352a. That is, the second part is thinner than the first part. In this embodiment, the first gate 315 covers the first part and the second part of the gate oxide layer 352. Similarly, the second gate 325 covers the first part and the second part of the gate oxide layer 352.

    [0041] The first drain/source terminal of the first antifuse transistor A1 is connected with the bit line BL. The gate terminal of the first antifuse transistor A1 is connected with a first antifuse control line AF1. The first drain/source terminal of the second antifuse transistor A2 is connected with the second drain/source terminal of the first antifuse transistor A1. The gate terminal of the second antifuse transistor A2 is connected with a second antifuse control line AF2. The second drain/source terminal of the second antifuse transistor A2 is connected with the bit line BL.

    [0042] In accordance with the second embodiment, the OTP memory cell c1 comprises two storing circuits. That is, the first antifuse transistor A1 is a first storing circuit, and the second antifuse transistor A2 is a second storing circuit. During the program cycle of the OTP memory cell c1, the high voltage stress is applied to both of the first antifuse transistor A1 and the second antifuse transistor A2. Under this circumstance, the gate oxide layer of one of the first antifuse transistor A1 and the second antifuse transistor A2 is ruptured. Consequently, the storing state of the first antifuse transistor A1 or the second antifuse transistor A2 is changed. Generally, the second part (i.e., the thinner part 352a) of the gate oxide layer 352 is ruptured more easily than the first part (i.e., the thicker part) of the gate oxide layer 352.

    [0043] During the read cycle, the storing states of the first antifuse transistor A1 and the second antifuse transistor A2 are sequentially read, and the storing state of the first antifuse transistor A1 is used as the random code of the PUF technology.

    [0044] FIGS. 5A∼5C schematically illustrate associated voltage signals for programming and reading the OTP memory cell for the PUF technology according to the second embodiment of the present invention.

    [0045] Please refer to FIG. 5A. For programming the OTP memory cell, a ground voltage (0V) is provided to the bit line BL, and a program voltage Vpp is provided to the first antifuse control line AF1 and the second antifuse control line AF2. In an embodiment, the program voltage Vpp is in the range between 3.6V and 11V.

    [0046] Since the program voltage Vpp is beyond the withstanding voltage range of the gate oxide layer, the gate oxide layer of one of the first antifuse transistor A1 and the second antifuse transistor A2 is ruptured. The ruptured gate oxide layer may be considered as a resistor with a low resistance value. When the second part (i.e., the thinner part) of the gate oxide layer 352 is ruptured, it means that the gate oxide layer 352 is ruptured.

    [0047] Due to the manufacturing variation of the OTP memory cell c1, the gate oxide layer of which antifuse transistor is ruptured during the program cycle cannot be realized. Consequently, the OTP memory cell c1 can utilize the PUF technology. Take the OTP memory cell c1 of FIG. 5A as an example. During the program cycle, the gate oxide layer of the first antifuse transistor A1 is ruptured, but the gate oxide layer of the second antifuse transistor A2 is not ruptured.

    [0048] After the OTP memory cell c1 is programmed, two read actions are performed to judge the storing states of the two storing circuits. Please refer to FIG. 5B. During the first read cycle, the ground voltage (0V) is provided to the bit line BL, a read voltage Vr is provided to the first antifuse control line AF1, and the ground voltage (0V) is provided to the second antifuse control line AF2. In an embodiment, the read voltage Vr is in the range between 0.75V and 3.6V.

    [0049] Since the gate oxide layer of the first antifuse transistor A1 is ruptured, a first read current Ir1 flowing through the bit line BL has a larger value. According to the first read current Ir1, the first antifuse transistor A1 (i.e., the first storing circuit) is verified to have a first storing state corresponding to the low resistance value.

    [0050] Please refer to FIG. 5C. During the second read cycle, the ground voltage (0V) is provided to the bit line BL, and the ground voltage (0V) is provided to the first antifuse control line AF1, and the read voltage Vr is provided to the second antifuse control line AF2.

    [0051] Since the gate oxide layer of the second antifuse transistor A2 is not ruptured, a second read current Ir2 flowing through the bit line BL has a small value (i.e., nearly zero). According to the second read current Ir2, the second antifuse transistor A2 (i.e., the second storing circuit) is verified to have a second storing state corresponding to the high resistance value.

    [0052] Then, according to the storing states of the first antifuse transistor A1 (i.e., the first storing circuit) and the second antifuse transistor A2 (i.e., the second storing circuit), one bit of the random code is determined and applied to the PUF technology.

    [0053] From the above descriptions, two read actions are performed to confirm the storing states of the two storing circuits and determine one bit of the random code. However, since the storing states are complementary to each other, one bit of the random code can be determined by reading the storing state of only one storing circuit.

    [0054] FIG. 6A is a schematic equivalent circuit diagram illustrating a memory array of OTP memory cells according to the second embodiment of the present invention. As shown in FIG. 6A, the memory array comprises OTP memory cells c11∼c22 in a 2×2 array. The structure of each of the OTP memory cells c11∼c22 is similar to the structure of the OTP memory cell as shown in FIG. 5A. In this embodiment, each of the OTP memory cells c11∼c22 comprises a first antifuse transistor A1 and a second antifuse transistor A2.

    [0055] FIGS. 6B∼6D schematically illustrate associated voltage signals for programming and reading the memory array for the PUF technology according to the second embodiment of the present invention. For example, the OTP memory cell c12 is a selected memory cell.

    [0056] Please refer to FIG. 6B. For programming the selected OTP memory cell c12, a ground voltage (0V) is provided to a first bit line BL1, and a program voltage Vpp is provided to a third antifuse control line AF3 and a fourth antifuse control line AF4. In an embodiment, the program voltage Vpp is in the range between 3.6V and 11V.

    [0057] The memory cells c11, c21 and c22 are unselected memory cells. For these unselected memory cells, a first voltage V1 is provided to a second bit line BL2, and the ground voltage (0V) is provided to a first antifuse control line AF1 and a second antifuse control line AF2. In an embodiment, the first voltage V1 is about the program voltage Vpp.

    [0058] Please refer to FIG. 6B again. Since the memory cell c12 is the selected memory cell, the bias voltage Vpp is applied to the gate oxide layer of the first antifuse transistor A1 and the gate oxide layer of the second antifuse transistor A2. Consequently, the gate oxide layer of one of the first antifuse transistor A1 and the second antifuse transistor A2 is ruptured. The ruptured gate oxide layer may be considered as a resistor with a low resistance value. For example, in the memory cell c12 as shown in FIG. 6B, the gate oxide layer of the first antifuse transistor A1 is ruptured, but the gate oxide layer of the second antifuse transistor A2 is not ruptured. When the second part (i.e., the thinner part) of the gate oxide layer 352 is ruptured, it means that the gate oxide layer 352 is ruptured.

    [0059] In case that the OTP memory cell c11, c21 or c22 is the selected memory cell, the bias voltages for performing the programming process are similar to those for the memory cell c12. The detailed description thereof is not redundantly described herein.

    [0060] After the selected memory cell c12 is programmed, two read actions are performed to judge the storing states of the two storing circuits of the selected memory cell c12. Please refer to FIG. 6C. During the first read cycle of the selected memory cell c12, the ground voltage (0V) is provided to the first bit line BL1, a read voltage Vr is provided to the third antifuse control line AF3, and the ground voltage (0V) is provided to the fourth antifuse control line AF4. In an embodiment, the read voltage Vr is in the range between 0.75V and 3.6V.

    [0061] For the unselected memory cells c11, c21 and c22, the second bit line BL2 is in a floating state, and the ground voltage (0V) is provided to the first antifuse control line AF1 and the second antifuse control line AF2.

    [0062] In the selected memory cell c12, since the gate oxide layer of the first antifuse transistor A1 is ruptured, a first read current Ir1 flowing through the first bit line BL1 has a larger value. According to the first read current Ir1, the first antifuse transistor A1 (i.e., the first storing circuit) is verified to have a first storing state corresponding to the low resistance value.

    [0063] Please refer to FIG. 6D. During the second read cycle of the selected memory cell c12, the ground voltage (0V) is provided to the first bit line BL1, the ground voltage (0V) is provided to the third antifuse control line AF3, and a read voltage Vr is provided to the fourth antifuse control line AF4.

    [0064] For the unselected memory cells c11, c21 and c22, the second bit line BL2 is in the floating state, and the ground voltage (0V) is provided to the first antifuse control line AF1 and the second antifuse control line AF2.

    [0065] In the selected memory cell c12, since the gate oxide layer of the second antifuse transistor A2 is not ruptured, a second read current Ir2 flowing through the first bit line BL1 has a small value (i.e., nearly zero). According to the second read current Ir2, the second antifuse transistor A2 (i.e., the second storing circuit) is verified to have a second storing state corresponding to the high resistance value. Then, according to the storing states of the first antifuse transistor A1 (i.e., the first storing circuit) and the second antifuse transistor A2 (i.e., the second storing circuit), one bit of the random code is determined and applied to the PUF technology.

    [0066] From the above descriptions, two read actions are performed to confirm the storing states of the two storing circuits and determine one bit of the random code. However, since the storing states are complementary to each other, one bit of the random code can be determined by reading the storing state of only one storing circuit.

    [0067] Moreover, after the program actions and the read actions of the four memory cells c11∼c22 are performed, a four-bit random code for the PUF technology is generated.

    [0068] FIG. 7A is a schematic top view of a one time programming memory cell according to a third embodiment of the present invention. FIG. 7B is a schematic equivalent circuit diagram of the one time programming memory cell according to the third embodiment of the present invention. In comparison with the second embodiment, the OTP memory cell of this embodiment is a differential memory cell.

    [0069] As shown in FIG. 7A, the OTP memory cell c1 comprises a first doped region 410, a second doped region 420, a third doped region 430 and a fourth doped region 440. A first gate 415 is formed on a gate oxide layer (not shown) and spanned over the first doped region 410 and the second doped region 420. Moreover, the first gate 415 is connected with a first antifuse control line AF1 of the memory cell c1. A second gate 425 is formed on the gate oxide layer and spanned over the second doped region 420 and the third doped region 430. Moreover, the second gate 425 is connected with an isolation control line IG of the memory cell c1. A third gate 435 is formed on the gate oxide layer and spanned over the third doped region 430 and the fourth doped region 440. Moreover, the third gate 435 is connected with a second antifuse control line AF2 of the memory cell c1. In this embodiment, the five gates 415, 425 and 435 are polysilicon gates or metal gates.

    [0070] A first metal layer 460 is connected with the first doped region 410 through a via. Moreover, first metal layer 460 is used as a bit line BL of the memory cell c1. A second metal layer 462 is connected with the fourth doped region 440 through another via. Moreover, the second metal layer 462 is used as an inverted bit line BL.

    [0071] Please refer to FIG. 7B. The first doped region 410, the second doped region 420 and the first gate 415 are collaboratively formed as a first antifuse transistor A1. The second doped region 420, the third doped region 430 and the second gate 425 are collaboratively formed as an isolation transistor O. The third doped region 430, the fourth doped region 440 and the third gate 435 are collaboratively formed as a second antifuse transistor A2. The gate oxide layer comprises a first part and a second part. The second part is the thinner part 452a. That is, the second part is thinner than the first part. In this embodiment, the first gate 415 covers the first part and the second part of the gate oxide layer. Similarly, the third gate 435 covers the first part and the second part of the gate oxide layer.

    [0072] The first antifuse transistor A1, the isolation transistor O and the second antifuse transistor A2 are serially connected between the bit line BL and the inverted bit line BL. The gate terminal of the first antifuse transistor A1 is connected with a first antifuse control line AF1. The gate terminal of the isolation transistor O is connected with an isolation control line IG. The gate terminal of the second antifuse transistor A2 is connected with a second antifuse control line AF2.

    [0073] In accordance with the third embodiment, the OTP memory cell c1 comprises two storing circuits. That is, the first antifuse transistor A1 is a first storing circuit, and the second antifuse transistor A2 is a second storing circuit. During the program cycle of the OTP memory cell c1, the high voltage stress is applied to both of the first antifuse transistor A1 and the second antifuse transistor A2. Under this circumstance, the gate oxide layer of one of the first antifuse transistor A1 and the second antifuse transistor A2 is ruptured. Consequently, the storing state of the first antifuse transistor A1 or the second antifuse transistor A2 is changed. Generally, the second part (i.e., the thinner part 452a) of the gate oxide layer is ruptured more easily than the first part (i.e., the thicker part) of the gate oxide layer.

    [0074] During the read cycle, the storing states of the first antifuse transistor A1 and the second antifuse transistor A2 are directly read, and the storing states thereof are used as the random code of the PUF technology.

    [0075] FIGS. 8A∼8B schematically illustrate associated voltage signals for programming and reading the memory array for the PUF technology according to the third embodiment of the present invention.

    [0076] Please refer to FIG. 8A. For programming the selected OTP memory cell c1, a ground voltage (0V) is provided to the bit line BL and the inverted bit line BL, a program voltage Vpp is provided to the first antifuse control line AF1 and the second antifuse control line AF2, and a second voltage V2 is provided to the isolation line IG. In an embodiment, the program voltage Vpp is in the range between 3.6V and 11V. Moreover, the second voltage V2 is larger than or equal to the select voltage Vdd and smaller than three-fourths of the program voltage Vpp (i.e., Vdd ≤ V2 < 3Vpp/4).

    [0077] Since the program voltage Vpp is beyond the withstanding voltage range of the gate oxide layer, the gate oxide layer of one of the first antifuse transistor A1 and the second antifuse transistor A2 is ruptured. The ruptured gate oxide layer may be considered as a resistor with a low resistance value. When the second part (i.e., the thinner part) of the gate oxide layer is ruptured, it means that the gate oxide layer is ruptured.

    [0078] Due to the manufacturing variation of the OTP memory cell c1, the gate oxide layer of which antifuse transistor is ruptured during the program cycle cannot be realized. Consequently, the OTP memory cell c1 can utilize the PUF technology. Take the OTP memory cell c1 of FIG. 8A as an example. During the program cycle, the gate oxide layer of the first antifuse transistor A1 is not ruptured, but the gate oxide layer of the second antifuse transistor A2 is ruptured.

    [0079] After the memory cell c1 is completely programmed, one read action is performed to confirm the storing states of the two storing circuits of the memory cell c1. After the OTP memory cell c1 is programmed, one read action is performed to judge the storing states of the two storing circuits.

    [0080] Please refer to FIG. 8B. During the read cycle, the ground voltage (0V) is provided to the bit line BL and the inverted bit line BL, a read voltage Vr is provided to the first antifuse control line AF1 and the second antifuse control line AF2, and the ground voltage (0V) is provided to the isolation control line IG. In an embodiment, the read voltage Vr is in the range between 0.75V and 3.6V.

    [0081] Since the gate oxide layer of the first antifuse transistor A1 is not ruptured but the gate oxide layer of the second antifuse transistor is ruptured, a first read current Ir1 flowing through the bit line BL has a small value (i.e., nearly zero) and a second read current Ir2 flowing through the inverted bit line BL has a larger value. According to the first read current Ir1 and the second read current Ir2, the first antifuse transistor A1 (i.e., the first storing circuit) is verified to have a second storing state corresponding to the high resistance value, and the second antifuse transistor A2 (i.e., the second storing circuit) is verified to have a first storing state corresponding to the low resistance value.

    [0082] From the above descriptions, one read action is performed to confirm the storing states of the two storing circuits and determine one bit of the random code.

    [0083] Alternatively, one bit of the random code can be determined by using a differential sensing operation. For example, if the first read current Ir1 is larger than the second read current Ir2, the OTP memory cell c1 is defined as a first storing state; and if the first read current Ir1 is smaller than the second read current Ir2, the OTP memory cell c1 is defined as a second storing state.

    [0084] FIG. 9A is a schematic equivalent circuit diagram illustrating a memory array of OTP memory cells according to the third embodiment of the present invention. As shown in FIG. 9A, the memory array comprises OTP memory cells c11∼c22 in a 2×2 array. The structure of each of the OTP memory cells c11∼c22 is similar to the structure of the OTP memory cell as shown in FIG. 7A. In this embodiment, each of the OTP memory cells c11∼c22 comprises a first antifuse transistor A1, a second antifuse transistor A2 and an isolation transistor O.

    [0085] FIGS. 9B∼9C schematically illustrate associated voltage signals for programming and reading the memory array for the PUF technology according to the third embodiment of the present invention. For example, the OTP memory cell c21 is a selected memory cell.

    [0086] Please refer to FIG. 9B. For programming the selected OTP memory cell c21, a ground voltage (0V) is provided to a second bit line BL2 and a second inverted bit line BL2, a program voltage Vpp is provided to a first antifuse control line AF1 and a second antifuse control line AF2, and a second voltage V2 is provided to a first isolation control line IG1. In an embodiment, the program voltage Vpp is in the range between 3.6V and 11V. Moreover, the second voltage V2 is larger than or equal to the select voltage Vdd and smaller than three-fourths of the program voltage Vpp (i.e., Vdd ≤ V2 < 3Vpp/4).

    [0087] The memory cells c11, c12 and c22 are unselected memory cells. For these unselected memory cells, a first voltage V1 is provided to a first bit line BL1 and a first inverted bit line BL1, and the ground voltage (0V) is provided to a third antifuse control line AF3, a fourth antifuse control line AF4 and a second isolation control line IG2. In an embodiment, the first voltage V1 is about the program voltage Vpp.

    [0088] Please refer to FIG. 9B again. Since the memory cell c21 is the selected memory cell, the bias voltage Vpp is applied to the gate oxide layer of the first antifuse transistor A1 and the gate oxide layer of the second antifuse transistor A2. Consequently, the gate oxide layer of one of the first antifuse transistor A1 and the second antifuse transistor A2 is ruptured. The ruptured gate oxide layer may be considered as a resistor with a low resistance value. For example, in the memory cell c21 as shown in FIG. 9B, the gate oxide layer of the first antifuse transistor A1 is not ruptured, but the gate oxide layer of the second antifuse transistor A2 is ruptured. When the second part (i.e., the thinner part) of the gate oxide layer is ruptured, it means that the gate oxide layer is ruptured.

    [0089] In case that the OTP memory cell c11, c12 or c22 is the selected memory cell, the bias voltages for performing the programming process are similar to those for the memory cell c21. The detailed description thereof is not redundantly described herein.

    [0090] After the memory cell c21 is completely programmed, one read action is performed to confirm the storing states of the two storing circuits of the memory cell c21. Please refer to FIG. 9C. During the read cycle of the selected memory cell c21, a ground voltage (0V) is provided to the second bit line BL2 and the second inverted bit line BL2, a read voltage Vr is provided to the first antifuse control line AF1 and the second antifuse control line AF2, and the ground voltage (0V) is provided to a first isolation control line IG1. In an embodiment, the read voltage Vr is in the range between 0.75V and 3.6V.

    [0091] For the unselected memory cells c11, c12 and c22, the first bit line BL1 and the first inverted bit line BL1 are in a floating state, and the ground voltage (0V) is provided to the third antifuse control line AF3, the fourth antifuse control line AF4 and the second isolation control line IG2.

    [0092] In the selected memory cell c21, since the gate oxide layer of the first antifuse transistor A1 is not ruptured but the gate oxide layer of the second antifuse transistor is ruptured, a first read current Ir1 flowing through the second bit line BL2 has a small value (i.e., nearly zero) and a second read current Ir2 flowing through the second inverted bit line BL2 has a larger value. According to the first read current Ir1 and the second read current Ir2, the first antifuse transistor A1 (i.e., the first storing circuit) is verified to have a second storing state corresponding to the high resistance value, and the second antifuse transistor A2 (i.e., the second storing circuit) is verified to have a first storing state corresponding to the low resistance value.

    [0093] Then, according to the storing states of the first antifuse transistor A1 (i.e., the first storing circuit) and the second antifuse transistor A2 (i.e., the second storing circuit), one bit of the random code is determined and applied to the PUF technology.

    [0094] Moreover, after the program actions and the read actions of the four memory cells c11∼c22 are performed, a four-bit random code for the PUF technology is generated.

    [0095] FIG. 10A is a schematic top view of a one time programming memory cell according to a fourth embodiment of the present invention. FIG. 10B is a schematic equivalent circuit diagram of the one time programming memory cell according to the fourth embodiment of the present invention. In comparison with the fifth embodiment, the OTP memory cell of this embodiment is a differential memory cell.

    [0096] As shown in FIG. 10A, the OTP memory cell c1 comprises a first doped region 610, a second doped region 620, a third doped region 630, a fourth doped region 640, a fifth doped region 650, a sixth doped region 660, a sixth doped region 670 and an eighth doped region 680. A first gate 615 is formed on a gate oxide layer (not shown) and spanned over the first doped region 610 and the second doped region 620. Moreover, the first gate 615 is connected with a word line WL of the memory cell c1. A second gate 625 is formed on the gate oxide layer and spanned over the second doped region 620 and the third doped region 630. Moreover, the second gate 625 is connected with a switch control line SW of the memory cell c1. A third gate 635 is formed on the gate oxide layer and spanned over the third doped region 630 and the fourth doped region 640. Moreover, the third gate 635 is connected with a first antifuse control line AF1 of the memory cell c1. A fourth gate 645 is formed on the gate oxide layer and spanned over the fourth doped region 640 and the fourth doped region 650. Moreover, the fourth gate 645 is connected with an isolation control line IG of the memory cell c1. A fifth gate 655 is formed on the gate oxide layer and spanned over the fifth doped region 650 and the sixth doped region 660. Moreover, the fifth gate 655 is connected with a second antifuse control line AF2 of the memory cell c1. A sixth gate 665 is formed on the gate oxide layer and spanned over the sixth doped region 660 and the seventh doped region 670. Moreover, the sixth gate 665 is connected with the switch control line SW of the memory cell c1. A seventh gate 675 is formed on the gate oxide layer and spanned over the seventh doped region 670 and the eighth doped region 680. Moreover, the seventh gate 675 is connected with the word line WL of the memory cell c1.

    [0097] A first metal layer 692 is connected with the first doped region 610 through a via. Moreover, first metal layer 692 is used as a bit line BL of the memory cell c1. A second metal layer 694 is connected with the eighth doped region 680 through another via. Moreover, the second metal layer 694 is used as an inverted bit line BL. The first gate 615 and the fifth gate 675a are connected with each other through a third metal layer 696. The second gate 625 and the sixth gate 665 are connected with each other through a fourth metal layer 698.

    [0098] Please refer to FIG. 10B. The first doped region 610, the second doped region 620 and the first gate 625 are collaboratively formed as a first select transistor S1. The second doped region 620, the third doped region 630 and the second gate 625 are collaboratively formed as a first switch transistor W1. The third doped region 630, the fourth doped region 640 and the third gate 635 are collaboratively formed as a first antifuse transistor A1. The fourth doped region 640, the fifth doped region 650 and the fourth gate 645 are collaboratively formed as an isolation transistor O. The fifth doped region 650, the sixth doped region 660 and the fifth gate 655 are collaboratively formed as a second antifuse transistor A2. The sixth doped region 660, the seventh doped region 670 and the sixth gate 665 are collaboratively formed as a second switch transistor W2. The seventh doped region 670, the eighth doped region 680 and the seventh gate 675 are collaboratively formed as a second select transistor S2.

    [0099] The gate terminal of the first select transistor S1 is connected with the word line WL. The gate terminal of the first switch transistor W1 is connected with the switch control line SW. The gate terminal of the first antifuse transistor A1 is connected with a first antifuse control line AF1. The gate terminal of the isolation transistor O is connected with an isolation control line IG. The gate terminal of the second antifuse transistor A2 is connected with a second antifuse control line AF2. The gate terminal of the second switch transistor W2 is connected with the switch control line SW. The gate terminal of the second select transistor S2 is connected with the word line WL.

    [0100] In accordance with the fourth embodiment, the OTP memory cell c1 comprises two storing circuits. That is, the first antifuse transistor A1 is a first storing circuit, and the second antifuse transistor A2 is a second storing circuit. During the program cycle of the OTP memory cell c1, the high voltage stress is applied to both of the first antifuse transistor A1 and the second antifuse transistor A2. Under this circumstance, the gate oxide layer of one of the first antifuse transistor A1 and the second antifuse transistor A2 is ruptured. Consequently, the storing state of the first antifuse transistor A1 or the second antifuse transistor A2 is changed. During the read cycle, the storing states of the first antifuse transistor A1 and the second antifuse transistor A2 are directly read, and the storing states thereof are used as the random code of the PUF technology.

    [0101] FIGS. 11A∼11B schematically illustrate associated voltage signals for programming and reading the memory array for the PUF technology according to the fourth embodiment of the present invention.

    [0102] Please refer to FIG. 11A. For programming the selected OTP memory cell c1, a ground voltage (0V) is provided to the bit line BL and the inverted bit line BL, a select voltage Vdd is provided to the word line WL, a program voltage Vpp is provided to the first antifuse control line AF1 and the second antifuse control line AF2, a second voltage V2 is provided to the switch control line SW, and a third voltage V3 is provided to the isolation line IG. In an embodiment, the select voltage Vdd is in the range between 0.75V and 3.6V, and the program voltage Vpp is in the range between 3.6V and 11V. Moreover, the second voltage V2 is larger than or equal to the select voltage Vdd and smaller than three-fourths of the program voltage Vpp (i.e., Vdd ≤ V2 < 3Vpp/4), and the third voltage V3 is larger than or equal to the select voltage Vdd and smaller than three-fourths of the program voltage Vpp (i.e., Vdd ≤ V3 < 3Vpp/4).

    [0103] When the select voltage Vdd is provided to the word line WL, the second voltage V2 is provided to the switch control line SW, the third voltage V3 is provided to the isolation line IG and the ground voltage is provided to the bit line BL and the inverted bit line BL, the first select transistor S1, the second select transistor S2, the first switch transistor W1, the second switch transistor W2 and the isolation transistor O are turned on. Consequently, a bias voltage Vpp is applied to the gate oxide layer of the first antifuse transistor A1 and the gate oxide layer of the second antifuse transistor A2. Since the program voltage Vpp is beyond the withstanding voltage range of the gate oxide layer, the gate oxide layer of one of the first antifuse transistor A1 and the second antifuse transistor A2 is ruptured. The ruptured gate oxide layer may be considered as a resistor with a low resistance value.

    [0104] Due to the manufacturing variation of the OTP memory cell c1, the gate oxide layer of which antifuse transistor is ruptured during the program cycle cannot be realized. Consequently, the OTP memory cell c1 can utilize the PUF technology. Take the OTP memory cell c1 of FIG. 11A as an example. During the program cycle, the gate oxide layer of the first antifuse transistor A1 is not ruptured, but the gate oxide layer of the second antifuse transistor A2 is ruptured.

    [0105] After the OTP memory cell c1 is programmed, one read action is performed to judge the storing states of the two storing circuits. Please refer to FIG. 11B. During the first read cycle, the ground voltage (0V) is provided to the bit line BL and the inverted bit line BL, the select voltage Vdd is provided to the word line WL, the second voltage V2 is provided to the switch control line SW, a read voltage Vr is provided to the first antifuse control line AF1 and the second antifuse control line AF2, and the ground voltage (0V) is provided to the isolation control line IG. In an embodiment, the read voltage Vr is in the range between 0.75V and 3.6V.

    [0106] Since the gate oxide layer of the first antifuse transistor A1 is not ruptured but the gate oxide layer of the second antifuse transistor A2 is ruptured, a first read current Ir1 flowing through the bit line BL has a small value (i.e., nearly zero) and a second read current Ir2 flowing through the inverted bit line BL has a larger value. According to the first read current Ir1 and the second read current Ir2, the first antifuse transistor A1 (i.e., the first storing circuit) is verified to have a second storing state corresponding to the high resistance value, and the second antifuse transistor A2 (i.e., the second storing circuit) is verified to have a first storing state corresponding to the low resistance value.

    [0107] Then, according to the storing states of the first antifuse transistor A1 (i.e., the first storing circuit) and the second antifuse transistor A2 (i.e., the second storing circuit), one bit of the random code is determined and applied to the PUF technology.

    [0108] Alternatively, one bit of the random code can be determined by using a differential sensing operation. For example, if the first read current Ir1 is larger than the second read current Ir2, the OTP memory cell c1 is defined as a first storing state; and if the first read current Ir1 is smaller than the second read current Ir2, the OTP memory cell c1 is defined as a second storing state.

    [0109] FIG. 12A is a schematic equivalent circuit diagram illustrating a memory array of OTP memory cells according to the fourth embodiment of the present invention.

    [0110] As shown in FIG. 12A, the memory array comprises OTP memory cells c11∼c22 in a 2×2 array. The structure of each of the OTP memory cells c11∼c22 is similar to the structure of the OTP memory cell as shown in FIG. 10A. In this embodiment, each of the OTP memory cells c11∼c22 comprises a first select transistor S1, a second select transistor S2, a first antifuse transistor A1, a second antifuse transistor A2, a first switch transistor W1, a second switch transistor W2 and an isolation transistor O.

    [0111] FIGS. 12B∼12C schematically illustrate associated voltage signals for programming and reading the memory array for the PUF technology according to the fourth embodiment of the present invention. For example, the OTP memory cell c12 is a selected memory cell.

    [0112] Please refer to FIG. 12B. For programming the selected OTP memory cell c12, a ground voltage (0V) is provided to a first bit line BL1 and a first inverted bit line BL1, a select voltage Vdd is provided to a second word line WL2, a second voltage V2 is provided to a second switch control line SW2, a program voltage Vpp is provided to a third antifuse control line AF3 and a fourth antifuse control line AF4, and a third voltage V3 is provided to a second isolation control line IG2. In an embodiment, the select voltage Vdd is in the range between 0.75V∼3.6V, and the program voltage Vpp is in the range between 3.6V and 11V. Moreover, the second voltage V2 is larger than or equal to the select voltage Vdd and smaller than three-fourths of the program voltage Vpp (i.e., Vdd ≤ V2 < 3Vpp/4) and the third voltage V3 is larger than or equal to the select voltage Vdd and smaller than three-fourths of the program voltage Vpp (i.e., Vdd ≤ V3 < 3Vpp/4).

    [0113] The memory cells c11, c21 and c22 are unselected memory cells. For these unselected memory cells, a first voltage V1 is provided to a second bit line BL2 and a second inverted bit line BL2, the ground voltage (0V) is provided to a first isolation control line IG1, a first word line WL1 and a first switch control line SW1, and the ground voltage (0V) is provided to a first antifuse control line AF1 and a second antifuse control line AF2. In an embodiment, the first voltage V1 is equal to or larger than the select voltage Vdd, and the first voltage V1 is smaller than a half of the program voltage Vpp (i.e., Vdd≤V1<Vpp/2).

    [0114] Please refer to FIG. 12B again. Since the memory cell c12 is the selected memory cell, the bias voltage Vpp is applied to the gate oxide layer of the first antifuse transistor A1 and the gate oxide layer of the second antifuse transistor A2. Consequently, the gate oxide layer of one of the first antifuse transistor A1 and the second antifuse transistor A2 is ruptured. The ruptured gate oxide layer may be considered as a resistor with a low resistance value. For example, in the memory cell c12 as shown in FIG. 12B, the gate oxide layer of the first antifuse transistor A1 is not ruptured, but the gate oxide layer of the second antifuse transistor A2 is ruptured.

    [0115] In case that the OTP memory cell c11, c21 or c22 is the selected memory cell, the bias voltages for performing the programming process are similar to those for the memory cell c12. The detailed description thereof is not redundantly described herein.

    [0116] After the memory cell c12 is completely programmed, one read action is performed to confirm the storing states of the two storing circuits of the memory cell c12. Please refer to FIG. 12C. During the read cycle of the selected memory cell c12, the ground voltage (0V) is provided to the first bit line BL1 and the first inverted bit line BL1, the select voltage Vdd is provided to the second word line WL2, the second voltage V2 is provided to the second switch control line SW2, the ground voltage (0V) is provided to the second isolation control line IG1, and a read voltage Vr is provided to the third antifuse control line AF3 and the fourth antifuse control line AF4. In an embodiment, the read voltage Vr is in the range between 0.75V and 3.6V.

    [0117] For the unselected memory cells c11, c21 and c22, the second bit line BL2 and the second inverted bit line BL2 are in a floating state, the ground voltage (0V) is provided to the second word line WL2 and the second switch control line SW2, and the ground voltage (0V) is provided to the first isolation control line IG1, the first antifuse control line AF1 and the second antifuse control line AF2.

    [0118] In the selected memory cell c12, since the gate oxide layer of the first antifuse transistor A1 is not ruptured but the gate oxide layer of the second antifuse transistor is ruptured, a first read current Ir1 flowing through the second bit line BL2 has a small value (i.e., nearly zero) and a second read current Ir2 flowing through the second inverted bit line BL2 has a larger value. According to the first read current Ir1 and the second read current Ir2, the first antifuse transistor A1 (i.e., the first storing circuit) is verified to have a second storing state corresponding to the high resistance value, and the second antifuse transistor A2 (i.e., the second storing circuit) is verified to have a first storing state corresponding to the low resistance value.

    [0119] Then, according to the storing states of the first antifuse transistor A1 (i.e., the first storing circuit) and the second antifuse transistor A2 (i.e., the second storing circuit), one bit of the random code is determined and applied to the PUF technology.

    [0120] Moreover, after the program actions and the read actions of the four memory cells c11∼c22 are performed, a four-bit random code for the PUF technology is generated.

    [0121] From the above descriptions, the present invention provides a one time programming memory cell and a memory array for a physically unclonable function (PUF) technology. FIG. 13 is a schematic functional diagram illustrating the first type OTP memory cell of the present invention. The OTP memory cells described in the first embodiment and the fourth embodiment maybe classified into the first type OTP memory cells.

    [0122] As shown in FIG. 13, the first type OTP memory cell c1 comprises a selecting circuit 910, a first antifuse storing circuit 912, a second antifuse storing circuit 914 and an isolation circuit 916. The selecting circuit 910 is connected with a bit line BL, an inverted bit line BL and a word line WL. The selecting circuit 910 is connected to at least two antifuse storing circuits. As shown in FIG. 13, the first antifuse storing circuit 912 is connected with a first antifuse control line AF1, the isolation circuit 916 and the selecting circuit 910. The second antifuse storing circuit 914 is connected with a second antifuse control line AF2, the isolation circuit 916 and the selecting circuit 910.

    [0123] According to the embodiment of the present invention, the first antifuse storing circuit 912 and the second antifuse storing circuit 914 are disposed symmetrically in the semiconductor. The selecting circuit 910 includes at least one select transistor, and each antifuse storing circuit 912 and 914 includes at least one antifuse transistor, and the isolation circuit 916 includes an isolation transistor. In another embodiment, the selecting circuit may includes select transistors and switch transistors, and the antifuse storing circuit may include more antifuse transistors connecting to corresponding antifuse control lines, and the isolation circuit may include more isolation transistors.

    [0124] For programming the OTP memory cell c1, a ground voltage (0V) is provided to the bit line BL and the inverted bit line BL, a select voltage Vdd is provided to the word line WL, an on voltage is provided to an isolation control line IG, and a program voltage Vpp is provided to the first antifuse control line AF1 and the second antifuse control line AF2.

    [0125] The isolation circuit 916 is connected with the first antifuse storing circuit 912 and the second antifuse storing circuit 914. The selecting circuit 910 provides the ground voltage (0V) to the first antifuse storing circuit 912 and the second antifuse storing circuit 914. During the program cycle of the OTP memory cell c1, the program voltage is applied to both of the first antifuse storing circuit 912 and the second antifuse storing circuit 914. Consequently, the storing state of the first antifuse storing circuit 912 or the second antifuse storing circuit 914 is changed.

    [0126] During the read cycle of the OTP memory cell c1, the ground voltage (0V) is provided to the bit line BL and the inverted bit line BL, the select voltage Vdd is provided to the word line WL, a read voltage Vr is provided to the first antifuse control line AF1 and the second antifuse control line AF2, and an off voltage is provided to the isolation control line IG to isolate the two antifuse storing circuits 912 and 914. Consequently, the first antifuse storing circuit 912 generates a first read current to the bit line BL. The second antifuse storing circuit 914 generates a second read current to the inverted bit line BL. According to the first read current and the second read current, the first antifuse storing circuit 902 is judged to have a first storing state and the second antifuse storing circuit 914 is judged to have a second storing state. That is to say that the storing state of the first antifuse storing circuit 912 and the second antifuse storing circuit 914 is judged by comparing the first read current and the second read current. Moreover, one bit of the random code for the PUF technology is determined according to the first storing state of the first antifuse storing circuit 912.

    [0127] Alternatively, one bit of the random code can be determined by using a differential sensing operation to compare the first read current and the second read current of the differential OTP memory cell.

    [0128] The same, when programming the OTP memory cell, the antifuse storing circuits in the OTP memory cell receive the same predetermined voltage difference, and then one of the antifuse storing circuits changes the storing state. After reading the OTP memory cell, the storing states (ruptured conditions) of the antifuse storing circuits are determined and recorded. In this invention, the ruptured conditions are determined based on the manufacturing variation of the programmed antifuse storing circuits. Then, a random code is capable of being generated in response to the recorded ruptured conditions.

    [0129] Furthermore, the recorded ruptured conditions mentioned above can be directly used as the random code. Or, the recorded ruptured conditions may be processed to generate the random code. For example, input the recorded ruptured conditions to a look up table, and then the random code is generated according to the look up table.


    Claims

    1. A memory array comprising a first bit line (BL), a first inverted bit line (/BL), a first word line (WL), a first isolation line (IG), a first antifuse control line (AF1), a second antifuse control line (AF2)and a first one time programming memory cell, wherein the first one time programming memory cell comprises:

    a first selecting circuit (910) connected with the first bit line (BL), the first inverted bit line (/BL)and the first word line (WL);

    a first isolation circuit (916) connected with the first isolation control line (IG);

    a first antifuse storing circuit (912) connected with the first antifuse control line (AF1), the first isolation circuit (916) and the first selecting circuit (910); and

    a second antifuse storing circuit (914) connected with the second antifuse control line (AF2), the first isolation circuit (916) and the first selecting circuit (910),

    characterized in that

    during a program cycle, a select voltage is provided to the first word line (WL), a ground voltage is provided to the first bit line (BL) and the first inverted bit line (/BL), an on voltage is provided to the first isolation control line (IG), and a program voltage is provided to the first antifuse control line (AF1) and the second antifuse control line (AF2), wherein the first antifuse storing circuit (912) and the second antifuse storing circuit (914) are connected to each other by the first isolation circuit (916) in response to the on voltage, the first selecting circuit (910) provides the ground voltage to the first antifuse storing circuit (912) and the second antifuse storing circuit (914), and the program voltage is applied to both of the first antifuse storing circuit (912) and the second antifuse storing circuit (914), so that a storing state of the first antifuse storing circuit (912) or the second antifuse storing circuit (914) is changed,

    wherein during a read cycle, the select voltage is provided to the first word line (WL), the ground voltage is provided to the first bit line (BL) and the first inverted bit line (/BL), a read voltage is provided to the first antifuse control line (AF1) and the second antifuse storing circuit (AF2), and an off voltage is provided to the first isolation control line (IG), so that the first antifuse storing circuit (912) and the second antifuse storing circuit (914) are isolated by the first isolation circuit (916) in response to the off voltage, the first antifuse storing circuit (912) generates a first read current to the first bit line (BL) and the second antifuse storing circuit (914) generates a second read current to the first inverted bit line (/BL), wherein one bit of a random code for a physically unclonable function technology is realized according to the first read current of the first antifuse storing circuit (912).


     
    2. The memory array as claimed in claim 1, further comprising a second one time programming memory cell, wherein the second one time programming memory cell comprises:

    a second selecting circuit connected with the first bit line, the first inverted bit line and a second word line;

    a second isolation circuit connected with a second isolation control line;

    a third antifuse storing circuit connected with a third antifuse control line, the second isolation circuit and the second selecting circuit; and

    a fourth antifuse storing circuit connected with a fourth antifuse control line, the second isolation circuit and the second selecting circuit.


     
    3. The memory array as claimed in claim 2, further comprising a third one time programming memory cell, wherein the third one time programming memory cell comprises:

    a third selecting circuit connected with a second bit line, a second inverted bit line and the first word line;

    a third isolation circuit connected with the first isolation control line;

    a fifth antifuse storing circuit connected with the first antifuse control line, the third isolation circuit and the third selecting circuit; and

    a sixth antifuse storing circuit connected with the second antifuse control line, the third isolation circuit and the third selecting circuit.


     
    4. The memory array as claimed in claim 1, wherein the first selecting circuit comprises a first select transistor and a second select transistor, the first antifuse storing circuit comprises a first antifuse transistor, the second antifuse storing circuit comprises a second antifuse transistor, and the isolation circuit comprises an isolation transistor, wherein a first drain/source terminal of the first select transistor is connected with the first bit line, a gate terminal of the first select transistor is connected with the first word line, a first drain/source terminal of the first antifuse transistor is connected with a second drain/source terminal of the first select transistor, a gate terminal of the first antifuse transistor is connected with the first antifuse control line, a first drain/source terminal of the isolation transistor is connected with a second drain/source terminal of the first antifuse transistor, a gate terminal of the isolation transistor is connected with the first isolation control line, a first drain/source terminal of the second antifuse transistor is connected with a second drain/source terminal of the isolation transistor, a gate terminal of the second antifuse transistor is connected with the second antifuse control line, a first drain/source terminal of the second select transistor is connected with a second drain/source terminal of the second antifuse transistor, a gate terminal of the second select transistor is connected with the first word line, and a second drain/source terminal of the second select transistor is connected with the inverted first bit line.
     
    5. The memory array as claimed in claim 1, wherein the first selecting circuit comprises a first select transistor, a second select transistor, a first switch transistor and a second switch transistor, the first antifuse storing circuit comprises a first antifuse transistor, the second antifuse storing circuit comprises a second antifuse transistor, and the isolation circuit comprises an isolation transistor, wherein a first drain/source terminal of the first select transistor is connected with the first bit line, a gate terminal of the first select transistor is connected with the first word line, a first drain/source terminal of the first switch transistor is connected with a second drain/source terminal of the first select transistor, a gate terminal of the first switch transistor is connected with a switch control line, a first drain/source terminal of the first antifuse transistor is connected with a second drain/source terminal of the first switch transistor, a gate terminal of the first antifuse transistor is connected with the first antifuse control line, a first drain/source terminal of the isolation transistor is connected with a second drain/source terminal of the first antifuse transistor, a gate terminal of the isolation transistor is connected with the first isolation control line, a first drain/source terminal of the second antifuse transistor is connected with a second drain/source terminal of the isolation transistor, a gate terminal of the second antifuse transistor is connected with the second antifuse control line, a first drain/source terminal of the second switch transistor is connected with a second drain/source terminal of the second antifuse transistor, a gate terminal of the second switch transistor is connected with the switch control line, a first drain/source terminal of the second select transistor is connected with a second drain/source terminal of the second switch transistor, a gate terminal of the second select transistor is connected with the first word line, and a second drain/source terminal of the second select transistor is connected with the inverted first bit line.
     
    6. The memory array as claimed in claim 1, wherein the first antifuse storing circuit and the second antifuse storing circuit are disposed symmetrically in a semiconductor.
     


    Ansprüche

    1. Speicher-Array mit einer ersten Bit-Leitung (BL), einer ersten invertierten Bit-Leitung (/BL), einer ersten Word-Leitung (WL), einer ersten Isolationsleitung (IG), einer ersten Antifuse-Steuerleitung (AF1), einer zweiten Antifuse-Steuerleitung (AF2) und einer ersten One-Time-Programming-Speicherzelle, wobei die erste One-Time-Programming-Speicherzelle aufweist:

    eine erste Auswahlschaltung (910), die mit der ersten Bit-Leitung (BL), der ersten invertierten Bit-Leitung (/BL) und der ersten Word-Leitung (WL) verbunden ist;

    eine erste Isolationsschaltung (916), die mit der ersten Isolationssteuerleitung (IG) verbunden ist;

    eine erste Antifuse-Speicherschaltung (912), die mit der ersten Antifuse-Steuerleitung (AF1), der ersten Isolationsschaltung (916) und der ersten Auswahlschaltung (910) verbunden ist; und

    eine zweite Antifuse-Speicherschaltung (914), die mit der zweiten Antifuse-Steuerleitung (AF2), der ersten Isolationsschaltung (916) und der ersten Auswahlschaltung (910) verbunden ist,

    dadurch gekennzeichnet, dass

    während eines Programmzyklus der Word-Leitung (WL) eine Auswahlspannung bereitgestellt wird, der ersten Bit-Leitung (BL) und der ersten invertierten Bit-Leitung (/BL) eine Grundspannung bereitgestellt wird, der ersten Isolationssteuerleitung (IG) eine Einschaltspannung bereitgestellt wird und der ersten Antifuse-Steuerleitung (AF1) und der zweiten Antifuse-Steuerleitung (AF2) eine Programmspannung bereitgestellt wird, wobei die erste Antifuse-Speicherschaltung (912) und die zweite Antifuse-Speicherschaltung (914) durch die erste Isolationsschaltung (916) miteinander verbunden sind als Reaktion auf die Einschaltspannung, wobei die erste Auswahlschaltung (910) der ersten Antifuse-Speicherschaltung (912) und der zweiten Antifuse-Speicherschaltung (914) die Grundspannung bereitstellt und die Programmspannung sowohl an die erste Antifuse-Speicherschaltung (912) als auch an die zweite Antifuse-Speicherschaltung (914) angelegt wird, so dass ein Speicherzustand der ersten Antifuse-Speicherschaltung (912) oder der zweiten Antifuse-Speicherschaltung (914) geändert wird,

    wobei während eines Lesezyklus der ersten Word-Leitung (WL) die Auswahlspannung bereitgestellt wird, der ersten Bit-Leitung (BL) und der ersten invertierten Bit-Leitung (/BL) die Grundspannung bereitgestellt wird, der ersten Antifuse-Steuerleitung (AF1) und der zweiten Antifuse-Steuerleitung (AF2) eine Lesespannung bereitgestellt wird und der ersten Isolationssteuerleitung (IG) eine Ausschaltspannung bereitgestellt wird, so dass die erste Antifuse-Speicherschaltung (912) und die zweite Antifuse-Speicherschaltung (914) durch die erste Isolationsschaltung (916) isoliert werden als Reaktion auf die Ausschaltspannung, wobei die erste Antifuse-Speicherschaltung (912) einen ersten Lesestrom für die erste Bit-Leitung (BL) erzeugt und die zweite Antifuse-Speicherschaltung (914) einen zweiten Lesestrom für die erste invertierte Bit-Leitung (/BL) erzeugt, wobei ein Bit eines Zufallscodes für eine physikalisch unklonbare Funktionstechnologie gemäß dem ersten Lesestrom der ersten Antifuse-Speicherschaltung (912) realisiert wird.


     
    2. Speicher-Array nach Anspruch 1, ferner mit einer zweiten One-Time-Programming-Speicherzelle, wobei die zweite One-Time-Programming-Speicherzelle aufweist:

    eine zweite Auswahlschaltung, die mit der ersten Bit-Leitung, der ersten invertierten Bit-Leitung und einer zweiten Word-Leitung verbunden ist;

    eine zweite Isolationsschaltung, die mit einer zweiten Isolationssteuerleitung verbunden ist;

    eine dritte Antifuse-Speicherschaltung, die mit einer dritten Antifuse-Steuerleitung, der zweiten Isolationsschaltung und der zweiten Auswahlschaltung verbunden ist; und

    eine vierte Antifuse-Speicherschaltung, die mit einer vierten Antifuse-Steuerleitung, der zweiten Isolationsschaltung und der zweiten Auswahlschaltung verbunden ist.


     
    3. Speicher-Array nach Anspruch 2, ferner mit einer dritten One-Time-Programming-Speicherzelle, wobei die dritte One-Time-Programming-Speicherzelle aufweist:

    eine dritte Auswahlschaltung, die mit einer zweiten Bit-Leitung, einer zweiten invertieren Bit-Leitung und der ersten Word-Leitung verbunden ist;

    eine dritte Isolationsschaltung, die mit der erste Isolationssteuerleitung verbunden ist;

    eine fünfte Antifuse-Speicherschaltung, die mit der ersten Antifuse-Steuerleitung, der dritten Isolationsschaltung und der dritten Auswahlschaltung verbunden ist; und

    einer sechsten Antifuse-Speicherschaltung, die mit der zweiten Antifuse-Steuerleitung, der dritten Isolationsschaltung und der dritten Auswahlschaltung verbunden ist.


     
    4. Speicher-Array nach Anspruch 1, wobei die erste Auswahlschaltung einen ersten Auswahltransistor und einen zweiten Auswahltransistor aufweist, die erste Antifuse-Speicherschaltung einen ersten Antifuse-Transistor aufweist, die zweite Antifuse-Speicherschaltung einen zweiten Antifuse-Transistor aufweist und die Isolationsschaltung einen Isolationstransistor aufweist, wobei ein erstes Drain-Source-Terminal des ersten Auswahltransistors mit der ersten Bit-Leitung verbunden ist, ein Gate-Terminal des ersten Auswahltransistors mit der ersten Word-Leitung verbunden ist, ein erstes Drain-Source-Terminal des ersten Antifuse-Transistors mit einem zweiten Drain-Source-Terminal des ersten Auswahltransistors verbunden ist, ein Gate-Terminal des ersten Antifuse-Transistors mit der ersten Antifuse-Steuerleitung verbunden ist, ein erstes Drain-Source-Terminal des Isolationstransistors mit einem zweiten Drain-Source-Terminal des ersten Antifuse-Transistors verbunden ist, ein Gate-Terminal des Isolationstransistors mit der ersten Isolationssteuerleitung verbunden ist, ein erstes Drain-Source-Terminal des zweiten Antifuse-Transistors mit einem zweiten Drain-Source-Terminal des Isolationstransistors verbunden ist, ein Gate-Terminal des zweiten Antifuse-Transistors mit der zweiten Antifuse-Steuerleitung verbunden ist, ein erstes Drain-Source-Terminal des zweiten Auswahltransistors mit einem zweiten Drain-Source-Terminal des zweiten Antifuse-Transistors verbunden ist, ein Gate-Terminal des zweiten Auswahltransistors mit der ersten Word-Leitung verbunden ist und ein zweites Drain-Source-Terminal des zweiten Auswahltransistors mit der invertierten ersten Bit-Leitung verbunden ist.
     
    5. Speicher-Array nach Anspruch 1, wobei die erste Auswahlschaltung einen ersten Auswahltransistor, einen zweiten Auswahltransistor, einen ersten Schaltertransistor und einen zweiten Schaltertransistor aufweist, die erste Antifuse-Speicherschaltung einen ersten Antifuse-Transistor aufweist, die zweite Antifuse-Speicherschaltung einen zweiten Antifuse-Transistor aufweist und die Isolationsschaltung einen Isolationstransistor aufweist, wobei ein erstes Drain-Source-Terminal des ersten Auswahltransistors mit der ersten Bit-Leitung verbunden ist, ein Gate-Terminal des ersten Auswahltransistors mit der ersten Word-Leitung verbunden ist, ein erstes Drain-Source-Terminal des ersten Schaltertransistors mit einem zweiten Drain-Source-Terminal des ersten Auswahltransistors verbunden ist, ein Gate-Terminal des erste Schaltertransistors mit einer Schalter-Steuerleitung verbunden ist, ein erstes Drain-Source-Terminal des ersten Antifuse-Transistors mit einem zweiten Drain-Source-Terminal des ersten Schaltertransistors verbunden ist, ein Gate-Terminal des ersten Antifuse-Transistors mit der ersten Antifuse-Steuerleitung verbunden ist, ein erstes Drain-Source-Terminal des Isolationstransistors mit einem zweiten Drain-Source-Terminal des ersten Antifuse-Transistors verbunden ist, ein Gate-Terminal des Isolationstransistors mit der ersten Isolationssteuerleitung verbunden ist, ein erstes Drain-Source-Terminal des zweiten Antifuse-Transistors mit einem zweiten Drain-Source-Terminal des Isolationstransistors verbunden ist, ein Gate-Terminal des zweiten Antifuse-Transistors mit der zweiten Antifuse-Steuerleitung verbunden ist, ein erstes Drain-Source-Terminal des zweiten Schaltertransistors mit einem zweiten Drain-Source-Terminal des zweiten Antifuse-Transistors verbunden ist, ein Gate-Terminal des zweiten Schaltertransistors mit der Schalter-Steuerleitung verbunden ist, ein erstes Drain-Source-Terminal des zweiten Auswahltransistors mit einem zweiten Drain-Source-Terminal des zweiten Schaltertransistors verbunden ist, ein Gate-Terminal des zweiten Auswahltransistors mit der ersten Word-Leitung verbunden ist und ein zweites Drain-Source-Terminal des zweite Auswahltransistors mit der invertierten ersten Bit-Leitung verbunden ist.
     
    6. Speicher-Array nach Anspruch 1, wobei die erste Antifuse-Speicherschaltung und die zweite Antifuse-Speicherschaltung symmetrisch in einem Halbleiter angeordnet sind.
     


    Revendications

    1. Réseau de mémoire comprenant une première ligne de bit (BL), une première ligne de bit inversée (/BL), une première ligne de mot (WL), une première ligne d'isolation (IG), une première ligne de commande d'anti-fusible (AF1), une deuxième ligne de commande d'anti-fusible (AF2) et une première cellule de mémoire à programmation unique, dans lequel la première cellule de mémoire à programmation unique comprend:

    un premier circuit de sélection (910) connecté à la première ligne de bit (BL), à la première ligne de bit inversée (/BL) et à la première ligne de mot (WL);

    un premier circuit d'isolation (916) connecté à la première ligne de commande d'isolation (IG);

    un premier circuit de mémorisation anti-fusible (912) connecté à la première ligne de commande d'anti-fusible (AF1), au premier circuit d'isolation (916) et au premier circuit de sélection (910); et

    un deuxième circuit de mémorisation anti-fusible (914) connecté à la deuxième ligne de commande d'anti-fusible (AF2), au premier circuit d'isolation (916) et au premier circuit de sélection (910),

    caractérisé par le fait que

    pendant un cycle de programme, une tension de sélection est fournie à la première ligne de mot (WL), une tension de terre est fournie à la première ligne de bit (BL) et à la première ligne de bit inversée (/BL), une tension d'activation est fournie à la première ligne de commande d'isolement (IG), et une tension de programme est fournie à la première ligne de commande d'anti-fusible (AF1) et à la deuxième ligne de commande d'anti-fusible (AF2), où le premier circuit de mémorisation anti-fusible (912) et le deuxième circuit de mémorisation anti-fusible (914) sont connectés l'un à l'autre par le premier circuit d'isolation (916) en réponse à la tension d'activation, le premier circuit de sélection (910) fournit la tension de terre au premier circuit de mémorisation anti-fusible (912) et au deuxième circuit de mémorisation anti-fusible (914), et la tension de programme est appliquée tant au premier circuit de mémorisation anti-fusible (912) qu'au deuxième circuit de mémorisation anti-fusible (914), de sorte que soit changé un état de mémorisation du premier circuit de mémorisation anti-fusible (912) ou du deuxième circuit de mémorisation anti-fusible (914),

    dans lequel, pendant un cycle de lecture, la tension de sélection est fournie à la première ligne de mot (WL), la tension de terre est fournie à la première ligne de bit (BL) et à la première ligne de bit inversée (/BL), une tension de lecture est fournie à la première ligne de commande d'anti-fusible (AF1) et au deuxième circuit de mémorisation anti-fusible (AF2), et une tension de désactivation est fournie à la première ligne de commande d'isolation (IG), de sorte que le premier circuit de mémorisation anti-fusible (912) et le deuxième circuit de mémorisation anti-fusible (914) soient isolés par le premier circuit d'isolation (916) en réaction à la tension de désactivation, le premier circuit de mémorisation anti-fusible (912) génère un premier courant de lecture pour la première ligne de bit (BL) et le deuxième circuit de mémorisation anti-fusible (914) génère un deuxième courant de lecture pour la première ligne de bit inversée (/BL), dans lequel un bit d'un code aléatoire pour une technologie de fonction physiquement non clonable est réalisé selon le premier courant de lecture du premier circuit de mémorisation anti-fusible (912).


     
    2. Réseau de mémoire selon la revendication 1, comprenant par ailleurs une deuxième cellule de mémoire à programmation unique, dans lequel la deuxième cellule de mémoire à programmation unique comprend:

    un deuxième circuit de sélection connecté à la première ligne de bit, à la première ligne de bit inversée et à une deuxième ligne de mot;

    un deuxième circuit d'isolation connecté à une deuxième ligne de commande d'isolation;

    un troisième circuit de mémorisation anti-fusible connecté à une troisième ligne de commande d'anti-fusible, au deuxième circuit d'isolation et au deuxième circuit de sélection; et

    un quatrième circuit de mémorisation anti-fusible connecté à une quatrième ligne de commande d'anti-fusible, au deuxième circuit d'isolation et au deuxième circuit de sélection.


     
    3. Réseau de mémoire selon la revendication 2, comprenant par ailleurs une troisième cellule de mémoire à programmation unique, dans lequel la troisième cellule de mémoire à programmation unique comprend:

    un troisième circuit de sélection connecté à une deuxième ligne de bit, à une deuxième ligne de bit inversée et à la première ligne de mot;

    un troisième circuit d'isolation connecté à la première ligne de commande d'isolation;

    un cinquième circuit de mémorisation anti-fusible connecté à la première ligne de commande d'anti-fusible, au troisième circuit d'isolation et au troisième circuit de sélection; et

    un sixième circuit de mémorisation anti-fusible connecté à la deuxième ligne de commande d'anti-fusible, au troisième circuit d'isolation et au troisième circuit de sélection.


     
    4. Réseau de mémoire selon la revendication 1, dans lequel le premier circuit de sélection comprend un premier transistor de sélection et un deuxième transistor de sélection, le premier circuit de mémorisation anti-fusible comprend un premier transistor à anti-fusible, le deuxième circuit de mémorisation anti-fusible comprend un deuxième transistor à anti-fusible, et le circuit d'isolation comprend un transistor d'isolation, dans lequel une première borne de drain/source du premier transistor de sélection est connectée à la première ligne de bit, une borne de grille du premier transistor de sélection est connectée à la première ligne de mot, une première borne de drain/source du premier transistor à anti-fusible est connectée à une deuxième borne de drain/source du premier transistor de sélection, une borne de grille du premier transistor à anti-fusible est connectée à la première ligne de commande d'anti-fusible, une première borne de drain/source du transistor d'isolation est connecté à une deuxième borne de drain/source du premier transistor à anti-fusible, une borne de grille du transistor d'isolation est connectée à la première ligne de commande d'isolation, une première borne de drain/source du deuxième transistor à anti-fusible est connectée à une deuxième borne de drain/source du transistor d'isolation, une borne de grille du deuxième transistor à anti-fusible est connectée à la deuxième ligne de commande d'anti-fusible, une première borne de drain/source du deuxième transistor de sélection est connectée à une deuxième borne de drain/source du deuxième transistor à anti-fusible, une borne de grille du deuxième transistor de sélection est connectée à la première ligne de mot, et une deuxième borne de drain/source du deuxième transistor de sélection est connectée à la première ligne de bit inversée.
     
    5. Réseau de mémoire selon la revendication 1, dans lequel le premier circuit de sélection comprend un premier transistor de sélection, un deuxième transistor de sélection, un premier transistor de commutation et un deuxième transistor de commutation, le premier circuit de mémorisation anti-fusible comprend un premier transistor à anti-fusible, le deuxième circuit de mémorisation anti-fusible comprend un deuxième transistor à anti-fusible, et le circuit d'isolation comprend un transistor d'isolation, dans lequel une première borne de drain/source du premier transistor de sélection est connectée à la première ligne de bit, une borne de grille du premier transistor de sélection est connectée à la première ligne de mot, une première borne de drain/source du premier transistor de commutation est connectée à une deuxième borne de drain/source du premier transistor de sélection, une borne de grille du premier transistor de commutation est connectée à une ligne de commande de commutation, une première borne de drain/source du premier transistor à anti-fusible est connectée à une deuxième borne de drain/source du premier transistor de commutation, une borne de grille du premier transistor à anti-fusible est connectée à la première ligne de commande d'anti-fusible, une première borne de drain/source du transistor d'isolation est connectée à une deuxième borne de drain/source du premier transistor à anti-fusible, une borne de grille du transistor d'isolation est connectée à la première ligne de commande d'isolation, une première borne de drain/source du deuxième le transistor à anti-fusible est connectée à une deuxième borne de drain/source du transistor d'isolation, une borne de grille du deuxième transistor à anti-fusible est connectée à la deuxième ligne de commande d'anti-fusible, une première borne de drain/source du deuxième transistor de commutation est connectée à une deuxième borne de drain/source du deuxième transistor à anti-fusible, une borne de grille du deuxième transistor de commutation est connectée à la ligne de commande du commutation, une première borne de drain/source du deuxième transistor de sélection est connectée à une deuxième borne de drain/source du deuxième transistor de commutation, une borne de grille du deuxième transistor de sélection est connectée à la première ligne de mot, et une deuxième borne de drain/source du deuxième transistor de sélection est connectée à la première ligne de bit inversée.
     
    6. Réseau de mémoire selon la revendication 1, dans lequel le premier circuit de mémorisation anti-fusible et le deuxième circuit de mémorisation anti-fusible sont disposés de manière symétrique dans un semi-conducteur.
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description