(19)
(11)EP 3 217 553 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
23.10.2019 Bulletin 2019/43

(21)Application number: 16160043.2

(22)Date of filing:  11.03.2016
(51)International Patent Classification (IPC): 
H03K 19/0175(2006.01)

(54)

INTEGRATED CIRCUITRY

INTEGRIERTE SCHALTUNG

CIRCUIT INTÉGRÉ


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(43)Date of publication of application:
13.09.2017 Bulletin 2017/37

(73)Proprietor: Socionext Inc.
Yokohama-shi, Kanagawa 222-0033 (JP)

(72)Inventors:
  • DEDIC, Ian Juso
    Northolt, Middlesex UB5 5HW (GB)
  • DARZY, Saul
    Edgeware, Middlesex HA8 8HN (GB)

(74)Representative: Haseltine Lake Kempner LLP 
Lincoln House, 5th Floor 300 High Holborn
London WC1V 7JH
London WC1V 7JH (GB)


(56)References cited: : 
WO-A1-93/16493
RU-C2- 2 569 043
US-A1- 2008 001 671
WO-A1-2015/037953
US-A1- 2006 001 507
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description


    [0001] The present invention relates to integrated circuitry, in particular to integrated circuitry configured to improve the frequency-response (and thus performance) of high-speed circuitry. For example, the high-speed circuitry may be analogue-to-digital converter (ADC) or digital-to-analogue converter (DAC) circuitry.

    [0002] Examples of such ADC circuitry are described in detail in EP 2211468. Examples of such DAC circuitry are described in detail in EP 2849345.

    [0003] Figure 1 presents example step response and frequency response graphs, indicating problems identified in such ADC and DAC circuitry.

    [0004] For the sake of argument, it may be assumed that a target "ideal" step response is one which rises immediately to 100% of full scale as indicated, i.e. to logic high, and that an "ideal" frequency response bandwidth is one in which a target -3dB point is achieved at 20 GHz as an example. This bandwidth (DC to 20 GHz) is very wide.

    [0005] It was found in such existing circuitry, designed to have such an "ideal" target step response and target frequency response bandwidth that the "actual" performance was as indicated in Figure 1, i.e., with a lower -3dB point, e.g., at 16GHz, and a corresponding step response rising quickly to around 90-95% of the ideal value and then creeping up to 100% from there.

    [0006] Such performance issues could potentially come from anywhere in the high-speed circuitry, leading to a complex design problem. Given the particularly wideband performance desired (e.g., DC to 20GHz as in Figure 1), it is difficult to tune out the problems, given that for example a digital filter may need a lot of taps to compensate for the error. This is to be contrasted with narrowband (e.g. radio frequency (RF)) applications where such digital filtering may be practical.

    [0007] It is desirable to solve some or all of the above problems, in particular to provide such integrated circuitry with improved wideband and step response performance.

    [0008] Reference may be made to WO 93/16493, which relates to variable electrical impedance termination for leads on integrated circuit chips, and to US 2008/0001671 A1, which relates to an input inductive network for sample and hold amplifiers in high speed data converters.

    [0009] It is also reported the PCT application WO 2015037953 A1 disclosing an high-integration filter type shifter for shifting phase of a signal from an antenna in order to reduce insertion loss of a switch parasitic capacitor.

    [0010] According to an embodiment of a first aspect of the present invention there is provided integrated circuitry, as claimed in claim 1. Specific embodiments are defined in the dependent claims.

    [0011] The resistors and the inductor are connected (together) so as to compensate for parasitic capacitance at, or associated with, or of, the connection pad. Such compensation advantageously has been found to address the performance problems discussed above.

    [0012] The resistance of the first resistor may be substantially larger or much larger than the resistance of the second resistor, and the inductor may be connected in parallel with the second resistor. For example, the resistance of the first resistor may be 5 to 10 times larger than that of the second resistor. The ratio of resistances of the resistors may be same as the "step response creep-up" size. For example, if this is 10% then the ratio may be 10:1, if this is 5% then the ratio may be 20:1. In practice, the error is usually less than 10% so the ratio may be 10:1 or more.

    [0013] The signal path may be a signal output path, for example an analogue output path. The signal path may be a signal input path, for example an analogue input path.

    [0014] The termination circuit may be connected between the signal path and a low or ground (logic low) voltage reference (i.e. a voltage reference source) or between the signal path and a high or VDD (logic high) voltage reference. Effectively, the termination circuit may be connected between the signal path and AC ground.

    [0015] The termination circuit may be connected between the signal path and a substrate of the integrated circuitry. The signal path may be implemented as a transmission line.

    [0016] The termination circuit may be a passive termination circuit, in that it comprises (only) passive components. The termination circuit may comprise active components in some embodiments. The resistors and inductors may be variable resistors and inductors in some embodiments, enabling the above performance issues to be tuned out after fabrication. Alternatively, they may be fixed-value components, with the performance issues being tuned out through design of the integrated circuitry.

    [0017] The connection pad may be a metalized connection pad or land, for example for connection to external circuitry. The connection pad may be referred to as an input/output pad or land.

    [0018] A resistance of the substrate of the integrated circuitry may be set to be high, or as high as possible. A resistance of the substrate of the integrated circuitry may be set to be substantially higher, typically 10 to 20 times higher, than a resistance of the termination circuit.

    [0019] The circuit block may comprise digital-to-analogue converter circuitry and/or analogue-to-digital converter circuitry.

    [0020] According to an embodiment of a second aspect of the present invention there is provided digital-to-analogue converter circuitry or analogue-to-digital converter circuitry, comprising integrated circuitry according to the aforementioned first aspect of the present invention.

    [0021] According to an embodiment of a third aspect of the present invention there is provided an IC chip, such as a flip chip, comprising integrated circuitry according to the aforementioned first aspect of the present invention, or digital-to-analogue converter circuitry or analogue-to-digital converter circuitry according to the aforementioned second aspect of the present invention.

    [0022] The present disclosure extends to method aspects corresponding in scope with the apparatus aspects, and will be understood accordingly.

    [0023] Reference will now be made, by way of example only, to the accompanying drawings, of which:

    Figure 1, mentioned above, presents example step response and frequency response graphs relating to previously-considered circuitry;

    Figure 2 is a schematic diagram representing integrated circuitry useful for understanding embodiments of the present invention;

    Figure 3 presents a frequency response graph showing a change in input impedance over frequency;

    Figure 4 is a schematic diagram of example circuitry alongside existing circuitry for comparison purposes; and

    Figure 5 is another schematic diagram of example circuitry alongside existing circuitry for comparison purposes.



    [0024] Figure 2 is a schematic diagram representing integrated circuitry 1 useful for understanding embodiments of the present invention. The integrated circuitry is shown in a simplified form.

    [0025] Integrated circuitry 1 comprises a high-speed, wideband circuitry block 2, an input or output signal line 4, a connection pad 6, a termination resistor 8, and a substrate 10. Also shown by dashed-line connection is a capacitor CPAD 12, representing the parasitic capacitance of the connection pad 6.

    [0026] Incidentally, although focus is placed on analogue output signal lines here it will be appreciated that the present invention is equally applicable to analogue input signal lines, and the present disclosure will be understood accordingly.

    [0027] The connection pad 6 may be a metalized connection pad or land, useful as an external terminal of the circuitry. For example the connection pad 6 may be suitable to be soldered to a connection pad in another circuit or on a carrier substrate. For example, circuitry 1 may be implemented as a flip chip for connection via one or more such connection pads to a substrate of a flip-chip package.

    [0028] For the sake of further explanation, it is assumed that the high-speed circuitry block 2 is DAC or ADC circuitry, for example as mentioned above.

    [0029] As indicated in Figure 2, and taking an output signal line as an example, the output signal line 4 connects an output of the circuitry block 2 to the connection pad 6. In the case of DAC circuitry, this could be an overall analogue output of that circuitry. The termination resistor 8, for example a 50Ω resistor, connects the signal line 4 to the substrate 10, i.e. to ground supply, to terminate that signal line.

    [0030] Of importance here is the parasitic capacitance of the connection pad 6, identified by the present inventors as contributing to the performance problems mentioned above. This parasitic capacitance is modelled here for the benefit of explanation as the discrete capacitor CPAD 12 connected between the connection pad 6 and the substrate 10. However, it will be understood that this represents a parasitic capacitance, and that no discrete capacitor 12 is provided in the circuitry 1 as such.

    [0031] This clear insight - the identification and isolation of capacitor CPAD 12 as being a source of the performance problems discussed above - is of course a significant contribution and step towards the embodiments disclosed herein. For example, it will be appreciated that circuitry block 2 itself may be very complex, having many thousands of components, with the overall circuitry 1 being similarly complex. Note that the pad 6 will also have some resistance in practice, which may also be taken into account.

    [0032] Figure 3 presents a frequency response graph showing how the input impedance may vary over frequency given the circuitry 1 of Figure 2. A representation of the circuitry 1 is shown in the upper right-hand corner with the circuit block 2 modelled as a current source 2 and with a resistance RSUBSTRATE 14 modelling the resistance of the substrate explicitly shown in series between the capacitor 12 (parasitic pad capacitance) and ground.

    [0033] Assuming (as a running example) a target input impedance ZIN of 50Ω, and thus with the termination resistor 8 being a 50Ω resistor and the signal line 4 being 50Ω transmission line, the lower trace 22 in Figure 3 shows the effect of capacitor 12. The 50Ω termination resistor appears as such at DC and low frequencies, but as a 45Ω termination resistor at high frequency. The transition is shown here at around 5GHz merely as an example, and the value 45Ω is also simply an example.

    [0034] The upper trace 24 in Figure 3 shows in this example that by employing a 55Ω termination resistor the target 50Ω input impedance may be experienced at high frequency. However, this may be unsatisfactory given the desired wideband performance.

    [0035] Figure 4 is a schematic diagram showing representative circuitry 20 and 30 in order to better explain embodiments of the present invention.

    [0036] Representative circuitry 20 of Figure 4(a) corresponds to that shown in Figure 3 and is provided for comparison purposes.

    [0037] Figure 4(b) presents representative circuitry 30. As can be seen from Figure 4, compared to representative circuitry 20, in representative circuitry 30 the termination resistor 8 has been replaced with a termination circuit 32. The termination circuit 32 comprises termination resistor 8 and an inductor 34. For example, the termination resistance itself may have some inductance. Although the termination resistors 8 are denoted in the same way in Figures 4(a) and 4(b), their resistance values may be different from one another.

    [0038] By maximising or increasing the resistance of the substrate RSUBSTRATE 14 in the circuitry 30, for example relative to that in circuitry 20, it is effectively possible to minimise the impact of the parasitic capacitance CPAD 12 of the connection pad 6. The resistance of the substrate may be set when configuring the eventual fabrication of the integrated circuitry, in relation to the materials and processes used. With the resistance of the substrate itself usually fixed by the fabrication process, beyond configuring the fabrication process another possibility is to have a big gap between the pad and other circuits (which adds area, and is often undesirable or even impossible in a practical layout).

    [0039] Figure 5 is a schematic diagram showing representative circuitry 20 and 40 also in order to better explain embodiments of the present invention.

    [0040] Representative circuitry 20 of Figure 5(a) corresponds to that shown in Figures 3 and 4(a) and is again provided for comparison purposes.

    [0041] Figure 5(b) presents representative circuitry 40, which embodies the present invention. As can be seen from Figure 5, compared to representative circuitry 20, in representative circuitry 40 the termination resistor 8 has been replaced with a termination circuit 42. The termination circuit 42 comprises a first termination resistor 44, a second termination resistor 46 and an inductor 48. Also indicated in termination circuit 42 for the benefit of explanation is the real resistance of the (in practice, non-ideal) inductor 48, denoted RINDUCTOR 50. However, it will be appreciated that this resistance is a property of the non-ideal inductor in practice and not a separate discrete resistance as such.

    [0042] The first and second termination resistors 44 and 46 are connected in series with one another and in place of the termination resistor 8 of the representative circuitry 20. The inductor 48 is connected in parallel with the second termination resistor 46. The real resistance 50 of the inductor 48 is shown in series with the inductor 48 (as an ideal circuit element) itself. Thus, the combination of elements 50 and 48 correspond to a real non-ideal inductor.

    [0043] As above, by maximising the resistance of the substrate RSUBSTRATE 14 in the circuitry 40 it is effectively possible to minimise the impact of the parasitic capacitance CPAD 12 of the connection pad.

    [0044] By setting the values of the indicated components it is possible to configure the circuitry 40 to compensate for the parasitic capacitance CPAD 12 of the connection pad 6.

    [0045] For example, if RSUBSTRATE is 500Ω and RTERM(ideal) is 50Ω, and if step error is 10%, this may require RTERM to increase by ΔP=5Ω at high frequencies. Without RINDUCTOR, this would give RTERM1=50ohms and RTERM2=5ohms. The two time constants (RC and L/R) need to match for effective compensation. If CPAD=60fF, then RC=RSUBSTRATE*CPAD=500Ω*60fF = 30ps = L/RTERM2 which gives L=150pH. With RINDUCTOR=3Ω, to keep ΔR=5Ω this gives RTERM2=8Ω. This means L=240pH and RTERM1=47Ω (50Ω - RINDUCTOR).

    [0046] Example values therefore could be:
    • RTERM1 = 47Ω
    • RTERM2 = 8Ω
    • L = 240pH
    • RINDUCTOR = 3Ω
    • CPAD = 60fF
    • RSUBSTRATE = 500Ω


    [0047] It will be appreciated that one or more of the first and second termination resistors 44 and 46 and the inductor 48 (Figure 5(b)) could be implemented as variable components, i.e. as variable resistors or inductors. This would enable the performance problems to be tuned out in a particular circuit, for example dynamically if need be. However, in practice it may be that fixed components designed to tune out the performance problems may be used. Thus, the termination circuit 42 may be implemented as dynamic-value (i.e. adjustable) or fixed-value circuit. Such circuits may in some embodiments include active components and in other embodiments only passive components.

    [0048] It will be appreciated that the circuitry embodying the present invention could be provided in the form of an IC chip having high-speed circuitry 20. The high-speed circuitry 20 could comprise mixed-signal circuitry such as DAC or ADC circuitry. Embodiments of the present invention thus may be represented by the circuitry 1 of Figure 2, except with the termination resistor 8 replaced by the termination circuit 32 or 42.

    [0049] Such a chip may have one or more contact or connection pads corresponding to connection pad 6, and thus the present invention may be embodied in respect of one, a plurality, or in respect of all of such connection pads.

    [0050] It will also be appreciated that the circuitry disclosed herein could be described as a DAC or ADC. Circuitry of the present invention may be implemented as integrated circuitry, for example on an IC chip. The present invention extends to integrated circuitry and IC chips as mentioned above, circuit boards comprising such IC chips, and communication networks (for example, internet fiber-optic networks and wireless networks) and network equipment of such networks, comprising such circuit boards.

    [0051] The present invention may be embodied in many different ways in the light of the above disclosure, within the scope of the appended claims.


    Claims

    1. Integrated circuitry, comprising:

    a signal path (4) connected to a connection pad, for connection to external circuitry;

    a substrate configured to act as a voltage reference; and

    a termination circuit (40) connected between the signal path and the substrate and configured to compensate for parasitic capacitance (12) associated with the connection pad,

    wherein:

    the termination circuit (42) comprises first (44) and second (46) resistors connected in series between the signal path and the substrate, and an inductor (48) connected in parallel with one of the resistors; and

    a resistance of the substrate is higher than a resistance of the termination circuit.


     
    2. The integrated circuitry of claim 1, wherein the resistance of the first resistor (44) is larger than the resistance of the second resistor, and wherein the inductor is connected in parallel with the second resistor.
     
    3. The integrated circuitry of claim 1 or 2, wherein the signal path is a signal output path or a signal input path.
     
    4. The integrated circuitry of any of the preceding claims, wherein the voltage reference is a ground voltage reference.
     
    5. The integrated circuitry of any of the preceding claims, wherein the signal path is implemented as a transmission line.
     
    6. The integrated circuitry of any of the preceding claims, wherein the termination circuit is a passive termination circuit.
     
    7. The integrated circuitry of any of the preceding claims, wherein the connection pad is a metalized connection pad or land.
     
    8. The integrated circuitry of any of the preceding claims, wherein the circuit block comprises digital-to-analogue converter circuitry and/or analogue-to-digital converter circuitry.
     
    9. Digital-to-analogue converter circuitry or analogue-to-digital converter circuitry, comprising the integrated circuitry of any of the preceding claims.
     
    10. An IC chip, such as a flip chip, comprising the integrated circuitry of any of claims 1 to 8, or the digital-to-analogue converter circuitry or analogue-to-digital converter circuitry of claim 9.
     


    Ansprüche

    1. Integrierte Schaltung, umfassend:

    einen Signalpfad (4), der mit einer Verbindungskontaktstelle verbunden ist, zur Verbindung mit einer externen Schaltung;

    ein Substrat, das eingerichtet ist, um als Spannungsreferenz zu fungieren; und

    eine Anschlussschaltung (40), die zwischen dem Signalpfad und dem Substrat verbunden ist und eingerichtet ist, um eine der Verbindungskontaktstelle zugeordnete parasitäre Kapazität (12) zu kompensieren,

    wobei:

    die Anschlussschaltung (42) einen ersten (44) und zweiten (46) Widerstand, die zwischen dem Signalpfad und dem Substrat in Reihe geschaltet sind, und einen Induktor (48), der mit einem der Widerstände in Reihe geschaltet ist, umfasst; und

    ein Wirkwiderstand des Substrats höher ist als ein Wirkwiderstand der Anschlussschaltung.


     
    2. Integrierte Schaltung nach Anspruch 1, wobei der Wirkwiderstand des ersten Widerstands (44) größer ist als der Wirkwiderstand des zweiten Widerstands und wobei der Induktor mit dem zweiten Widerstand parallel geschaltet ist.
     
    3. Integrierte Schaltung nach Anspruch 1 oder 2, wobei der Signalpfad ein Signalausgangspfad oder ein Signaleingangspfad ist.
     
    4. Integrierte Schaltung nach einem der vorhergehenden Ansprüche, wobei die Spannungsreferenz eine Massespannungsreferenz ist.
     
    5. Integrierte Schaltung nach einem der vorhergehenden Ansprüche, wobei der Signalpfad als eine Übertragungsleitung implementiert ist.
     
    6. Integrierte Schaltung nach einem der vorhergehenden Ansprüche, wobei die die Anschlussschaltung eine passive Anschlussschaltung ist.
     
    7. Integrierte Schaltung nach einem der vorhergehenden Ansprüche, wobei die Verbindungskontaktstelle eine metallisierte Verbindungskontaktstelle oder -fläche ist.
     
    8. Integrierte Schaltung nach einem der vorhergehenden Ansprüche, wobei der Schaltungsblock eine Digital-zu-analog-Wandlerschaltung und/oder eine Analog-zu-digital-Wandlerschaltung umfasst.
     
    9. Digital-zu-analog-Wandlerschaltung oder Analog-zu-digital-Wandlerschaltung, umfassend die integrierte Schaltung nach einem der vorhergehenden Ansprüche.
     
    10. IC-Chip, wie etwa ein Flip-Chip, umfassend die integrierte Schaltung nach einem der Ansprüche 1 bis 8 oder die Digital-zu-analog-Wandlerschaltung oder Analog-zu-digital-Wandlerschaltung nach Anspruch 9.
     


    Revendications

    1. Circuits intégrés comprenant :

    un trajet de signal (4) connecté à un plot de connexion, pour une connexion à des circuits externes ;

    un substrat configuré pour agir en tant que référence de tension ; et

    un circuit de terminaison (40) connecté entre le trajet de signal et le substrat et configuré pour compenser une capacité parasite (12) associée au plot de connexion,

    dans lesquels :

    le circuit de terminaison (42) comprend des première (44) et seconde (46) résistances connectées en série entre le trajet de signal et le substrat, et une inductance (48) connectée en parallèle à l'une des résistances ; et

    une résistance du substrat est supérieure à une résistance du circuit de terminaison.


     
    2. Circuits intégrés selon la revendication 1, dans lesquels la résistance de la première résistance (44) est supérieure à la résistance de la seconde résistance, et dans lesquels l'inductance est connectée en parallèle à la seconde résistance.
     
    3. Circuits intégrés selon la revendication 1 ou 2, dans lesquels le trajet de signal est un trajet de sortie de signal ou un trajet d'entrée de signal.
     
    4. Circuits intégrés selon l'une quelconque des revendications précédentes, dans lesquels la référence de tension est une référence de tension de masse.
     
    5. Circuits intégrés selon l'une quelconque des revendications précédentes, dans lesquels le trajet de signal est mis en oeuvre sous la forme d'une ligne de transmission.
     
    6. Circuits intégrés selon l'une quelconque des revendications précédentes, dans lesquels le circuit de terminaison est un circuit de terminaison passif.
     
    7. Circuits intégrés selon l'une quelconque des revendications précédentes, dans lesquels le plot de connexion est un plot ou une plage de connexion métallisé(e).
     
    8. Circuits intégrés selon l'une quelconque des revendications précédentes, dans lesquels le bloc de circuits comprend des circuits de convertisseur numérique-analogique et/ou des circuits de convertisseur analogique-numérique.
     
    9. Circuits de convertisseur numérique-analogique ou circuits de convertisseur analogique-numérique, comprenant les circuits intégrés selon l'une quelconque des revendications précédentes.
     
    10. Puce à circuits intégrés, telle qu'une puce retournée, comprenant les circuits intégrés selon l'une quelconque des revendications 1 à 8, ou les circuits de convertisseur numérique-analogique ou les circuits de convertisseur analogique-numérique selon la revendication 9.
     




    Drawing




















    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description