(19)
(11)EP 3 244 583 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
29.07.2020 Bulletin 2020/31

(21)Application number: 15876507.3

(22)Date of filing:  11.02.2015
(51)International Patent Classification (IPC): 
H04L 25/49(2006.01)
H04L 1/00(2006.01)
H04B 14/02(2006.01)
(86)International application number:
PCT/CN2015/072816
(87)International publication number:
WO 2016/109999 (14.07.2016 Gazette  2016/28)

(54)

DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS

DATENVERARBEITUNGSVERFAHREN UND DATENVERARBEITUNGSVORRICHTUNG

PROCÉDÉ DE TRAITEMENT DE DONNÉES ET APPAREIL DE TRAITEMENT DE DONNÉES


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 08.01.2015 WO PCT/CN2015/070314

(43)Date of publication of application:
15.11.2017 Bulletin 2017/46

(73)Proprietor: Huawei Technologies Co., Ltd.
Longgang District Shenzhen, Guangdong 518129 (CN)

(72)Inventors:
  • YANG, Wenbin
    Shenzhen Guangdong 518129 (CN)
  • WANG, Xinyuan
    Shenzhen Guangdong 518129 (CN)
  • WANG, Tongtong
    Shenzhen Guangdong 518129 (CN)

(74)Representative: Thun, Clemens 
Mitscherlich PartmbB Patent- und Rechtsanwälte Sonnenstraße 33
80331 München
80331 München (DE)


(56)References cited: : 
CN-A- 1 335 722
CN-A- 103 718 490
US-A1- 2006 228 116
CN-A- 102 984 110
US-A1- 2004 091 055
US-A1- 2012 257 896
  
  • MD J HOSSAIN ET AL: "Constellation and Interleaver Design for BICM", GLOBAL TELECOMMUNICATIONS CONFERENCE (GLOBECOM 2011), 2011 IEEE, IEEE, 5 December 2011 (2011-12-05), pages 1-6, XP032118835, DOI: 10.1109/GLOCOM.2011.6133634 ISBN: 978-1-4244-9266-4
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

TECHNICAL FIELD



[0001] The present invention relates to the field of mobile communications, and in particular, to a data processing method and a data processing apparatus.

BACKGROUND



[0002] A modulation technology commonly used in Ethernet is pulse amplitude modulation (PAM). The following uses a PAM-4 circuit as an example to describe a working procedure of a PAM circuit. The PAM-4 circuit receives data sent by a link 0 and data sent by a link 1, modulates the data sent by the link 0 to a level (level) corresponding to 20, and modulates the data sent by the link 1 to a level corresponding to 21. At a time, data sent by each link is 0 or 1. Therefore, the PAM-4 circuit separately modulates four types of data 00, 01, 10, and 11 sent by the link 0 and the link 1, so as to obtain pulse signals whose amplitudes are 0, 1, 2, and 3 respectively. The PAM-4 circuit sends an obtained pulse signal to a receive end. After receiving the pulse signal, the receive end demodulates the received pulse signal so as to obtain one type of data 00, 01, 10, or 11, and sends the data obtained by demodulation to two forward error correction (FEC) circuits by using two links respectively.

[0003] However, a bit error may occur in a transmission process in which a pulse signal is transmitted to a receive end. In addition, bit error rates corresponding to data transmitted on different links may be different. Therefore, the receive end needs to configure different FEC circuits for different links, so as to separately perform error correction on data transmitted on the different links. For example, for data with a relatively high bit error rate, a relatively complex FEC circuit is used to perform error correction; for data with a relatively low bit error rate, a relatively simple FEC circuit is used to perform error correction. As a result, implementation complexity is relatively high.

[0004] Patent Application US 2006/0228116 discloses a method and system for averaging the effects of polarization distortions across a multitude of transmitted data streams in a dual polarization multiplexed optical communications system.

[0005] MD J HOSSAIN ET AL: "Constellation and Interleaver Design for BiCM", GLOBAL TELECOMMUNICATIONS CONFERENCE (GLOBECOM 2011), 2011 IEEE, IEEE, (20111205), doi:10.1109/GLOCOM.2011.6133634, ISBN 978-1-4244-9266-4, pages 1 - 6, XP032118835, discloses a new BICM design, which considers hierarchical constellations, a bit-level multiplexer, and multiple interleavers.

[0006] Patent Application US 2012/0257896 discloses ultra-high speed optical transport systems.

SUMMARY



[0007] Embodiments of the present invention provide a data processing method, in which multiple FEC circuits of a same specification may be used to perform error correction on multiple received data streams respectively, thereby helping to reduce implementation complexity.

[0008] The present invention is defined in the appended independent claims. Further implementations are disclosed in the appended dependent claims. In the following, embodiments not falling within the scope of the claims are to be understood as examples useful for understanding the invention.

[0009] According to a first aspect, a data processing method is provided, including:

receiving, by an encoding circuit, m data streams by using m receive ports respectively, where m is an integer greater than 1, the m receive ports are in a one-to-one correspondence with the m data streams, and the m data streams include m×m data units, where each data stream of the m data streams includes m data units, the m×m data units form an m-order matrix A, the m×m data units are m×m elements in the matrix A, m 1×m matrices in the matrix A are in a one-to-one correspondence with the m data streams, m elements located in a same m×1 matrix of m m×1 matrices in the matrix A are received by the encoding circuit at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix A, an element located on a right side is received by the encoding circuit earlier than an element located on a left side;

keeping, by the encoding circuit, a location of one element in each row in the matrix A unchanged and moving remaining m-1 elements to remaining m-1 rows respectively so as to form an m-order matrix B, where a column number of each element in the remaining m-1 elements in the matrix A before the element is moved equals a column number of the element in the remaining m-1 elements in the matrix B after the element is moved, and the m×m elements in the matrix A are in a one-to-one correspondence with m×m elements in the matrix B; and

sending, by the encoding circuit by using m transmit ports, the m×m elements in the matrix B to m different levels of a PAM circuit respectively for performing modulation, where m 1×m matrices in the matrix B are in a one-to-one correspondence with the m different levels of the PAM circuit, m elements located in a same m×1 matrix of m m×1 matrices in the matrix B are sent by the encoding circuit at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix B, an element located on a right side is sent by the encoding circuit earlier than an element located on a left side;

the method further comprises:

receiving, by the encoding circuit, m data units by using the m receive ports respectively, wherein the received m data units are in a one-to-one correspondence with the m receive ports, the received m data units are received by the encoding circuit at a same time, and the time at which the encoding circuit receives the received m data units is different from a time at which the encoding circuit receives m data units in any m×1 matrix of the m m×1 matrices in the matrix A; and

sending, by the encoding circuit by using the m transmit ports, the received m data units to the m different levels of the PAM circuit respectively for performing modulation, wherein the received m data units are in a one-to-one correspondence with the m different levels.



[0010] With reference to the first aspect, in a first implementation manner of the first aspect, the m×m elements in the matrix A are denoted by aij, the m×m elements in the matrix B are denoted by bij, i=1, ..., m, and j=1, ..., m, where
bij = axj, and a value of x complies with the following constraints:

when i+k≤m, x=i+k, and when i+k>m, x=i+k-m, where k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix B correspond to different k values respectively; or

when i-k>0, x=i-k, and when i-k≤0, x=i-k+m, where k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix B correspond to different k values respectively.



[0011] With reference to the first implementation manner of the first aspect, in a second implementation manner of the first aspect, a difference between k values corresponding to two adjacent elements of elements in each row in the matrix B is 1.

[0012] According to a second aspect, a data processing method is provided, including:

receiving, by a decoding circuit, m demodulated data streams by using m receive ports respectively, where m is an integer greater than 1, the m receive ports are in a one-to-one correspondence with the m data streams, and the m data streams include m×m data units, where each data stream of the m data streams includes m data units, the m×m data units form an m-order matrix C, the m×m data units are m×m elements in the matrix C, m 1×m matrices in the matrix C are in a one-to-one correspondence with the m data streams, m elements located in a same m×1 matrix of m m×1 matrices in the matrix C are received by the decoding circuit at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix C, an element located on a right side is received by the decoding circuit earlier than an element located on a left side;

keeping, by the decoding circuit, a location of one element in each row in the matrix C unchanged and moving remaining m-1 elements to remaining m-1 rows respectively so as to form an m-order matrix D, where a column number of each element in the remaining m-1 elements in the matrix C before the element is moved equals a column number of the element in the remaining m-1 elements in the matrix D after the element is moved, and the m×m elements in the matrix C are in a one-to-one correspondence with m×m elements in the matrix D; and

sending, by the decoding circuit, the m×m elements in the matrix D by using m transmit ports, where m elements located in a same m×1 matrix of m m×1 matrices in the matrix D are sent by the decoding circuit at a same time, and among m elements located in a same 1×m matrix of m 1×m matrices in the matrix D, an element located on a right side is sent by the encoding circuit earlier than an element located on a left side;

the method further comprises:

receiving, by the decoding circuit, m demodulated data units by using the m receive ports respectively, wherein the received and demodulated m data units are in a one-to-one correspondence with the m receive ports, the received and demodulated m data units are received by the decoding circuit at a same time, and the time at which the decoding circuit receives the received and demodulated m data units is different from a time at which the decoding circuit receives m data units in any m×1 matrix of the m m×1 matrices in the matrix C; and

sending, by the decoding circuit, the received and demodulated m data units by using the m transmit ports respectively, wherein the received and demodulated m data units are in a one-to-one correspondence with the m transmit ports.



[0013] With reference to the second aspect, in a first implementation manner of the second aspect, the m×m elements in the matrix C are denoted by cij, the m×m elements in the matrix D are denoted by dij, i=1, ..., m, and j=1, ..., m, where
dij = cyj, and a value of y is:

when i-k>0, y=i-k, and when i-k≤0, y=i-k+m, where k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix D correspond to different k values respectively; or

when i+k≤m, y=i+k, and when i+k>m, y=i+k-m, where k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix D correspond to different k values respectively.



[0014] With reference to the first implementation manner of the second aspect, in a second implementation manner of the second aspect, a difference between k values corresponding to two adjacent elements of elements in each row in the matrix D is 1.

[0015] According to a third aspect, a data processing apparatus is provided, including:

a receiving unit, configured to receive m data streams by using m receive ports respectively, where m is an integer greater than 1, the m receive ports are in a one-to-one correspondence with the m data streams, and the m data streams include m×m data units, where each data stream of the m data streams includes m data units, the m×m data units form an m-order matrix A, the m×m data units are m×m elements in the matrix A, m 1×m matrices in the matrix A are in a one-to-one correspondence with the m data streams, m elements located in a same m×1 matrix of m m×1 matrices in the matrix A are received by the receiving unit at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix A, an element located on a right side is received by the receiving unit earlier than an element located on a left side;

an encoding unit, configured to keep a location of one element in each row in the matrix A received by the receiving unit unchanged and move remaining m-1 elements to remaining m-1 rows respectively so as to form an m-order matrix B, where a column number of each element in the remaining m-1 elements in the matrix A before the element is moved equals a column number of the element in the remaining m-1 elements in the matrix B after the element is moved, and the m×m elements in the matrix A are in a one-to-one correspondence with m×m elements in the matrix B; and

a sending unit, configured to send, by using m transmit ports, the m×m elements in the matrix B generated by the encoding unit to m different levels of a PAM circuit respectively for performing modulation, where m 1×m matrices in the matrix B are in a one-to-one correspondence with the m different levels of the PAM circuit, m elements located in a same m×1 matrix of m m×1 matrices in the matrix B are sent by the sending unit at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix B, an element located on a right side is sent by the sending unit earlier than an element located on a left side;

the receiving unit is further configured to receive m data units by using the m receive ports respectively, wherein the received m data units are in a one-to-one correspondence with the m receive ports, the received m data units are received by the receiving unit at a same time, and the time at which the receiving unit receives the received m data units is different from a time at which the receiving unit receives m data units in any m×1 matrix of the m m×1 matrices in the matrix A; and

the sending unit is further configured to send, by using the m transmit ports, the received m data units to the m different levels of the PAM circuit respectively for performing modulation, wherein the received m data units are in a one-to-one correspondence with the m different levels.



[0016] With reference to the third aspect, in a first implementation manner of the third aspect, the m×m elements in the matrix A are denoted by aij, the m×m elements in the matrix B are denoted by bij, i=1, ..., m, and j=1, ..., m, where
bij = axj, and a value of x is:

when i+k≤m, x=i+k, and when i+k>m, x=i+k-m, where k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix B correspond to different k values respectively; or

when i-k>0, x=i-k, and when i-k≤0, x=i-k+m, where k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix B correspond to different k values respectively.



[0017] With reference to the first implementation manner of the third aspect, in a second implementation manner of the third aspect,
a difference between k values corresponding to two adjacent elements of elements in each row in the matrix B is 1.

[0018] According to a fourth aspect, a data processing apparatus is provided, including:

a receiving unit, configured to receive m demodulated data streams by using m receive ports respectively, where m is an integer greater than 1, the m receive ports are in a one-to-one correspondence with the m data streams, and the m data streams include m×m data units, where each data stream of the m data streams includes m data units, the m×m data units form an m-order matrix C, the m×m data units are m×m elements in the matrix C, m 1×m matrices in the matrix C are in a one-to-one correspondence with the m data streams, m elements located in a same m×1 matrix of m m×1 matrices in the matrix C are received by the receiving unit at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix C, an element located on a right side is received by the receiving unit earlier than an element located on a left side;

a decoding unit, configured to keep a location of one element in each row in the matrix C received by the receiving unit unchanged and move remaining m-1 elements to remaining m-1 rows respectively so as to form an m-order matrix D, where a column number of each element in the remaining m-1 elements in the matrix C before the element is moved equals a column number of the element in the remaining m-1 elements in the matrix D after the element is moved, and the m×m elements in the matrix C are in a one-to-one correspondence with m×m elements in the matrix D; and

a sending unit, configured to send, by using m transmit ports, the m×m elements in the matrix D generated by the decoding unit, where m elements located in a same m×1 matrix of m m×1 matrices in the matrix D are sent by the sending unit at a same time, and among m elements located in a same 1×m matrix of m 1×m matrices in the matrix D, an element located on a right side is sent by the sending unit earlier than an element located on a left side;

the receiving unit is further configured to receive m demodulated data units by using the m receive ports respectively, wherein the received and demodulated m data units are in a one-to-one correspondence with the m receive ports, the received and demodulated m data units are received by the receiving unit at a same time, and the time at which the receiving unit receives the received and demodulated m data units is different from a time at which the receiving unit receives m data units in any m×1 matrix of the m m×1 matrices in the matrix C; and

the sending unit is further configured to send the received and demodulated m data units by using the m transmit ports respectively, wherein the received and demodulated m data units are in a one-to-one correspondence with the m transmit ports.



[0019] With reference to the fourth aspect, in a first implementation manner of the fourth aspect, the m×m elements in the matrix C are denoted by cij, the m×m elements in the matrix D are denoted by dij, i=1, ..., m, and j=1, ..., m, where
dij = cyj, and a value of y is:

when i-k>0, y=i-k, and when i-k≤0, y=i-k+m, where k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix D correspond to different k values respectively; or

when i+k≤m, y=i+k, and when i+k>m, y=i+k-m, where k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix D correspond to different k values respectively.



[0020] With reference to the first implementation manner of the fourth aspect, in a second implementation manner of the fourth aspect, a difference between k values corresponding to two adjacent elements of elements in each row in the matrix D is 1.

[0021] It can be seen from the foregoing technical solutions that, the embodiments of the present invention have the following advantages:
In the background art, bit error rates that occur in different links are different. In the embodiments of the present invention, before data streams in m links are sent to m different levels of a PAM circuit for performing modulation, an m-order matrix A formed by m data units on each link of the m links is coded by using an encoding circuit, so that m data units that are originally located in a same link and are to enter a same level of the PAM circuit for performing modulation are transmitted on the m links respectively and enter the m different levels of the PAM circuit respectively for performing modulation. After a pulse signal sent by the PAM circuit is demodulated and decoded by a receive end, in data transmitted on the m links, a bit error rate corresponding to data transmitted on each link is the same or approximately the same. Therefore, a same FEC circuit may be configured for different links, which helps to reduce implementation complexity.

BRIEF DESCRIPTION OF DRAWINGS



[0022] 

FIG. 1 is a schematic structural diagram of a PAM-M circuit according to this embodiment;

FIG. 2 is a flowchart of an embodiment of a data processing method according to the present invention;

FIG. 3 is a schematic diagram of a matrix A, a matrix B, m links, and a PAM-M circuit;

FIG. 4 is a flowchart of an embodiment of a data processing method according to the present invention;

FIG. 5 is a schematic structural diagram of an embodiment of a data processing apparatus according to the present invention;

FIG. 6 is a schematic structural diagram of an embodiment of a data processing apparatus according to the present invention; and

FIG. 7 is a schematic structural diagram of an embodiment of an encoding circuit according to the present invention.


DESCRIPTION OF EMBODIMENTS



[0023] In a data transmission network provided in an embodiment of the present invention, a transmit end may perform modulation on data before sending the data to a receive end. As shown in FIG. 1, FIG. 1 is a schematic structural diagram of a PAM-M circuit provided in this embodiment. Data transmitted on m links is input to the PAM-M circuit for performing modulation. The PAM-M circuit is configured to modulate data transmitted on the kth link of the m links to a level corresponding to 2k-1, where k=1, ..., m.

[0024] At the transmit end, the m links are connected to the PAM-M circuit separately, and the m links send the data to the PAM-M circuit for performing modulation. The data transmitted on the kth link of the m links is modulated to the level corresponding to 2k-1 . At a time, the kth link sends only one data unit to the PAM-M circuit for performing modulation, where k=1, ..., m. The data unit may be one bit or one symbol (symbol), where one symbol includes at least two bits. The PAM-M circuit modulates m data units received at a same time into a pulse signal having an amplitude corresponding to the m data units, and sends the pulse signal to the receive end.

[0025] After the receive end receives the pulse signal, a demodulation circuit at the receive end demodulates the pulse signal into m data units according to the amplitude of the pulse signal, and transmits the m data units by using m links respectively.

[0026] An error may occur in a transmission process in which the pulse signal is transmitted to the receive end, so that a bit error may occur in the m data units obtained after demodulation. Therefore, at the receive end, an FEC circuit is configured for each link of the m links separately, and is configured to perform error correction on data transmitted on the link.

[0027] After demodulation, bit error rates corresponding to data transmitted on different links of the m links may be different. In order to enable the m links to use a same FEC circuit, data transmitted on the m links may be processed first, and then the processed data is sent, by using the m links, to the PAM-M circuit at the transmit end for performing modulation. Performing data processing on the data transmitted on the m links is specifically coding the data transmitted on the m links.

[0028] After the demodulation circuit at the receive end demodulates modulated data, the receive end may perform a reverse operation of the foregoing data processing on demodulated data by using a decoding circuit. Then, m FEC circuits at the receive end perform error correction on data obtained after the reverse operation. Specifically, the receive end performs a reverse operation of coding on the data transmitted on the m links, so as to try to generate data that is before an encoding circuit at the transmit end performs a coding operation on the data transmitted on the m links. In this way, bit error rates of data transmitted on the m links and generated by the decoding circuit can be approximately the same or the same. Further, the m links at the receive end may use a same FEC circuit to perform error correction on the data transmitted on the m links respectively. Therefore, the foregoing solution helps to reduce implementation complexity.

[0029] For example, the data processing may be executed by the encoding circuit. The encoding circuit may be a component in a PHY, a PHY chip (PHY chip), a system chip (system chip), a multi-port Ethernet device (multi-port Ethernet device), or an optical module (Optical Module).

[0030] The PHY may be implemented by using an FPGA or an ASIC. The PHY may be a component in a network interface card (Network Interface Card, NIC), where the NIC may be a line card (Line Card) or a PIC (Physical Interface Card, physical interface card). The PHY may include a Media-Independent Interface (media-independent interface, MII) for interfacing to (for interfacing to) a MAC.

[0031] The PHY chip may include multiple PHYs. The PHY chip may be implemented by using an FPGA or an ASIC.

[0032] The system chip may include multiple MACs and multiple PHYs. The system chip may be implemented by using an FPGA or an ASIC.

[0033] The multi-port Ethernet device may be an Ethernet hub, an Ethernet router, or an Ethernet switch. The multi-port Ethernet device includes multiple ports, where each port may include a system chip, and the system chip may include a MAC and a PHY. The multi-port Ethernet device may further integrate multiple MACs into one MAC chip (MAC chip), and integrate multiple PHYs into one PHY chip. The multi-port Ethernet device may further integrate multiple MACs and multiple PHYs into one system chip.

[0034] The reverse operation of the data processing may be executed by the decoding circuit. The decoding circuit may be a component in a PHY, a PHY chip, a system chip, a multi-port Ethernet device, or an Optical Module.

[0035] In order to enable a person skilled in the art to better understand the solutions in the embodiments of the present invention, the following describes the embodiments of the present invention in more detail with reference to accompanying drawings and implementation manners.

[0036] Referring to FIG. 2, FIG. 2 is a flowchart of an embodiment of a data processing method according to the present invention. This embodiment describes in detail how an encoding circuit codes received data. In this embodiment, the data processing method includes:
S201: The encoding circuit receives m data streams by using m receive ports respectively, where m is an integer greater than 1, the m receive ports are in a one-to-one correspondence with the m data streams, and the m data streams include m×m data units, where each data stream of the m data streams includes m data units, the m×m data units form an m-order matrix A, the m×m data units are m×m elements in the matrix A, m 1×m matrices in the matrix A are in a one-to-one correspondence with the m data streams, m elements located in a same m×1 matrix of m m×1 matrices in the matrix A are received by the encoding circuit at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix A, an element located on a right side is received by the encoding circuit earlier than an element located on a left side.

[0037] In this embodiment, the m receive ports of the encoding circuit are in a one-to-one correspondence with m links respectively, and each receive port is configured to receive, in chronological sequence, data transmitted on a link corresponding to the receive port. For ease of description, in this embodiment, r is used to indicate a link of the m links, and t is used to indicate a receive port of the m receive ports, where r=1, ..., m, and t=1, ..., m. A receive port w is configured to receive, in chronological sequence, data transmitted on a link w. For example, a receive port 2 is configured to receive, in chronological sequence, data transmitted on a link 2. It should be noted that, in this specification, the link w and the wth link refer to a same link.

[0038] For example, m may be equal to 2, 3, 4, or 5.

[0039] Each receive port of the encoding circuit receives only one data unit at a time. For example, each receive port of the encoding circuit receives only one data unit during one clock cycle. The m receive ports receive m data units at a same time. For example, the m receive ports receive m data units during a same clock cycle. In order to make description of the solution clearer, in the whole specification, m data units in data transmitted on each link are regarded as one data stream. In addition, a matrix, which is a basic concept in mathematics, is used to describe the m data streams. In the following description, one element in a matrix is one data unit in a data stream.

[0040] In order to describe more intuitively the m-order matrix A corresponding to the m data streams, refer to FIG. 3. FIG. 3 is a schematic diagram of a matrix A, a matrix B, m links, and a PAM-M circuit. One data stream on each link of the m links form one line of the m-order matrix A, and each row consists of m data units. That is, one data stream on each link corresponds to one 1×m matrix, and the m-order matrix A includes m 1×m matrices. Moreover, a row number of a data stream in the matrix A is equal to a number of a link in which the data stream is located. For example, m elements located in the 3rd row in the matrix A are a data stream transmitted on a link 3.

[0041] The m data units in each data stream of the m data streams are the 1st data unit to the mth data unit respectively. A time sequence in which the encoding circuit receives the m data units in each data stream is from the mth data unit to the 1st data unit separately. For example, when m is equal to 3, the encoding circuit receives the 3rd data unit, the 2nd data unit, and the 1st data unit in the 1st clock cycle, the 2nd clock cycle, and the 3rd clock cycle respectively. The 1st clock cycle is a clock cycle previous to the 2nd clock cycle, and the 2nd clock cycle is a clock cycle previous to the 3rd clock cycle. The ith data unit in each data stream of the m data streams forms the ith (where i=1, ..., m) column of the m-order matrix. Each column of the m-order matrix consists of m data units. That is, each column corresponds to one m×1 matrix. The m-order matrix includes m m×1 matrices, and m elements located in a same m×1 matrix are received by the encoding circuit at a same time.

[0042] For any two adjacent data units in any 1×m matrix of the m 1×m matrices, a data unit located on a right side is received by the encoding circuit earlier than a data unit located on a left side. As shown in FIG. 3, a flow direction of the M data streams is from left to right. The flow direction of the M data streams in FIG. 3 is only exemplary, and does not indicate that a flow direction of a data stream in all scenarios applied to the embodiments of the present invention can only be from left to right.

[0043] S202: The encoding circuit keeps a location of one element in each row in the matrix A unchanged and moves remaining m-1 elements to remaining m-1 rows respectively so as to form an m-order matrix B, where a column number of each element in the remaining m-1 elements in the matrix A before the element is moved equals a column number of the element in the remaining m-1 elements in the matrix B after the element is moved, and the m×m elements in the matrix A are in a one-to-one correspondence with m×m elements in the matrix B.

[0044] For example, when the encoding circuit codes received data units, content of the data units is not changed, and only locations of the data units in the matrix A are changed so as to form the matrix B. When locations of elements in the matrix A are changed, a location of one element in each row in the matrix A is kept unchanged, and remaining m-1 elements are moved to remaining m-1 rows respectively so as to form the matrix B. In a process in which each element in the remaining m-1 elements is moved, a number of a row in which the element is located is changed, but a number of a column in which the element is located is not changed. An element, whose location is kept unchanged, in each row in the matrix A is referred to as a fixed element, and m fixed elements in the matrix A may be located in a same column, or may be located in different columns respectively.

[0045] In order to describe the solution more clearly, aij is introduced below to indicate the m×m elements in the matrix A, and bij is introduced to indicate the m×m elements in the matrix B, where i =1, ..., m, and j=1, ..., m. The following describes a first specific implementation manner of a method for changing locations of elements in the matrix A.

[0046] For elements in the 1st column on a left side of the matrix A, locations of all the elements are kept unchanged.

[0047] That is, bi1 = ax1, where x=i.

[0048] For elements in the 2nd column on the left side of the matrix A, all the elements are moved downward by one row; then, in the 2nd column, an element located in the mth row is moved to the 1st row.

[0049] That is, bi2 = ax2, where when i-1>0, x=i-1, and when i-1≤0, x=i-1+m, that is, when i=1, x=m.

[0050] For elements in the 3rd column on the left side of the matrix A, all the elements are moved downward by two rows; then, in the 3rd column, an element located in the mth row is moved to the 2nd row, and an element located in the m-1th row is moved to the 1st row.

[0051] That is, bi3 = ax3, where when i-2>0, x=i-2, and when i-2<0, x=i-2+m; that is, when i=2, x=m, and when i=1, x=m-1.

[0052] Elements in another column on the left side of the matrix A are deduced by analogy. That is, bij = axj, and a value of x complies with the following constraints: when i-k>0, x=i-k, and when i-k≤0, x=i-k+m, where k is a quantity of rows by which elements in the k+1th column on the left side of the matrix A are moved downward, and k is an integer greater than or equal to 0 and less than m, that is, k=0, ..., m-1. In the matrix B, m elements in a same row correspond to different k values respectively. A difference between k values corresponding to two adjacent elements of elements in each row in the matrix B is 1.

[0053] Alternatively, in a second specific implementation manner of the method for changing locations of elements in the matrix A, it may also be that locations of elements in the 1st column on a right side of the matrix A are kept unchanged. Elements in the 2nd column on the right side of the matrix A are moved downward by one row, elements in the 3rd column on the right side of the matrix A are moved downward by two rows, and another column on the right side of the matrix A is deduced by analogy. That is, bij = axj, and a value of x complies with the following constraints: when i-k>0, x=i-k, and when i-k≤0, x=i-k+m, where k is a quantity of rows by which elements in the k+1th column on the right side of the matrix A are moved downward, and k is an integer greater than or equal to 0 and less than m, that is, k=0, ..., m-1. In the matrix B, m elements in a same row correspond to different k values respectively. A difference between k values corresponding to two adjacent elements of elements in each row in the matrix B is 1.

[0054] Alternatively, when the locations of the elements in the matrix A are changed, elements in each column may moved upward instead of moving downward. The following describes a third specific implementation manner of the method for changing locations of elements in the matrix A.

[0055] For elements in the 1st column on a left side of the matrix A, locations of all the elements are kept unchanged.

[0056] That is, bi1 = ax1, where x=i.

[0057] For elements in the 2nd column on the left side of the matrix A, all the elements are moved upward by one row; then, in the 2nd column, an element located in the 1st row is moved to the mth row.

[0058] That is, bi2 = ax2, where when i+1≤m, x=i+1, and when i+1>m, x=i+1-m, that is, when i=m, x=1.

[0059] For elements in the 3rd column on the left side of the matrix A, all the elements are moved upward by two rows; then, in the 3rd column, an element located in the 2nd row is moved to the mth row, and an element located in the 1st row is moved to the m-1th row.

[0060] That is, bi3 = ax3, where when i+2≤m, x=i+2, and when i+2>m, x=i+2-m; that is, when i=m, x=2, and when i=m-1, x=1.

[0061] Elements in another column on the left side of the matrix A are deduced by analogy. That is, bij = axj, and a value of x complies with the following constraints: when i+k≤m, x=i+k, and when i+k>m, x=i+k-m, where k is a quantity of rows by which elements in the k+1th column on the left side of the matrix A are moved upward, and k is an integer greater than or equal to 0 and less than m, that is, k=0, ..., m-1. In the matrix B, m elements in a same row correspond to different k values respectively. A difference between k values corresponding to two adjacent elements of elements in each row in the matrix B is 1.

[0062] Alternatively, in a fourth specific implementation manner of the method for changing locations of elements in the matrix A, it may also be that locations of elements in the 1st column on a right side of the matrix A are kept unchanged. Elements in the 2nd column on the right side of the matrix A are moved upward by one row, elements in the 3rd column on the right side of the matrix A are moved upward by two rows, and another column on the right side of the matrix A is deduced by analogy. That is, bij = axj, and a value of x complies with the following constraints: when i+k≤m, x=i+k, and when i+k>m, x=i+k-m, where k is a quantity of rows by which elements in the k+1th column on the right side of the matrix A are moved upward, and k is an integer greater than or equal to 0 and less than m, that is, k=0, ..., m-1. In the matrix B, m elements in a same row correspond to different k values respectively. A difference between k values corresponding to two adjacent elements of elements in each row in the matrix B is 1.

[0063] In the foregoing four specific implementation manners of the method for changing locations of elements in the matrix A, a difference between k values corresponding to two adjacent elements of m elements in each row in the matrix B is 1, and a value of k corresponding to elements in the 1st column on a left side or elements in the 1st column on a right side of the matrix B is 0. Alternatively, in another specific implementation manner of the method for changing locations of elements in the matrix A, a value of k corresponding to elements in the 1st column on a left side or elements in the 1st column on a right side of the matrix B may also not be 0, but be any integer greater than 0 and less than m.

[0064] Further, in another specific implementation manner of the method for changing locations of elements in the matrix A, a difference between k values corresponding to two adjacent elements of elements in each row in the matrix B may also not be 1 but anther value, as long as m elements in a same row in the matrix B correspond to different k values respectively, where k is an integer greater than or equal to 0 and less than m.

[0065] S203: The encoding circuit sends, by using m transmit ports, the m×m elements in the matrix B to m different levels of a PAM circuit respectively for performing modulation, where m 1×m matrices in the matrix B are in a one-to-one correspondence with the m different levels of the PAM circuit, m elements located in a same m×1 matrix of m m×1 matrices in the matrix B are sent by the encoding circuit at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix B, an element located on a right side is sent by the encoding circuit earlier than an element located on a left side.

[0066] In this embodiment, the m transmit ports of the encoding circuit are in a one-to-one correspondence with m rows of elements in the matrix B, and each transmit port is configured to send, in chronological sequence, one line of elements corresponding to the transmit port. As shown in FIG. 3, for ease of description, in this embodiment, e is used to indicate a transmit port of the m transmit ports, where e=1, ..., m. A transmit port w is configured to send, in chronological sequence, elements in the wth row in the matrix B. For example, a transmit port 4 is configured to send, in chronological sequence, m elements in the 4th row in the matrix B.

[0067] Among m elements in each row in the matrix B, an element located on a right side is received by the encoding circuit earlier than an element on a left side. Moreover, during sending, m elements located in a same column in the matrix B are sent by the encoding circuit at a same time.

[0068] Optionally, in the foregoing technical solution, the data processing method shown in FIG. 2 may further include:
receiving, by the encoding circuit, m data units by using the m receive ports respectively.

[0069] The received m data units are in a one-to-one correspondence with the m receive ports, the received m data units are received by the encoding circuit at a same time, and the time at which the encoding circuit receives the received m data units is different from a time at which the encoding circuit receives m data units in any m×1 matrix of the m m×1 matrices in the matrix A.

[0070] The encoding circuit sends, by using the m transmit ports, the received m data units to the m different levels of the PAM circuit respectively for performing modulation.

[0071] The received m data units are in a one-to-one correspondence with the m different levels.

[0072] Specifically, the received m data units are independent of the m×m data units in the matrix A, the received m data units are not a subset of the m×m data units in the matrix A, and the time at which the encoding circuit receives the received m data units is different from a time at which the encoding circuit receives m data units in any m×1 matrix of the m m×1 matrices in the matrix A. For example, the time at which the encoding circuit receives the received m data units is different from a time at which the encoding circuit receives m data units in an m×1 matrix on the far left of the m m×1 matrices in the matrix A; the time at which the encoding circuit receives the received m data units is different from a time at which the encoding circuit receives m data units in an m×1 matrix on the far right of the m m×1 matrices in the matrix A.

[0073] By using the foregoing technical solution, the encoding circuit may perform different processing on data units received at different times. Specifically, for some data units (for example, the m×m data units in the matrix A), processing (for example, moving locations of data units in the matrix) of S202 may be executed. For other data units (for example, the received m data units), the processing of S202 is not executed before the data units are sent to the m different levels of the PAM circuit for performing modulation, which is equivalent to bypassing the processing of S202.

[0074] In this embodiment, a schematic structural diagram of the PAM-M circuit may be that shown in FIG. 1 and FIG. 3. Data transmitted on m links is input to the PAM-M circuit for performing modulation. The PAM-M circuit is configured to modulate data transmitted on the kth link of the m links to a level corresponding to 2k-1 , where k=1, ..., m.

[0075] As shown in FIG. 3, the m transmit ports of the encoding circuit are in a one-to-one correspondence with the m links, and data sent by each transmit port w enters the PAM-M circuit in chronological sequence by using the link w, and is modulated by the PAM-M circuit to a level corresponding to 2w-1. For example, data sent by a transmit port 5 is sent to the PAM-M circuit by using a link 5, and is modulated by the PAM-M circuit to a level corresponding to 24.

[0076] It should be noted that, data sent by the encoding circuit may not necessarily directly enter the PAM-M circuit for performing modulation. Another apparatus, for example, a precoding circuit, may also be disposed between the encoding circuit and the PAM-M circuit, which is not limited herein.

[0077] In this embodiment, before data streams in m links are sent to m different levels of a PAM circuit for performing modulation, an m-order matrix A formed by m data units on each link of the m links is coded by using an encoding circuit, so that m data units that are originally located in a same link and are to enter a same level of the PAM circuit for performing modulation are dispersed to the m links respectively and enter the m different levels of the PAM circuit respectively for performing modulation. In this way, when m pulse signals sent by the PAM circuit are successively demodulated and decoded to the m links, a probability that a bit error occurs on each link can be balanced, and therefore FEC circuits corresponding to different links may use a same FEC gain, and system implementation complexity is reduced.

[0078] The foregoing describes a data processing method at a transmit end with reference to FIG. 2 and FIG. 3. The following describes a reverse operation of the foregoing data processing method at a receive end with reference to FIG. 4. For ease of description, the reverse operation of the foregoing data processing method is referred to as a data processing method.

[0079] Referring to FIG. 4, FIG. 4 is a flowchart of an embodiment of a data processing method according to the present invention. In this embodiment, the data processing method includes:
S401: A decoding circuit receives m demodulated data streams by using m receive ports respectively, where m is an integer greater than 1, the m receive ports are in a one-to-one correspondence with the m data streams, and the m data streams include m×m data units, where each data stream of the m data streams includes m data units, the m×m data units form an m-order matrix C, the m×m data units are m×m elements in the matrix C, m 1×m matrices in the matrix C are in a one-to-one correspondence with the m data streams, m elements located in a same m×1 matrix of m m×1 matrices in the matrix C are received by the decoding circuit at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix C, an element located on a right side is received by the decoding circuit earlier than an element located on a left side.

[0080] For example, m may be equal to 2, 3, 4, or 5.

[0081] For example, the m data streams may be obtained by using the following way: a demodulation circuit receives a pulse signal sent by a transmit end, and the demodulation circuit demodulates the pulse signal into m data units and transmits the m data units by using m links respectively.

[0082] Each receive port of the decoding circuit receives only one data unit at a time. For example, each receive port of the decoding circuit receives only one data unit during one clock cycle. The m receive ports receive m data units at a same time. For example, the m receive ports receive m data units during a same clock cycle.

[0083] The m receive ports of the decoding circuit are in a one-to-one correspondence with m links respectively, and each receive port is configured to receive, in chronological sequence, data transmitted on a link corresponding to the receive port.

[0084] A process in which the m receive ports of the decoding circuit receive the m demodulated data streams respectively is similar to a process in which "m receive ports of an encoding circuit receive m data streams respectively" in S201 in the embodiment shown in FIG. 2. For details, reference may be made to related description of S201, which is not described herein again.

[0085] S402: The decoding circuit keeps a location of one element in each row in the matrix C unchanged and moves remaining m-1 elements to remaining m-1 rows respectively so as to form an m-order matrix D, where a column number of each element in the remaining m-1 elements in the matrix C before the element is moved equals a column number of the element in the remaining m-1 elements in the matrix D after the element is moved, and the m×m elements in the matrix C are in a one-to-one correspondence with m×m elements in the matrix D.

[0086] For example, when the decoding circuit decodes received data units, content of the data units is not changed, and only locations of the data units in the matrix C are changed so as to form the matrix D.

[0087] When locations of elements in the matrix C are changed, a location of one element in each row in the matrix C is kept unchanged, and remaining m-1 elements are moved to remaining m-1 rows respectively so as to form the matrix D. In a process in which each element in the remaining m-1 elements is moved, a number of a row in which the element is located is changed, but a number of a column in which the element is located is not changed. An element, whose location is kept unchanged, in each row in the matrix C is referred to as a fixed element.

[0088] The decoding circuit decodes the received data units to execute a reverse operation corresponding to data processing in the embodiment shown in FIG. 2. Therefore, a fixed element in each row in the matrix C is separately the same as a fixed element in each row in the matrix A in the embodiment shown in FIG. 2. When the remaining m-1 elements in each row in the matrix C are moved to the remaining m-1 rows respectively, a specific implementation manner depends on a specific implementation manner that is used by the encoding circuit at the transmit end to change locations of elements in the matrix A.

[0089] In order to describe the solution more clearly, cij is introduced below to indicate the m×m elements in the matrix C, and dij is introduced to indicate the m×m elements in the matrix D, where i=1, ..., m, and j=1, ..., m.

[0090] When a method for changing locations of elements in the matrix A is specifically the first specific implementation manner of S202 in the embodiment shown in FIG. 2, a method for changing locations of elements in the matrix C is specifically as follows:
For elements in the 1st column on a left side of the matrix C, locations of all the elements are kept unchanged.

[0091] That is, di1 = cy1, where y=i.

[0092] For elements in the 2nd column on the left side of the matrix C, all the elements are moved upward by one row; then, in the 2nd column, an element located in the 1st row is moved to the mth row.

[0093] That is, di2 = cy2, where when i+1≤m, y=i+1, and when i+1>m, y=i+1-m, that is, when i=m, y=1.

[0094] For elements in the 3rd column on the left side of the matrix C, all the elements are moved upward by two rows; then, in the 3rd column, an element located in the 2nd row is moved to the mth row, and an element located in the 1st line is moved to the m-1th row.

[0095] That is, di3 = cy3, where when i+2≤m, y=i+2, and when i+2>m, y=i+2-m; that is, when i=m, y=2, and when i= m-1, y=1.

[0096] Elements in another column on the left side of the matrix C are deduced by analogy. That is, dij = cyj, and a value of y complies with the following constraints: when i+k≤m, y=i+k, and when i+k>m, y=i+k-m, where k is a quantity of rows by which elements in the k+1th column on the left side of the matrix C are moved upward, and k is an integer greater than or equal to 0 and less than m, that is, k=0, ..., m-1. In the matrix D, m elements in a same row correspond to different k values respectively. A difference between k values corresponding to two adjacent elements of elements in each row in the matrix D is 1.

[0097] When the method for changing locations of elements in the matrix A is specifically the second specific implementation manner of S202 in the embodiment shown in FIG. 2, the method for changing locations of elements in the matrix C is specifically as follows:
Locations of elements in the 1st column on a right side of the matrix C are kept unchanged. Elements in the 2nd column on the right side of the matrix C are moved upward by one row, elements in the 3rd column on the right side of the matrix C are moved upward by two rows, and another column on the right side of the matrix C is deduced by analogy. It can be obtained that bij = ayj, and a value of y complies with the following constraints: when i+k≤m, y=i+k, and when i+k>m, y=i+k-m, where k is a quantity of rows by which elements in the k+1th column on the right side of the matrix C are moved upward, and k is an integer greater than or equal to 0 and less than m, that is, k=0, ..., m-1. In the matrix D, m elements in a same row correspond to different k values respectively. A difference between k values corresponding to two adjacent elements of elements in each row in the matrix D is 1.

[0098] When the method for changing locations of elements in the matrix A is specifically the third specific implementation manner of S202 in the embodiment shown in FIG. 2, the method for changing locations of elements in the matrix C is specifically as follows:
For elements in the 1st column on a left side of the matrix C, locations of all the elements are kept unchanged.

[0099] That is, di1 = cy1, where y=i.

[0100] For elements in the 2nd column on the left side of the matrix C, all the elements are moved downward by one row; then, in the 2nd column, an element located in the mth row is moved to the 1st row.

[0101] That is, di2 = cy2, where when i-1>0, y=i-1, and when i-1≤0, y=i-1+m, that is, when i=1, y=m.

[0102] For elements in the 3rd column on the left side of the matrix C, all the elements are moved downward by two rows; then, in the 3rd column, an element located in the mth row is moved to the 2nd row, and an element located in the m-1th row is moved to the 1st row.

[0103] That is, di3 = cy3, where when i-2>0, y=i-2, and when i-2≤0, y=i-2+m; that is, i=2, y=m, and when i=1, y=m-1.

[0104] Elements in another column on the left side of the matrix C are deduced by analogy. That is, bij = axj, and a value of y complies with the following constraints: when i-k>0, y=i-k, and when i-k≤0, y=i-k+m, where k is a quantity of rows by which elements in the k+1th column on the left side of the matrix C are moved downward, and k is an integer greater than or equal to 0 and less than m, that is, k=0, ..., m-1. In the matrix D, m elements in a same row correspond to different k values respectively. A difference between k values corresponding to two adjacent elements of elements in each row in the matrix D is 1.

[0105] When the method for changing locations of elements in the matrix A is specifically the fourth specific implementation manner of S202 in the embodiment shown in FIG. 2, the method for changing locations of elements in the matrix C is specifically as follows:
Locations of elements in the 1st column on a right side of the matrix C are kept unchanged. Elements in the 2nd column on the right side of the matrix C are moved downward by one row, elements in the 3rd column on the right side of the matrix C are moved downward by two rows, and another column on the right side of the matrix C is deduced by analogy. That is, dij = cij, and a value of y complies with the following constraints: when i-k>0, y=i-k, and when i-k≤0, y=i-k+m, where k is a quantity of rows by which elements in the k+1th column on the right side of the matrix C are moved downward, and k is an integer greater than or equal to 0 and less than m, that is, k=0, ..., m-1. In the matrix D, m elements in a same row correspond to different k values respectively. A difference between k values corresponding to two adjacent elements of elements in each row in the matrix D is 1.

[0106] In another specific implementation manner of changing locations of elements in the matrix A, that is, when a difference between k values corresponding to two adjacent elements of m elements in each row in the matrix B is 1, and a value of k corresponding to elements in the 1st column on a left side or elements in the 1st column on a right side of the matrix B is any integer (denoted by g) greater than 0 and less than m, the method for changing locations of elements in the matrix C is correspondingly: a difference between k values corresponding to two adjacent elements of m elements in each row in the matrix D is 1, and a value of k corresponding to elements in the 1st column on a left side or elements in the 1st column on a right side of the matrix D is g.

[0107] Further, when the method for changing locations of elements in the matrix A is that m elements in a same row in the matrix B correspond to different k values respectively, where k is an integer greater than or equal to 0 and less than m, the method for changing locations of elements in the matrix C is correspondingly: m elements in a same row in the matrix D correspond to different k values respectively, where k is an integer greater than or equal to 0 and less than m.

[0108] S403: The decoding circuit sends the m×m elements in the matrix D by using m transmit ports, where m elements located in a same m×1 matrix of m m×1 matrices in the matrix D are sent by the decoding circuit at a same time, and among m elements located in a same 1×m matrix of m 1×m matrices in the matrix D, an element located on a right side is sent by the encoding circuit earlier than an element located on a left side.

[0109] In this embodiment, a process in which the m transmit ports of the decoding circuit send the m×m elements in the matrix D is similar to a process in which "m transmit ports of an encoding circuit send m×m elements in the matrix B" in S203 in the embodiment shown in FIG. 2. For details, reference may be made to related description of S203, which is not described herein again.

[0110] Optionally, in the foregoing technical solution, the data processing method shown in FIG. 4 may further include:
receiving, by the decoding circuit, m demodulated data units by using the m receive ports respectively.

[0111] The received and demodulated m data units are in a one-to-one correspondence with the m receive ports, the received and demodulated m data units are received by the decoding circuit at a same time, and the time at which the decoding circuit receives the received and demodulated m data units is different from a time at which the decoding circuit receives m data units in any m×1 matrix of the m m×1 matrices in the matrix C.

[0112] The decoding circuit sends the received and demodulated m data units by using the m transmit ports respectively.

[0113] The received and demodulated m data units are in a one-to-one correspondence with the m transmit ports.

[0114] Specifically, the received and demodulated m data units are independent of the m×m data units in the matrix C, the received and demodulated m data units are not a subset of the m×m data units in the matrix C, and the time at which the decoding circuit receives the received and demodulated m data units is different from a time at which the decoding circuit receives m data units in any m×1 matrix of the m m×1 matrices in the matrix C. For example, the time at which the decoding circuit receives the received and demodulated m data units is different from a time at which the decoding circuit receives m data units in an m×1 matrix on the far left of the m m×1 matrices in the matrix C; the time at which the decoding circuit receives the received and demodulated m data units is different from a time at which the decoding circuit receives m data units in an m×1 matrix on the far right of the m m×1 matrices in the matrix C.

[0115] By using the foregoing technical solution, the decoding circuit may perform different processing on data units received at different times. Specifically, for some data units (for example, the m×m data units in the matrix C), processing (for example, moving locations of data units in the matrix) of S402 may be executed. For other data units (for example, the received and demodulated m data units), the processing of S402 is not executed before the data units are sent by using the m transmit ports, which is equivalent to bypassing the processing of S402.

[0116] The foregoing describes a data processing method in an embodiment of the present invention. The following describes a data processing apparatus in an embodiment of the present invention. Referring to FIG. 5, FIG. 5 is a schematic structural diagram of an embodiment of a data processing apparatus according to the present invention. A data processing apparatus 500 in this embodiment may be configured to execute the data processing method in the embodiment shown in FIG. 2. The data processing apparatus 500 in this embodiment of the present invention includes a receiving unit 501, an encoding unit 502, and a sending unit 503.

[0117] The receiving unit 501 is configured to receive m data streams by using m receive ports respectively, where m is an integer greater than 1, the m receive ports are in a one-to-one correspondence with the m data streams, and the m data streams include m×m data units, where each data stream of the m data streams includes m data units, the m×m data units form an m-order matrix A, the m×m data units are m×m elements in the matrix A, m 1×m matrices in the matrix A are in a one-to-one correspondence with the m data streams, m elements located in a same m×1 matrix of m m×1 matrices in the matrix A are received by the receiving unit 501 at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix A, an element located on a right side is received by the receiving unit 501 earlier than an element located on a left side.

[0118] For example, the receiving unit 501 in this embodiment may be a receiver. The receiving unit 501 may be configured to execute S201 in the data processing method shown in FIG. 2. For details about the receiving unit 501, reference may be made to related description of S201, which is not described herein again.

[0119] The encoding unit 502 is configured to keep a location of one element in each row in the matrix A received by the receiving unit 501 unchanged and move remaining m-1 elements to remaining m-1 rows respectively so as to form an m-order matrix B, where a column number of each element in the remaining m-1 elements in the matrix A before the element is moved equals a column number of the element in the remaining m-1 elements in the matrix B after the element is moved, and the m×m elements in the matrix A are in a one-to-one correspondence with m×m elements in the matrix B.

[0120] For example, the encoding unit 502 in this embodiment may be an encoder.

[0121] Optionally, the m×m elements in the matrix A are denoted by aij, the m×m elements in the matrix B are denoted by bij, i=1, ..., m, and j=1, ..., m, where
bij = axj, and a value of x is:

when i+k≤m, x=i+k, and when i+k>m, x=i+k-m, where k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix B correspond to different k values respectively; or

when i-k>0, x=i-k, and when i-k≤0, x=i-k+m, where k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix B correspond to different k values respectively.



[0122] Optionally, a difference between k values corresponding to two adjacent elements of elements in each row in the matrix B is 1.

[0123] The encoding unit 502 may be configured to execute S202 in the data processing method shown in FIG. 2. For details about the encoding unit 502, reference may be made to related description of S202, which is not described herein again.

[0124] The sending unit 503 is configured to send, by using m transmit ports, the m×m elements in the matrix B generated by the encoding unit to m different levels of a PAM circuit respectively for performing modulation, where m 1×m matrices in the matrix B are in a one-to-one correspondence with the m different levels of the PAM circuit, m elements located in a same m×1 matrix of m m×1 matrices in the matrix B are sent by the sending unit 503 at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix B, an element located on a right side is sent by the sending unit 503 earlier than an element located on a left side.

[0125] For example, the sending unit 503 in this embodiment may be a transmitter. The sending unit 503 may be configured to execute S203 in the data processing method shown in FIG. 2. For details about the sending unit 503, reference may be made to related description of S203, which is not described herein again.

[0126] Optionally, in the foregoing technical solution:
the receiving unit 501 is further configured to receive m data units by using the m receive ports respectively.

[0127] The received m data units are in a one-to-one correspondence with the m receive ports, the received m data units are received by the receiving unit 501 at a same time, and the time at which the receiving unit 501 receives the received m data units is different from a time at which the receiving unit 501 receives m data units in any m×1 matrix of the m m×1 matrices in the matrix A.

[0128] The sending unit 503 is further configured to send, by using the m transmit ports, the received m data units to the m different levels of the PAM circuit respectively for performing modulation.

[0129] The received m data units are in a one-to-one correspondence with the m different levels.

[0130] For details about the received m data units, reference may be made to the description in the embodiment corresponding to FIG. 2, which is not described herein again.

[0131] Referring to FIG. 6, FIG. 6 is a schematic structural diagram of an embodiment of a data processing apparatus according to the present invention. A data processing apparatus 600 in this embodiment may be configured to execute the data processing method in the embodiment shown in FIG. 4. The data processing apparatus 600 in this embodiment of the present invention includes a receiving unit 601, a decoding unit 602, and a sending unit 603.

[0132] The receiving unit 601 is configured to receive m demodulated data streams by using m receive ports respectively, where m is an integer greater than 1, the m receive ports are in a one-to-one correspondence with the m data streams, and the m data streams include m×m data units, where each data stream of the m data streams includes m data units, the m×m data units form an m-order matrix C, the m×m data units are m×m elements in the matrix C, m 1×m matrices in the matrix C are in a one-to-one correspondence with the m data streams, m elements located in a same m×1 matrix of m m×1 matrices in the matrix C are received by the receiving unit 601 at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix C, an element located on a right side is received by the receiving unit 601 earlier than an element located on a left side.

[0133] For example, the receiving unit 601 in this embodiment may be a receiver. The receiving unit 601 may be configured to execute S401 in the data processing method shown in FIG. 4. For details about the receiving unit 601, reference may be made to related description of S401, which is not described herein again.

[0134] The decoding unit 602 is configured to keep a location of one element in each row in the matrix C received by the receiving unit 601 unchanged and move remaining m-1 elements to remaining m-1 rows respectively so as to form an m-order matrix D, where a column number of each element in the remaining m-1 elements in the matrix C before the element is moved equals a column number of the element in the remaining m-1 elements in the matrix D after the element is moved, and the m×m elements in the matrix C are in a one-to-one correspondence with m×m elements in the matrix D.

[0135] For example, the decoding unit 602 in this embodiment may be a decoder.

[0136] Optionally, the m×m elements in the matrix C are denoted by cij, the m×m elements in the matrix D are denoted by dij, i=1, ..., m, and j=1, ..., m, where
dij = cyj, and a value of y is:

when i-k>0, y=i-k, and when i-k≤0, y=i-k+m, where k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix D correspond to different k values respectively; or

when i+k≤m, y=i+k, and when i+k>m, y=i+k-m, where k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix D correspond to different k values respectively.



[0137] Optionally, a difference between k values corresponding to two adjacent elements of elements in each row in the matrix D is 1.

[0138] The decoding unit 602 may be configured to execute S402 in the data processing method shown in FIG. 4. For details about the decoding unit 602, reference may be made to related description of S402, which is not described herein again.

[0139] The sending unit 603 is configured to send, by using m transmit ports, the m×m elements in the matrix D generated by the decoding unit 602, where m elements located in a same m×1 matrix of m m×1 matrices in the matrix D are sent by the sending unit 603 at a same time, and among m elements located in a same 1×m matrix of m 1×m matrices in the matrix D, an element located on a right side is sent by the sending unit 603 earlier than an element located on a left side.

[0140] For example, the sending unit 603 in this embodiment may be a transmitter. The sending unit 603 may be configured to execute S403 in the data processing method shown in FIG. 4. For details about the sending unit 603, reference may be made to related description of S403, which is not described herein again.

[0141] Optionally, in the foregoing technical solution:
the receiving unit 601 is further configured to receive m demodulated data units by using the m receive ports respectively.

[0142] The received and demodulated m data units are in a one-to-one correspondence with the m receive ports, the received and demodulated m data units are received by the receiving unit 601 at a same time, and the time at which the receiving unit 601 receives the received and demodulated m data units is different from a time at which the receiving unit 601 receives m data units in any m×1 matrix of the m m×1 matrices in the matrix C.

[0143] The sending unit 603 is further configured to send the received and demodulated m data units by using the m transmit ports respectively.

[0144] The received and demodulated m data units are in a one-to-one correspondence with the m transmit ports.

[0145] For details about the received and demodulated m data units, reference may be made to the description in the embodiment corresponding to FIG. 4, which is not described herein again.

[0146] FIG. 7 is a schematic structural diagram of an encoding circuit provided in an embodiment. Referring to FIG. 7, an encoding circuit 700 includes a port 701, an encoding module 702, a selector 703, a port 704, and a port 705. The port 701 is coupled to an input end of the encoding module 702. An output end of the encoding module 702 is coupled to a first input end of the selector 703. The port 701 is coupled to a second input end of the selector 703. The port 705 is coupled to a selection signal input end of the selector 703. An output end of the selector 703 is coupled to the port 704. In addition, a register 706 is coupled to the port 705. A central processing unit (central processing unit, CPU) 707 is coupled to the register 706. The encoding circuit 700 may be configured to implement the data processing apparatus 500 shown in FIG. 5.

[0147] For example, the port 701 may be configured to implement the receiving unit 501. Specifically, the port 701 may be the m receive ports in the embodiment corresponding to FIG. 5. The port 704 may be configured to implement the sending unit 503. Specifically, the port 704 may be the m transmit ports in the embodiment corresponding to FIG. 5. The encoding module 702 may be configured to implement the encoding unit 502.

[0148] Referring to FIG. 7, after receiving data, the port 701 duplicates the received data so as to obtain data 1 and data 2. The received data is the same as the data 1. The data 1 is the same as the data 2. The port 701 sends the data 1 to the encoding module 702. The port 701 sends the data 2 to the second input end of the selector 703. Therefore, data received by the selector 703 by using the first input end is data processed by the encoding module 702, and data received by the selector 703 by using the second input end is data not processed by the encoding module 702. The central processing unit 707 may set a value of the register 706 to 0 or 1. The selection signal input end of the selector 703 may obtain the value of the register 706 by using the port 705. When a signal received by the selection signal input end of the selector 703 is 0, the selector 703 sends, by using the output end of the selector 703, data (that is, the data processed by the encoding module 702) received by the first input end to the port 704. When a signal received by the selection signal input end of the selector 703 is 1, the selector 703 sends, by using the output end of the selector 703, data (that is, the data not processed by the encoding module 702) received by the second input end to the port 704. That is, the central processing unit 707 may set the value of the register 706 to different values at different times, so as to control whether the selector 703 outputs the data processed by the encoding module 702. For example, with reference to the embodiment shown in FIG. 5, when the central processing unit 707 sets the value of the register 706 to 0, the selector 703 may send the m×m elements in the matrix B in the embodiment shown in FIG. 5 to the port 704. When the central processing unit 707 sets the value of the register 706 to 1, the selector 703 may send the received m data units in the embodiment shown in FIG. 5 to the port 704.

[0149] In addition, a decoding circuit may be obtained by using a working principle of the encoding circuit 700 shown in FIG. 7 and properly reconstructing the encoding circuit 700 (for example, replacing the encoding module 702 with a decoding module capable of executing processing of S402). A person skilled in the art may understand that the decoding circuit obtained by using the working principle of the encoding circuit 700 and performing proper reconstruction can implement the data processing apparatus shown in FIG. 6.

[0150] Based on the foregoing descriptions of the implementation manners, a person skilled in the art may clearly understand that all or some steps of the methods in the foregoing embodiments may be implemented by software in addition to a general hardware platform. Based on such an understanding, the technical solutions of the present invention essentially or the part contributing to the prior art may be implemented in a form of a software product. The computer software product is stored in a storage medium, such as a ROM/RAM, a hard disk, or an optical disc, and includes several instructions for instructing a computer device (which may be a personal computer, a server, or a network communications device such as a media gateway) to perform the methods described in the embodiments or some parts of the embodiments of the present invention.

[0151] It should be noted that the embodiments in this specification are all described in a progressive manner, for same or similar parts in the embodiments, reference may be made to these embodiments, and each embodiment focuses on a difference from other embodiments. Especially, device and system embodiments are basically similar to a method embodiment, and therefore are described briefly; for related parts, reference may be made to partial descriptions in the method embodiment. The described device and system embodiments are merely exemplary. The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual requirements to achieve the objectives of the solutions of the embodiments. A person of ordinary skill in the art may understand and implement the embodiments of the present invention without creative efforts.

[0152] The foregoing descriptions are merely preferred implementation manners of the present invention, but are not intended to limit the protection scope of the present invention. It should be noted that a person of ordinary skill in the art may make some improvements and polishing without departing from the principle of the present invention and the improvements and polishing shall fall within the protection scope of the present invention, as defined by the following claims.


Claims

1. A data processing method, comprising:

receiving (S201), by an encoding circuit, m data streams by using m receive ports respectively, wherein m is an integer greater than 1, the m receive ports are in a one-to-one correspondence with the m data streams, and the m data streams comprise m×m data units, wherein each data stream of the m data streams comprises m data units, the m×m data units form an m-order matrix A, the m×m data units are m×m elements in the matrix A, m 1×m matrices in the matrix A are in a one-to-one correspondence with the m data streams, m elements located in a same m×1 matrix of m m×1 matrices in the matrix A are received by the encoding circuit at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix A, an element located on a right side is received by the encoding circuit earlier than an element located on a left side;

keeping (S202), by the encoding circuit, a location of one element in each row in the matrix A unchanged and moving remaining m-1 elements to remaining m-1 rows respectively so as to form an m-order matrix B, wherein a column number of each element in the remaining m-1 elements in the matrix A before the element is moved equals a column number of the element in the remaining m-1 elements in the matrix B after the element is moved, and the m×m elements in the matrix A are in a one-to-one correspondence with m×m elements in the matrix B; and

sending (S203), by the encoding circuit by using m transmit ports, the m×m elements in the matrix B to m different levels of a pulse amplitude modulation, PAM, circuit respectively for performing modulation, wherein m 1×m matrices in the matrix B are in a one-to-one correspondence with the m different levels of the PAM circuit, m elements located in a same m×1 matrix of m m×1 matrices in the matrix B are sent by the encoding circuit at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix B, an element located on a right side is sent by the encoding circuit earlier than an element located on a left side;

performing, by the PAM circuit, modulation to the m×m elements in the matrix B on the m different levels;

the method further comprises:

receiving, by the encoding circuit, m data units by using the m receive ports respectively, wherein the received m data units are in a one-to-one correspondence with the m receive ports, the received m data units are received by the encoding circuit at a same time, and the time at which the encoding circuit receives the received m data units is different from a time at which the encoding circuit receives m data units in any m×1 matrix of the m m×1 matrices in the matrix A; and

sending, by the encoding circuit by using the m transmit ports, the received m data units to the m different levels of the PAM circuit respectively for performing modulation, wherein the received m data units are in a one-to-one correspondence with the m different levels.


 
2. The data processing method according to claim 1, wherein the m×m elements in the matrix A are denoted by aij, the m×m elements in the matrix B are denoted by bij, i=1, ..., m, and j=1, ..., m, wherein
bij = axj, and a value of x complies with the following constraints:

when i+k≤m, x=i+k, and when i+k>m, x=i+k-m, wherein k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix B correspond to different k values respectively; or

when i-k>0, x=i-k, and when i-k≤0, x=i-k+m, wherein k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix B correspond to different k values respectively.


 
3. The data processing method according to claim 2, wherein:
a difference between k values corresponding to two adjacent elements of elements in each row in the matrix B is 1.
 
4. A data processing method, comprising:

demodulating, by a demodulation circuit, a pulse signal sent by a transmit end into m demodulated data streams, according to the amplitude of the pulse signal;

transmitting, by the demodulation circuit, the m demodulated data streams to a decoding circuit by using m links respectively, wherein the m demodulated data streams are in a one-to-one correspondence with the m links, the m links are in a one-to-one correspondence with m receive ports of the decoding circuit;

receiving (S401), by the decoding circuit, m demodulated data streams by using the m receive ports respectively, wherein m is an integer greater than 1, the m receive ports are in a one-to-one correspondence with the m data streams, and the m data streams comprise m×m data units, wherein each data stream of the m data streams comprises m data units, the m×m data units form an m-order matrix C, the m×m data units are m×m elements in the matrix C, m 1×m matrices in the matrix C are in a one-to-one correspondence with the m data streams, m elements located in a same m×1 matrix of m m×1 matrices in the matrix C are received by the decoding circuit at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix C, an element located on a right side is received by the decoding circuit earlier than an element located on a left side;

keeping (S402), by the decoding circuit, a location of one element in each row in the matrix C unchanged and moving remaining m-1 elements to remaining m-1 rows respectively so as to form an m-order matrix D, wherein a column number of each element in the remaining m-1 elements in the matrix C before the element is moved equals a column number of the element in the remaining m-1 elements in the matrix D after the element is moved, and the m×m elements in the matrix C are in a one-to-one correspondence with m×m elements in the matrix D; and

sending (S403), by the decoding circuit, the m×m elements in the matrix D by using m transmit ports, wherein m elements located in a same m×1 matrix of m m×1 matrices in the matrix D are sent by the decoding circuit at a same time, and among m elements located in a same 1×m matrix of m 1×m matrices in the matrix D, an element located on a right side is sent by the decoding circuit earlier than an element located on a left side;

the method further comprises:

receiving, by the decoding circuit, m demodulated data units by using the m receive ports respectively, wherein the received and demodulated m data units are in a one-to-one correspondence with the m receive ports, the received and demodulated m data units are received by the decoding circuit at a same time, and the time at which the decoding circuit receives the received and demodulated m data units is different from a time at which the decoding circuit receives m data units in any m×1 matrix of the m m×1 matrices in the matrix C; and

sending, by the decoding circuit, the received and demodulated m data units by using the m transmit ports respectively, wherein the received and demodulated m data units are in a one-to-one correspondence with the m transmit ports.


 
5. The data processing method according to claim 4, wherein the m×m elements in the matrix C are denoted by cij, the m×m elements in the matrix D are denoted by dij, i=1, ..., m, and j=1, ..., m, wherein
dij = cyj, and a value of y is:

when i-k>0, y=i-k, and when i-k≤0, y=i-k+m, wherein k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix D correspond to different k values respectively; or

when i+k≤m, y=i+k, and when i+k>m, y=i+k-m, wherein k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix D correspond to different k values respectively.


 
6. The data processing method according to claim 5, wherein:
a difference between k values corresponding to two adjacent elements of elements in each row in the matrix D is 1.
 
7. A data processing apparatus, comprising:

a receiving unit (501), configured to receive m data streams by using m receive ports respectively, wherein m is an integer greater than 1, the m receive ports are in a one-to-one correspondence with the m data streams, and the m data streams comprise m×m data units, wherein each data stream of the m data streams comprises m data units, the m×m data units form an m-order matrix A, the m×m data units are m×m elements in the matrix A, m 1×m matrices in the matrix A are in a one-to-one correspondence with the m data streams, m elements located in a same m×1 matrix of m m×1 matrices in the matrix A are received by the receiving unit at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix A, an element located on a right side is received by the receiving unit earlier than an element located on a left side;

an encoding unit (502), configured to keep a location of one element in each row in the matrix A received by the receiving unit unchanged and move remaining m-1 elements to remaining m-1 rows respectively so as to form an m-order matrix B, wherein a column number of each element in the remaining m-1 elements in the matrix A before the element is moved equals a column number of the element in the remaining m-1 elements in the matrix B after the element is moved, and the m×m elements in the matrix A are in a one-to-one correspondence with m×m elements in the matrix B; and

a sending unit (503), configured to send, by using m transmit ports, the m×m elements in the matrix B generated by the encoding unit to m different levels of a pulse amplitude modulation, PAM, circuit respectively for performing modulation, wherein m 1×m matrices in the matrix B are in a one-to-one correspondence with the m different levels of the PAM circuit, m elements located in a same m×1 matrix of m m×1 matrices in the matrix B are sent by the sending unit at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix B, an element located on a right side is sent by the sending unit earlier than an element located on a left side;

a PAM circuit configure to perform modulation to the m×m elements in the matrix B on the m different levels;

the receiving unit is further configured to receive m data units by using the m receive ports respectively, wherein the received m data units are in a one-to-one correspondence with the m receive ports, the received m data units are received by the receiving unit at a same time, and the time at which the receiving unit receives the received m data units is different from a time at which the receiving unit receives m data units in any m×1 matrix of the m m×1 matrices in the matrix A; and

the sending unit is further configured to send, by using the m transmit ports, the received m data units to the m different levels of the PAM circuit respectively for performing modulation, wherein the received m data units are in a one-to-one correspondence with the m different levels.


 
8. The data processing apparatus according to claim 7, wherein the m×m elements in the matrix A are denoted by aij, the m×m elements in the matrix B are denoted by bij, i=1, ..., m, and j=1, ..., m, wherein
bij = axj, and a value of x is:

when i+k≤m, x=i+k, and when i+k>m, x=i+k-m, wherein k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix B correspond to different k values respectively; or

when i-k>0, x=i-k, and when i-k≤0, x=i-k+m, wherein k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix B correspond to different k values respectively.


 
9. The data processing apparatus according to claim 8, wherein:
a difference between k values corresponding to two adjacent elements of elements in each row in the matrix B is 1.
 
10. A data processing apparatus, comprising:

a demodulation circuit, configured to: demodulate a pulse signal sent by a transmit end into m demodulated data streams, according to the amplitude of the pulse signal; ; and transmit the m demodulated data streams to a decoding circuit by using m links respectively, wherein the m demodulated data streams are in a one-to-one correspondence with the m links, the m links are in a one-to-one correspondence with m receive ports of the decoding circuit;

a receiving unit (601), configured to receive m demodulated data streams by using m receive ports respectively, wherein m is an integer greater than 1, the m receive ports are in a one-to-one correspondence with the m data streams, and the m data streams comprise m×m data units, wherein each data stream of the m data streams comprises m data units, the m×m data units form an m-order matrix C, the m×m data units are m×m elements in the matrix C, m 1×m matrices in the matrix C are in a one-to-one correspondence with the m data streams, m elements located in a same m×1 matrix of m m×1 matrices in the matrix C are received by the receiving unit at a same time, and among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix C, an element located on a right side is received by the receiving unit earlier than an element located on a left side;

a decoding unit (602), configured to keep a location of one element in each row in the matrix C received by the receiving unit unchanged and move remaining m-1 elements to remaining m-1 rows respectively so as to form an m-order matrix D, wherein a column number of each element in the remaining m-1 elements in the matrix C before the element is moved equals a column number of the element in the remaining m-1 elements in the matrix D after the element is moved, and the m×m elements in the matrix C are in a one-to-one correspondence with m×m elements in the matrix D;
and

a sending unit (603), configured to send, by using m transmit ports, the m×m elements in the matrix D generated by the decoding unit, wherein m elements located in a same m×1 matrix of m m×1 matrices in the matrix D are sent by the sending unit at a same time, and among m elements located in a same 1×m matrix of m 1×m matrices in the matrix D, an element located on a right side is sent by the sending unit earlier than an element located on a left side;

the receiving unit is further configured to receive m demodulated data units by using the m receive ports respectively, wherein the received and demodulated m data units are in a one-to-one correspondence with the m receive ports, the received and demodulated m data units are received by the receiving unit at a same time, and the time at which the receiving unit receives the received and demodulated m data units is different from a time at which the receiving unit receives m data units in any m×1 matrix of the m m×1 matrices in the matrix C; and

the sending unit is further configured to send the received and demodulated m data units by using the m transmit ports respectively, wherein the received and demodulated m data units are in a one-to-one correspondence with the m transmit ports.


 
11. The data processing apparatus according to claim 10, wherein the m×m elements in the matrix C are denoted by cij, the m×m elements in the matrix D are denoted by dij, i=1, ..., m, and j=1, ..., m, wherein
dij = cyj, and a value of y is:

when i-k>0, y=i-k, and when i-k≤0, y=i-k+m, wherein k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix D correspond to different k values respectively; or

when i+k≤m, y=i+k, and when i+k>m, y=i+k-m, wherein k is an integer greater than or equal to 0 and less than m, and m elements in a same row in the matrix D correspond to different k values respectively.


 
12. The data processing apparatus according to claim 11, wherein:
a difference between k values corresponding to two adjacent elements of elements in each row in the matrix D is 1.
 


Ansprüche

1. Datenverarbeitungsverfahren, das Folgendes umfasst:

Empfangen (S201) von m Datenströmen durch eine Codierungsschaltung unter Verwendung von jeweiligen m Empfangsanschlüssen, wobei m eine Ganzzahl größer als 1 ist, die m Empfangsanschlüsse eine Eins-zu-eins-Entsprechung mit den m Datenströmen aufweisen und die m Datenströme m×m Dateneinheiten umfassen, wobei jeder Datenstrom der m Datenströme m Dateneinheiten umfasst, die m×m Dateneinheiten eine Matrix A m-ter Ordnung bilden, die m×m Dateneinheiten m×m Elemente in der Matrix A sind, m 1×m-Matrices in der Matrix A eine Eins-zu-eins-Entsprechung mit den m Datenströmen aufweisen, m Elemente, die sich in einer selben m1×-Matrix von m m×1-Matrices in der Matrix A befinden, von der Codierungsschaltung zu einer selben Zeit empfangen werden und unter m Elementen, die sich in einer selben 1×m-Matrix der m 1×m-Matrices in der Matrix A befinden, ein Element, das sich auf einer rechten Seite befindet, von der Codierungsschaltung früher empfangen wird als ein Element, das sich auf einer linken Seite befindet;

Unverändertlassen (S202) einer Position eines Elements in jeder Zeile in der Matrix A und Bewegen von verbleibenden m-1 Elementen jeweils zu m-1 Zeilen durch die Codierungsschaltung, um eine Matrix B m-ter Ordnung zu bilden, wobei eine Spaltennummer jedes Elements in den verbleibenden m-1 Elementen in der Matrix A, bevor das Element bewegt wird, mit einer Spaltennummer des Elements in den verbleibenden m-1 Elementen in der Matrix B, nachdem das Element bewegt wurde, übereinstimmt und die m×m Elemente in der Matrix A eine Eins-zu-eins-Entsprechung mit m×m Elementen in der Matrix B aufweisen; und

Senden (S203) der m×m Elemente in der Matrix B durch die Codierungsschaltung unter Verwendung von m Übertragungsanschlüssen jeweils an m verschiedene Ebenen einer Pulsamplitudenmodulations(PAM)-Schaltung zum Durchführen einer Modulation, wobei m 1×m-Matrices in der Matrix B eine Eins-zu-eins-Entsprechung mit den m verschiedenen Ebenen der PAM-Schaltung aufweisen, m Elemente, die sich in einer selben m×1-Matrix von m m×1-Matrices in der Matrix B befinden, von der Codierungsschaltung zu einer selben Zeit gesendet werden und unter m Elementen, die sich in einer selben 1×m-Matrix der m 1×m-Matrices in der Matrix B befinden, ein Element, das sich auf einer rechten Seite befindet, von der Codierungsschaltung früher gesendet wird als ein Element, das sich auf einer linken Seite befindet;

Durchführen einer Modulation durch die PAM-Schaltung an den mxm Elementen in der Matrix B auf den m verschiedenen Ebenen;

das Verfahren umfasst ferner Folgendes:

Empfangen von m Dateneinheiten durch die Codierungsschaltung unter Verwendung der jeweiligen m Empfangsanschlüsse, wobei die empfangenen m Dateneinheiten eine Eins-zu-eins-Entsprechung mit den m Empfangsanschlüssen aufweisen, die empfangenen m Dateneinheiten von der Codierungsschaltung zu einer selben Zeit empfangen werden und die Zeit, zu der die Codierungsschaltung die empfangenen m Dateneinheiten empfängt, sich von einer Zeit, zu der die Codierungsschaltung m Dateneinheiten in einer beliebigen m×1-Matrix der m m×1-Matrices in der Matrix A empfängt, unterscheidet; und

Senden der empfangenen m Dateneinheiten durch die Codierungsschaltung unter Verwendung der m Übertragungsanschlüsse an die jeweiligen m verschiedenen Ebenen der PAM-Schaltung zum Durchführen einer Modulation, wobei die empfangenen m Dateneinheiten eine Eins-zu-eins-Entsprechung mit den m verschiedenen Ebenen aufweisen.


 
2. Datenverarbeitungsverfahren nach Anspruch 1, wobei die m×m Elemente in der Matrix A durch aij gekennzeichnet sind, die m×m Elemente in der Matrix B durch bij gekennzeichnet sind, i=1, ...m und j=1, ...m, wobei bij=axj und ein Wert von x mit den folgenden Einschränkungen konform ist:

wenn i+k≤m, x=i+k und wenn i+k>m, x=i+k-m, wobei k eine Ganzzahl größer als oder gleich 0 und kleiner als m ist und m Elemente in einer selben Zeile in der Matrix B jeweils verschiedenen k-Werten entsprechen; oder

wenn i-k>0, x=i-k und wenn i-k≤0, x=i-k+m, wobei k eine Ganzzahl größer als oder gleich 0 und kleiner als m ist und m Elemente in einer selben Zeile in der Matrix B jeweils verschiedenen k-Werten entsprechen.


 
3. Datenverarbeitungsverfahren nach Anspruch 2, wobei:
eine Differenz zwischen k-Werten, die zwei benachbarten Elementen von Elementen in jeder Zeile in der Matrix B entsprechen, 1 ist.
 
4. Datenverarbeitungsverfahren, das Folgendes umfasst:

Demodulieren eines Pulssignals, das von einem Übertragungsende gesendet wird, durch eine Demodulationsschaltung gemäß der Amplitude des Pulssignals in m demodulierte Datenströme;

Übertragen der m demodulierten Datenströme durch eine Demodulationsschaltung zu einer Decodierungsschaltung unter Verwendung von jeweils m Verbindungen, wobei die m demodulierten Datenströme eine Eins-zu-eins-Entsprechung mit den m Verbindungen aufweisen, die m Verbindungen eine Eins-zu-eins-Entsprechung mit den m Empfangsanschlüssen der Decodierungsschaltung aufweisen;

Empfangen (S401) von m demodulierten Datenströmen durch die Decodierungsschaltung unter Verwendung von jeweiligen m Empfangsanschlüssen, wobei m eine Ganzzahl größer als 1 ist, die m Empfangsanschlüsse eine Eins-zu-eins-Entsprechung mit den m Datenströmen aufweisen und die m Datenströme mxm Dateneinheiten umfassen, wobei jeder Datenstrom der m Datenströme m Dateneinheiten umfasst, die m×m Dateneinheiten eine Matrix C m-ter Ordnung bilden, die m×m Dateneinheiten m×m Elemente in der Matrix C sind, m 1×m-Matrices in der Matrix C eine Eins-zu-eins-Entsprechung mit den m Datenströmen aufweisen, m Elemente, die sich in einer selben m×1-Matrix von m m×1-Matrices in der Matrix C befinden, von der Decodierungsschaltung zu einer selben Zeit empfangen werden und unter m Elementen, die sich in einer selben 1×m-Matrix der m 1×m-Matrices in der Matrix C befinden, ein Element, das sich auf einer rechten Seite befindet, von der Decodierungsschaltung früher empfangen wird als ein Element, das sich auf einer linken Seite befindet;

Unverändertlassen (S402) einer Position eines Elements in jeder Zeile in der Matrix C und Bewegen von verbleibenden m-1 Elementen jeweils zu m-1 Zeilen durch die Decodierungsschaltung, um eine Matrix D m-ter Ordnung zu bilden, wobei eine Spaltennummer jedes Elements in den verbleibenden m-1 Elementen in der Matrix C, bevor das Element bewegt wird, mit einer Spaltennummer des Elements in den verbleibenden m-1 Elementen in der Matrix D, nachdem das Element bewegt wurde, übereinstimmt und die m×m Elemente in der Matrix C eine Eins-zu-eins-Entsprechung mit m×m Elementen in der Matrix D aufweisen; und

Senden (S403) der m×m Elemente in der Matrix D durch die Decodierungsschaltung unter Verwendung von m Übertragungsanschlüssen, wobei m Elemente, die sich in einer selben m×1-Matrix von m m×1-Matrices in der Matrix D befinden, von der Decodierungsschaltung zu einer selben Zeit gesendet werden und unter m Elementen, die sich in einer selben 1×m-Matrix von m 1×m-Matrices in der Matrix D befinden, ein Element, das sich auf einer rechten Seite befindet, von der Decodierungsschaltung früher gesendet wird als ein Element, das sich auf einer linken Seite befindet;

das Verfahren umfasst ferner Folgendes:

Empfangen von m demodulierten Dateneinheiten durch die Decodierungsschaltung unter Verwendung der jeweiligen m Empfangsanschlüsse, wobei die empfangenen und demodulierten m Dateneinheiten eine Eins-zu-eins-Entsprechung mit den m Empfangsanschlüssen aufweisen, die empfangenen und demodulierten m Dateneinheiten von der Decodierungsschaltung zu einer selben Zeit empfangen werden und die Zeit, zu der die Decodierungsschaltung die empfangenen und demodulierten m Dateneinheiten empfängt, sich von einer Zeit, zu der die Decodierungsschaltung m Dateneinheiten in einer beliebigen m×1-Matrix der m m×1-Matrices in der Matrix C empfängt, unterscheidet; und

Senden der empfangenen und demodulierten m Dateneinheiten durch die Decodierungsschaltung unter Verwendung der jeweiligen m Übertragungsanschlüsse, wobei die empfangenen und demodulierten m Dateneinheiten eine Eins-zu-eins-Entsprechung mit den m Übertragungsanschlüssen aufweisen.


 
5. Datenverarbeitungsverfahren nach Anspruch 4, wobei die m×m Elemente in der Matrix C durch cij gekennzeichnet sind, die m×m Elemente in der Matrix D durch dij gekennzeichnet sind, i=1, ...m und j=1, ...m, wobei dij=cyj und ein Wert von y Folgendes ist:

wenn i-k>0, y=i-k und wenn i-k≤0, y=i-k+m, wobei k eine Ganzzahl größer als oder gleich 0 und kleiner als m ist und m Elemente in einer selben Zeile in der Matrix D jeweils verschiedenen k-Werten entsprechen; oder

wenn i+k≤m, y=i+k und wenn i+k>m, y=i+k-m, wobei k eine Ganzzahl größer als oder gleich 0 und kleiner als m ist und m Elemente in einer selben Zeile in der Matrix D jeweils verschiedenen k-Werten entsprechen.


 
6. Datenverarbeitungsverfahren nach Anspruch 5, wobei:
eine Differenz zwischen k-Werten, die zwei benachbarten Elementen von Elementen in jeder Zeile in der Matrix D entsprechen, 1 ist.
 
7. Datenverarbeitungsvorrichtung, die Folgendes umfasst:

eine Empfangseinheit (501), die dazu ausgelegt ist, m Datenströme unter Verwendung von jeweiligen m Empfangsanschlüssen zu empfangen, wobei m eine Ganzzahl größer als 1 ist, die m Empfangsanschlüsse eine Eins-zu-eins-Entsprechung mit den m Datenströmen aufweisen und die m Datenströme m×m Dateneinheiten umfassen, wobei jeder Datenstrom der m Datenströme m Dateneinheiten umfasst, die m×m Dateneinheiten eine Matrix A m-ter Ordnung bilden, die m×m Dateneinheiten m×m Elemente in der Matrix A sind, m 1×m-Matrices in der Matrix A eine Eins-zu-eins-Entsprechung mit den m Datenströmen aufweisen, m Elemente, die sich in einer selben m×1-Matrix von m m×1-Matrices in der Matrix A befinden, von der Empfangseinheit zu einer selben Zeit empfangen werden und unter m Elementen, die sich in einer selben 1×m-Matrix der m 1×m-Matrices in der Matrix A befinden, ein Element, das sich auf einer rechten Seite befindet, von der Empfangseinheit früher empfangen wird als ein Element, das sich auf einer linken Seite befindet;

eine Codiereinheit (502), die dazu ausgelegt ist, eine Position eines Elements in jeder Zeile in der Matrix A, das von der Empfangseinheit empfangen wird, unverändert zu lassen und verbleibende m-1 Elemente jeweils zu m-1 Zeilen zu bewegen, um eine Matrix B m-ter Ordnung zu bilden, wobei eine Spaltennummer jedes Elements in den verbleibenden m-1 Elementen in der Matrix A, bevor das Element bewegt wird, mit einer Spaltennummer des Elements in den verbleibenden m-1 Elementen in der Matrix B, nachdem das Element bewegt wurde, übereinstimmt und die m×m Elemente in der Matrix A eine Eins-zu-eins-Entsprechung mit mxm Elementen in der Matrix B aufweisen; und

eine Sendeeinheit (503), die dazu ausgelegt ist, die m×m Elemente in der Matrix B, die von der Codiereinheit erzeugt werden, unter Verwendung von m Übertragungsanschlüssen jeweils an m verschiedene Ebenen einer Pulsamplitudenmodulations(PAM)-Schaltung zum Durchführen einer Modulation zu senden, wobei m 1×m-Matrices in der Matrix B eine Eins-zu-eins-Entsprechung mit den m verschiedenen Ebenen der PAM-Schaltung aufweisen, m Elemente, die sich in einer selben m×1-Matrix von m m×1-Matrices in der Matrix B befinden, von der Sendeeinheit zu einer selben Zeit gesendet werden und unter m Elementen, die sich in einer selben 1×m-Matrix der m 1×m-Matrices in der Matrix B befinden, ein Element, das sich auf einer rechten Seite befindet, von der Sendeeinheit früher gesendet wird als ein Element, das sich auf einer linken Seite befindet;

eine PAM-Schaltung, die dazu ausgelegt ist, an den m×m Elementen in der Matrix B auf den m verschiedenen Ebenen eine Modulation durchzuführen;

die Empfangseinheit ist ferner dazu ausgelegt, m Dateneinheiten unter Verwendung der jeweiligen m Empfangsanschlüsse zu empfangen, wobei die empfangenen m Dateneinheiten eine Eins-zu-eins-Entsprechung mit den m Empfangsanschlüssen aufweisen, die empfangenen m Dateneinheiten von der Empfangseinheit zu einer selben Zeit empfangen werden und die Zeit, zu der die Empfangseinheit die empfangenen m Dateneinheiten empfängt, sich von einer Zeit, zu der die Empfangseinheit m Dateneinheiten in einer beliebigen m×1-Matrix der m m×1-Matrices in der Matrix A empfängt, unterscheidet; und

die Sendeeinheit ist ferner dazu ausgelegt, die empfangenen m Dateneinheiten unter Verwendung der m Übertragungsanschlüsse an die jeweiligen m verschiedenen Ebenen der PAM-Schaltung zum Durchführen einer Modulation zu senden, wobei die empfangenen m Dateneinheiten eine Eins-zu-eins-Entsprechung mit den m verschiedenen Ebenen aufweisen.


 
8. Datenverarbeitungsvorrichtung nach Anspruch 7, wobei die mxm Elemente in der Matrix A durch aij gekennzeichnet sind, die m×m Elemente in der Matrix B durch bij gekennzeichnet sind, i=1, ...m und j=1, ...m, wobei bij=axj und ein Wert von x Folgendes ist:

wenn i+k≤m, x=i+k und wenn i+k>m, x=i+k-m, wobei k eine Ganzzahl größer als oder gleich 0 und kleiner als m ist und m Elemente in einer selben Zeile in der Matrix B jeweils verschiedenen k-Werten entsprechen; oder

wenn i-k>0, x=i-k und wenn i-k≤0, x=i-k+m, wobei k eine Ganzzahl größer als oder gleich 0 und kleiner als m ist und m Elemente in einer selben Zeile in der Matrix B jeweils verschiedenen k-Werten entsprechen.


 
9. Datenverarbeitungsvorrichtung nach Anspruch 8, wobei:
eine Differenz zwischen k-Werten, die zwei benachbarten Elementen von Elementen in jeder Zeile in der Matrix B entsprechen, 1 ist.
 
10. Datenverarbeitungsvorrichtung, die Folgendes umfasst:

eine Demodulationsschaltung, die zu Folgendem ausgelegt ist: Demodulieren eines Pulssignals, das von einem Übertragungsende gesendet wird, in m demodulierte Datenströme gemäß der Amplitude des Pulssignals und

Übertragen der m demodulierten Datenströme zu einer Decodierungsschaltung unter Verwendung von jeweils m Verbindungen, wobei die m demodulierten Datenströme eine Eins-zu-eins-Entsprechung mit den m Verbindungen aufweisen, die m Verbindungen eine Eins-zu-eins-Entsprechung mit den m Empfangsanschlüssen der Decodierungsschaltung aufweisen;

eine Empfangseinheit (601), die dazu ausgelegt ist, m demodulierte Datenströme unter Verwendung von jeweiligen m Empfangsanschlüssen zu empfangen, wobei m eine Ganzzahl größer als 1 ist, die m Empfangsanschlüsse eine Eins-zu-eins-Entsprechung mit den m Datenströmen aufweisen und die m Datenströme mxm Dateneinheiten umfassen, wobei jeder Datenstrom der m Datenströme m Dateneinheiten umfasst, die m×m Dateneinheiten eine Matrix C m-ter Ordnung bilden, die m×m Dateneinheiten m×m Elemente in der Matrix C sind, m 1×m-Matrices in der Matrix C eine Eins-zu-eins-Entsprechung mit den m Datenströmen aufweisen, m Elemente, die sich in einer selben m×1-Matrix von m m×1-Matrices in der Matrix C befinden, von der Empfangseinheit zu einer selben Zeit empfangen werden und unter m Elementen, die sich in einer selben 1×m-Matrix der m 1×m-Matrices in der Matrix C befinden, ein Element, das sich auf einer rechten Seite befindet, von der Empfangseinheit früher empfangen wird als ein Element, das sich auf einer linken Seite befindet;

eine Decodiereinheit (602), die dazu ausgelegt ist, eine Position eines Elements in jeder Zeile in der Matrix C, das von der Empfangseinheit empfangen wird, unverändert zu lassen und verbleibende m-1 Elemente jeweils zu m-1 Zeilen zu bewegen, um eine Matrix D m-ter Ordnung zu bilden, wobei eine Spaltennummer jedes Elements in den verbleibenden m-1 Elementen in der Matrix C, bevor das Element bewegt wird, mit einer Spaltennummer des Elements in den verbleibenden m-1 Elementen in der Matrix D, nachdem das Element bewegt wurde, übereinstimmt und die m×m Elemente in der Matrix C eine Eins-zu-eins-Entsprechung mit mxm Elementen in der Matrix D aufweisen;
und

eine Sendeeinheit (603), die dazu ausgelegt ist, unter Verwendung von m Übertragungsanschlüssen die m×m Elemente in der Matrix D, die durch die Decodiereinheit erzeugt werden, zu senden, wobei m Elemente, die sich in einer selben m×1-Matrix von m m×1-Matrices in der Matrix D befinden, von der Sendeeinheit zu einer selben Zeit gesendet werden und unter m Elementen, die sich in einer selben 1×m-Matrix von m 1×m-Matrices in der Matrix D befinden, ein Element, das sich auf einer rechten Seite befindet, von der Sendeeinheit früher gesendet wird als ein Element, das sich auf einer linken Seite befindet;

die Empfangseinheit ist ferner dazu ausgelegt, m demodulierte Dateneinheiten unter Verwendung der jeweiligen m Empfangsanschlüsse zu empfangen, wobei die empfangenen und demodulierten m Dateneinheiten eine Eins-zu-eins-Entsprechung mit den m Empfangsanschlüssen aufweisen, die empfangenen und demodulierten m Dateneinheiten von der Empfangseinheit zu einer selben Zeit empfangen werden und die Zeit, zu der die Empfangseinheit die empfangenen und demodulierten m Dateneinheiten empfängt, sich von einer Zeit, zu der die Empfangseinheit m Dateneinheiten in einer beliebigen m×1-Matrix der m m×1-Matrices in der Matrix C empfängt, unterscheidet; und

die Sendeeinheit ist ferner dazu ausgelegt, die empfangenen und demodulierten m Dateneinheiten unter Verwendung der jeweiligen m Übertragungsanschlüsse zu senden, wobei die empfangenen und demodulierten m Dateneinheiten eine Eins-zu-eins-Entsprechung mit den m Übertragungsanschlüssen aufweisen.


 
11. Datenverarbeitungsvorrichtung nach Anspruch 10, wobei die mxm Elemente in der Matrix C durch cij gekennzeichnet sind, die mxm Elemente in der Matrix D durch dij gekennzeichnet sind, i=1, ...m und j=1, ...m, wobei dij=cyj und ein Wert von y Folgendes ist:

wenn i-k>0, y=i-k und wenn i-k≤0, y=i-k+m, wobei k eine Ganzzahl größer als oder gleich 0 und kleiner als m ist und m Elemente in einer selben Zeile in der Matrix D jeweils verschiedenen k-Werten entsprechen; oder

wenn i+k≤m, y=i+k und wenn i+k>m, y=i+k-m, wobei k eine Ganzzahl größer als oder gleich 0 und kleiner als m ist und m Elemente in einer selben Zeile in der Matrix D jeweils verschiedenen k-Werten entsprechen.


 
12. Datenverarbeitungsvorrichtung nach Anspruch 11, wobei:
eine Differenz zwischen k-Werten, die zwei benachbarten Elementen von Elementen in jeder Zeile in der Matrix D entsprechen, 1 ist.
 


Revendications

1. Procédé de traitement de données, comprenant :

la réception (S201), par un circuit de codage, de m flux de données en utilisant respectivement m ports de réception, m étant un entier supérieur à 1, les m ports de réception étant en correspondance biunivoque avec les m flux de données, et les m flux de données comprenant m×m unités de données, chaque flux de données des m flux de données comprenant m unités de données, les m×m unités de données formant une matrice A d'ordre m, les m×m unités de données étant m×m éléments dans la matrice A, m matrices 1×m dans la matrice A étant en correspondance biunivoque avec les m flux de données, m éléments situés dans une même matrice m×1 des m matrices m×1 dans la matrice A étant reçus par le circuit de codage en même temps, et parmi les m éléments situés dans une même matrice 1×m des m matrices 1×m dans la matrice A, un élément situé sur un côté droit étant reçu par le circuit de codage plus tôt qu'un élément situé sur un côté gauche ;

le maintien (S202), par le circuit de codage, d'un emplacement d'un élément dans chaque rangée dans la matrice A inchangé et le déplacement respectivement des m-1 éléments restants vers les m-1 rangées restantes de manière à former une matrice B d'ordre m, un numéro de colonne de chaque élément dans les m-1 éléments restants dans la matrice A avant que l'élément soit déplacé étant égal à un numéro de colonne de l'élément dans les m-1 éléments restants dans la matrice B après que l'élément est déplacé, et les mxm éléments dans la matrice A étant en correspondance biunivoque avec les m×m éléments dans la matrice B ; et

l'envoi (S203), par le circuit de codage en utilisant m ports de transmission, des mxm éléments dans la matrice B à respectivement m niveaux différents d'un circuit de modulation d'amplitude d'impulsion, PAM, pour réaliser la modulation, m matrices 1×m dans la matrice B étant en correspondance biunivoque avec les m niveaux différents du circuit PAM, m éléments situés dans une même matrice m×1 des m matrices m×1 dans la matrice B étant envoyés par le circuit de codage en même temps, et, parmi les m éléments situés dans une même matrice 1×m des m matrices 1×m dans la matrice B, un élément situé sur un côté droit étant envoyé par le circuit de codage plus tôt qu'un élément situé sur un côté gauche ;

la réalisation, par le circuit PAM, d'une modulation sur les mxm éléments dans la matrice B sur les m différents niveaux ;

le procédé comprenant en outre :

la réception, par le circuit de codage, de m unités de données en utilisant respectivement les m ports de réception, les m unités de données reçues étant en correspondance biunivoque avec les m ports de réception, les m unités de données reçues étant reçues par le circuit de codage en même temps, et le moment auquel le circuit de codage reçoit les m unités de données reçues étant différent d'un moment auquel le circuit de codage reçoit m unités de données dans n'importe quelle matrice m×1 des matrices m×1 dans la matrice A ; et

l'envoi, par le circuit de codage en utilisant les m ports de transmission, des m unités de données reçues respectivement aux m différents niveaux du circuit PAM pour réaliser la modulation, les m unités de données reçues étant en correspondance biunivoque avec les m différents niveaux.


 
2. Procédé de traitement de données selon la revendication 1, les m×m éléments dans la matrice A étant désignés par aij, les m×m éléments dans la matrice B étant désignés par bij, i=1, ..., m, et j=1, ..., m, bij= axj, et une valeur de x étant conforme aux contraintes suivantes :

lorsque i+k≤m, x=i+k, et lorsque i+k>m, x=i+k-m, k étant un entier supérieur ou égal à 0 et inférieur à m, et m éléments dans une même rangée dans la matrice B correspondant respectivement à des valeurs k différentes ; ou

lorsque i-k>0, x=i-k, et lorsque i-k≤0, x=i-k+m, k étant un entier supérieur ou égal à 0 et inférieur à m, et m éléments dans une même rangée dans la matrice B correspondant respectivement à des valeurs k différentes.


 
3. Procédé de traitement de données selon la revendication 2,
une différence entre k valeurs correspondant à deux éléments adjacents d'éléments dans chaque rangée dans la matrice B étant égale à 1.
 
4. Procédé de traitement de données, comprenant :

la démodulation, par un circuit de démodulation, d'un signal d'impulsion envoyé par une extrémité d'émission en m flux de données démodulées, en fonction de l'amplitude du signal d'impulsion ;

la transmission, par le circuit de démodulation, des m flux de données démodulées à un circuit de décodage en utilisant respectivement m liaisons, les m flux de données démodulées étant en correspondance biunivoque avec les m liaisons, les m liaisons étant en correspondance biunivoque avec m ports de réception du circuit de décodage ;

la réception (S401), par le circuit de décodage, de m flux de données démodulées en utilisant respectivement les m ports de réception, m étant un entier supérieur à 1, les m ports de réception étant dans une correspondance biunivoque avec les m flux de données, et les m flux de données comprenant m×m unités de données, chaque flux de données des m flux de données comprenant m unités de données, les m×m unités de données formant une matrice C d'ordre m, les mxm unités de données étant m×m éléments dans la matrice C, m matrices 1×m dans la matrice C étant en correspondance biunivoque avec les m flux de données, m éléments situés dans une même matrice m×1 des m matrices 1×1 dans la matrice C étant reçus par le circuit de décodage en même temps, et parmi les m éléments situés dans une même matrice 1×m des m matrices 1×m dans la matrice C, un élément situé sur un côté droit étant reçu par le circuit de décodage plus tôt qu'un élément situé sur un côté gauche ;

le maintien (S402), par le circuit de décodage, d'un emplacement d'un élément dans chaque rangée dans la matrice C inchangé et le déplacement des m-1 éléments restants respectivement vers les m-1 rangées restantes de manière à former une matrice D d'ordre m, un numéro de colonne de chaque élément dans les m-1 éléments restants dans la matrice C avant que l'élément ne soit déplacé étant égal à un numéro de colonne de l'élément dans les m-1 éléments restants dans la matrice D après que l'élément a été déplacé, et les m×m éléments dans la matrice C étant en correspondance biunivoque avec les m×m éléments dans la matrice D ; et

l'envoi (S403), par le circuit de décodage, des m×m éléments dans la matrice D en utilisant m ports de transmission, m éléments situés dans une même matrice m×1 de matrices m×1 dans la matrice D étant envoyés par le circuit de décodage en même temps, et, parmi les m éléments situés dans une même matrice 1×m de m matrices 1×m dans la matrice D, un élément situé sur un côté droit étant envoyé par le circuit de décodage plus tôt qu'un élément situé sur un côté gauche ;

le procédé comprenant en outre :

la réception, par le circuit de décodage, de m unités de données démodulées en utilisant respectivement les m ports de réception, les m unités de données reçues et démodulées étant en correspondance biunivoque avec les m ports de réception, les m unités de données reçues et démodulées étant reçues par le circuit de décodage en même temps, et le moment auquel le circuit de décodage reçoit les m unités de données reçues et démodulées étant différent du moment auquel le circuit de décodage reçoit m unités de données dans une matrice m×1 quelconque des m matrices m×1 dans la matrice C ; et

l'envoi, par le circuit de décodage, des m unités de données reçues et démodulées en utilisant respectivement les m ports de transmission, les m unités de données reçues et démodulées étant en correspondance biunivoque avec les m ports de transmission.


 
5. Procédé de traitement de données selon la revendication 4, les m×m éléments dans la matrice C étant désignés par cij, les m×m éléments dans la matrice D étant désignés par dij, i=1, ..., m, et j=1, ..., m, dij= cyj, et une valeur de y étant :

lorsque i-k>0, y=i-k, et lorsque i-k ≤ 0, y=i-k+m, k étant un entier supérieur ou égal à 0 et inférieur à m, et m éléments dans une même rangée dans la matrice D correspondant respectivement à des valeurs k différentes ; ou

lorsque i+k ≤ m, y=i+k, et lorsque i+k>m, y=i+k-m, k étant un entier supérieur ou égal à 0 et inférieur à m, et m éléments dans une même rangée dans la matrice D correspondant respectivement à des valeurs k différentes.


 
6. Procédé de traitement de données selon la revendication 5,
une différence entre k valeurs correspondant à deux éléments adjacents d'éléments dans chaque rangée dans la matrice D étant égale à 1.
 
7. Appareil de traitement de données, comprenant :

une unité de réception (501), configurée pour recevoir m flux de données en utilisant respectivement m ports de réception, m étant un entier supérieur à 1, les m ports de réception étant dans une correspondance biunivoque avec les m flux de données, et les m flux de données comprenant m×m unités de données, chaque flux de données des m flux de données comprenant m unités de données, les m×m unités de données formant une matrice A d'ordre m, les m×m unités de données étant m×m éléments dans la matrice A, m matrices 1×m dans la matrice A étant en correspondance biunivoque avec les m flux de données, m éléments situés dans une même matrice m×1 des m matrices m×1 dans la matrice A étant reçus par l'unité de réception en même temps, et parmi les m éléments situés dans une même matrice 1×m des m matrices 1×m dans la matrice A, un élément situé sur un côté droit étant reçu par l'unité de réception plus tôt qu'un élément situé sur un côté gauche ;

une unité de codage (502), configurée pour maintenir inchangée une position d'un élément dans chaque rangée dans la matrice A reçue par l'unité de réception et pour déplacer les m-1 éléments restants respectivement vers les m-1 rangées restantes de manière à former une matrice B d'ordre m, un numéro de colonne de chaque élément dans les m-1 éléments restants dans la matrice A avant que l'élément ne soit déplacé étant égal à un numéro de colonne de l'élément dans les m-1 éléments restants dans la matrice B après que l'élément a été déplacé, et les m×m éléments dans la matrice A étant en correspondance biunivoque avec les m×m éléments dans la matrice B ; et

une unité d'envoi (503), configurée pour envoyer, en utilisant m ports de transmission, les m×m éléments dans la matrice B générés par l'unité de codage respectivement à m niveaux différents d'un circuit de modulation d'amplitude d'impulsion, PAM, pour réaliser la modulation, m matrices 1×m dans la matrice B étant en correspondance biunivoque avec les m niveaux différents du circuit PAM, m éléments situés dans une même matrice m×1 des m matrices m×1 dans la matrice B étant envoyés par l'unité d'envoi en même temps, et, parmi les m éléments situés dans une même matrice 1×m des m matrices 1×m dans la matrice B, un élément situé sur un côté droit étant envoyé par l'unité d'envoi plus tôt qu'un élément situé sur un côté gauche ;

un circuit PAM configuré pour réaliser la modulation des mxm éléments dans la matrice B sur les m différents niveaux ;

l'unité de réception étant en outre configurée pour recevoir m unités de données en utilisant les m ports de réception respectivement, les m unités de données reçues étant en correspondance biunivoque avec les m ports de réception, les m unités de données reçues étant reçues par l'unité de réception en même temps, et le moment auquel l'unité de réception reçoit les m unités de données reçues étant différent du moment auquel l'unité de réception reçoit m unités de données dans une matrice m×1 quelconque des m matrices m×1 dans la matrice A ; et

l'unité d'envoi étant en outre configurée pour envoyer, en utilisant les m ports de transmission, les m unités de données reçues respectivement aux m différents niveaux du circuit PAM pour réaliser la modulation, les m unités de données reçues étant en correspondance biunivoque avec les m différents niveaux.


 
8. Appareil de traitement de données selon la revendication 7, les m×m éléments dans la matrice A étant désignés par aij, les m×m éléments dans la matrice B étant désignés par bij, i=1, ..., m, et j=1, ..., m, bij = axj, et une valeur de x étant :

lorsque i+k≤m, x=i+k, et lorsque i+k>m, x=i+k-m, k étant un entier supérieur ou égal à 0 et inférieur à m, et m éléments dans une même rangée dans la matrice B correspondant respectivement à des valeurs k différentes ; ou

lorsque i-k>0, x=i-k, et lorsque i-k≤0, x=i-k+m, k étant un entier supérieur ou égal à 0 et inférieur à m, et m éléments dans une même rangée dans la matrice B correspondant respectivement à des valeurs k différentes.


 
9. Appareil de traitement de données selon la revendication 8,
une différence entre k valeurs correspondant à deux éléments adjacents d'éléments dans chaque rangée dans la matrice B étant égale à 1.
 
10. Appareil de traitement de données, comprenant :

un circuit de démodulation, configuré pour : démoduler un signal d'impulsion envoyé par une extrémité d'émission en m flux de données démodulées en fonction de l'amplitude du signal d'impulsion ; et transmettre les m flux de données démodulées à un circuit de décodage en utilisant respectivement m liaisons, les m flux de données démodulées étant en correspondance biunivoque avec les m liaisons, les m liaisons étant en correspondance biunivoque avec m ports de réception du circuit de décodage ;

une unité de réception (601), configurée pour recevoir m flux de données démodulées en utilisant respectivement m ports de réception, m étant un entier supérieur à 1, les m ports de réception étant en correspondance biunivoque avec les m flux de données, et les m flux de données comprenant m×m unités de données, chaque flux de données des m flux de données comprenant m unités de données, les m×m unités de données formant une matrice C d'ordre m, les m×m unités de données étant m×m éléments dans la matrice C, m matrices 1×m dans la matrice C étant en correspondance biunivoque avec les m flux de données, m éléments situés dans une même matrice m×1 des m matrices m×1 dans la matrice C étant reçus par l'unité de réception en même temps, et parmi m éléments situés dans une même matrice 1×m des m matrices 1×m dans la matrice C, un élément situé sur un côté droit étant reçu par l'unité de réception plus tôt qu'un élément situé sur un côté gauche ;

une unité de décodage (602), configurée pour maintenir inchangée une position d'un élément dans chaque rangée dans la matrice C reçue par l'unité de réception et pour déplacer les m-1 éléments restants respectivement vers les m-1 rangées restantes de manière à former une matrice D d'ordre m, un numéro de colonne de chaque élément dans les m-1 éléments restants dans la matrice C avant que l'élément ne soit déplacé étant égal à un numéro de colonne de l'élément dans les m-1 éléments restants dans la matrice D après que l'élément a été déplacé, et les m×m éléments dans la matrice C étant en correspondance biunivoque avec les m×m éléments dans la matrice D ; et

une unité d'envoi (603), configurée pour envoyer, en utilisant m ports de transmission, les mxm éléments dans la matrice D générée par l'unité de décodage, m éléments situés dans une même matrice m×1 de m matrices m×1 dans la matrice D étant envoyés par l'unité d'envoi en même temps, et parmi les m éléments situés dans une même matrice 1×m de m matrices 1×m dans la matrice D, un élément situé sur un côté droit étant envoyé par l'unité d'envoi plus tôt qu'un élément situé sur un côté gauche ;

l'unité de réception étant en outre configurée pour recevoir m unités de données démodulées en utilisant respectivement les m ports de réception, les m unités de données reçues et démodulées étant en correspondance biunivoque avec les m ports de réception, les m unités de données reçues et démodulées étant reçues par l'unité de réception en même temps, et le moment auquel l'unité de réception reçoit les m unités de données reçues et démodulées étant différent d'un moment auquel l'unité de réception reçoit m unités de données dans une matrice m×1 quelconque des m matrices m×1 dans la matrice C ; et

l'unité d'envoi étant en outre configurée pour envoyer les m unités de données reçues et démodulées en utilisant respectivement les m ports de transmission, les m unités de données reçues et démodulées étant en correspondance biunivoque avec les m ports de transmission.


 
11. Appareil de traitement de données selon la revendication 10, les m×m éléments dans la matrice C étant désignés par cij, les m×m éléments dans la matrice D étant désignés par dij, i=1, ..., m, et j=1, ..., m, dij=cyj, et une valeur de y étant :

lorsque i-k>0, y=i-k, et lorsque i-k ≤ 0, y=i-k+m, k étant un entier supérieur ou égal à 0 et inférieur à m, et m éléments dans une même rangée dans la matrice D correspondant respectivement à des valeurs k différentes ; ou

lorsque i+k ≤ m, y=i+k, et lorsque i+k>m, y=i+k-m, k étant un entier supérieur ou égal à 0 et inférieur à m, et m éléments dans une même rangée dans la matrice D correspondant respectivement à des valeurs k différentes.


 
12. Appareil de traitement de données selon la revendication 11,
une différence entre k valeurs correspondant à deux éléments adjacents d'éléments dans chaque rangée dans la matrice D étant égale à 1.
 




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Cited references

REFERENCES CITED IN THE DESCRIPTION



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Patent documents cited in the description




Non-patent literature cited in the description