(19)
(11)EP 3 261 257 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
29.07.2020 Bulletin 2020/31

(21)Application number: 15884415.9

(22)Date of filing:  26.11.2015
(51)International Patent Classification (IPC): 
H03M 1/12(2006.01)
H03M 1/06(2006.01)
G06F 1/06(2006.01)
H03M 1/46(2006.01)
(86)International application number:
PCT/CN2015/095694
(87)International publication number:
WO 2016/141737 (15.09.2016 Gazette  2016/37)

(54)

SAMPLING CLOCK GENERATION CIRCUIT AND ANALOGUE-TO-DIGITAL CONVERTER

ABTASTTAKTERZEUGUNGSSCHALTUNG UND ANALOG-DIGITAL-WANDLER

CIRCUIT GÉNÉRATEUR D'HORLOGE D'ÉCHANTILLONNAGE ET CONVERTISSEUR D'ANALOGIQUE EN NUMÉRIQUE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 11.03.2015 CN 201510105575

(43)Date of publication of application:
27.12.2017 Bulletin 2017/52

(73)Proprietor: Huawei Technologies Co. Ltd.
Shenzhen, Guangdong 518129 (CN)

(72)Inventors:
  • YANG, Jinda
    Shenzhen Guangdong 518129 (CN)
  • ZHOU, Liren
    Shenzhen Guangdong 518129 (CN)

(74)Representative: Thun, Clemens 
Mitscherlich PartmbB Patent- und Rechtsanwälte Sonnenstraße 33
80331 München
80331 München (DE)


(56)References cited: : 
EP-A2- 1 333 578
CN-A- 102 497 210
CN-U- 201 489 112
US-B1- 7 068 195
CN-A- 102 062 798
CN-A- 104 270 154
JP-A- H08 274 600
  
  • MAYMANDI-NEJAD M ET AL: "A Monotonic Digitally Controlled Delay Element", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 40, no. 11, 1 November 2005 (2005-11-01), pages 2212-2219, XP011141629, ISSN: 0018-9200, DOI: 10.1109/JSSC.2005.857370
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

TECHNICAL FIELD



[0001] The present invention relates to the field of digital signal processing, and in particular, to a sampling clock generating circuit and an analog to digital converter.

BACKGROUND



[0002] Due to process and device development limitations, a sampling frequency of a single Analog to Digital Converter (ADC) chip cannot be very high, and a higher sampling frequency may be implemented by means of interlaced sampling, driven by sampling clocks at different phases, of multiple ADC chips.

[0003] The sampling clocks at the different phases are generally implemented by using the following solution: A logic circuit divides a clock source signal into n channels to obtain n channels of signals whose frequencies are equal to a frequency of the clock source signal divided by n and whose phases are different from each other, where n≥2 and n is an integer; and different quantities of phase inverters are respectively connected in series in transmission channels of the n channels of signals to perform delaying, so as to obtain n channels of sampling clocks, and sampling points of interlaced sampling driven by the n channels of sampling clocks are the same as sampling points of sampling driven by the clock source signal.

[0004] In a process of implementing the present invention, the inventor finds that the prior art has at least the following problems:

[0005] Based on the process limitations, features of devices in the logic circuit cannot reach theoretical features, which causes a timing offset in picoseconds (ps) between sampling points of the n channels of sampling clocks obtained by using the logic circuit and sampling points of the clock source signal. Because a delay of the phase inverters connected in series in the transmission channels can be only as low as 20 ps, and the timing offset between the sampling points cannot be effectively adjusted, the interlaced sampling, driven by the n channels of sampling clocks, of the multiple ADC chips is non-uniform sampling, harmonic occurs in a signal obtained after analog-to-digital conversion, and conversion precision of the ADC is reduced.

[0006] US 7,068,195 B1 discloses a time interleaved ADC system which includes a delay circuit that has a dynamically adjusted speed to achieve uniformly spaced sampling intervals.

[0007] MAYMANDI-NEJAD M ET AL, "A Monotonic Digitally Controlled Delay Element", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, (20051101), vol. 40, no. 11, doi:10.1109/JSSC.2005.857370, ISSN 0018-9200, pages 2212 - 2219, XP011141629, discloses a Monotonic Digitally Controlled Delay Element (DCDE). Due to its monotonic behaviour, the design of the DCDE is rather straightforward.

[0008] EP 1 333 578 A2 discloses an interleaved clock signal generator having serial delay and ring counter architecture.

[0009] JP H08 274600 A discloses a CMOS variable delay circuit to provide optimized design of a gate size of a MOSFET and to improve performance.

SUMMARY



[0010] To resolve a problem in the prior art that a timing offset between sampling points cannot be effectively adjusted and conversion precision of an ADC is reduced, embodiments of the present invention provide a sampling clock generating circuit and an analog to digital converter. The technical solutions are as follows:

[0011] According to one aspect, an embodiment of the present invention provides a sampling clock generating circuit, where the sampling clock generating circuit includes a resistance variable circuit, a NOT-gate type circuit, and a capacitor, where the NOT-gate type circuit includes an input end, an output end, a power supply terminal, and a ground terminal; the input end of the NOT-gate type circuit receives a pulse signal whose period is T; the output end of the NOT-gate type circuit is connected to one end of the capacitor; the other end of the capacitor is grounded; the power supply terminal of the NOT-gate type circuit is connected to a power supply; the ground terminal of the NOT-gate type circuit is connected to one end of the resistance variable circuit; and the other end of the resistance variable circuit is grounded;
the NOT-gate type circuit is configured to: when the pulse signal is a high level, output a low level; and when the pulse signal is a low level, output a high level; and
the resistance variable circuit comprising n gating switches, is configured to change a resistance value at intervals of duration T between n resistance values, where the resistance value has period of nT, and resistance values after changes within each period are different from each other, where n≥2 and n is an integer.

[0012] In a possible implementation manner of the present invention, the resistance variable circuit includes a field effect transistor Q1101 and n first gating switches K1102 to K(1101+n), where each first gating switch includes an input end, an output end, and a control end; a drain of the field effect transistor Q1101 is connected to the ground terminal of the NOT-gate type circuit, a source of the field effect transistor Q1101 is grounded, and a gate of the field effect transistor Q1101 is connected to the output end of each first gating switch; the input end of each first gating switch receives a signal whose voltage value is constant, and the voltage values of the signals received by the input ends of all the first gating switches are different from each other; and the control end of each first gating switch receives a signal whose period is nT, and within each period nT, the signal whose period is nT is a first level within only a time segment whose duration is T and is a second level within other time segments, and time segments within which the signals received by the control ends of all the gating switches are the first level s do not coincide, where
when the signal received by the control end of the first gating switch is the first level, the input end of the first gating switch is connected to the output end of the first gating switch; and when the signal received by the control end of the first gating switch is the second level, the input end of the first gating switch is disconnected from the output end of the first gating switch.

[0013] Optionally, the field effect transistor Q1101 is a junction field effect transistor JFET, an enhanced metal-oxide semiconductor field-effect transistor MOSFET, or a depletion MOSFET.

[0014] Optionally, the resistance variable circuit further includes a field effect transistor Q(1102+n), where a gate of the field effect transistor Q(1102+n) is connected to the power supply, a drain of the field effect transistor Q(1102+n) is connected to the drain of the field effect transistor Q1101, and a source of the field effect transistor Q(1102+n) is connected to the source of the field effect transistor Q1101, where
the field effect transistor Q(1102+n) and the field effect transistor Q1101 are both P-channel field-effect transistors, or the field effect transistor Q(1102+n) and the field effect transistor Q1101 are both N-channel field-effect transistors.

[0015] Specifically, the field effect transistor Q(1102+n) is a JFET, an enhanced MOSFET, or a depletion MOSFET.

[0016] Optionally, the resistance variable circuit further includes a resistor R(1103+n), where one end of the resistor R(1103+n) is connected to the drain of the field effect transistor Q1101, and the other end of the resistor (1103+n) is connected to the source of the field effect transistor Q1101.

[0017] Optionally, the sampling clock generating circuit further includes level adjustment circuits that are in a one-to-one correspondence to the first gating switches K1102 to K(1101+n), where each level adjustment circuit is connected to the input end of the first gating switch that corresponds to the level adjustment circuit; and
each level adjustment circuit is configured to provide a signal whose voltage value is constant and adjustable to the input end of the first gating switch that corresponds to the level adjustment circuit, where the voltage values of the signals provided by all the level adjustment circuits are different from each other.

[0018] Specifically, each level adjustment circuit includes m resistors R41 to R(40+m), m+1 second gating switches K(41+m) to K(41+2m), and a register IR, where m≥2 and m is an integer; each second gating switch includes an input end, an output end, and a control end; the m resistors R41 to R(40+m) are connected in series between the power supply and the ground, and each node that is connected in series is connected to the input end of the second gating switch, and the input ends of the second gating switches that are connected to all the nodes that are connected in series are different from each other; the output end of each second gating switch is connected to the input end of the first gating switch that corresponds to the level adjustment circuit; and the control end of each second gating switch is connected to the register IR.

[0019] In another possible implementation manner of the present invention, the NOT-gate type circuit is a phase inverter, a NAND gate circuit, or a NOR gate circuit.

[0020] Optionally, the phase inverter includes a field effect transistor Q211 and a field effect transistor Q212, where a gate of the field effect transistor Q211 and a gate of the field effect transistor Q212 are both input ends of the NOT-gate type circuit; a drain of the field effect transistor Q211 and a drain of the field effect transistor Q212 are both output ends of the NOT-gate type circuit; a source of the field effect transistor Q211 is the power supply terminal of the NOT-gate type circuit; and a source of the field effect transistor Q212 is the ground terminal of the NOT-gate type circuit, where
the field effect transistor Q211 is a P-channel enhanced metal-oxide semiconductor field-effect transistor MOSFET, and the field effect transistor Q212 is an N-channel MOSFET; or the field effect transistor Q211 is an N-channel MOSFET, and the field effect transistor Q212 is a P-channel MOSFET.

[0021] In still another possible implementation manner of the present invention, the level of the pulse signal and the resistance value of the resistance variable circuit are changed non-simultaneously.

[0022] According to another aspect, an embodiment of the present invention provides an analog to digital converter ADC, where the ADC includes n ADC chips, and the ADC further includes a sampling clock generating circuit and a mixer, where the sampling clock generating circuit is connected to the mixer, and the mixer is connected to the n ADC chips;
the sampling clock generating circuit includes a resistance variable circuit, a NOT-gate type circuit, and a capacitor, where the NOT-gate type circuit includes an input end, an output end, a power supply terminal, and a ground terminal; the input end of the NOT-gate type circuit receives a pulse signal whose period is T; the output end of the NOT-gate type circuit is connected to one end of the capacitor; the other end of the capacitor is grounded; the power supply terminal of the NOT-gate type circuit is connected to a power supply; the ground terminal of the NOT-gate type circuit is connected to one end of the resistance variable circuit; and the other end of the resistance variable circuit is grounded;
the NOT-gate type circuit is configured to: when the pulse signal is a high level, output a low level; and when the pulse signal is a low level, output a high level;
the resistance variable circuit comprising n gating switches, is configured to change a resistance value at intervals of duration T, where the resistance value is changed based on a period of nT, and resistance values after changes within each period are different from each other, where n≥2 and n is an integer; and
the mixer is configured to generate n channels of sampling signals whose periods are nT, where within each period nT, a high level of an ith channel of sampling signals is the same as a high level of an output signal of the sampling clock generating circuit within an (i-1)th time segment whose duration is T and is a low level within other time segments; and an ith ADC chip uses the ith channel of sampling signals as a sampling clock.

[0023] The technical solutions provided by the embodiments of the present invention have the following beneficial effects:

[0024] An RC circuit is formed by using a resistance variable circuit, a NOT-gate type circuit, and a capacitor, and when a pulse signal is changed from a low level to a high level, the capacitor discharges by using the RC circuit, so that because of a discharge function, an level of an output signal of the sampling clock generating circuit consisting of the resistance variable circuit, the NOT-gate type circuit, and the capacitor is not immediately changed from a high level to a low level with an level change of the pulse signal, but is maintained at a high level for a period of time and then changed to a low level. If a timing offset between sampling points that is caused by duration within which a high level is maintained is used to cancel a timing offset between sampling points that is generated by dividing the output signal of the sampling clock generating circuit into n channels by using a logic circuit or another circuit, the timing offset between the sampling points can be adjusted. Because duration within which a high level is maintained is related to a resistance value of the resistance variable circuit, according to a relational expression between the duration within which a high level is maintained and the resistance value of the resistance variable circuit, even if adjustment precision of the resistance value of the resistance variable circuit just reaches an average level, adjustment precision of the duration within which a high level is maintained is relatively high and adjustment precision of the timing offset between the sampling points can reach hundreds of femtoseconds, thereby effectively correcting the timing offset between the sampling points, avoiding occurrence of harmonic in a signal obtained after analog-to-digital conversion, enlarging a spurious free dynamic range (Spurious Free Dynamic Range, SFDR for short, a ratio of a root mean square value of a carrier frequency to a root mean square value of a submaximal noise component or a root mean square value of a harmonic distortion component), and improving conversion precision of an ADC.

BRIEF DESCRIPTION OF DRAWINGS



[0025] To describe the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings required for describing the embodiments. Apparently, the accompanying drawings in the following description show merely some embodiments of the present invention, and a person of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a circuit in which multiple ADC chips perform parallel sampling according to an embodiment of the present invention;

FIG. 2 is a schematic waveform diagram of parallel sampling by multiple ADC chips according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a sampling clock generating circuit according to Embodiment 1 of the present invention;

FIG. 4 is a schematic waveform diagram of an input signal and an output signal of a NOT-gate type circuit according to Embodiment 1 of the present invention;

FIG. 5 is a schematic diagram of a resistance value change of a resistance variable circuit according to Embodiment 1 of the present invention;

FIG. 6 is a schematic waveform diagram of a working process of the sampling clock generating circuit according to Embodiment 1 of the present invention;

FIG. 7a to 7b are schematic structural diagrams of a sampling clock generating circuit according to Embodiment 2 of the present invention;

FIG. 8 is a schematic diagram of end points of first gating switches according to Embodiment 2 of the present invention;

FIG. 9 is a schematic structural diagram of an level adjustment circuit according to Embodiment 2 of the present invention;

FIG. 10a to FIG. 10f are schematic structural diagrams of a NOT-gate type circuit according to Embodiment 2 of the present invention;

FIG. 11 is a schematic diagram of changes of a pulse signal and a resistance value of a resistance variable circuit according to Embodiment 2 of the present invention;

FIG. 12 is a schematic structural diagram of a sampling clock generating circuit according to Embodiment 3 of the present invention;

FIG. 13 is a schematic structural diagram of a sampling clock generating circuit according to Embodiment 4 of the present invention;

FIG. 14 is a schematic structural diagram of an analog to digital converter according to Embodiment 5 of the present invention; and

FIG. 15 is a schematic waveform diagram of an output signal in theoretical and practical cases and an input signal of a mixer according to Embodiment 5 of the present invention.


DESCRIPTION OF EMBODIMENTS



[0026] To make the objectives, technical solutions, and advantages of the present invention clearer, the following further describes the embodiments of the present invention in detail with reference to the accompanying drawings.

[0027] The following briefly describes an application scenario of a sampling clock generating circuit provided by an embodiment of the present invention with reference to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 are respectively a schematic structural diagram and a schematic waveform diagram of a circuit in which multiple ADC chips perform parallel sampling. It can be seen from FIG. 1 that the sampling clock generating circuit is connected to four ADC chips: ADC1, ADC2, ADC3, and ADC4, so as to provide sampling clocks to the four ADC chips: ADC1, ADC2, ADC3, and ADC4 respectively; and driven by the sampling clocks, the four ADC chips: ADC1, ADC2, ADC3, and ADC4 separately perform sampling on an input signal; and signals obtained by performing sampling by the four ADC chips: ADC1, ADC2, ADC3, and ADC4 form an output signal. As shown in FIG. 2, for the sampling clocks that the sampling clock generating circuit provides for the four ADC chips: ADC1, ADC2, ADC3, and ADC4, frequencies are the same and phases are different from each other, so that in terms of timing, the ADC1, the ADC2, the ADC3, and the ADC4 perform sampling on the input signal periodically in order, thereby obtaining an effect of performing sampling at a sampling frequency equal to four times of the sampling clock.

[0028] It should be noted that a quantity of the ADC chips, the circuit in which the multiple ADC chips perform parallel sampling, and the waveform presented by the circuit are merely examples, and the present invention is not limited thereto.

Embodiment 1



[0029] This embodiment of the present invention provides a sampling clock generating circuit. As shown in FIG. 3, the sampling clock generating circuit includes a resistance variable circuit 1, a NOT-gate type circuit 2, and a capacitor C, where the NOT-gate type circuit 2 includes an input end, an output end, a power supply terminal, and a ground terminal; the input end of the NOT-gate type circuit 2 receives a pulse signal whose period is T; the output end of the NOT-gate type circuit 2 is an output end of the sampling clock generating circuit, and the output end of the NOT-gate type circuit 2 is connected to one end of the capacitor C; the other end of the capacitor C is grounded; the power supply terminal of the NOT-gate type circuit 2 is connected to a power supply; the ground terminal of the NOT-gate type circuit 2 is connected to one end of the resistance variable circuit 1; and the other end of the resistance variable circuit 1 is grounded.

[0030] Referring to FIG. 4, the NOT-gate type circuit 2 is configured to: when the pulse signal is a high level (that is, an input signal of the NOT-gate type circuit is a high level), output a low level (that is, an output signal of the NOT-gate type circuit is a low level); and when the pulse signal is a low level (that is, the input signal of the NOT-gate type circuit is a low level), output a high level (that is, the output signal of the NOT-gate type circuit is a high level).

[0031] The resistance variable circuit 1 is configured to change a resistance value at intervals of duration T, where the resistance value is changed based on a period of nT, and resistance values after changes within each period are different from each other, where n≥2 and n is an integer. For example, when n=2, as shown in FIG. 5, the resistance value of the resistance variable circuit is R1 within first duration T, is R2 within second duration T, is R1 again within third duration T, and is R2 again within fourth duration T, where R1≠R2, that is, the resistance value changes at intervals of duration T, the resistance value changes based on a period of 2T, and at the beginning of each period, the resistance value is changed from R2 to R1, after duration T, the resistance value is changed from R1 to R2, and after duration T again, a period ends and another period starts, the resistance value is changed from R2 to R1, that is, the resistance values after the changes within each period are different from each other.

[0032] Specifically, n is equal to a quantity of ADC chips performing parallel sampling. Using FIG. 1 as an example, the ADC chips performing parallel sampling are four chips: ADC1, ADC2, ADC3, and ADC4, and in this case, n=4.

[0033] It should be noted that a high level and a low level are allegations in electrical engineering, and a high level is a high voltage relative to a low level. Specifically, a high level is an allowed input (or output) level when input/output of a logic gate is ensured to be 1, and a low level is an allowed input (or output) level when the input/output of the logic gate is ensured to be 0. For example, for a signal whose voltage value change range is 0-5 V, when a voltage value is 0-0.25 V, the logic gate is 1, and an level is a high level; and when the voltage value is 3.5-5 V, the logic gate is 0, and the level is a low level.

[0034] The following briefly describes the working principle of the sampling clock generating circuit provided by this embodiment of the present invention with reference to FIG. 6:

[0035] Referring to FIG. 3, when the pulse signal is changed from a high level to a low level, the output signal of the NOT-gate type circuit 2 is a high level, and the output signal (a high level) of the NOT-gate type circuit 2 is divided into two channels, one channel charges the capacitor C, and the other channel is output as an output signal of the sampling clock generating circuit, that is, the output signal of the sampling clock generating circuit is a high level. For example, as shown in FIG. 6, (FIG. 6 corresponds to a case in which n=2), the output signal of the sampling clock generating circuit whose corresponding pulse signal is a low level is a high level.

[0036] When the pulse signal is changed from a low level to a high level, the output signal of the NOT-gate type circuit 2 is a low level, and in this case, the capacitor C, the NOT-gate type circuit 2, and the resistance variable circuit 1 form an RC discharge circuit, electricity that is charged into the capacitor C before (when the pulse signal is a low level) is released by using the resistance variable circuit 1, the output signal of the sampling clock generating circuit (the output end of the NOT-gate type circuit 2 is the output end of the sampling clock generating circuit) is not changed to a low level immediately, but is maintained at a high level for a period of time, and then is changed to a low level when the electricity of the capacitor C is released to some extent. For example, as shown in FIG. 6, (FIG. 6 corresponds to the case in which n=2), the output signal of the sampling clock generating circuit whose corresponding pulse signal is a high level is maintained at a high level for a period of time and then changed to a low level.

[0037] When the pulse signal is changed from a high level to a low level again, the output signal of the NOT-gate type circuit 2 is changed to a high level again, and in this case, the capacitor C is charged, and the output signal of the sampling clock generating circuit (the output end of the NOT-gate type circuit 2 is the output end of the sampling clock generating circuit) is a high level, and the cycle repeats as shown in FIG. 6.

[0038] Duration within which the output signal of the sampling clock generating circuit is maintained at a high level is related to a speed at which the capacitor C releases the electricity. It is easily known that a larger resistance value of the resistance variable circuit 1 indicates that a speed at which the capacitor C releases the electricity is lower, and the duration within which the output signal of the sampling clock generating circuit is maintained at a high level is longer. Because the resistance value of the resistance variable circuit 1 changes at intervals of duration T, the resistance value is changed based on the period of nT, and the resistance values after the changes within each period are different from each other, the output signal of the sampling clock generating circuit is a signal whose period is nT, and within each period, after the pulse signal (whose period is T) is changed from a low level to a high level each time, the duration within which the output signal of the sampling clock generating circuit is maintained at a high level is different from each other. For example, when n=2, as shown in FIG. 6, the output signal of the sampling clock generating circuit is a signal whose period is 2T, and within first duration T of the period 2T, after the pulse signal is changed from a low level to a high level, the duration within which the output signal of the sampling clock generating circuit is maintained at a high level is T1; and within second duration T of the period 2T, after the pulse signal is changed from a low level to a high level, the duration within which the output signal of the sampling clock generating circuit is maintained at a high level is T2, where T1≠T2, that is, within each period, after the pulse signal (whose period is T) is changed from a low level to a high level , the duration within which the output signal of the sampling clock generating circuit is maintained at a high level is different from each other.

[0039] In this embodiment of the present invention, an RC circuit is formed by using a resistance variable circuit, a NOT-gate type circuit, and a capacitor, and when a pulse signal is changed from a low level to a high level, the capacitor discharges by using the RC circuit, so that because of a discharge function, an level of an output signal of the sampling clock generating circuit consisting of the resistance variable circuit, the NOT-gate type circuit, and the capacitor is not immediately changed from a high level to a low level with an level change of the pulse signal, but is maintained at a high level for a period of time and then changed to a low level . If a timing offset between sampling points that is caused by duration within which a high level is maintained is used to cancel a timing offset between sampling points that is generated by dividing the output signal of the sampling clock generating circuit into n channels by using a logic circuit or another circuit, the timing offset between the sampling points can be adjusted. Because duration within which a high level is maintained is related to a resistance value of the resistance variable circuit, according to a relational expression between the duration within which a high level is maintained and the resistance value of the resistance variable circuit, even if adjustment precision of the resistance value of the resistance variable circuit just reaches an average level, adjustment precision of the duration within which a high level is maintained is relatively high and adjustment precision of the timing offset between the sampling points can reach hundreds of femtoseconds, thereby effectively correcting the timing offset between the sampling points, avoiding occurrence of harmonic in a signal obtained after analog-to-digital conversion, enlarging a spurious free dynamic range (Spurious Free Dynamic Range, SFDR for short, a ratio of a root mean square value of a carrier frequency to a root mean square value of a submaximal noise component or a root mean square value of a harmonic distortion component), and improving conversion precision of an ADC.

Embodiment 2



[0040] This embodiment of the present invention provides a sampling clock generating circuit. A resistance variable circuit in this embodiment is specifically implemented by using a field effect transistor and a gating switch. Referring to FIG. 7a or FIG. 7b, the sampling clock generating circuit includes a resistance variable circuit 1, a NOT-gate type circuit 2, and a capacitor C, where the NOT-gate type circuit 2 includes an input end, an output end, a power supply terminal, and a ground terminal; the input end of the NOT-gate type circuit 2 receives a pulse signal whose period is T; the output end of the NOT-gate type circuit 2 is an output end of the sampling clock generating circuit, and the output end of the NOT-gate type circuit 2 is connected to one end of the capacitor C; the other end of the capacitor C is grounded; the power supply terminal of the NOT-gate type circuit 2 is connected to a power supply; the ground terminal of the NOT-gate type circuit 2 is connected to one end of the resistance variable circuit 1; and the other end of the resistance variable circuit 1 is grounded.

[0041] The NOT-gate type circuit 2 is configured to: when the pulse signal is a high level, output a low level; and when the pulse signal is a low level, output a high level (as shown in FIG. 4).

[0042] The resistance variable circuit 1 is configured to change a resistance value at intervals of duration T, where the resistance value is changed based on a period of nT, and resistance values after changes within each period are different from each other, where n≥2 and n is an integer (as shown in FIG. 5).

[0043] In this embodiment, the resistance variable circuit 1 may include a field effect transistor Q1101 and n first gating switches K1102 to K(1101+n), where each first gating switch includes an input end, an output end, and a control end.

[0044] A drain of the field effect transistor Q1101 is connected to the ground terminal of the NOT-gate type circuit 2, a source of the field effect transistor Q1101 is grounded, and a gate of the field effect transistor Q1101 is connected to the output end of each first gating switch.

[0045] The input end of each first gating switch receives a signal whose voltage value is constant, and the voltage values of the signals received by the input ends of all the first gating switches are different from each other. For example, when n=2, as shown in FIG. 8, the input end of the first gating switch K1102 receives a signal whose voltage value is constantly V1, and an input end of a first gating switch K1103 receives a signal whose voltage value is constantly V2, where V1≠V2.

[0046] The control end of each first gating switch receives a signal whose period is nT, and within each period nT, the signal whose period is nT is a first level within only a time segment whose duration is T and is a second level within other time segments, and time segments within which the signals received by the control ends of all the first gating switches are first level s do not coincide. For example, when n=2, as shown in FIG. 8, the control end of the first gating switch K1102 receives a signal whose period is 2T and that is a high level (the first level) within a first time segment whose duration is T within each period, and a control end of the first gating switch K1102 receives a signal whose period is 2T and that is a high level (the first level) within a second time segment whose duration is T within each period.

[0047] When the signal received by the control end of the first gating switch is the first level, the input end of the first gating switch is connected to the output end of the first gating switch; and when the signal received by the control end of the first gating switch is the second level, the input end of the first gating switch is disconnected from the output end of the first gating switch.

[0048] Specifically, the first level is a high level, and the second level is a low level ; or the first level is a low level, and the second level is a high level. In FIG. 8, an example in which the first level is a high level and the second level is a low level is used for description, which is not intended to limit the present invention.

[0049] It may be understood that a signal received by the gate of the field effect transistor Q1101 is a signal whose voltage value changes at intervals of duration T and whose period is nT, and voltage values after changes within each period are different from each other. For example, when n=2, using FIG. 8 as an example, the voltage value of the signal received by the gate of the field effect transistor Q1101 is V1 within a first time segment whose duration is T, is V2 within a second time segment whose duration is T, is V1 again within a third time segment whose duration is T, and is V2 again within a fourth time segment whose duration is T, that is, the signal changes at intervals of duration T and its period is 2T, and voltage values after changes within each period are different from each other.

[0050] Specifically, the field effect transistor Q1101 may be an N-channel field-effect transistor, or may be a P-channel field-effect transistor. In FIG. 7a and FIG. 7b, an example in which the field effect transistor Q1101 is an N-channel field-effect transistor is used, which is not intended to limit the present invention.

[0051] Optionally, the field effect transistor Q1101 may be a junction field effect transistor (JFET), an enhanced metal-oxide semiconductor field-effect transistor (MOSFET), or a depletion MOSFET.

[0052] In an implementation manner of this embodiment, as shown in FIG. 7a, the resistance variable circuit 1 may further include a field effect transistor Q(1102+n), where a gate of the field effect transistor Q(1102+n) is connected to the power supply, a drain of the field effect transistor Q(1102+n) is connected to the drain of the field effect transistor Q1101, and a source of the field effect transistor Q(1102+n) is connected to the source of the field effect transistor Q1101.

[0053] The field effect transistor Q(1102+n) and the field effect transistor Q1101 are both P-channel field-effect transistors, or the field effect transistor Q(1102+n) and the field effect transistor Q1101 are both N-channel field-effect transistors. In FIG. 7a, an example in which the field effect transistor Q(1102+n) and the field effect transistor Q1101 are both N-channel field-effect transistors is used, which is not intended to limit the present invention.

[0054] Optionally, the field effect transistor Q(1102+n) may be a JFET, an enhanced MOSFET, or a depletion MOSFET.

[0055] In another implementation manner of this embodiment, as shown in FIG. 7b, the resistance variable circuit 1 may further include a resistor R(1103+n), where one end of the resistor R(1103+n) is connected to the drain of the field effect transistor Q1101, and the other end of the resistor (1103+n) is connected to the source of the field effect transistor Q1101.

[0056] It is easily known that the field effect transistor Q(1102+n) or the resistor R(1103+n) is or is equivalent to a resistor that is connected in parallel between the drain and the source of the field effect transistor Q1101, which can decrease a change amplitude of an equivalent resistor between the drain and the source of the field effect transistor Q1101, thereby decreasing a change amplitude of the resistance value of the resistance variable circuit 1. For example, before a resistor is connected in parallel, when a resistance value of the equivalent resistor between the drain and the source of the field effect transistor Q1101 is increased from r to 2r, the change amplitude of the resistance value of the resistance variable circuit 1 is 2r-r=r; and after a resistor whose resistance value is r is connected in parallel, when the resistance value of the equivalent resistor between the drain and the source of the field effect transistor Q1101 is increased from r to 2r, the change amplitude of the resistance value of the resistance variable circuit 1 is 1/(1/(2r)+1/r)-1/(1/r+1/r)=2r/3-r/2=r/6, where r/6 is obviously less than r; therefore, either of the foregoing two implementation manners may be used to decrease the change amplitude of the resistance value of the resistance variable circuit 1, thereby implementing more precise adjustment.

[0057] In still another implementation manner of this embodiment, referring to FIG. 7a or FIG. 7b, the sampling clock generating circuit may further include level adjustment circuits 4 that are in a one-to-one correspondence to the first gating switches K1102 to K(1101+n), where each level adjustment circuit is connected to the input end of the first gating switch that corresponds to the level adjustment circuit.

[0058] Each level adjustment circuit 4 is configured to provide a signal whose voltage value is constant and adjustable to the input end of the first gating switch that corresponds to the level adjustment circuit, where the voltage values of the signals provided by all the level adjustment circuits 4 are different from each other.

[0059] The voltage value being constant and adjustable refers to that the voltage value of the signal is generally maintained unchanged at a value, but the value maintained unchanged is adjustable. For example, the voltage value of the signal is adjusted from being maintained at V1 to being maintained at V2, where V1≠V2.

[0060] It may be understood that when the level adjustment circuit 4 adjusts the voltage value of the signal received by the input end of the corresponding first gating switch, the voltage value of the signal received by the gate of the field effect transistor Q1101 is changed with the voltage value of the signal. When the field effect transistor Q1101 works in a linear region, a voltage between the drain and the source of the field effect transistor Q1101 and a current of the drain are both changed with the adjusted voltage value of the signal received by the input end of the corresponding first gating switch and change speeds are different, the equivalent resistor between the drain and the source of the field effect transistor Q1101 is changed, and the resistance value of the resistance variable circuit 1 is changed.

[0061] Because a larger resistance value of the resistance variable circuit 1 indicates that when the pulse signal is changed from a high level to a low level, a discharge speed at which the capacitor C releases the electricity by using the resistance variable circuit 1 is lower, and duration within which an output signal of the sampling clock generating circuit is maintained at a high level is longer, when the resistance value of the resistance variable circuit 1 is changed, the discharge speed of the capacitor C and the duration within which a high level is maintained are changed in order with the resistance value of the resistance variable circuit 1.

[0062] If a timing offset between sampling points that is caused by duration within which a high level is maintained is used to cancel a timing offset between sampling points that is generated by dividing the output signal of the sampling clock generating circuit into n channels by using a logic circuit or another circuit, the timing offset between the sampling points can be adjusted and corrected. Because duration within which a high level is maintained is related to a resistance value of the resistance variable circuit, according to a relational expression between the duration within which a high level is maintained and the resistance value of the resistance variable circuit (which is the prior art and is not listed herein again), even if adjustment precision of the resistance value of the resistance variable circuit just reaches an average level, adjustment precision of the duration within which a high level is maintained is relatively high and adjustment precision of the timing offset between the sampling points can reach at least hundreds of femtoseconds.

[0063] In addition, by adjusting the voltage values of the signals received by the input ends of the first gating switches K1102 to K(1101+n), the resistance value of the resistance variable circuit 1 is adjusted, thereby improving the adjustment precision of the resistance value of the resistance variable circuit 1; therefore, the adjustment precision of the timing offset between the sampling points may further reach hundreds of femtoseconds, and conversion precision of an ADC is further improved.

[0064] Optionally, as shown in FIG. 9, each level adjustment circuit 4 may include m resistors R41 to R(40+m), m+1 second gating switches K(41+m) to K(41+2m), and a register IR, where m≥2 and m is an integer. Each second gating switch includes an input end, an output end, and a control end. The m resistors R41 to R(41+m) are connected in series between the power supply and the ground, and each node that is connected in series is connected to the input end of the second gating switch, and the input ends of the second gating switches that are connected to all the nodes that are connected in series are different from each other. The output end of each second gating switch is connected to the input end of the first gating switch that corresponds to the level adjustment circuit 4; and the control end of each second gating switch is connected to the register IR.

[0065] It may be understood that the resistors R41 to R(40+m) that are connected in series between the power supply and the ground divide a power supply voltage into m+1 levels, and voltages of the levels are different from each other. Each node that is connected in series is connected to the input end of the second gating switch, and the input ends of the second gating switches that are connected to the nodes that are connected in series are different from each other; therefore, each second gating switch receives a signal with a different voltage. By using different control signals output by the register IR, one of the second gating switches K(41+m) to K(41+2m) can be controlled to be connected, and a voltage of a node connected to the connected second gating switch is the voltage of the signal received by the input end of the first gating switch, so that the voltage value of the signal received by the input end of the first gating switch is changed by connecting different second gating switches.

[0066] Specifically, a value of m depends on adjustment precision of the voltage value of the signal received by the input end of the first gating switch, for example, if the power supply voltage is 5 V and the adjustment precision is 1 V, the power supply voltage is divided into six levels: 5 V, 4 V, 3 V, 2 V, 1V, and 0 V, that is, m=5.

[0067] In specific implementation, the NOT-gate type circuit 2 may be a phase inverter, a NAND gate circuit, or a NOR gate circuit. When the NOT-gate type circuit 2 is any one of a phase inverter, a NAND gate circuit, and a NOR gate circuit, a specific implementation circuit thereof may have several implementation manners. For example, when the NOT-gate type circuit 2 is a phase inverter, there may be at least the following implementation manners:

[0068] In a first implementation manner, referring to FIG. 10a, the phase inverter may include a field effect transistor Q211 and a field effect transistor Q212, where a gate of the field effect transistor Q211 and a gate of the field effect transistor Q212 are both input ends of the NOT-gate type circuit 2; a drain of the field effect transistor Q211 and a drain of the field effect transistor Q212 are both output ends of the NOT-gate type circuit 2; a source of the field effect transistor Q211 is the power supply terminal of the NOT-gate type circuit 2; and a source of the field effect transistor Q212 is the ground terminal of the NOT-gate type circuit 2.

[0069] The field effect transistor Q211 is a P-channel enhanced MOSFET, and the field effect transistor Q212 is an N-channel MOSFET; or the field effect transistor Q211 is an N-channel MOSFET, and the field effect transistor Q212 is a P-channel MOSFET. In FIG. 10a, an example in which the field effect transistor Q211 is a P-channel enhanced MOSFET and the field effect transistor Q212 is an N-channel MOSFET is used, which is not intended to limit the present invention.

[0070] In a second implementation manner, referring to FIG. 10b, the phase inverter may include a bipolar junction transistor Q221 and a bipolar junction transistor Q222, where a base of the bipolar junction transistor Q221 and a base of the bipolar junction transistor Q222 are both input ends of the NOT-gate type circuit 2; an emitter of the bipolar junction transistor Q221 and an emitter of the bipolar junction transistor Q222 are output ends of the NOT-gate type circuit 2; a collector of the bipolar junction transistor Q221 is the power supply terminal of the NOT-gate type circuit 2; and a collector of the bipolar junction transistor Q222 is the ground terminal of the NOT-gate type circuit 2.

[0071] The bipolar junction transistor Q221 is an NPN bipolar junction transistor, and the bipolar junction transistor Q222 is a PNP bipolar junction transistor; or the Q221 is a PNP bipolar junction transistor, and the bipolar junction transistor Q222 is an NPN bipolar junction transistor. In FIG. 10b, an example in which the bipolar junction transistor Q221 is an NPN bipolar junction transistor, and the bipolar junction transistor Q222 is a PNP bipolar junction transistor is used, which is not intended to limit the present invention.

[0072] In a third implementation manner, as shown in FIG. 10c, the phase inverter may include a field effect transistor Q231 and a resistor R232, where a gate of the field effect transistor Q231 is the input end of the NOT-gate type circuit 2; a drain of the field effect transistor Q231 is the output end of the NOT-gate type circuit 2; a source of the field effect transistor Q231 is the ground terminal of the NOT-gate type circuit 2; the drain of the field effect transistor Q231 is connected to one end of the resistor R232; and the other end of the resistor R232 is the power supply terminal of the NOT-gate type circuit 2.

[0073] The field effect transistor Q231 is an enhanced MOSFET.

[0074] Specifically, the field effect transistor Q231 may be an N-channel field-effect transistor, or may be a P-channel field-effect transistor. In FIG. 10c, an example in which the field effect transistor Q231 is an N-channel field-effect transistor is used, which is not intended to limit the present invention.

[0075] In a fourth implementation manner, as shown in FIG. 10d, the phase inverter may include a field effect transistor Q241 and a resistor R242, where a gate of the field effect transistor Q241 is the input end of the NOT-gate type circuit 2; a source of the field effect transistor Q241 is the output end of the NOT-gate type circuit 2; a drain of the field effect transistor Q241 is the power supply terminal of the NOT-gate type circuit 2; the source of the field effect transistor Q241 is connected to one end of the resistor R242; and the other end of the resistor R242 is the ground terminal of the NOT-gate type circuit 2.

[0076] The field effect transistor Q241 is an enhanced MOSFET.

[0077] Specifically, the field effect transistor Q241 may be a P-channel field-effect transistor, or may be an N-channel field-effect transistor. In FIG. 10d, an example in which the field effect transistor Q241 is a P-channel field-effect transistor is used, which is not intended to limit the present invention.

[0078] For another example, when the NOT-gate type circuit 2 is a NAND gate circuit, the NAND gate circuit may use the following implementation manners:

[0079] Referring to FIG. 10e, the NAND gate circuit may include a field effect transistor Q251, a field effect transistor Q252, a field effect transistor Q253, and a field effect transistor Q254, where a gate of the field effect transistor Q251, a gate of the field effect transistor Q252, a gate of the field effect transistor Q253, and a gate of the field effect transistor Q254 are all input ends of the NOT-gate type circuit 2; a drain of the field effect transistor Q251, a drain of the field effect transistor Q252, and a drain of the field effect transistor Q253 are all output ends of the NOT-gate type circuit 2; a source of the field effect transistor Q251 and a source of the field effect transistor Q252 are both power supply terminals of the NOT-gate type circuit 2; a source of the field effect transistor Q253 is connected to a drain of the field effect transistor Q254; and a source of the field effect transistor Q254 is the ground terminal of the NOT-gate type circuit 2.

[0080] The field effect transistor Q251 and the field effect transistor Q252 are both P-channel field-effect transistors, and the field effect transistor Q253 and the field effect transistor Q254 are both N-channel field-effect transistors; or the field effect transistor Q251 and the field effect transistor Q252 are both N-channel field-effect transistors, and the field effect transistor Q253 and the field effect transistor Q254 are both P-channel field-effect transistors. In FIG. 10e, an example in which the field effect transistor Q251 and the field effect transistor Q252 are both P-channel field-effect transistors, and the field effect transistor Q253 and the field effect transistor Q254 are both N-channel field-effect transistors is used, which is not intended to limit the present invention.

[0081] For another example, when the NOT-gate type circuit 2 is a NOR gate circuit, the NOR gate circuit may use the following implementation manners:

[0082] Referring to FIG. 10f, the NOR gate circuit may include a field effect transistor Q261, a field effect transistor Q262, and a resistor R263, where a gate of the field effect transistor Q261 and a gate of the field effect transistor Q262 are both input ends of the NOT-gate type circuit 2; a drain of the field effect transistor Q261 and a drain of the field effect transistor Q262 are both output ends of the NOT-gate type circuit 2; a source of the field effect transistor Q261 and a source of the field effect transistor Q262 are both power supply terminals of the NOT-gate type circuit 2; one end of the resistor R263 is the ground terminal of the NOT-gate type circuit 2; and the other end of the resistor R263 is connected to both the drain of the field effect transistor Q261 and the drain of the field effect transistor Q262.

[0083] The field effect transistor Q261 and the field effect transistor Q262 are both N-channel field-effect transistors; or the field effect transistor Q261 and the field effect transistor Q262 are both P-channel field-effect transistors. In FIG. 10f, an example in which the field effect transistor Q261 and the field effect transistor Q262 are both N-channel field-effect transistors is used, which is not intended to limit the present invention.

[0084] In comprehensive considerations to the foregoing implementation manners, when the NOT-gate type circuit 2 uses a phase inverter, compared with using a NAND gate circuit or a NOR gate circuit, fewer devices are required, smaller space is occupied, and costs are also lower; therefore, the phase inverter is preferably used to implement the NOT-gate type circuit 2. Specifically, in the provided four circuit implementing the phase inverter, compared with other three implementation manners, in the first implementation manner, only a field effect transistor is used and a resistor is not involved, so that an integration level and stability are both relatively good; therefore, the first implementation manner is an optimal implementation manner.

[0085] In still another implementation manner of this embodiment, referring to FIG. 11, the level of the pulse signal and the resistance value of the resistance variable circuit 1 are changed non-simultaneously.

[0086] In specific implementation, an level timing of the pulse signal and a resistance value timing of the resistance variable circuit 1 may be adjusted, for example, a pulse signal of a required timing is output by directly controlling a pulse signal generator, or a phase inverter or another device is used to delay the pulse signal, to implement non-simultaneous changes of the level of the pulse signal and the resistance value of the resistance variable circuit 1.

[0087] It is easily known that the level of the pulse signal and the resistance value of the resistance variable circuit are changed non-simultaneously, so that when the pulse signal is changed from a low level to a high level, the resistance value of the resistance variable circuit remains unchanged, and voltages at two ends of the resistance variable circuit are stable, thereby improving stability of the sampling clock generating circuit.

[0088] It should be noted that in this embodiment, positive and negative voltages of the power supply, and types of the field effect transistors or the bipolar junction transistors, such as an N-channel field-effect transistor, a P-channel field-effect transistor, a JFET, an enhanced MOSFET, a depletion MOSFET, a PNP bipolar junction transistor, or an NPN bipolar junction transistor, need to be cooperated with each other, as long as a required effect is reached.

[0089] In this embodiment of the present invention, an RC circuit is formed by using a resistance variable circuit, a NOT-gate type circuit, and a capacitor, and when a pulse signal is changed from a low level to a high level, the capacitor discharges by using the RC circuit, so that because of a discharge function, an level of an output signal of the sampling clock generating circuit consisting of the resistance variable circuit, the NOT-gate type circuit, and the capacitor is not immediately changed from a high level to a low level with an level change of the pulse signal, but is maintained at a high level for a period of time and then changed to a low level . If a timing offset between sampling points that is caused by duration within which a high level is maintained is used to cancel a timing offset between sampling points that is generated by dividing the output signal of the sampling clock generating circuit into n channels by using a logic circuit or another circuit, the timing offset between the sampling points can be adjusted. Because duration within which a high level is maintained is related to a resistance value of the resistance variable circuit, according to a relational expression between the duration within which a high level is maintained and the resistance value of the resistance variable circuit, even if adjustment precision of the resistance value of the resistance variable circuit just reaches an average level, adjustment precision of the duration within which a high level is maintained is relatively high and adjustment precision of the timing offset between the sampling points can reach hundreds of femtoseconds, thereby effectively correcting the timing offset between the sampling points, avoiding occurrence of harmonic in a signal obtained after analog-to-digital conversion, enlarging an SFDR, and improving conversion precision of an ADC.

Embodiment 3



[0090] This embodiment of the present invention provides a sampling clock generating circuit, and a difference from Embodiment 2 lies in that: a resistance variable circuit in this embodiment is implemented by using resistors and gating switches that are in a one-to-one correspondence, and branches, obtained after the resistors are connected in series to the gating switches that respectively correspond to the resistors, are connected in parallel.

[0091] Specifically, as shown in FIG. 12, the resistance variable circuit 1 may include n resistors R1201 to R(1200+n) and n third gating switches K(1201+n) to K(1200+2n) that are in a one-to-one correspondence to the n the resistors R1201 to R(1200+n), where resistance values of the resistors are different from each other, and each third gating switch includes an input end, an output end, and a control end. Branches formed by connecting the resistors in series to the third gating switches that respectively correspond to the resistors are connected in parallel between the ground terminal of the NOT-gate type circuit 2 and the ground. The control end of each third gating switch receives a signal whose period is nT, and within each period nT, the signal whose period is nT is a first level within only a time segment whose duration is T and is a second level within other time segments, and time segments within which the signals received by the control ends of all the third gating switches are first level s do not coincide.

[0092] When the signal received by the control end of the third gating switch is the first level, the input end of the third gating switch is connected to the output end of the third gating switch; and when the signal received by the control end of the third gating switch is the second level, the input end of the third gating switch is disconnected from the output end of the third gating switch.

[0093] Specifically, the first level is a high level, and the second level is a low level ; or the first level is a low level, and the second level is a high level.

[0094] In this embodiment of the present invention, an RC circuit is formed by using a resistance variable circuit, a NOT-gate type circuit, and a capacitor, and when a pulse signal is changed from a low level to a high level, the capacitor discharges by using the RC circuit, so that because of a discharge function, an level of an output signal of the sampling clock generating circuit consisting of the resistance variable circuit, the NOT-gate type circuit, and the capacitor is not immediately changed from a high level to a low level with an level change of the pulse signal, but is maintained at a high level for a period of time and then changed to a low level . If a timing offset between sampling points that is caused by duration within which a high level is maintained is used to cancel a timing offset between sampling points that is generated by dividing the output signal of the sampling clock generating circuit into n channels by using a logic circuit or another circuit, the timing offset between the sampling points can be adjusted. Because duration within which a high level is maintained is related to a resistance value of the resistance variable circuit, according to a relational expression between the duration within which a high level is maintained and the resistance value of the resistance variable circuit, even if adjustment precision of the resistance value of the resistance variable circuit just reaches an average level, adjustment precision of the duration within which a high level is maintained is relatively high and adjustment precision of the timing offset between the sampling points can reach hundreds of femtoseconds, thereby effectively correcting the timing offset between the sampling points, avoiding occurrence of harmonic in a signal obtained after analog-to-digital conversion, enlarging an SFDR, and improving conversion precision of an ADC.

Embodiment 4



[0095] This embodiment of the present invention provides a sampling clock generating circuit, and a difference from Embodiment 2 lies in that: a resistance variable circuit in this embodiment is implemented by using resistors and gating switches that are in a one-to-one correspondence, and branches, obtained after the resistors are connected in parallel to the gating switches that respectively correspond to the resistors, are connected in series.

[0096] Specifically, as shown in FIG. 13, the resistance variable circuit 1 may include n resistors R1301 to R(1300+n) and n fourth gating switches K(1301+n) to K(1300+2n) that are in a one-to-one correspondence to the n the resistors R1301 to R(1300+n), where resistance values of the resistors are different from each other, and each fourth gating switch includes an input end, an output end, and a control end. Branches formed by connecting the resistors in parallel to the fourth gating switches that respectively correspond to the resistors are connected in series between the ground terminal of the NOT-gate type circuit 2 and the ground. The control end of each fourth gating switch receives a signal whose period is nT, and within each period nT, the signal whose period is nT is a first level within only a time segment whose duration is T and is a second level within other time segments, and time segments within which the signals received by the control ends of all the fourth gating switches are second level s do not coincide.

[0097] When the signal received by the control end of the fourth gating switch is the first level, the input end of the fourth gating switch is connected to the output end of the fourth gating switch; and when the signal received by the control end of the fourth gating switch is the second level, the input end of the fourth gating switch is disconnected from the output end of the fourth gating switch.

[0098] Specifically, the first level is a high level, and the second level is a low level ; or the first level is a low level, and the second level is a high level.

[0099] In this embodiment of the present invention, an RC circuit is formed by using a resistance variable circuit, a NOT-gate type circuit, and a capacitor, and when a pulse signal is changed from a low level to a high level, the capacitor discharges by using the RC circuit, so that because of a discharge function, an level of an output signal of the sampling clock generating circuit consisting of the resistance variable circuit, the NOT-gate type circuit, and the capacitor is not immediately changed from a high level to a low level with an level change of the pulse signal, but is maintained at a high level for a period of time and then changed to a low level . If a timing offset between sampling points that is caused by duration within which a high level is maintained is used to cancel a timing offset between sampling points that is generated by dividing the output signal of the sampling clock generating circuit into n channels by using a logic circuit or another circuit, the timing offset between the sampling points can be adjusted. Because duration within which a high level is maintained is related to a resistance value of the resistance variable circuit, according to a relational expression between the duration within which a high level is maintained and the resistance value of the resistance variable circuit, even if adjustment precision of the resistance value of the resistance variable circuit just reaches an average level, adjustment precision of the duration within which a high level is maintained is relatively high and adjustment precision of the timing offset between the sampling points can reach hundreds of femtoseconds, thereby effectively correcting the timing offset between the sampling points, avoiding occurrence of harmonic in a signal obtained after analog-to-digital conversion, enlarging an SFDR, and improving conversion precision of an ADC.

Embodiment 5



[0100] This embodiment of the present invention provides an ADC. Referring to FIG. 14, the ADC includes n ADC chips IC100 to IC(n100), a sampling clock generating circuit (n+1)100, and a mixer (n+2)100, where the sampling clock generating circuit (n+1)100 is connected to the mixer (n+2)100, and the mixer (n+2)100 is connected to the n ADC chips IC100 to IC(n100).

[0101] The sampling clock generating circuit (n+1)100 may be the same as the sampling clock generating circuit provided by any embodiment of Embodiment 1 to Embodiment 4.

[0102] The mixer (n+2)100 is configured to generate n channels of sampling signals whose periods are nT, where within each period nT, an level of an ith channel of sampling signals is the same as an level of an output signal of the sampling clock generating circuit (n+1)100 in an (i-1)th time segment whose duration is T and is a low level within other time segments; and an ith ADC chip uses the ith channel of sampling signals as a sampling clock. For example, when n=2, as shown in FIG. 15, the mixer generates two channels of sampling signals whose periods are 2T, and in a theoretical case, within each period 2T, an level of a first channel of sampling signals is the same as the level of the output signal of the sampling clock generating circuit (n+1)100 (an input signal of the mixer (n+2)100) in a first time segment whose duration is T and is a low level within other time segments; and an level of a second channel of sampling clock signals is the same as the level of the output signal of the sampling clock generating circuit (n+1)100 (the input signal of the mixer (n+2)100) in a second time segment whose duration is T and is a low level within other time segments.

[0103] It may be understood that in an actual application, because features of devices of the mixer (n+2)100 cannot reach theoretical features, a timing offset exists between sampling points of the n channels of signals generated by the mixer (n+2)100 and sampling points of the output signal of the sampling clock generating circuit (n+1)100, and as long as a timing offset between sampling points of the output signal of the sampling clock generating circuit (n+1)100 is properly adjusted, a timing offset between sampling points that is generated due to the features of the devices in the mixer (n+2)100 can be canceled, so that the mixer (n+2)100 generates n channels of sampling signals whose periods are nT and that have a same frequency and different phases, and sampling points of the n channels of sampling signals are the same as sampling points of a pulse signal, as shown in FIG. 15.

[0104] In this embodiment of the present invention, an RC circuit is formed by using a resistance variable circuit, a NOT-gate type circuit, and a capacitor, and when a pulse signal is changed from a low level to a high level, the capacitor discharges by using the RC circuit, so that because of a discharge function, an level of an output signal of the sampling clock generating circuit consisting of the resistance variable circuit, the NOT-gate type circuit, and the capacitor is not immediately changed from a high level to a low level with an level change of the pulse signal, but is maintained at a high level for a period of time and then changed to a low level . If a timing offset between sampling points that is caused by duration within which a high level is maintained is used to cancel a timing offset between sampling points that is generated by dividing the output signal of the sampling clock generating circuit into n channels by using a logic circuit or another circuit, the timing offset between the sampling points can be adjusted. Because duration within which a high level is maintained is related to a resistance value of the resistance variable circuit, according to a relational expression between the duration within which a high level is maintained and the resistance value of the resistance variable circuit, even if adjustment precision of the resistance value of the resistance variable circuit just reaches an average level, adjustment precision of the duration within which a high level is maintained is relatively high and adjustment precision of the timing offset between the sampling points can reach hundreds of femtoseconds, thereby effectively correcting the timing offset between the sampling points, avoiding occurrence of harmonic in a signal obtained after analog-to-digital conversion, enlarging an SFDR, and improving conversion precision of an ADC.

[0105] The sequence numbers of the foregoing embodiments of the present invention are merely for illustrative purposes, and are not intended to indicate priorities of the embodiments.

[0106] A person of ordinary skill in the art may understand that all or some of the steps of the embodiments may be implemented by hardware or a program instructing related hardware. The program may be stored in a computer-readable storage medium. The storage medium may include: a read-only memory, a magnetic disk, an optical disc, or the like.

[0107] The foregoing descriptions are merely exemplary embodiments of the present invention, but are not intended to limit the present invention. Any modification, and improvement made without departing from the principle of the present invention shall fall within the protection scope of the present invention, without departing from the scope of the attached claims.


Claims

1. A sampling clock generating circuit, wherein the sampling clock generating circuit comprises a resistance variable circuit (1), a NOT-gate type circuit (2), and a capacitor;
wherein the NOT-gate type circuit (2) comprises an input end, an output end, a power supply terminal, and a ground terminal; the input end of the NOT-gate type circuit (2) receives a pulse signal whose period is T; the output end of the NOT-gate type circuit (2) is connected to one end of the capacitor; the other end of the capacitor is grounded; the power supply terminal of the NOT-gate type circuit (2) is connected to a power supply; the ground terminal of the NOT-gate type circuit (2) is connected to one end of the resistance variable circuit (1); and the other end of the resistance variable circuit (1) is grounded;
the NOT-gate type circuit (2) is configured to: when the pulse signal is at a high level, output a low level; and when the pulse signal is a low level, output a high level; and
the resistance variable circuit (1) comprising n gating switches, is configured to change a resistance value at intervals of duration T between n resistance values,
wherein the resistance value is changed based on a period of nT, and resistance values after changes within each period are different from each other, wherein n≥2 and n is an integer.
 
2. The sampling clock generating circuit according to claim 1, wherein the resistance variable circuit (1) comprises a field effect transistor Q1101 and n first gating switches K1102 to K(1101+n), wherein each first gating switch comprises an input end, an output end, and a control end; a drain of the field effect transistor Q1101 is connected to the ground terminal of the NOT-gate type circuit, a source of the field effect transistor Q1101 is grounded, and a gate of the field effect transistor Q1101 is connected to the output end of each first gating switch; the input end of each first gating switch receives a signal whose voltage value is constant, and the voltage values of the signals received by the input ends of all the first gating switches are different from each other; and the control end of each first gating switch receives a signal whose period is nT, and within each period nT, the signal whose period is nT is a first level within only a time segment whose duration is T and is a second level within other time segments, and time segments within which the signals received by the control ends of all the gating switches are the first level s do not coincide, wherein
when the signal received by the control end of the first gating switch is the first level, the input end of the first gating switch is connected to the output end of the first gating switch; and when the signal received by the control end of the first gating switch is the second level, the input end of the first gating switch is disconnected from the output end of the first gating switch.
 
3. The sampling clock generating circuit according to claim 2, wherein the field effect transistor Q1101 is a junction field effect transistor, JFET, an enhanced metal-oxide semiconductor field-effect transistor, MOSFET, or a depletion MOSFET.
 
4. The sampling clock generating circuit according to claim 2, wherein the resistance variable circuit (1) further comprises a field effect transistor Q(1102+n), wherein a gate of the field effect transistor Q(1102+n) is connected to the power supply, a drain of the field effect transistor Q(1102+n) is connected to the drain of the field effect transistor Q1101, and a source of the field effect transistor Q(1102+n) is connected to the source of the field effect transistor Q1101, wherein
the field effect transistor Q(1102+n) and the field effect transistor Q1101 are both P-channel field-effect transistors, or the field effect transistor Q(1102+n) and the field effect transistor Q1101 are both N-channel field-effect transistors.
 
5. The sampling clock generating circuit according to claim 4, wherein the field effect transistor Q(1102+n) is a JFET, an enhanced MOSFET, or a depletion MOSFET.
 
6. The sampling clock generating circuit according to claim 2, wherein the resistance variable circuit (1) further comprises a resistor R(1103+n), wherein one end of the resistor R(1103+n) is connected to the drain of the field effect transistor Q1101, and the other end of the resistor R(1103+n) is connected to the source of the field effect transistor Q1101.
 
7. The sampling clock generating circuit according to claim 2, wherein the sampling clock generating circuit further comprises level adjustment circuits (4) that are in a one-to-one correspondence to the first gating switches K1102 to K(1101+n), wherein each level adjustment circuit is connected to the input end of the first gating switch that corresponds to the level adjustment circuit; and
each level adjustment circuit is configured to provide a signal whose voltage value is constant and adjustable to the input end of the first gating switch that corresponds to the level adjustment circuit, wherein the voltage values of the signals provided by all the level adjustment circuits (4) are different from each other.
 
8. The sampling clock generating circuit according to claim 7, wherein each level adjustment circuit (4) comprises m resistors R41 to R(40+m), m+1 second gating switches K(41+m) to K(41+2m), and a register IR, wherein m≥2 and m is an integer; each second gating switch comprises an input end, an output end, and a control end; the m resistors R41 to R(40+m) are connected in series between the power supply and the ground, and each node that is connected in series is connected to the input end of the second gating switch, and the input ends of the second gating switches that are connected to all the nodes that are connected in series are different from each other; the output end of each second gating switch is connected to the input end of the first gating switch that corresponds to the level adjustment circuit; and the control end of each second gating switch is connected to the register IR.
 
9. The sampling clock generating circuit according to claim 1, wherein the NOT-gate type circuit (2) is a phase inverter, a NAND gate circuit, or a NOR gate circuit.
 
10. The sampling clock generating circuit according to claim 9, wherein the phase inverter comprises a field effect transistor Q211 and a field effect transistor Q212, wherein a gate of the field effect transistor Q211 and a gate of the field effect transistor Q212 are both input ends of the NOT-gate type circuit; a drain of the field effect transistor Q211 and a drain of the field effect transistor Q212 are both output ends of the NOT-gate type circuit; a source of the field effect transistor Q211 is the power supply terminal of the NOT-gate type circuit; and a source of the field effect transistor Q212 is the ground terminal of the NOT-gate type circuit, wherein
the field effect transistor Q211 is a P-channel enhanced metal-oxide semiconductor field-effect transistor MOSFET, and the field effect transistor Q212 is an N-channel MOSFET; or the field effect transistor Q211 is an N-channel MOSFET, and the field effect transistor Q212 is a P-channel MOSFET.
 
11. The sampling clock generating circuit according to any one of claims 1 to 10, wherein the level of the pulse signal and the resistance value of the resistance variable circuit (1) are changed non-simultaneously.
 
12. An analog to digital converter, ADC, wherein the ADC comprises n ADC chips, and the ADC further comprises a sampling clock generating circuit according to any one of claims 1-11 and a mixer, wherein the sampling clock generating circuit is connected to the mixer, and the mixer is connected to the n ADC chips;
the mixer is configured to generate n channels of sampling signals whose periods are nT, wherein within each period nT, a high level of an ith channel of sampling signals is the same as a high level of an output signal of the sampling clock generating circuit within an (i-1)th time segment whose duration is T and is a low level within other time segments; and an ith ADC chip uses the ith channel of sampling signals as a sampling clock.
 


Ansprüche

1. Abtasttakterzeugungsschaltung, wobei die Abtasttakterzeugungsschaltung eine Schaltung mit variablem Widerstand (1), eine Schaltung vom Typ NICHT-Gate (2) und einen Kondensator umfasst;
wobei die Schaltung vom Typ NICHT-Gate (2) ein Eingangsende, ein Ausgangsende, einen Leistungsversorgungsanschluss und einen Erdungsanschluss umfasst; wobei das Eingangsende der Schaltung vom Typ NICHT-Gate (2) ein Impulssignal empfängt, dessen Periode T ist; wobei das Ausgangsende der Schaltung vom Typ NICHT-Gate (2) mit einem Ende des Kondensators verbunden ist; wobei das andere Ende des Kondensators geerdet ist; wobei der Leistungsversorgungsanschluss der Schaltung vom Typ NICHT-Gate (2) mit einer Leistungsversorgung verbunden ist; wobei der Erdungsanschluss der Schaltung vom Typ NICHT-Gate (2) mit einem Ende der Schaltung mit variablem Widerstand (1) verbunden ist; und wobei das andere Ende der Schaltung mit variablem Widerstand (1) geerdet ist;
wobei die Schaltung vom Typ NICHT-Gate (2) zu Folgendem konfiguriert ist: wenn sich das Impulssignal auf einem hohen Niveau befindet, Ausgeben eines niedrigen Niveaus; und wenn sich das Impulssignale auf einem niedrigen Niveau befindet, Ausgaben eines hohen Niveaus; und
wobei die Schaltung mit variablem Widerstand (1), die n Gating-Schalter umfasst, dazu konfiguriert ist, einen Widerstandswert in Intervallen der Dauer T zwischen n Widerstandswerten zu ändern,
wobei der Widerstandswert basierend auf einer Periode von nT geändert wird und sich die Widerstandswerte nach den Änderungen innerhalb jeder Periode voneinander unterscheiden, wobei n≥2 und n eine ganze Zahl ist.
 
2. Abtasttakterzeugungsschaltung nach Anspruch 1, wobei die Schaltung mit variablem Widerstand (1) einen Feldeffekttransistor Q1101 und n erste Gating-Schalter K1102 bis K(1101+n) umfasst, wobei jeder erste Gating-Schalter ein Eingangsende, ein Ausgangsende und ein Steuerende umfasst; wobei ein Drain des Feldeffekttransistors Q1101 mit dem Erdungsanschluss der Schaltung vom Typ NICHT-Gate verbunden ist, eine Quelle des Feldeffekttransistors Q1101 geerdet ist und ein Gate des Feldeffekttransistors Q1101 mit dem Ausgangsende jedes ersten Gating-Schalters verbunden ist; wobei das Eingangsende jedes ersten Gating-Schalters ein Signal empfängt, dessen Spannungswert konstant ist, und wobei sich die Spannungswerte der durch die Eingangsenden aller ersten Gating-Schalter empfangenen Signale voneinander unterscheiden; und wobei das Steuerende jedes ersten Gating-Schalters ein Signal empfängt, dessen Periode nT ist, und wobei innerhalb jeder Periode nT das Signal, dessen Periode nT ist, ein erstes Niveau innerhalb nur eines Zeitsegments, dessen Dauer T ist, darstellt und ein zweites Niveau innerhalb anderer Zeitsegmente darstellt, und wobei die Zeitsegmente, innerhalb derer die durch die Steuerenden aller Gating-Schalter empfangenen Signale das erste Niveau s darstellen, nicht zusammenfallen, wobei wenn das durch das Steuerende des ersten Gating-Schalters empfangene Signal das erste Niveau darstellt, das Eingangsende des ersten Gating-Schalters mit dem Ausgangsende des ersten Gating-Schalters verbunden ist; und wenn das durch das Steuerende des ersten Gating-Schalters empfangene Signal das zweite Niveau darstellt, das Eingangsende des ersten Gating-Schalters von dem Ausgangsende des ersten Gating-Schalters getrennt ist.
 
3. Abtasttakterzeugungsschaltung nach Anspruch 2, wobei es sich bei dem Feldeffekttransistor Q1101 um einen Sperrschicht-Feldeffekttransistor, JFET, einen verstärkten Metalloxid-Halbleiter-Feldeffekttransistor, MOSFET, oder einen Verarmungs-MOSFET handelt.
 
4. Abtasttakterzeugungsschaltung nach Anspruch 2, wobei die Schaltung mit variablem Widerstand (1) ferner einen Feldeffekttransistor Q(1102+n) umfasst, wobei ein Gate des Feldeffekttransistors Q(1102+n) mit der Leistungsversorgung verbunden ist, ein Drain des Feldeffekttransistors Q(1102+n) mit dem Drain des Feldeffekttransistors Q1101 verbunden ist und eine Quelle des Feldeffekttransistors Q(1102+n) mit der Quelle des Feldeffekttransistors Q1101 verbunden ist, wobei der Feldeffekttransistor Q(1102+n) und der Feldeffekttransistor Q1101 beide P-Kanal-Feldeffekttransistoren sind oder der Feldeffekttransistor Q(1102+n) und der Feldeffekttransistor Q1101 beide N-Kanal-Feldeffekttransistoren sind.
 
5. Abtasttakterzeugungsschaltung nach Anspruch 4, wobei es sich bei dem Feldeffekttransistor Q(1102+n) um einen JFET, einen verstärkten MOSFET oder einen Verarmungs-MOSFET handelt.
 
6. Abtasttakterzeugungsschaltung nach Anspruch 2, wobei die Schaltung mit variablem Widerstand (1) ferner einen Widerstand R(1103+n) umfasst, wobei ein Ende des Widerstands R(1103+n) mit dem Drain des Feldeffekttransistors Q1101 verbunden ist und das andere Ende des Widerstands R(1103+n) mit der Quelle des Feldeffekttransistors Q1101 verbunden ist.
 
7. Abtasttakterzeugungsschaltung nach Anspruch 2, wobei die Abtasttakterzeugungsschaltung ferner Niveaueinstellschaltungen (4) umfasst, die in einer Eins-zueins-Entsprechung zu den ersten Gating-Schaltern K1102 bis K(1101+n) stehen, wobei jede Niveaueinstellschaltung mit dem Eingangsende des ersten Gating-Schalters verbunden ist, welcher der Niveaueinstellschaltung entspricht; und
wobei jede Niveaueinstellschaltung dazu konfiguriert ist, ein Signal bereitzustellen, dessen Spannungswert konstant und auf das Eingangsende des ersten Gating-Schalters, welcher der Niveaueinstellschaltung entspricht, einstellbar ist, wobei sich die Spannungswerte der durch alle Niveaueinstellschaltungen (4) bereitgestellten Signale voneinander unterscheiden.
 
8. Abtasttakterzeugungsschaltung nach Anspruch 7, wobei jede Niveaueinstellschaltung (4) m Widerstände R41 bis R(40+m), m+1 zweite Gating-Schalter K(41+m) bis K(41+2m) und ein Register IR umfasst, wobei m≥2 und m eine ganze Zahl ist; wobei jeder zweite Gating-Schalter ein Eingangsende, ein Ausgangsende und ein Steuerende umfasst; wobei die m Widerstände R41 bis R(40+m) zwischen der Leistungsversorgung und der Erdung in Reihe geschaltet sind, und wobei jeder Knoten, der in Reihe geschaltet ist, mit dem Eingangsende des zweiten Gating-Schalters verbunden ist, und wobei sich die Eingangsenden der zweiten Gating-Schalter, die mit allen Knoten, welche in Reihe geschaltet sind, verbunden sind, voneinander unterscheiden; wobei das Ausgangsende jedes zweiten Gating-Schalters mit dem Eingangsende des ersten Gating-Schalters verbunden ist, welcher der Niveaueinstellschaltung entspricht; und wobei das Steuerende jedes zweiten Gating-Schalters mit dem Register IR verbunden ist.
 
9. Abtasttakterzeugungsschaltung nach Anspruch 1, wobei es sich bei der Schaltung vom Typ NICHT-Gate (2) um einen Phaseninverter, eine NICHT-UND-Gate-Schaltung oder eine NICHT-ODER-Gate-Schaltung handelt.
 
10. Abtasttakterzeugungsschaltung nach Anspruch 9, wobei der Phaseninverter einen Feldeffekttransistor Q211 und einen Feldeffekttransistor Q212 umfasst, wobei ein Gate des Feldeffekttransistors Q211 und ein Gate des Feldeffekttransistors Q212 beide Eingangsenden der Schaltung vom Typ NICHT-Gate sind; wobei ein Drain des Feldeffekttransistors Q211 und ein Drain des Feldeffekttransistors Q212 beide Ausgangsenden der Schaltung vom Typ NICHT-Gate sind; wobei eine Quelle des Feldeffekttransistors Q211 der Leistungsversorgungsanschluss der Schaltung vom Typ NICHT-Gate ist; und wobei eine Quelle des Feldeffekttransistors Q212 der Erdungsanschluss der Schaltung vom Typ NICHT-Gate ist, wobei
der Feldeffekttransistor Q211 ein verstärkter P-Kanal-Metalloxid-Halbleiter-Feldeffekttransistor, MOSFET, ist und der Feldeffekttransistor Q212 ein N-Kanal-MOSFET ist; oder wobei der Feldeffekttransistor Q211 ein N-Kanal-MOSFET ist und der Feldeffekttransistor Q212 ein P-Kanal-MOSFET ist.
 
11. Abtasttakterzeugungsschaltung nach einem der Ansprüche 1 bis 10, wobei das Niveau des Impulssignals und der Widerstandswert der Schaltung mit variablem Widerstand (1) nicht gleichzeitig geändert werden.
 
12. Analog-Digital-Wandler, ADC, wobei der ADC n ADC-Chips umfasst, und wobei der ADC ferner eine Abtasttakterzeugungsschaltung nach einem der Ansprüche 1 bis 11 und eine Mischeinrichtung umfasst, wobei die Abtasttakterzeugungsschaltung mit der Mischeinrichtung verbunden ist, und wobei die Mischeinrichtung mit den n ADC-Chips verbunden ist;
wobei die Mischeinrichtung dazu konfiguriert ist, n Kanäle von Abtastsignalen, deren Perioden nT sind, zu erzeugen, wobei innerhalb jeder Periode nT ein hohes Niveau eines i-ten Kanals von Abtastsignalen das gleiche ist wie ein hohes Niveau eines Ausgangssignals der Abtasttakterzeugungsschaltung innerhalb eines (i-1)-ten Zeitsegments, dessen Dauer T ist, und ein niedriges Niveau innerhalb anderer Zeitsegmente darstellt; und wobei ein i-ter ADC-Chip den i-ten Kanal von Abtastsignalen als Abtasttaktung verwendet.
 


Revendications

1. Circuit générateur d'horloge d'échantillonnage, dans lequel le circuit générateur d'horloge d'échantillonnage comprend un circuit à résistance variable (1), un circuit de type à porte NON (2) et un condensateur ;
dans lequel le circuit de type à porte NON (2) comprend une extrémité d'entrée, une extrémité de sortie, une borne d'alimentation électrique, et une borne de terre ; l'extrémité d'entrée du circuit de type à porte NON (2) reçoit un signal d'impulsion dont la période est T ; l'extrémité de sortie du circuit de type à porte NON (2) est connectée à une extrémité du condensateur ; l'autre extrémité du condensateur est mise à la terre ; la borne d'alimentation électrique du circuit de type à porte NON (2) est connectée à un bloc d'alimentation électrique ; la borne de terre du circuit de type à porte NON (2) est connectée à une extrémité du circuit à résistance variable (1) ; et l'autre extrémité du circuit à résistance variable (1) est mise à la terre ;
le circuit de type à porte NON (2) est conçu pour : lorsque le signal d'impulsion est à un état haut, fournir en sortie un état bas; et lorsque le signal d'impulsion est un état bas, fournir en sortie un état haut; et
le circuit à résistance variable (1) comprenant n commutateurs de portillonnage, est conçu pour changer une valeur de résistance à des intervalles de durée T entre n valeurs de résistance,
dans lequel la valeur de résistance est changée d'après une période de n T, et des valeurs de résistance après changements dans chaque période sont différentes les unes des autres, dans lequel n ≥ 2 et n est un nombre entier.
 
2. Circuit générateur d'horloge d'échantillonnage selon la revendication 1, dans lequel le circuit à résistance variable (1) comprend un transistor à effet de champ Q1101 et n premiers commutateurs de portillonnage K1102 à K(1101 + n), dans lequel chaque premier commutateur de portillonnage comprend une extrémité d'entrée, une extrémité de sortie, et une extrémité de commande ; un drain du transistor à effet de champ Q1101 est connecté à la borne de terre du circuit de type à porte NON, une source du transistor à effet de champ Q1101 est mise à la terre, et une porte du transistor à effet de champ Q1101 est connectée à l'extrémité de sortie de chaque premier commutateur de portillonnage ; l'extrémité d'entrée de chaque premier commutateur de portillonnage reçoit un signal dont une valeur de tension est constante, et les valeurs de tension des signaux reçus par les extrémités d'entrée de tous les premiers commutateurs de portillonnage sont différentes les unes des autres ; et l'extrémité de commande de chaque premier commutateur de portillonnage reçoit un signal dont la période est n T, et dans chaque période n T, le signal dont la période est n T est un premier état uniquement dans un segment de temps dont la durée est T et est un second état dans d'autres segments de temps, et des segments de temps dans lesquels les signaux reçus par les extrémités de commande de tous les commutateurs de portillonnage sont le premier état ne coïncident pas, dans lequel
lorsque le signal reçu par l'extrémité de commande du premier commutateur de portillonnage est le premier état, l'extrémité d'entrée du premier commutateur de portillonnage est connectée à l'extrémité de sortie du premier commutateur de portillonnage ; et lorsque le signal reçu par l'extrémité de commande du premier commutateur de portillonnage est le second état, l'extrémité d'entrée du premier commutateur de portillonnage est déconnectée de l'extrémité de sortie du premier commutateur de portillonnage.
 
3. Circuit générateur d'horloge d'échantillonnage selon la revendication 2, dans lequel le transistor à effet de champ Q1101 est un transistor à effet de champ à jonctions, JFET, un transistor à effet de champ à semi-conducteur à oxyde métallique, MOSFET, amélioré, ou un MOSFET à appauvrissement.
 
4. Circuit générateur d'horloge d'échantillonnage selon la revendication 2, dans lequel le circuit à résistance variable (1) comprend en outre un transistor à effet de champ Q(1102 + n), dans lequel une porte du transistor à effet de champ Q(1102 + n) est connectée au bloc d'alimentation électrique, un drain du transistor à effet de champ Q(1102 + n) est connecté au drain du transistor à effet de champ Q1101, et une source du transistor à effet de champ Q(1102 + n) est connectée à la source du transistor à effet de champ Q1101, dans lequel
le transistor à effet de champ Q(1102 + n) et le transistor à effet de champ Q1101 sont tous deux des transistors à effet de champ à canal P, ou le transistor à effet de champ Q(1102 + n) et le transistor à effet de champ Q1101 sont tous deux des transistors à effet de champ à canal N.
 
5. Circuit générateur d'horloge d'échantillonnage selon la revendication 4, dans lequel le transistor à effet de champ Q(1102 + n) est un JFET, un MOSFET amélioré ou un MOSFET à appauvrissement.
 
6. Circuit générateur d'horloge d'échantillonnage selon la revendication 2, dans lequel le circuit à résistance variable (1) comprend en outre un résistor R(1103 + n), dans lequel une extrémité du résistor R(1103 + n) est connectée au drain du transistor à effet de champ Q1101, et l'autre extrémité du résistor R(1103 + n) est connectée à la source du transistor à effet de champ Q1101.
 
7. Circuit générateur d'horloge d'échantillonnage selon la revendication 2, dans lequel le circuit générateur d'horloge d'échantillonnage comprend en outre des circuits d'ajustement d'état (4) qui sont dans une correspondance biunivoque avec les premiers commutateurs de portillonnage K1102 à K(1101 + n), dans lequel chaque circuit d'ajustement d'état est connecté à l'extrémité d'entrée du premier commutateur de portillonnage qui correspond au circuit d'ajustement d'état ; et
chaque circuit d'ajustement d'état est conçu pour fournir un signal dont la valeur de tension est constante et ajustable à l'extrémité d'entrée du premier commutateur de portillonnage qui correspond au circuit d'ajustement d'état, dans lequel les valeurs de tension des signaux fournis par tout les circuits d'ajustement d'état (4) sont différentes les unes des autres.
 
8. Circuit générateur d'horloge d'échantillonnage selon la revendication 7, dans lequel chaque circuit d'ajustement d'état (4) comprend m résistors R41 à R(40 + m), m + 1 seconds commutateurs de portillonnage K(41 + m) à K(41 + 2 m), et un registre IR, dans lequel m ≥ 2 et m est un nombre entier ; chaque second commutateur de portillonnage comprend une extrémité d'entrée, une extrémité de sortie et une extrémité de commande ; les m résistors R41 à R(40 + m) sont connectés en série entre le bloc d'alimentation électrique et la terre, et chaque nœud qui est connecté en série est connecté à l'extrémité d'entrée du second commutateur de portillonnage, et les extrémités d'entrée des seconds commutateurs de portillonnage qui sont connectées à tous les nœuds qui sont connectés en série sont différentes les unes des autres ; l'extrémité de sortie de chaque second commutateur de portillonnage est connectée à l'extrémité d'entrée du premier commutateur de portillonnage qui correspond au circuit d'ajustement d'état ; et l'extrémité de commande de chaque second commutateur de portillonnage est connectée au registre IR.
 
9. Circuit générateur d'horloge d'échantillonnage selon la revendication 1, dans lequel le circuit de type à porte NON (2) est un inverseur de phase, un circuit à porte NON-ET ou un circuit à porte NON-OU.
 
10. Circuit générateur d'horloge d'échantillonnage selon la revendication 9, dans lequel l'inverseur de phase comprend un transistor à effet de champ Q211 et un transistor à effet de champ Q212, dans lequel une porte du transistor à effet de champ Q211 et une porte du transistor à effet de champ Q212 sont toutes deux des extrémités d'entrée du circuit de type à porte NON ; un drain du transistor à effet de champ Q211 et un drain du transistor à effet de champ Q212 sont tous deux des extrémités de sortie du circuit de type à porte NON; une source du transistor à effet de champ Q211 est la borne d'alimentation électrique du circuit de type à porte NON; et une source du transistor à effet de champ Q212 est la borne de terre du circuit de type à porte NON, dans lequel
le transistor à effet de champ Q211 est un transistor à effet de champ à semi-conducteur à oxyde métallique, MOSFET, amélioré à canal P, et le transistor à effet de champ Q212 est un MOSFET à canal N ; ou le transistor à effet de champ Q211 est un MOSFET à canal N, et le transistor à effet de champ Q212 est un MOSFET à canal P.
 
11. Circuit générateur d'horloge d'échantillonnage selon l'une quelconque des revendications 1 à 10, dans lequel l'état du signal d'impulsion et la valeur de résistance du circuit à résistance variable (1) sont changés de façon non simultanée.
 
12. Convertisseur d'analogique en numérique, ADC, dans lequel l'ADC comprend n puces ADC, et l'ADC comprend en outre un circuit générateur d'horloge d'échantillonnage selon l'une quelconque des revendications 1 à 11 et un mélangeur, dans lequel le circuit générateur d'horloge d'échantillonnage est connecté au mélangeur, et le mélangeur est connecté aux n puces ADC ;
le mélangeur est conçu pour générer n canaux de signaux d'échantillonnage dont les périodes sont n T, dans lequel dans chaque période n T, un état haut d'un ième canal de signaux d'échantillonnage est le même qu'un état haut d'un signal de sortie du circuit générateur d'horloge d'échantillonnage dans un (i - 1)ième segment de temps dont la durée est T et est un état bas dans d'autres segments de temps ; et une ième puce ADC utilise le ième canal de signaux d'échantillonnage en tant qu'horloge d'échantillonnage.
 




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Cited references

REFERENCES CITED IN THE DESCRIPTION



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Patent documents cited in the description




Non-patent literature cited in the description