(19)
(11)EP 3 265 921 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
29.04.2020 Bulletin 2020/18

(21)Application number: 16710384.5

(22)Date of filing:  04.03.2016
(51)International Patent Classification (IPC): 
G06F 13/24(2006.01)
G06F 13/26(2006.01)
(86)International application number:
PCT/US2016/020942
(87)International publication number:
WO 2016/144777 (15.09.2016 Gazette  2016/37)

(54)

MICROCONTROLLER OR MICROPROCESSOR WITH DUAL MODE INTERRUPT

MIKROCONTROLLER ODER MIKROPROZESSOR MIT DOPPELMODUSUNTERBRECHUNG

MICROCONTRÔLEUR OU MICROPROCESSEUR AVEC DOUBLE MODE D'INTERRUPTION


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 06.03.2015 US 201562129481 P
03.03.2016 US 201615060553

(43)Date of publication of application:
10.01.2018 Bulletin 2018/02

(73)Proprietor: Microchip Technology Incorporated
Chandler, AZ 85224-6199 (US)

(72)Inventors:
  • CURTIS, Keith E.
    Gilbert, Arizona 85297 (US)
  • SENAPATI, Ashish
    Tempe, Arizona 85281 (US)
  • GARCIA, Anthony
    Maricopa, Arizona 85138 (US)
  • SARVEPALLI, Vijay
    Chandler, Arizona 85224 (US)
  • PULIPAKA, Prashanth
    Chandler, Arizona 85226 (US)
  • KILZER, Kevin
    Chandler, Arizona 85225 (US)
  • FORST, David
    Queen Creek, Arizona 85143 (US)
  • KENNEDY, Rob
    Chandler, Arizona 85249 (US)
  • CASTRO, Primo
    Chandler, Arizona 85249 (US)
  • BARTON, Aaron
    Chandler, Arizona 85224 (US)

(74)Representative: sgb europe 
Lechnerstraße 25a
82067 Ebenhausen
82067 Ebenhausen (DE)


(56)References cited: : 
EP-A1- 0 977 125
US-B1- 6 654 839
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description


    [0001] The present disclosure relates to microprocessors or microcontrollers.

    [0002] Microcontrollers are single chip systems on a chip comprising a central processing unit (CPU), memory, I/O interfaces and a plurality of different peripheral devices such as serial interfaces, analog-to-digital converters. PWM modulators, timers, etc. Generally, many applications do not require a lot of processing power. Thus to keep costs low, certain microcontrollers, such as 8-bit microcontrollers with a limited amount of program memory and data memory often are implemented without any type of external or internal interrupts or with a limited number of interrupts due to the fact that such interrupt logic requires significant real estate on a die. For example a baseline microcontroller family of a manufacturer may include devices that do not comprise any interrupt capability or only a single interrupt. A mid-range family may be designed to allow for a single interrupt and an associated interrupt controller that receives a plurality of interrupts and generates an output signal fed to the single interrupt input of the CPU. Both of these microcontroller types may comprise a CPU with single interrupt input wherein when asserted causes the program execution to finish a currently pending instruction and then branch to a defined address (interrupt vector), e.g. address 0004h. A higher end family of microcontrollers of the manufacturer may include devices with a CPU that has two interrupt inputs one being assigned a low priority and one being assigned a high priority as well as an interrupt controller for distributing interrupts from various sources to these two interrupt inputs of the CPU.

    [0003] The present application thus focuses on microcontrollers comprising a central processing unit that has a limited number of interrupts, e.g. a single or two interrupt inputs and associated interrupt controller with a limited interrupt functionality. In many applications this may still not be sufficient and a higher end device, for example a 16-bit or 32-bit microcontroller must be chosen due to the fact that the interrupt capabilities of the 8-bit microcontrollers are too limiting. Also, if such microcontrollers are intended to have an increased number of peripherals the central processing unit may not be able to support an associated interrupt function due to the limited interrupt functionality.

    [0004] US patent 6,654,839 discloses an interrupt controller, ASIC, and electronic equipment that makes it possible to branch directly to interrupt processing routines at a plurality of locations.

    [0005] Hence, there exists a need for a microcontroller with an improved or more flexible interrupt handling. This and other objects can be achieved by a microcontroller and method as defined in the independent claims. Further enhancements are characterized in the dependent claims.

    [0006] According to an embodiment, a microcontroller may comprise a central processing unit comprising at least one interrupt input, an interrupt controller configured to provide at least one interrupt signal to the at least one interrupt input of the central processing unit, a plurality of peripherals coupled with the central processing unit and the interrupt controller, and a mode register comprising at least one bit controlling an operating mode of the microcontroller, wherein the microcontroller is configured to operate in a first and in a second mode, wherein in the first operating mode upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the central processing unit and the peripheral sets an associated interrupt flag, wherein the interrupt causes the central processing unit to branch to a predefined interrupt address associated with the interrupt input, wherein in the second operating mode upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the central processing unit and the central processing unit receives additional interrupt information from the peripheral that generated the interrupt, wherein the additional interrupt information is used to generate a vector address.

    [0007] According to a further embodiment, in the second operating mode, after receiving an interrupt, the central processing unit can be configured to perform a context save before entering a service routine and wherein a register of the central processing unit receives data configured to identify an interrupt source after said context save. According to a further embodiment, the register can be a working register of the arithmetic logic unit. According to a further embodiment, said additional information provided by a peripheral that generated the interrupt can be used to shift a constant value and wherein the shifted constant value is moved into the register. According to a further embodiment, said additional information can be an interrupt number which is directly stored in a working register of the CPU. According to a further embodiment, in the second operating mode, a base register can be provided that stores a base address and an offset address depending on an interrupt source is forwarded to the central processing unit, wherein an interrupt vector is generated by adding the vector address to the base address stored in the base register. According to a further embodiment, in the second mode, the microcontroller can be programmed to provide for an interrupt service routine that evaluates the content of the working register to branch to a respective service routine associated with an interrupt source that generated the interrupt. According to a further embodiment, in the first mode, the microcontroller can be programmed to provide for an interrupt service routine that polls an interrupt flag in a special function register to determine an interrupt source that generated the interrupt. According to a further embodiment, the central processing unit may comprise only a single interrupt input. According to a further embodiment, the central processing unit may comprise only a first and a second interrupt input, wherein the first interrupt input has a higher priority than the second interrupt input. According to a further embodiment, when a higher priority interrupt interrupts a lower priority service routine, the higher priority interrupt can be configured to clear a lower priority interrupt and an associated service routine returns directly to a main code without returning through the low priority service routine. According to a further embodiment, when a higher priority interrupt interrupts a lower priority service routine, the higher priority interrupt can be configured to return directly to the lower priority interrupt service routine without returning to a main code. According to a further embodiment, interrupt controller may comprise controllable logic to enable interrupts received from the peripherals.

    [0008] According to another embodiment, a method for providing interrupt functionality within a microcontroller comprising a central processing unit comprising at least one interrupt input and an interrupt controller configured to provide at least one interrupt signal to the at least one interrupt input of the central processing unit, may comprise the steps of: setting a first or a second operating mode; receiving an interrupt by the interrupt controller; and when operating in the first operating mode, forwarding by the interrupt controller an interrupt signal to the central processing unit and setting an associated interrupt flag, wherein the interrupt causes the central processing unit to branch to a predefined interrupt address associated with the interrupt input; and when operating in the second operating mode, forwarding by the interrupt controller an interrupt signal to the central processing unit and receiving by the central processing unit additional interrupt information from the peripheral that generated the interrupt, wherein the additional interrupt information is used to generate a vector address.

    [0009] According to a further embodiment of the method, in the second operating mode, after receiving an interrupt, the method may perform a context save before entering a service routine and receiving additional information by the central processing unit configured to identify an interrupt source after said context save and storing said additional information or data derived from said additional information in a register. According to a further embodiment of the method said additional information can be an interrupt number which is directly stored in a working register of the CPU. According to a further embodiment of the method, the method may further comprise the step of calculating an address after entering the service routine using said data and branching to said address to service said interrupt. According to a further embodiment of the method said data may be used to shift a constant value and wherein the shifted constant value is moved into the register. According to a further embodiment of the method, the method may further comprise the step of using said shifted value as an offset address to branch to an address to service said interrupt. According to a further embodiment of the method, in the second operating mode a base register may be provided that stores a base address and an offset address depending on an interrupt source is forwarded to the central processing unit, and generating an interrupt vector by adding the vector address to the base address stored in the base register. According to a further embodiment of the method, in the second operating mode, an interrupt service routine may evaluate the content of the working register to branch to a respective address providing instructions associated with an interrupt source that generated the interrupt. According to a further embodiment of the method, in the first mode, an interrupt service routine may poll an interrupt flag in a special function register to determine an interrupt source that generated the interrupt. According to a further embodiment of the method, the central processing unit may comprise only a single interrupt input. According to a further embodiment of the method, the central processing unit may comprise only a first and a second interrupt input, wherein the first interrupt input has a higher priority than the second interrupt input. According to a further embodiment of the method, when a higher priority interrupt interrupts a lower priority service routine, the higher priority interrupt may be configured to clear a lower priority interrupt and an associated service routine may return directly to a main code without returning through the low priority service routine. According to a further embodiment of the method, when a higher priority interrupt interrupts a lower priority service routine, the higher priority interrupt may be configured to return directly to the lower priority interrupt service routine without returning to a main code.

    [0010] According to yet another embodiment, a microcontroller may comprise a central processing unit comprising at least one interrupt input and a register coupled with an arithmetic logic unit; an interrupt controller configured to provide at least one interrupt signal to the at least one interrupt input of the central processing unit; a plurality of peripherals coupled with the central processing unit and the interrupt controller; wherein upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the central processing unit and the central processing unit receives additional interrupt information from the peripheral that generated the interrupt, wherein the additional interrupt information or data derived from the additional interrupt information is stored in said register.

    [0011] According to a further embodiment of the above microcontroller, after receiving an interrupt, the central processing unit may be configured to perform a context save before entering a service routine and the register may receive the additional interrupt information after said context save. According to a further embodiment of the above microcontroller, said additional information may be used to shift a constant value and wherein the shifted constant value is moved into the register. According to a further embodiment of the above microcontroller, said additional information can be an interrupt number which is directly stored in a working register of the CPU. According to a further embodiment of the above microcontroller, the microcontroller can be programmed to provide for an interrupt service routine that evaluates the content of the working register to branch to a respective service routine associated with an interrupt source that generated the interrupt.

    Fig. 1 shows a block diagram of a microcontroller according to an embodiment;

    Fig. 2 shows an embodiment of interrupt controller logic;

    Fig. 3 shows an embodiment of how a vector address can be generated;

    Fig. 4 shows an embodiment of how a vector address can be moved to a working register;

    Fig. 5 shows an embodiment of a microcontroller in which additional interrupt information is moved to a register.

    Fig. 6 shows a state diagram of a system using high and low priority interrupts;

    Fig. 7 shows another embodiment of a microcontroller in which additional interrupt information is moved to a register.

    Fig. 8 shows another embodiment of interrupt controller logic.



    [0012] According to various embodiments, a vectored interrupt system can be created that is compatible with an existing design of microcontrollers. The features discussed below are not limited to 8-bit microcontrollers but may also apply to 16-bit or 32-bit microcontrollers if such devices comprise an insufficient interrupt control architecture. According to various embodiments, an existing interrupt handling is maintained and a second mode of operation is provided. In the first operating mode, such a microcontroller having a single interrupt input may operate as originally designed, e.g. branch to the single pre-defined interrupt vector, e.g., address 0004h. In a second operating mode, the microcontroller may use a plurality of interrupt vectors associated with a single interrupt input.

    [0013] Present existing designs of non-vectored microcontroller systems may be insufficient for an expanded number of peripherals which may be made possible by new core architecture designs. A vectored interrupt system may allow for integrating such peripherals with respect to individual interrupt functionality.

    [0014] In particular, microcontrollers manufactured by the Assignee of the present application, such as microcontrollers from the PIC10/12/16 family all use a single interrupt vector at location 0004x in the program memory. The more advanced microcontrollers from the PIC18 family use a dual priority vectored system.

    [0015] Assignee's PIC16 family of microcontrollers does not provide for vectors. The more advanced PIC 18 family does not have a software solution and does not have supervisory interrupt control. Moreover, the more advanced PIC18 family as well as the PIC 16 family need to trim latency in particular due to the sheer number of interrupt sources on some of the microcontrollers. The PIC 16/18 family both have blocks to boot loader implementations.

    [0016] The existing conventional PIC 18 vectored interrupt system is expanded according to various embodiments with a base address register that allows the movement of the vector table to support boot loaders.

    [0017] According to an embodiment, the latency time can be trimmed by removing return to main instructions, e.g., from a High interrupt transitioning to another pending High interrupt, a Low interrupt transitioning to another pending Low interrupt, and a High interrupt transitioning to a Low interrupt. In other words, a return from interrupt instruction can be removed and the system jumps directly to the next pending interrupt routine.

    [0018] Context for both High and Low priority interrupts can be made accessible for RTOS support.

    [0019] According to other embodiments, for systems that use high priority timer interrupts to watch dog low priority communication peripherals, the ability to clear interrupted low priority interrupts without using the global interrupt enable bit GIE is provided. According to various embodiments, a POP instruction may be added to the core if not already present to remove a respective return vector from the Low priority interrupt.

    [0020] According to yet another embodiment, a context save for both Low and High priority interrupts are visible through context registers. Register space is conserved through the context control register that allow toggling between low and high access. The improved microcontrollers have the ability to clear low context on command to support watch dog functions.

    [0021] The solution according to some embodiments, are backward compatible with legacy mode option to interrupt to location 0004x. The Mode is expanded by the addition of function that loads interrupt number into W register prior to branch to 0004x

    [0022] According to some embodiments, such a dual mode vector interrupt may be implemented with 2 levels of priority that employs both a straight vector table and a vector number for software based systems.

    [0023] Fig. 1 shows a block diagram of a microcontroller 100 with a CPU 110 having a single interrupt input. The CPU 110 is coupled with a plurality of peripherals 130a..n via a system bus 160. The CPU 110 can be designed according to the Harvard architecture as shown having a separate data memory 140 and program memory 150. However, the architecture may also use the von Neumann architecture with a unified memory space.

    [0024] Data memory 140 may be accessible through the system bus and program memory 150 may have its own bus. However, other designs may be chosen. Some of the peripherals 130a..n or all of them may generate an interrupt signal which is fed to an interrupt controller 120. The interrupt controller may generate a single interrupt signal which is fed to the respective input of the CPU 110.

    [0025] Fig. 2 shows a block diagram of a possible implementation for an interrupt controller 120 operating in the first mode. A plurality of special function registers may be provided which allows to individually enable or disable one of a plurality of interrupts and store associated interrupt flags which may be generated by various peripherals of the microcontroller as shown on the left side in Fig. 2. The right side of Fig. 2 shows a further interrupt control register bit that allows to generally enable or disable all interrupts, e.g. via the global interrupt enable bit GIE. The interrupt control register may comprise further bits to control system interrupts as shown in the center of Fig. 2. A separate enable/disable control for all peripheral interrupts is handled by the PEIE bit. An external interrupt is controlled by the enable bit INTE and associated flag INTF. Furthermore, an external port change sensing control is provided by the RB port change interrupt enable bit and associated flag RBIF. This functionality may be expanded to other ports according to other embodiments. Finally the timer 0 overflow interrupt may be handled on this level. In this embodiment, INTE/INTF, RBIE/RBIF, and T0IE/T0IF are "system interrupts", however, according to other embodiments, all interrupts may treated as peripheral interrupts without a specific PEIE enablement bit. These interrupt architectures allow for a plurality of interrupts using a single interrupt input at the CPU. To accomplish this, the interrupt routine must query the respective flags to distinguish between the various sources. For the CPU every interrupt looks the same because only a single interrupt input is provided. However, each interrupt source may set an associated flag when they generate an interrupt. Thus, the interrupt handler software must check these flags in the interrupt handling routine to determine who asserted the interrupt. Furthermore, one the interrupt has been handled, the service routine generally resets the respective flag. Other logic may be used to allow handling of multiple interrupt sources with a single interrupt input. Fig. 2 shows merely one possible solution as it is implemented in many mid-range microcontrollers manufactured by the assignee of the present application.

    [0026] A vectored system is shown in Figure 3. Each interrupt provides a different vector and the source of the interrupt is added to a base register to select the appropriate interrupt vector. Thus, contrary to the interrupt handling described above where only a single interrupt vector, e.g. vector 0004h is generated, such a system requires that additional information, e.g., a vector offset, is generated when the interrupt signal is generated. While still using only a single interrupt input at the CPU, the CPU would now branch to different interrupt vectors depending on the additional information provided to the CPU. Different techniques using such additional information to accomplish branching without polling any flags will be explained below in more detail. A CPU can either directly generate a respective vector that replaces the fixed single interrupt vector or use the fixed single interrupt vector and provide a software branching with or without hardware assistance. However, in this second operating mode, there is no polling of interrupt flags necessary which can reduce software overhead significantly.

    [0027] A mode control register 170 can be provided that allows the interrupt controller and CPU to operate in a first mode (compatibility mode) in which only a single interrupt signal is generated and the software must poll the interrupt flags as shown in Fig. 1. According to various embodiments, a second mode is now provided which forwards the interrupt information through additional data lines 180 as shown in Fig. 1. The interrupt information can be for example the vector offset or the actual interrupt number or any other information that allows for implementation of an interrupt vector system. The interrupt information, such as for example the interrupt number can be provided by the peripheral 130a..n. Thus, for example as shown in Fig. 1, each coupling between a peripheral 130a..n and the interrupt controller 120 may include additional lines that provide for the interrupt information such as the interrupt number. Alternatively, such information can be forwarded through the system bus 160 to the interrupt controller 120 or directly to the CPU 110. In one embodiment, a vector offset is automatically added to the single fixed interrupt vector address. Thus, the system has different entry points for each interrupt. The offset may be set such that enough instruction can be placed between two adjacent interrupt numbers to branch to associated service routines. Alternatively, the interrupt information is directly loaded into a register, e.g. a special function register or the working register of the arithmetic logic unit. This solution, allows to use this data in a software branching performed immediately after the service routine at the fixed interrupt vector address is entered as will be explained in more detail below.

    [0028] Figure 4 shows the second mode according to one embodiment in which the general interrupt vector is in the traditional location, e.g. at address 0004h, but the interrupt number is transferred into a working register W of the CPU after context save to provide a backward compatible solution, plus the ability to build a software based solution. The context save is only required to be prior to the additional information transfer if the additional information such as the interrupt number is transferred into a register that carries information used by other routines, such as a working register. The working register will be overwritten and therefore it is amongst other special function registers part of the context that must be saved when entering an interrupt service routine. Thus, after entry into the interrupt service routine, the working register includes the source of the interrupt which allows the following service routine to branch to the correct service instructions for that specific source. This could be accomplished by a vector that is calculated from the interrupt number or by simply querying the working register and branching to the respective routine. This specific solution of a vectored interrupt system has the benefit of being compatible with the existing interrupt system of microcontrollers manufactured by the Assignee. Alternatively, this information could be used later in a common interrupt service routine that first executes instructions common to all assigned interrupts and then branches off to individual routines. Other software solutions are possible using the information stored in the register.

    [0029] Figure 5 shows a microcontroller with two interrupt inputs 125a and 125b. The first input 125a may be assigned a high priority and the second input 125b may be assigned a low priority. Thus, the high priority interrupt at input 125a is capable of interrupting a pending low priority interrupt routine whereas a low priority interrupt at input 125b cannot interrupt a pending high priority interrupt routine. The system also has the ability to stay in interrupt if there are pending interrupts of the same priority or higher. According to various embodiments, such a system can be enhanced in the same way as described above by allowing each interrupt input to also receive additional information, e.g. an interrupt number, through line(s) 180 when operating in the second mode. Hence, the enhancement described above is not limited to a system with a CPU having a single interrupt input but can be used with a CPU with more than one interrupt wherein each interrupt or at least one of them is enhanced as described above.

    [0030] According to one embodiment, the enhancement may further be used in a single interrupt mode which only uses the second mode as described above. This embodiment allows for a reduced hardware solution. According to this embodiment, the additional information is directly loaded into a register of the CPU, preferably a working register of the ALU. This solution provides for the flexibility of a vectored interrupt system without the requirement of hardware that must decode the information and automatically set the respective interrupt vector.

    [0031] The state diagram in Fig. 6 shows the various transitions that are possible in such a two-priority system. Such a system may also have the ability of a higher priority interrupt to clear a lower priority interrupt and return directly to the main code without returning through the low priority.

    [0032] Fig. 5 indicates that the additional information is loaded directly into the working register 115 of the arithmetic logic unit (ALU) within the CPU. Such a transfer can be made directly after a context safe has been made which saves the content of the working register according to one embodiment. A context safe automatically transfers the content of certain registers onto a stack or into shadow registers without software overhead. According to other embodiments, the transfer into a different register, e.g. a dedicated register that is not used otherwise, can be made in parallel with the context safe. Therefore, the additional information does not need to be transferred into the working register but could also be transferred into another dedicated special function register according to other implementations. However, the use of a working register is beneficial as such a register can be directly used to manipulate an address. The same accounts for any other CPU register and therefore depends on the CPU architecture.

    [0033] Fig. 7 shows yet another embodiment of a single operating mode or an operating mode with two modes. Here the additional information such as the interrupt number controls a shift register 185 which is, for example, preset with 0001h or 0002h or any other suitable offset number, the shifted result is then directly moved to the working register. This solution provides an offset value that can be used directly to access a jump table without the need to execute further address calculation instructions within the interrupt service routine. As shown in Fig. 7, only a single interrupt input Int 0 is provided. However, this design can also be applied to a CPU with more than one interrupt input.

    [0034] According to other implementations of the two operating modes, as mentioned above, the vector does not need to be calculated by software within the interrupt service routine. While such a solution provides for backward compatibility, other architectures might allow a hardware calculation of the vector that is directly applied when the interrupt is received thereby allowing to directly jump to various vector addresses depending on the provided vector address.

    [0035] The system is designed to work within 8-bit architecture, in particular those, designed by the Assignee of the present application. However, the proposed implementations may also apply to other 8-bit systems as well as 16-bit or 32-bit systems that use corresponding interrupt logic.


    Claims

    1. A microcontroller comprising:

    a central processing unit (110) comprising at least one interrupt input (125);

    an interrupt controller (120) configured to provide at least one interrupt signal to the at least one interrupt input (125) of the central processing unit (110);

    a plurality of peripherals (130) coupled with the central processing unit (110) and the interrupt controller (120);

    a mode control register (170) comprising at least one bit controlling an operating mode of the microcontroller (100), wherein the microcontroller (100) is configured to operate in a first and in a second mode, wherein in the first operating mode upon assertion of an interrupt by a peripheral (130) of the microcontroller (100), the interrupt controller (120) forwards an interrupt signal to the central processing unit (110) and the peripheral (130) sets an associated interrupt flag;

    wherein in the second operating mode upon assertion of an interrupt by a peripheral (130) of the microcontroller (100), the interrupt controller (120) forwards an interrupt signal to the central processing unit (110) and the central processing unit (110) receives additional interrupt information from the peripheral (130) that generated the interrupt, and

    wherein in either operating mode, the interrupt causes the central processing unit (110) to directly branch to a predefined interrupt address associated with the interrupt input (125 characterized in that in the second mode of operation the additional interrupt information is directly stored in a register (115) of the central processing unit (110). .


     
    2. A method for providing interrupt functionality within a microcontroller (100) comprising a plurality of peripherals (130) and a central processing unit (110) comprising at least one interrupt input (125) and an interrupt controller (120) configured to provide at least one interrupt signal to the at least one interrupt input (125) of the central processing unit (110), the method comprising:

    setting a first or a second operating mode;

    receiving an interrupt by the interrupt controller (120) from a peripheral (130) of the microcontroller (100); and

    when operating in the first operating mode, forwarding by the interrupt controller (120) an interrupt signal to the central processing unit (110) and setting an associated interrupt flag by the peripheral (130);

    when operating in the second operating mode, forwarding by the interrupt controller (120) an interrupt signal to the central processing unit (110) and storing additional interrupt information received from the peripheral (130) that generated the interrupt directly into a register of the CPU (110);

    and

    after receipt of the interrupt by the central processing unit (110), directly branching to a predefined interrupt address associated with the interrupt input (125).


     
    3. The microcontroller according to claim 1 or the method according to claim 2, wherein in the second operating mode, after receiving an interrupt, the central processing unit (110) is configured to perform a context save before entering a service routine and wherein the register (115) of the central processing unit (110) receives data configured to identify an interrupt source after said context save.
     
    4. The microcontroller or method according to one of the preceding claims, wherein the register (115) is a working register of an arithmetic logic unit of the central processing unit (110).
     
    5. The microcontroller or method according to one of the preceding claims, wherein said additional interrupt information provided by a peripheral (130) that generated the interrupt is used to shift a constant value and wherein the shifted constant value is moved into the register (115).
     
    6. The microcontroller or method according to one of the preceding claims, wherein said additional interrupt information is an interrupt number which is directly stored in a working register (115) of the CPU (110).
     
    7. The microcontroller or method according to one of the preceding claims, wherein in the second mode, the microcontroller (100) is programmed to provide for an interrupt service routine that evaluates the content of a working register (115) to branch to a respective service routine associated with an interrupt source that generated the interrupt.
     
    8. The microcontroller or method according to one of the preceding claims, wherein in the first mode, the microcontroller (100) is programmed to provide for an interrupt service routine that polls an interrupt flag in a special function register associated with the peripheral (130) that caused the interrupt to determine an interrupt source.
     
    9. The microcontroller or method according to one of the preceding claims, wherein the central processing unit (100) comprises only a single interrupt input (125).
     
    10. The microcontroller or method according to one of the preceding claims, wherein the central processing unit (110) comprises only a first and a second interrupt input (125a, 125b), wherein the first interrupt input (125a) has a higher priority than the second interrupt input (125b).
     
    11. The microcontroller or method according to claim 10, wherein when a higher priority interrupt interrupts a lower priority service routine, the higher priority interrupt is configured to clear a lower priority interrupt and an associated service routine returns directly to a main code without returning through the low priority service routine.
     
    12. The microcontroller or method according to claim 10, wherein when a higher priority interrupt interrupts a lower priority service routine, the higher priority interrupt is configured to return directly to the lower priority interrupt service routine without returning to a main code.
     
    13. The microcontroller or method according to one of the preceding claims, wherein interrupt controller comprises controllable logic to enable interrupts received from the peripherals.
     


    Ansprüche

    1. Mikrocontroller, der aufweist:

    eine zentrale Prozessoreinheit (110) mit zumindest einem Interrupt-Eingang (125);

    eine Interrupt-Steuerung (120), die konfiguriert ist, um zumindest ein Interrupt-Signal an den zumindest einen Interrupt-Eingang (125) der zentralen Prozessoreinheit (110) bereitzustellen;

    eine Vielzahl von Peripheriegeräten (130), die mit der zentralen Prozessoreinheit (110) und der Interrupt-Steuerung (120) gekoppelt sind;

    ein Modussteuerregister (170), das zumindest ein Bit aufweist, das einen Betriebsmodus des Mikrocontrollers (100) steuert, wobei der Mikrocontroller (100) so konfiguriert ist, dass er in einem ersten und in einem zweiten Modus arbeitet, wobei in dem ersten Betriebsmodus die Interrupt-Steuerung (120) bei Aktivierung eines Interrupts durch ein Peripheriegerät (130) des Mikrocontrollers (100) ein Interrupt-Signal an die zentrale Prozessoreinheit (110) weiterleitet und das Peripheriegerät (130) ein zugeordnetes Interrupt-Flag setzt;

    wobei in dem zweiten Betriebsmodus die Interrupt-Steuerung (120) bei Aktivierung eines Interrupts durch ein Peripheriegerät (130) des Mikrocontrollers (100) ein Interrupt-Signal an die zentrale Prozessoreinheit (110) weiterleitet und die zentrale Prozessoreinheit (110) zusätzliche Interrupt-Informationen von dem Peripheriegerät (130) empfängt, das den Interrupt erzeugt hat, und

    wobei in jedem Betriebsmodus der Interrupt die zentrale Prozessoreinheit (110) veranlasst, direkt zu einer vordefinierten Interrupt-Adresse zu verzweigen, die dem Interrupt-Eingang (125) zugeordnet ist, dadurch gekennzeichnet, dass in dem zweiten Betriebsmodus die zusätzlichen Interrupt-Informationen direkt in ein Register (115) der zentralen Prozessoreinheit (110) gespeichert werden.


     
    2. Verfahren zum Bereitstellen einer Interrupt-Funktionalität in einem Mikrocontroller (100), der eine Vielzahl von Peripheriegeräten (130) und eine zentrale Prozessoreinheit (110) aufweist, die zumindest einen Interrupt-Eingang (125) und einen Interrupt-Controller (120) aufweist, der konfiguriert ist, um zumindest ein Interrupt-Signal an den zumindest einen Interrupt-Eingang (125) der zentralen Prozessoreinheit (110) bereitzustellen, wobei das Verfahren aufweist:

    Einstellen eines ersten oder eines zweiten Betriebsmodus;

    Empfangen eines Interrupts von einem Peripheriegerät (130) des Mikrocontrollers (100) durch die Interrupt-Steuerung (120); und

    wenn in dem ersten Betriebsmodus gearbeitet wird, Weiterleiten eines Interrupt-Signals durch die Interrupt-Steuerung (120) an die zentrale Prozessoreinheit (110) und Setzen eines zugehörigen Interrupt-Flags durch das Peripheriegerät (130);

    wenn in dem zweiten Betriebsmodus gearbeitet wird, Weiterleiten eines Interrupt-Signals durch die Interrupt-Steuerung (120) an die zentrale Prozessoreinheit (110) und Speichern zusätzlicher Interrupt-Informationen, die von dem Peripheriegerät (130) empfangen wurden, das den Interrupt direkt in ein Register der CPU (110) erzeugt hat;

    und

    nach Empfang des Interrupts durch die zentrale Prozessoreinheit (110), direktes Verzweigen zu einer vordefinierten Interrupt-Adresse, die dem Interrupt-Eingang (125) zugeordnet ist.


     
    3. Mikrocontroller gemäß Anspruch 1 oder Verfahren gemäß Anspruch 2, wobei in dem zweiten Betriebsmodus die zentrale Prozessoreinheit (110) nach Empfang eines Interrupts konfiguriert ist, eine Sicherung des Kontexts durchzuführen, bevor sie in eine Serviceroutine eintritt, und wobei das Register (115) der zentralen Prozessoreinheit (110) Daten empfängt, die konfiguriert sind, um nach dem Sichern des Kontexts eine Interrupt-Quelle zu identifizieren.
     
    4. Mikrocontroller oder Verfahren gemäß einem der vorhergehenden Ansprüche, wobei das Register (115) ein Arbeitsregister einer arithmetischen Logikeinheit der zentralen Prozessoreinheit (110) ist.
     
    5. Mikrocontroller oder Verfahren gemäß einem der vorhergehenden Ansprüche, wobei die zusätzliche Interrupt-Information, die von einem Peripheriegerät (130) bereitgestellt wird, das den Interrupt erzeugt hat, verwendet wird, um einen konstanten Wert zu verschieben, und wobei der verschobene konstante Wert in das Register (115) übertragen wird.
     
    6. Mikrocontroller oder Verfahren gemäß einem der vorhergehenden Ansprüche, wobei die zusätzliche Interrupt-Information eine Interrupt-Nummer ist, die direkt in einem Arbeitsregister (115) der CPU (110) gespeichert ist.
     
    7. Mikrocontroller oder Verfahren gemäß einem der vorhergehenden Ansprüche, wobei der Mikrocontroller (100) im zweiten Modus so programmiert ist, dass er eine Interrupt-Serviceroutine bereitstellt, die den Inhalt eines Arbeitsregisters (115) auswertet, um zu einer entsprechenden Serviceroutine zu verzweigen, die einer Interrupt-Quelle zugeordnet ist, die den Interrupt erzeugt hat.
     
    8. Mikrocontroller oder Verfahren gemäß einem der vorhergehenden Ansprüche, wobei der Mikrocontroller (100) im ersten Modus so programmiert ist, dass er eine Interrupt-Serviceroutine bereitstellt, die ein Interrupt-Flag in einem speziellen Funktionsregister abfragt, das dem Peripheriegerät (130) zugeordnet ist, das den Interrupt veranlasst hat, um eine Interrupt-Quelle zu bestimmen.
     
    9. Mikrocontroller oder Verfahren gemäß einem der vorhergehenden Ansprüche, wobei die zentrale Prozessoreinheit (100) nur einen einzelnen Interrupt-Eingang (125) aufweist.
     
    10. Mikrocontroller oder Verfahren gemäß einem der vorhergehenden Ansprüche, wobei die zentrale Prozessoreinheit (110) nur einen ersten und einen zweiten Interrupt-Eingang (125a, 125b) aufweist, wobei der erste Interrupt-Eingang (125a) eine höhere Priorität aufweist als der zweite Interrupt-Eingang (125b).
     
    11. Mikrocontroller oder Verfahren gemäß Anspruch 10, wobei, wenn ein Interrupt mit höherer Priorität eine Serviceroutine mit niedrigerer Priorität unterbricht, der Interrupt mit höherer Priorität konfiguriert ist, um einen Interrupt mit niedrigerer Priorität zu löschen, und eine zugeordnete Serviceroutine direkt zu einem Hauptcode zurückkehrt, ohne durch die Serviceroutine mit niedriger Priorität zurückzukehren.
     
    12. Mikrocontroller oder Verfahren gemäß Anspruch 10, wobei, wenn ein Interrupt mit höherer Priorität eine Serviceroutine mit niedrigerer Priorität unterbricht, der Interrupt mit höherer Priorität so konfiguriert ist, dass er direkt zu der Interrupt-Serviceroutine mit niedrigerer Priorität zurückkehrt, ohne zu einem Hauptcode zurückzukehren.
     
    13. Mikrocontroller oder Verfahren gemäß einem der vorhergehenden Ansprüche, wobei der Interrupt-Controller eine steuerbare Logik aufweist, um von den Peripheriegeräten empfangene Interrupts zu ermöglichen.
     


    Revendications

    1. Microcontrôleur comprenant :

    une unité centrale de traitement (110) comprenant au moins une entrée d'interruption (125) ;

    un contrôleur d'interruption (120) configuré de manière à fournir au moins un signal d'interruption à ladite au moins une entrée d'interruption (125) de l'unité centrale de traitement (110) ;

    une pluralité de périphériques (130) couplés à l'unité centrale de traitement (110) et au contrôleur d'interruptions (120) ;

    un registre de commande de mode (170) comprenant au moins un bit commandant un mode de fonctionnement du microcontrôleur (100), dans lequel le microcontrôleur (100) est configuré de manière à fonctionner dans un premier mode et dans un second mode, dans lequel, dans le premier mode de fonctionnement, lors de l'affirmation d'une interruption par un périphérique (130) du microcontrôleur (100), le contrôleur d'interruption (120) achemine un signal d'interruption vers l'unité centrale de traitement (110) et le périphérique (130) définit un drapeau d'interruption associé ;

    dans lequel, dans le second mode de fonctionnement, suite à l'affirmation d'une interruption par un périphérique (130) du microcontrôleur (100), le contrôleur d'interruption (120) achemine un signal d'interruption vers l'unité centrale de traitement (110), et l'unité centrale de traitement (110) reçoit des informations d'interruption supplémentaires en provenance du périphérique (130) ayant généré l'interruption ; et

    dans lequel, dans l'un ou l'autre des modes de fonctionnement, l'interruption amène l'unité centrale de traitement (110) à effectuer un branchement directement vers une adresse d'interruption prédéfinie associée à l'entrée d'interruption (125), caractérisé en ce que, dans le second mode de fonctionnement, les informations d'interruption supplémentaires sont directement stockées dans un registre (115) de l'unité centrale de traitement (110).


     
    2. Procédé de fourniture d'une fonctionnalité d'interruption dans un microcontrôleur (100) comprenant une pluralité de périphériques (130) et une unité centrale de traitement (110) comprenant au moins une entrée d'interruption (125) et un contrôleur d'interruption (120) configuré de manière à fournir au moins un signal d'interruption à ladite au moins une entrée d'interruption (125) de l'unité centrale de traitement (110), le procédé comprenant les étapes ci-dessous consistant à :

    définir un premier mode de fonctionnement ou un second mode de fonctionnement ;

    recevoir une interruption, par le biais du contrôleur d'interruption (120), en provenance d'un périphérique (130) du microcontrôleur (100) ; et

    lors d'un fonctionnement dans le premier mode de fonctionnement, acheminer, par le biais du contrôleur d'interruption (120), un signal d'interruption vers l'unité centrale de traitement (110), et définir un drapeau d'interruption associé, par le biais du périphérique (130) ;

    lors d'un fonctionnement dans le second mode de fonctionnement, acheminer, par le biais du contrôleur d'interruption (120), un signal d'interruption vers l'unité centrale de traitement (110), et stocker des informations d'interruption supplémentaires reçues en provenance du périphérique (130) ayant généré l'interruption, directement dans un registre de l'unité centrale de traitement, CPU, (110) ; et

    suite à la réception de l'interruption par l'unité centrale de traitement (110), effectuer un branchement directement vers une adresse d'interruption prédéfinie associée à l'entrée d'interruption (125).


     
    3. Microcontrôleur selon la revendication 1 ou procédé selon la revendication 2, dans lequel, dans le second mode de fonctionnement, suite à la réception d'une interruption, l'unité centrale de traitement (110) est configurée de manière à mettre en Ĺ“uvre une sauvegarde de contexte avant d'entrer dans une routine de service, et dans lequel le registre (115) de l'unité centrale de traitement (110) reçoit des données configurées de manière à identifier une source d'interruption après ladite sauvegarde de contexte.
     
    4. Microcontrôleur ou procédé selon l'une quelconque des revendications précédentes, dans lequel le registre (115) est un registre de travail d'une unité arithmétique et logique de l'unité centrale de traitement (110).
     
    5. Microcontrôleur ou procédé selon l'une quelconque des revendications précédentes, dans lequel lesdites informations d'interruption supplémentaires fournies par un périphérique (130) ayant généré l'interruption sont utilisées pour décaler une valeur constante, et dans lequel la valeur constante décalée est déplacée dans le registre (115).
     
    6. Microcontrôleur ou procédé selon l'une quelconque des revendications précédentes, dans lequel lesdites informations d'interruption supplémentaires correspondent à un numéro d'interruption qui est directement stocké dans un registre de travail (115) de l'unité CPU (110).
     
    7. Microcontrôleur ou procédé selon l'une quelconque des revendications précédentes, dans lequel dans le second mode, le microcontrôleur (100) est programmé de manière à fournir une routine de service d'interruption qui évalue le contenu d'un registre de travail (115) en vue d'effectuer un branchement vers une routine de service respective associée à une source d'interruption ayant généré l'interruption.
     
    8. Microcontrôleur ou procédé selon l'une quelconque des revendications précédentes, dans lequel dans le premier mode, le microcontrôleur (100) est programmé de manière à fournir une routine de service d'interruption qui interroge un drapeau d'interruption dans un registre de fonction spéciale associé au périphérique (130) ayant occasionné l'interruption, en vue de déterminer une source d'interruption.
     
    9. Microcontrôleur ou procédé selon l'une quelconque des revendications précédentes, dans lequel l'unité centrale de traitement (100) ne comprend qu'une seule entrée d'interruption (125).
     
    10. Microcontrôleur ou procédé selon l'une quelconque des revendications précédentes, dans lequel l'unité centrale de traitement (110) comprend uniquement une première entrée d'interruption et une seconde entrée d'interruption (125a, 125b), dans lequel la première entrée d'interruption (125a) a une priorité supérieure à celle de la seconde entrée d'interruption (125b).
     
    11. Microcontrôleur ou procédé selon la revendication 10, dans lequel, lorsqu'une interruption de priorité supérieure interrompt une routine de service de priorité inférieure, l'interruption de priorité supérieure est configurée de manière à effacer une interruption de priorité inférieure, et une routine de service associée revient directement à un code principal sans passer par la routine de service de priorité inférieure.
     
    12. Microcontrôleur ou procédé selon la revendication 10, dans lequel, lorsqu'une interruption de priorité supérieure interrompt une routine de service de priorité inférieure, l'interruption de priorité supérieure est configurée de manière à revenir directement à la routine de service d'interruption de priorité inférieure sans passer par un code principal.
     
    13. Microcontrôleur ou procédé selon l'une quelconque des revendications précédentes, dans lequel le contrôleur d'interruption comprend une logique pouvant être commandée en vue de permettre des interruptions reçues en provenance des périphériques.
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description