(19)
(11)EP 3 276 828 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
27.05.2020 Bulletin 2020/22

(21)Application number: 17191587.9

(22)Date of filing:  18.12.2008
(51)Int. Cl.: 
H03K 5/131  (2014.01)

(54)

PROGRAMMABLE DELAY CIRCUIT WITH INTEGER AND FRACTIONAL TIME RESOLUTION

PROGRAMMIERBARE VERZÖGERUNGSSCHALTUNG MIT GANZZAHLIGER UND FRAKTIONIERTER PRÄZISION

CIRCUIT RETARD PROGRAMMABLE AVEC RÉSOLUTION TEMPORELLE ENTIÈRE ET FRACTIONNELLE


(84)Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR

(30)Priority: 20.12.2007 US 962045

(43)Date of publication of application:
31.01.2018 Bulletin 2018/05

(62)Application number of the earlier application in accordance with Art. 76 EPC:
08867868.5 / 2235823

(73)Proprietor: QUALCOMM Incorporated
San Diego, CA 92121-1714 (US)

(72)Inventors:
  • KESKIN, Mustafa
    San Diego, CA California 92121-1714 (US)
  • PEDRALI-NOY, Marzio
    San Diego, CA California 92121-1714 (US)

(74)Representative: Schmidbauer, Andreas Konrad 
Wagner & Geyer Partnerschaft mbB Patent- und Rechtsanwälte Gewürzmühlstrasse 5
80538 München
80538 München (DE)


(56)References cited: : 
EP-A- 0 208 049
US-A1- 2005 184 775
US-A1- 2002 093 872
US-B1- 6 373 312
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    BACKGROUND


    I. Field



    [0001] The present disclosure relates generally to electronics circuits, and more specifically to a delay circuit.

    II. Background



    [0002] A synchronous circuit such as a flip-flop or a latch may receive a data signal from one source and a clock signal from another source. The data and clock signals may have different propagation delays and may not be time aligned at the synchronous circuit. It may be desirable to delay the clock signal and/or the data signal by a proper amount so that these signals are time aligned. This may then allow the synchronous circuit to operate at a faster rate and/or achieve more timing margins, both of which are desirable.

    [0003] Attention is drawn to US 2002/093872 A1 describing that in performing a read operation or a write operation in a memory cell, a row control circuit is first operated to activate a word line. Subsequently, a command control circuit receives a column operation command in synchronization with a clock signal so as to operate a column control circuit. Here, under the control of a timing adjusting circuit, the column control circuit starts operating a predetermined delay time after the reception of the column operation command. By delaying the operation of the column control circuit, the read operation or the write operation in the memory cell can be performed at the optimum timing corresponding to the operating timing of an internal circuit independent of the cycle of the clock signal. As a result, the number of times in receiving commands per unit time can be increased to enhance the bus occupation rate of data. Since the column control circuit is operated at the optimum timing corresponding to the operating timing of the internal circuit, a read cycle time and a write cycle time can be shortened.

    [0004] Attention is further drawn to US 2005/184775 A1 describing a delay locked loop for use in an integrated circuit device that includes a coarse delay chain in series with a micro-stepped delay chain. The coarse delay chain includes a plurality of coarse delay units configured for selectively providing a coarse delay with respect to an input clock signal, and the micro-stepped delay chain is configured for selectively providing a fine delay adjustment with respect to the input clock signal. The micro-stepped delay chain further includes a plurality of parallel signal paths, wherein one or more of the parallel signal paths are capacitively loaded so as to provide the fine delay adjustment.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0005] 
    FIG. 1
    shows a device having a central processing unit (CPU) and two memories.
    FIG. 2
    shows a block diagram of an input interface circuit.
    FIG. 3
    shows a block diagram of a programmable delay circuit.
    FIG. 4
    shows a schematic diagram of an N-stage full delay circuit.
    FIG. 5
    shows a schematic diagram of a fractional delay circuit.
    FIG. 6
    shows a schematic diagram of another fractional delay circuit.
    FIG. 7
    shows a block diagram of a wireless communication device.

    DETAILED DESCRIPTION



    [0006] In accordance with the present invention an apparatus, and a method, as set forth in the independent claims, respectively, are provided. Preferred embodiments of the invention are described in the dependent claims.

    [0007] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any exemplary embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other exemplary embodiments.

    [0008] The programmable delay circuit described herein may be used to match the delays of signals provided to synchronous circuits such as flip-flops, latches, etc. The programmable delay circuit may be used for interface circuits between different devices such as CPUs and memories, which may be implemented on the same integrated circuit (IC) or different ICs. The programmable delay circuit may also be used for internal circuits within a given device or IC.

    [0009] FIG. 1 shows a block diagram of a device 100 having a CPU 110 and memories 120 and 130. CPU 110 may comprise any type of processor such as a digital signal processor (DSP), a general-purpose processor, a micro-processor, a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, etc. Memories 120 and 130 may be the same or different types of memories. For example, memory 120 may be a synchronous dynamic random access memory (SDRAM), and memory 130 may be a Flash memory such as a NAND Flash or a NOR Flash. CPU 110 and memories 120 and 130 may be implemented on a single IC such as an application specific integrated circuit (ASIC). Alternatively, CPU 110 and memories 120 and 130 may be implemented on separate ICs.

    [0010] CPU 110 includes an input/output interface circuit (I/O Ckt) 112 for exchanging data with memory 120. Memory 120 includes I/O circuits 122 and 124 for exchanging data with CPU 110 and memory 130, respectively. Memory 130 includes an I/O circuit 132 for exchanging data with memory 120. It may be desirable to operate the interfaces between CPU 110 and memories 120 and 130 at clock rates that are as high as possible in order to improve data throughput. High clock rates may be supported by using the programmable delay circuit described herein in I/O circuits 112, 122, 124 and 132.

    [0011] FIG. 2 shows a schematic diagram of an exemplary design of an input interface circuit 200, which may be used in each of the I/O circuits shown in FIG. 1. In this exemplary design, input interface circuit 200 includes a programmable delay circuit 210 and a synchronous circuit 220, which may comprise a flip-flop, a latch, etc. Programmable delay circuit 210 receives a clock signal and provides a delayed clock signal. Synchronous circuit 220 receives a data signal and the delayed clock signal and provides an output signal. Programmable delay circuit 210 provides a suitable amount of delay such that the delayed clock signal is time aligned with the data signal at the inputs of synchronous circuit 220. The amount of delay may be programmable and determined by a select control.

    [0012] In an aspect, programmable delay circuit 210 can provide a delay with integer and fractional time resolution. Integer time resolution may be obtained with unit delay cells that can be efficiently implemented. Fractional time resolution may be efficiently obtained as described below. The fractional time resolution can provide finer delay resolution, which may allow the clock signal to be delayed or skewed with finer frequency resolution.

    [0013] FIG. 3 shows a block diagram of an exemplary design of programmable delay circuit 210 in FIG. 2. In this exemplary design, programmable delay circuit 210 includes an N-stage full delay circuit 310, a half delay circuit 320, a quarter delay circuit 330, and a single-ended-to-differential converter 340, all of which are coupled in series. Full delay circuit 310 receives the clock signal and provides a delay of 1 to N time units, where N may be any integer value greater than one. A time unit Tunit may be any suitable time duration and may be selected based on various factors such as the application for which programmable delay circuit 210 is used, the desired integer delay resolution, etc. For example, Tunit may be on the order of picoseconds (ps), tens of picoseconds, etc. Half delay circuit 320 receives the output of full delay circuit 310 and provides a delay of one half time unit when enabled. Quarter delay circuit 330 receives the output of half delay circuit 320 and provides a delay of one quarter time unit when enabled. The combination of delay circuits 320 and 330 can provide a fractional delay of zero to 3 Tunit/4, plus a time offset described below.

    [0014] Delay circuits 310, 320 and 330 may be arranged in different orders than the order shown in FIG. 3. Furthermore, one or more additional fractional delay circuits (e.g., an eighth delay circuit, a sixteenth delay circuit, etc.) may be used to provide even finer delay resolution. Single-ended-to-differential converter 340 receives a single-ended signal from the last delay circuit 330, performs single-ended to differential conversion, and provides a differential delayed clock signal Clockp and Clockn.

    [0015] FIG. 4 shows a schematic diagram of an exemplary design of N-stage full delay circuit 310 in FIG. 3. In this exemplary design, full delay circuit 310 includes N unit delay cells 410a through 410n coupled in series. Unit delay cells 410a through 410n may be enabled in a sequential order based on control signals S1 and R1 through SN and RN to obtain the desired amount of delay. For example, a delay of Tunit may be obtained by enabling only unit delay cell 410a, a delay of 2Tunit may be obtained by enabling two unit delay cells 410a and 410b, and so on, and a delay of N·Tunit may be obtained by enabling all N unit delay cells 410a through 410n.

    [0016] Each unit delay cell 410 includes (i) an upper path composed of a NAND gate 412 and (ii) a lower path composed of a NAND gate 416. Each unit delay cell 410 further includes a NAND gate 414 for coupling an output signal from the upper path to the lower path. For the n-th unit delay cell, where 1 ≤ n ≤ N, NAND gate 412 receives an input signal Xn for the upper path and a control signal Sn and provides an output signal Yn for the upper path. NAND gate 414 receives the output signal Yn and a control signal Rn and provides its output to NAND gate 416. NAND gate 416 receives an input signal Un for the lower path and the output of NAND gate 414 provides an output signal Vn for the lower path.

    [0017] Each unit delay cell 410 operates as follows. NAND gate 412 passes (i) the input signal Xn if the control signal Sn is at logic high or (ii) logic high if the control signal Sn is at logic low. NAND gate 414 passes (i) the output signal Yn if the control signal Rn is at logic high or (ii) logic high if the control signal Rn is at logic low. NAND gate 416 passes (i) the output of NAND gate 414 if the control signal Rn is at logic high or (ii) the input signal Un for the lower path if the control signal Rn is at logic low. Table 1 gives the output signal Yn for the upper path and the output signal Vn for the lower path versus control signals Sn and Rn, respectively.
    Table 1
    SnYn
    0 logic high
    1 Xn
    RnVn
    0 Yn
    1 Un


    [0018] Each unit delay cell 410 receives an output signal Yn-1 from the upper path of a preceding unit delay cell, delays this signal by a delay of Thalf-unit = Tunit / 2, and provides an output signal Yn to the upper path of the next unit delay cell if enabled by the control signal Sn. Each unit delay cell 410 also passes the output signal Yn from the upper path to the lower path via NAND gate 414 if enabled by the control signal Rn. Each unit delay cell 410 further receives an output signal Vn+1 from the lower path of the next unit delay cell, passes the signal Yn or Vn+1 based on the control signal Rn, delays the passed signal by a delay of Thalf-unit, and provides an output signal Vn to the lower path of the preceding unit delay cell.

    [0019] A delay of k·Tunit, where 1 ≤ k ≤ N , may be obtained by passing the input signal through the upper paths of the first k unit delay cells, then from the upper path to the lower path of the k-th unit delay cell, and then through the lower paths of the first k unit delay cells. This may be achieved by (i) setting control signals S1 through Sk to logic high to enable the first k unit delay cells, (ii) setting the remaining control signals Sk+1 through SN to logic low to disable the remaining N - k unit delay cells, (iii) setting control signal Rk to logic high to pass the signal from the upper path to the lower path of the k-th unit delay cell, and (iv) setting the N-1 remaining control signals R1 through Rk-1 and Rk+1 through RN to logic low.

    [0020] The total delay provided by full delay circuit 310 may be expressed as:

    where Toffset is the delay of the coupling path from the upper path to the lower path,

    k is the number of unit delay cells selected, and

    Tinteger is the total delay provided by full delay circuit 310.



    [0021] As shown in equation (1), the total delay includes a portion Toffset that is present regardless of the number of unit delay cells selected. Toffset may thus be considered as a fixed offset. The total delay may be selected in increments of Tunit by enabling a proper number of unit delay cells.

    [0022] In the exemplary design shown in FIG. 4, each unit delay cell has one NAND gate 412 in the upper path, one NAND gate 416 in the lower path, and one NAND gate 414 in the coupling path from the upper path to the lower path. When k unit delay cells are selected, where 1 ≤ k ≤ N , the input signal passes through 2k NAND gates in the upper and lower paths of the k selected unit delay cells plus one NAND gate in the coupling path of the k-th unit delay cell. The input signal thus passes through an odd number of NAND gates regardless of the number of unit delay cells selected. An inverter may be inserted at either the input or the output of the first unit delay cell 410a (not shown in FIG. 4) in order to obtain an even number of inversions. This would result in the output signal having the same polarity as the input signal. Alternatively, the inversion by this inverter may be achieved by swapping the Clockp and Clockn signals from converter 340 in FIG. 3.

    [0023] FIG. 5 shows a schematic diagram of an exemplary design of a fractional delay circuit 500, which may be used for each of delay circuits 320 and 330 in FIG. 3. Fractional delay circuit 500 includes an inverter 510, three NAND gates 512, 514 and 516, and L dummy NAND gates 518a through 518ℓ, where in general L ≥ 1. Inverter 510 receives a control signal Sel and provides an inverted control signal. NAND gate 512 receives an input signal Iin and the inverted control signal, and NAND gate 514 receives the input signal and the control signal. NAND gate 516 receives the outputs of NAND gates 512 and 514 and provides an output signal Out. NAND gates 518a through 518ℓ have their inputs coupled together and further to the output of NAND gate 514.

    [0024] Fractional delay cell 500 includes a short path composed of NAND gates 512 and 516 and a long path composed of NAND gates 514 and 516. The short path is selected when the control signal Sel is at logic low. In this case, the input signal passes through NAND gates 512 and 516 to the output. The long path is selected when the control signal Sel is at logic high. In this case, the input signal passes through NAND gates 514 and 516 to the output.

    [0025] The fractional delay provided by delay circuit 500 may be expressed as:

    where Tshort is the delay of the short path,

    Tlong is the delay of the long path, and

    Tfrac is the fractional delay provided by delay circuit 500 when selected.



    [0026] The delay through fractional delay circuit 500 includes a portion Tshort that is present regardless of whether or not delay circuit 500 is selected. Tshort may thus be considered as a fixed offset.

    [0027] NAND gates 518a through 518ℓ act as dummy gates that provide extra loading for NAND gate 514 and hence increase the propagation delay of the long path. NAND gates 518 may be designed to provide the desired fractional delay Tfrac. In one exemplary design, different numbers of NAND gates 518 may be used to obtain different amounts of fractional delay. For example, a fractional delay of Tunit/8 may be obtained with one NAND gate, a fractional delay of Tunit/4 may be obtained with two NAND gates, and a fractional delay of Tunit/2 may be obtained with four NAND gates. In another exemplary design, only one NAND gate 518a may be used as the dummy gate, but the dimension (e.g., width and/or length) of the transistors within NAND gate 518a may be selected to obtain the desired fractional delay. Computer simulations indicate that the delay of the long path increases linearly with the width of the transistors for dummy NAND gate 518a. The desired fractional delay may thus be obtained by selecting a suitable width for the transistors within dummy NAND gate 518a.

    [0028] Fractional delay circuit 500 may be used for half delay circuit 320 in FIG. 3. In this case, NAND gates 518a through 518ℓ may be designed to provide a fractional delay of Tunit/2 when half delay circuit 320 is selected. Fractional delay circuit 500 may also be used for quarter delay circuit 330 in FIG. 3. In this case, NAND gates 518a through 518ℓ may be designed to provide a fractional delay of Tunit /4 when quarter delay circuit 330 is selected. In general, fractional delay circuit 500 may be designed to provide any desired fractional delay.

    [0029] FIG. 6 shows a schematic diagram of an exemplary design of a fractional delay circuit 600, which may be used for both of delay circuits 320 and 330 in FIG. 3. Fractional delay circuit 600 includes an inverter 610 and three NAND gates 612, 614 and 616 that are coupled in the same manner as inverter 510 and NAND gates 512, 514 and 516 in FIG. 5. Fractional delay circuit 600 further includes multiple (T) dummy NAND gates 618a through 618t coupled to the output of NAND gate 614 via T switches 620a through 620t, respectively. Each dummy NAND gate 618 has its inputs coupled together and to the output of NAND gate 614 via a respective switch 620.

    [0030] In one exemplary design, the T dummy NAND gates 618a through 618t have the same size. The number of dummy NAND gates 618 to couple to the output of NAND gate 614 is determined by the desired fractional delay. For example, one, two, or four dummy NAND gates 618 may be coupled to the output of NAND gate 614 to obtain fractional delays of Tunit/8, Tunit/4, or Tunit/2, respectively. In another exemplary design, different dummy NAND gates have different transistor dimensions, and a proper dummy NAND gate may be coupled to the output of NAND gate 614 based on the desired fractional delay.

    [0031] In the exemplary designs shown in FIGS. 5 and 6, NAND gates are used for the logic gates in the short and long paths as well as for the dummy logic gates that provide extra loading in the long path. In general, the extra loading may be obtained with any type of logic gate, e.g., AND gates, OR gates, NOR gates, exclusive OR (XOR) gates, inverters, etc. The extra loading may also be obtained with transistors and/or other circuit elements. It may be desirable to implement the dummy logic gates using the same type of logic gate used in the short and long paths. This may allow the dummy logic gates to be fabricated using the same IC process used for the logic gates in the short and long paths. This may also provide a more accurate fractional delay across IC process, temperature, and power supply variations.

    [0032] The programmable delay circuit described herein may be used to delay clock signals to time align the clock signals with data signals for synchronous circuits such as flip-flops, latches, etc. The programmable delay circuit may be used in high-speed interface circuits (e.g., as shown in FIG. 1) to time align the data and clock signals. These high-speed interface circuits may be for CPUs, memories, registers of programmable blocks, etc. The programmable delay circuit may also be used for internal circuits where accurate delay matching of clock/control signals and data signals is desired.

    [0033] The programmable delay circuit described herein may be used for various applications such as communication, networking, computing, consumer electronics, etc. The programmable delay circuit may be used for cellular phones, personal digital assistants (PDAs), wireless communication devices, handheld devices, wireless modems, laptop computers, cordless phones, etc. An example use of the programmable delay circuit in a wireless communication device is described below.

    [0034] FIG. 7 shows a block diagram of an exemplary design of a wireless communication device 700 in a wireless communication system. Wireless device 700 may be a cellular phone, a terminal, a handset, a PDA, etc. The wireless communication system may be a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, etc.

    [0035] Wireless device 700 is capable of providing bi-directional communication via a receive path and a transmit path. In the receive path, signals transmitted by base stations (not shown) are received by an antenna 712 and provided to a receiver (RCVR) 714. Receiver 714 conditions the received signal and provides an input signal to an ASIC 720. In the transmit path, a transmitter (TMTR) 716 receives and conditions an output signal from ASIC 720 and generates a modulated signal, which is transmitted via antenna 712 to the base stations.

    [0036] ASIC 720 may include various processing, interface, and memory units such as, e.g., a modem processor 722, a CPU 724, a graphics processing unit (GPU) 726, an internal memory 728, a controller/processor 730, external bus interfaces (EBIs) 732 and 734, and an external driver 736. Modem processor 722 may perform processing for data transmission and reception, e.g., encoding, modulation, demodulation, decoding, etc. CPU 724 may perform various types of processing for wireless device 700, e.g., processing for higher layer applications. GPU 726 may perform graphics and video processing for wireless device 700. Internal memory 728 may store data and/or instructions for various units within ASIC 720. Controller/processor 730 may direct the operation of various processing and interface units within ASIC 720. EBI 732 may facilitate transfer of data between ASIC 720 and an SDRAM 742. EBI 734 may facilitate transfer of data between ASIC 720 and a Flash memory 744. External driver 736 may drive external device(s) 746 via an analog or digital interface. The programmable delay circuit described herein may be implemented in any of the processing, memory and interface units shown in FIG. 7, e.g., in any of the I/O circuits (I/O) shown in FIG. 7.

    [0037] The programmable delay circuit described herein may be implemented in various hardware units such as DSPs, digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, electronics devices, memory devices, etc. The programmable delay circuit may be used in various types of IC such as ASICs, digital ICs, analog ICs, mixed-signal ICs, radio frequency ICs (RFICs), etc. The programmable delay circuit may be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (N-MOS), P-channel MOS (P-MOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc. The programmable delay circuit may also be fabricated with any device size technology, e.g., 130 nanometers (nm), 90 nm, 65 nm, 45 nm, 32 nm, etc.

    [0038] An apparatus implementing the programmable delay circuit described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an ASIC such as a mobile station modem (MSM), (iv) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (v) a module that may be embedded within other devices, (vi) a cellular phone, wireless device, handset, or mobile unit, (vii) etc.

    [0039] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.


    Claims

    1. An apparatus comprising:

    first means (310) for providing a first delay of an integer number of time units; and

    second means (500) coupled to the first means and providing a second delay of a fraction of one time unit;

    the second means comprising a first path (512, 516) providing a shorter delay when the first path is selected, a second path (514, 516) providing a longer delay when the second path is selected, and plural circuit elements (518) coupled to the second path and providing extra loading to obtain the longer delay for the second path;

    the first path comprising first and second logic gates (512, 516), the second path comprising the second logic gate (516) and a third logic gate (514), and the circuit elements (518) being coupled to the third logic gate;

    wherein the first, second and third logic gates are of the same type of logic gate;

    and wherein the circuit elements comprise at least one dummy logic gate (518a) being the same type of logic gate as the first, second and third logic gates.


     
    2. The apparatus of claim 1, wherein the first logic gate (512) and the second logic gate (516) are coupled in series, the third logic gate (514) and the second logic gate are coupled in series, and wherein the circuit elements (518) are coupled to an output of the third logic gate and to an input of the second logic gate.
     
    3. The apparatus of claim 1 or 2, wherein the first, second and third logic gates are NAND gates.
     
    4. The apparatus of any of claims 1-3, wherein the circuit elements and the first, second and third logic gates are fabricated using the same IC process.
     
    5. The apparatus of any of claims 1-4, the circuit elements being selectable to obtain different longer delays for the second path.
     
    6. The apparatus of any of claims 1-5, the first means comprising multiple unit delay cells (410) coupled in series, each unit delay cell providing a delay of one time unit when enabled.
     
    7. The apparatus of any of claims 1-6, the circuit elements being implemented with transistors having a predetermined dimension, and the number of circuit elements being determined based on a target difference between the longer delay and the shorter delay.
     
    8. The apparatus of any of claims 1-6, the circuit elements being implemented with transistors having a predetermined dimension, the dimension being determined based on the desired fractional delay.
     
    9. The apparatus of any of claims 1-8, wherein the first means (310) are implemented by a first delay circuit and wherein the second means (500) are implemented by a second delay circuit.
     
    10. A method comprising:

    delaying an input signal by a first delay of an integer number of time units; and

    delaying the input signal further by a second delay of a fraction of one time unit based on extra loading provided by plural circuit elements (518);

    the delaying the input signal further by the second delay comprises:

    passing the input signal via a first path (512, 516) providing a shorter delay when the first path is selected, and passing the input signal via a second path (514, 516) providing a longer delay when the second path is selected, and the circuit elements (518) coupled to the second path and providing extra loading to obtain the longer delay for the second path;

    the first path comprising first and second logic gates (512, 516), the second path comprising the second logic gate (516) and a third logic gate (514), and the circuit elements being coupled to the third logic gate;

    wherein the first, second and third logic gates are of the same type of logic gate;

    and wherein the circuit elements comprise at least one dummy logic gate being the same type of logic gate as the first, second and third logic gates.


     
    11. The method of claim 10, wherein the first logic gate (512) and the second logic gate (516) are coupled in series, the third logic gate (514) and the second logic gate are coupled in series, and wherein the circuit elements (518) are coupled to an output of the third logic gate and to an input of the second logic gate.
     
    12. The method of claim 10 or 11, wherein the first, second and third logic gates are NAND gates.
     
    13. The method of any of claims 10-12, wherein the circuit elements and the first, second and third logic gates are fabricated using the same IC process.
     


    Ansprüche

    1. Eine Vorrichtung, die Folgendes aufweist:

    erste Mittel (310) zum Vorsehen einer ersten Verzögerung einer ganzzahligen Anzahl von Zeiteinheiten; und

    zweite Mittel (500), die an die ersten Mittel gekoppelt sind und eine zweite Verzögerung eine Bruchteils einer Zeiteinheit vorsehen;

    wobei die zweiten Mittel Folgendes aufweisen: einen ersten Pfad (512, 516), der eine kürzere Verzögerung vorsieht, wenn der erste Pfad ausgewählt wird, einen zweiten Pfad (514, 516), der eine längere Verzögerung vorsieht, wenn der zweite Pfad ausgewählt wird, und mehrere Schaltungselemente (518), die an den zweiten Pfad gekoppelt sind und eine zusätzliche Last vorsehen, um die längere Verzögerung für den zweiten Pfad zu erhalten;

    wobei der erste Pfad erste und zweite Logikgatter (512, 516) aufweist, wobei der zweite Pfad das zweite Logikgatter (516) und ein drittes Logikgatter (514) aufweist und die Schaltungselemente (518) an das dritte Logikgatter gekoppelt sind;

    wobei das erste, zweite und dritte Logikgatter ein gleicher Typ von Logikgatter sind;

    und wobei die Schaltungselemente wenigstens ein Dummy-Logikgatter (518a) aufweisen, das ein gleicher Typ von Logikgatter ist wie das erste, zweite und dritte Logikgatter.


     
    2. Vorrichtung nach Anspruch 1, wobei das erste Logikgatter (512) und das zweite Logikgatter (516) in Reihe gekoppelt sind, das dritte Logikgatter (514) und das zweite Logikgatter in Reihe gekoppelt sind und wobei die Schaltungselemente (518) an einen Ausgang des dritten Logik-Gatters und an einen Eingang des zweiten Logik-Gatters gekoppelt sind.
     
    3. Vorrichtung nach Anspruch 1 oder 2, wobei das erste, zweite und dritte Logikgatter NAND-Gatter sind.
     
    4. Vorrichtung nach einem der Ansprüche 1-3, wobei die Schaltungselemente und das erste, zweite und dritte Logikgatter unter Verwendung desselben IC-Prozesses hergestellt werden.
     
    5. Vorrichtung nach einem der Ansprüche 1-4, wobei die Schaltungselemente auswählbar sind um unterschiedliche längere Verzögerungen für den zweiten Pfad zu erhalten.
     
    6. Vorrichtung nach einem der Ansprüche 1-5, wobei die ersten Mittel mehrere Einheitsverzögerungszellen (410) aufweisen, die in Reihe gekoppelt sind, wobei jede Einheitsverzögerungszelle eine Verzögerung um eine Zeiteinheit vorsieht, wenn sie aktiviert ist.
     
    7. Vorrichtung nach einem der Ansprüche 1-6, wobei die Schaltungselemente mit Transistoren implementiert sind, die eine vorbestimmte Abmessung haben, und die Anzahl von Schaltungselementen bestimmt wird basierend auf einer Zieldifferenz zwischen der längeren Verzögerung und der kürzeren Verzögerung.
     
    8. Vorrichtung nach einem der Ansprüche 1-6, wobei die Schaltungselemente mit Transistoren implementiert sind, die eine vorbestimmte Abmessung haben, wobei die Abmessung basierend auf der erwünschten Bruchteilverzögerung bestimmt wird.
     
    9. Vorrichtung nach einem der Ansprüche 1-8, wobei die ersten Mittel (310) durch eine erste Verzögerungsschaltung implementiert werden und wobei die zweiten Mittel (500) durch eine zweite Verzögerungsschaltung implementiert werden.
     
    10. Ein Verfahren, das Folgendes aufweist:

    Verzögern eines Eingangssignals um eine erste Verzögerung einer ganzzahligen Anzahl von Zeiteinheiten; und

    Verzögern des Eingangssignals weiter um eine zweite Verzögerung eines Bruchteils einer Zeiteinheit basierend auf einer zusätzlichen Last, die durch mehrere Schaltungselemente (518) vorgesehen wird;

    wobei das Verzögern des Eingangssignals weiter um die zweite Verzögerung Folgendes aufweist:

    Leiten des Eingangssignals über einen ersten Pfad (512, 516), der eine kürzere Verzögerung vorsieht, wenn der erste Pfad ausgewählt ist, und Leiten des Eingangssignals über einen zweiten Pfad (514, 516), der eine längere Verzögerung vorsieht, wenn der zweite Pfad ausgewählt ist, und wobei die Schaltungselemente (518) an den zweiten Pfad gekoppelt sind und eine zusätzliche Last vorsehen, um die längere Verzögerung für den zweiten Pfad zu erhalten;

    wobei der erste Pfad erste und zweite Logikgatter (512, 516) aufweist, der zweite Pfad das zweite Logikgatter (516) und ein drittes Logikgatter (514) aufweist und die Schaltungselemente an das dritte Logikgatter gekoppelt sind;

    wobei die ersten, zweiten und dritten Logikgatter ein gleicher Typ von Logikgatter sind;

    und wobei die Schaltungselemente wenigstens ein Dummy-Logikgatter aufweisen, das der gleiche Typ von Logikgatter ist wie das erste, zweite und dritte Logikgatter.


     
    11. Verfahren nach Anspruch 10, wobei das erste Logikgatter (512) und das zweite Logikgatter (516) in Reihe gekoppelt sind, das dritte Logikgatter (514) und das zweite Logikgatter in Reihe gekoppelt sind und wobei die Schaltungselemente (518) an einen Ausgang des dritten Logik-Gatters und an einen Eingang des zweiten Logik-Gatters gekoppelt sind.
     
    12. Verfahren nach Anspruch 10 oder 11, wobei das erste, zweite und dritte Logikgatter NAND-Gatter sind.
     
    13. Verfahren nach einem der Ansprüche 10-12, wobei die Schaltungselemente und das erste, zweite und dritte Logikgatter unter Verwendung desselben IC-Prozesses hergestellt werden.
     


    Revendications

    1. Appareil comprenant :

    des premiers moyens (310) destinés à fournir un premier retard d'un nombre entier d'unités temporelles ; et

    des deuxièmes moyens (500) couplés aux premiers moyens et fournissant un deuxième retard d'une fraction d'une unité temporelle ;

    les deuxièmes moyens comprenant un premier chemin (512, 516) fournissant un retard plus court quand le premier chemin est sélectionné, un deuxième chemin (514, 516) fournissant un retard plus long quand le deuxième chemin est sélectionné, et plusieurs éléments de circuit (518) couplés au deuxième chemin et fournissant une charge supplémentaire pour obtenir le retard plus long pour le deuxième chemin ;

    le premier chemin comprenant des première et deuxième portes logiques (512, 516), le deuxième chemin comprenant la deuxième porte logique (516) et une troisième porte logique (514), et les éléments de circuit (518) étant couplés à la troisième porte logique ;

    dans lequel les première, deuxième et troisième portes logiques sont du même type de porte logique ; et

    dans lequel les éléments de circuit comprennent au moins une porte logique factice (518a) qui est du même type de porte logique que les première, deuxième et troisième portes logiques.


     
    2. Appareil selon la revendication 1, dans lequel la première porte logique (512) et la deuxième porte logique (516) sont couplées en série, la troisième porte logique (514) et la deuxième porte logique sont couplées en série, et dans lequel les éléments de circuit (518) sont couplés à une sortie de la troisième porte logique et à une entrée de la deuxième porte logique.
     
    3. Appareil selon la revendication 1 ou 2, dans lequel les première, deuxième et troisième portes logiques sont des portes non-et NAND.
     
    4. Appareil selon l'une quelconque des revendications 1 à 3, dans lequel les éléments de circuit et les première, deuxième et troisième portes logiques sont fabriqués en utilisant le même procédé IC.
     
    5. Appareil selon l'une quelconque des revendications 1 à 4, les éléments de circuit étant sélectionnables pour obtenir différents retards plus longs pour le deuxième chemin.
     
    6. Appareil selon l'une quelconque des revendications 1 à 5, les premiers moyens comprenant plusieurs cellules de retard unitaire (410) couplées en série, chaque cellule de retard unitaire fournissant un retard d'une unité temporelle quand elle est activée.
     
    7. Appareil selon l'une quelconque des revendications 1 à 6, les éléments de circuit étant réalisés avec des transistors ayant une dimension prédéterminée, et le nombre d'éléments de circuit étant déterminés sur la base d'une différence d'objectif entre le retard plus long et le retard plus court.
     
    8. Appareil selon l'une quelconque des revendications 1 à 6, les éléments de circuit étant réalisés avec des transistors ayant une dimension prédéterminée, la dimension étant déterminée sur la base du retard fractionné recherché.
     
    9. Appareil selon l'une quelconque des revendications 1 à 8, dans lequel les premiers moyens (310) sont réalisés par un premier circuit de retard et dans lequel les deuxièmes moyens (500) sont réalisés par un deuxième circuit de retard.
     
    10. Procédé comprenant les étapes suivantes :

    le retard d'un signal d'entrée par un premier retard d'un nombre entier d'unités temporelles ; et

    le retard supplémentaire du signal d'entrée par un deuxième retard d'une fraction d'une unité temporelle sur la base d'une charge supplémentaire fournie par plusieurs éléments de circuit (518) ;

    le retard supplémentaire du signal d'entrée par le deuxième retard comprenant les étapes suivantes :

    la transmission du signal d'entrée via un premier chemin (512, 516) fournissant un retard plus court quand le premier chemin est sélectionné, et la transmission du signal d'entrée via un deuxième chemin (514, 516) fournissant un retard plus long quand le deuxième chemin est sélectionné, et les éléments de circuit (518) étant couplés au deuxième chemin et la fourniture d'une charge supplémentaire pour obtenir le retard plus long pour le deuxième chemin ;

    le premier chemin comprenant des première et deuxième portes logiques (512, 516), le deuxième chemin comprenant la deuxième porte logique (516) et une troisième porte logique (514), et les éléments de circuit étant couplés à la troisième porte logique ;

    dans lequel les première, deuxième et troisième portes logiques sont du même type de porte logique ; et

    dans lequel les éléments de circuit comprennent au moins une porte logique factice qui est du même type de porte logique que les première, deuxième et troisième portes logiques.


     
    11. Procédé selon la revendication 10, dans lequel la première porte logique (512) et la deuxième porte logique (516) sont couplées en série, la troisième porte logique (514) et la deuxième porte logique sont couplées en série, et dans lequel les éléments de circuit (518) sont couplés à une sortie de la troisième porte logique et à une entrée de la deuxième porte logique.
     
    12. Procédé selon la revendication 10 ou 11, dans lequel les première, deuxième et troisième portes logiques sont des portes non-et NAND.
     
    13. Procédé selon l'une quelconque des revendications 10 à 12, dans lequel les éléments de circuit et les première, deuxième et troisième portes logiques sont fabriqués en utilisant le même procédé IC.
     




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    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description