(19)
(11)EP 3 281 117 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
25.03.2020 Bulletin 2020/13

(21)Application number: 16777285.4

(22)Date of filing:  07.04.2016
(51)International Patent Classification (IPC): 
G06F 13/00(2006.01)
H03K 19/0175(2006.01)
G06F 7/00(2006.01)
G06F 13/40(2006.01)
(86)International application number:
PCT/US2016/026464
(87)International publication number:
WO 2016/164594 (13.10.2016 Gazette  2016/41)

(54)

HIGH SPEED DATA SERIALIZATION THROUGH HERMETIC SEALS

HOCHGESCHWINDIGKEITSDATENSERIALISIERUNG DURCH HERMETISCHEN ABDICHTUNGEN

SÉRIALISATION DE DONNÉES À VITESSE ÉLEVÉE À TRAVERS DES JOINTS HERMÉTIQUES


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 09.04.2015 US 201562145187 P
13.04.2015 US 201562146701 P

(43)Date of publication of application:
14.02.2018 Bulletin 2018/07

(73)Proprietor: Thorlabs, Inc.
Newton, New Jersey 07860 (US)

(72)Inventors:
  • ORACH, Jeffrey
    Newton, NJ 07860 (US)
  • ERICKSON, Jeffrey
    Newton, NJ 07860 (US)
  • HUANG, Shih-Che
    Newton, NJ 07860 (US)
  • PRABALA, Ash
    Newton, NJ 07860 (US)

(74)Representative: Grättinger Möhring von Poschinger Patentanwälte Partnerschaft mbB 
Wittelsbacherstrasse 2b
82319 Starnberg
82319 Starnberg (DE)


(56)References cited: : 
WO-A2-02/25934
US-A1- 2007 139 080
US-B1- 6 789 959
US-A- 5 838 216
US-A1- 2012 030 400
US-B1- 6 789 959
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    FIELD OF THE INVENTION



    [0001] The invention generally relates to data serialization. More particularly, the invention relates to a method and an implementation of high speed data serialization for communication between the inside and outside of a hermetically sealed chamber.

    BACKGROUND



    [0002] In many data communication applications, for example, imaging using a Scientific CMOS (sCMOS) camera, there exists a with a costly design challenge of how to transmit image data from the sensor inside the chamber to the outside world for acquisition. Many such sensors have hundreds of pins necessary to power the sensor and acquire image data.

    [0003] Although communication with the sensor could be made using all the pins, it would have presented a manufacturing cost that far exceeded any reasonable targets for the design. Data serialization is often used to reduce pin count in board layouts, but often requires strict impedance control.

    [0004] Therefore, there is a need to provide a solution to implement such serialization between two PCBs (printed circuit boards) on either side of the chamber wall, without the above mentioned disadvantages. US5838216 discloses a hermetically sealed device having connector pins being interconnected to each other and to the housing via capacitive elements.

    SUMMARY



    [0005] One embodiment of the invention provides a method for transmitting data between the inside and outside of a hermetically sealed chamber, including: serializing first data into a first serial data for transmission; transmitting the first serial data at a first frequency using a first transmission line that connects the inside and outside of the hermetically sealed chamber; wherein the first transmission line is coupled to a first ground.

    [0006] In another embodiment, the above method further includes: serializing second data into a second serial data for transmission; and transmitting the second serial data at a second frequency using a second transmission line that connects the inside and outside of the hermetically sealed chamber; wherein the second frequency is greater than the first frequency; and wherein the second transmission line is coupled to the first transmission line, with the first transmission line acting as a second ground for the second transmission line.

    [0007] One embodiment of the invention provides an apparatus for transmitting data between the inside and outside of a hermetically sealed chamber, including: a processor configured to serialize first data into a first serial data for transmission; and a transmitter configured to transmit the first serial data at a first frequency using a first transmission line that connects the inside and outside of the hermetically sealed chamber; wherein the first transmission line is coupled to a first ground.

    [0008] In another embodiment, in the above apparatus, wherein the processor is further configured to serialize second data into a second serial data for transmission; wherein the transmitter is further configured to transmit the second serial data at a second frequency using a second transmission line that connects the inside and outside of the hermetically sealed chamber; wherein the second frequency greater than the first frequency; and wherein the second transmission line is coupled to the first transmission line, with the first transmission line acting as a second ground for the second transmission line.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0009] Fig. 1 illustrates a grounding scheme in accordance with an embodiment.

    DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS



    [0010] Feeding electrical connections through hermetically sealed chambers is costly, as each pin adds an incremental cost to the production of the chamber. Additionally, each pin adds an extra noise and thermal leakage path to the chamber. So, reduction of pin count is generally desirable.

    [0011] To reduce pin count in a scientific CMOS camera design, one can serialize the data. The class of sensors targeted for use have pin counts in the hundreds. While a first principles design would have connected such sensors by simply routing all of the pins out of the chamber, it is estimated that the cost were excessive for a reasonable design target. By combining several parallel data pins into pairs of differentially signaled pins communicating serially it is possible to reduce the pin count. This serializer-deserializer (SERDES) link is a technology provided by many FPGA (field-programmable gate array) vendors, and is used in many common high speed interfaces such as PCIe. Such interfaces operate with bit rates well into the gigahertz range.

    [0012] A major problem in maintaining performance in such high speed interfaces is to position these high speed serial pins close to ground reference pins to preserve signal integrity. This is necessary to maintain proper impedance control so signal integrity is maintained at these high frequencies. In printed circuit board applications, many techniques are used to estimate the transmission line impedance of the connection. Key in these designs is a stable ground plane at a known distance from the transmission line.

    [0013] In one design, it could have used excess ground pins to provide the grounds to couple the high speed transmission lines and help maintain the impedance. However, pin count can be further reduced by using lines that communicate at far slower rates (several orders of magnitude slower) as grounds. Since the difference in frequency is so large, appropriately selected capacitors are used to couple these slow transmission lines to ground.

    [0014] Using the principle that frequency dependent impedances are evaluated at the frequency of interest, in one embodiment, a grounding scheme is enhanced by connecting slow data pins to ground via capacitors selected to be very low impedance at the frequency of interest. Doing so means that it is able to communicate across the fast data pins as well as slowly signaled data pins because each end of the pin is presented with a low impedance connection to ground through these capacitors. This means that the high speed transmission lines see the low speed transmission lines as grounds due to the low impedance of the capacitors at this high frequency of interest, but the capacitance is sufficiently small that the low speed transmission lines do not suffer the roll off and other associated losses to signal integrity normally expected with a capacitive load.

    Implementation of the Principles



    [0015] Parallel data is delivered synchronously from an image sensor to a serializing device, for example, an FPGA. That device serializes the data for transmission. The transmitter is an LVDS (low-voltage differential signaling) driver operating at several gigabits per second. The LVDS transmission line leaving the serializing device is a pair of impedance controlled PCB traces. Those traces lead to holes in the PCB that receive conductive pins that are part of a hermetic feed through connector. The other end of the hermetic feed through is inserted into holes in a flexible circuit. The flex circuit has impedance controlled traces leading to a set of metalized fingers. These fingers mate to a connector mounted to a PCB. The connector provides electrical continuity from the flex circuit to a set of impedance controlled traces on this second PCB. These traces lead to the deserializing receivers of another FPGA.

    [0016] There are notably 4 locations where impedance control is lost: the solder joint between the serializing PCB and the hermetic feedthrough, throughout the hermetic feedthrough, the solder joint between the hermetic feedthrough and the flex circuit, and the contact between the flex circuit and the connector on the deserializing board. In accordance with one embodiment, a scheme for pin assignment in the connector preserves enough of the impedance control to make multi-gigahertz signaling possible.

    [0017] By serializing this data connection, it can reduce manufacturing cost, improve hermetic reliability, and minimize thermal and noise injection into the sensor. This results in a lower cost, more reliable, better performing product than one employing a fully parallel connector scheme.


    Claims

    1. A method for transmitting data between the inside and outside of a hermetically sealed chamber, comprising:

    serializing first data into a first serial data for transmission;

    transmitting the first serial data at a first frequency using a first transmission line (101) that connects the inside and outside of the hermetically sealed chamber;

    serializing second data into a second serial data for transmission; and

    transmitting the second serial data at a second frequency using a second transmission line (103) that connects the inside and outside of the hermetically sealed chamber;

    wherein the second frequency is greater than the first frequency;

    wherein the first transmission line (101) is coupled to a ground (102) via a frequency dependent impedance; and

    wherein the first transmission line acting as a ground for the second transmission line.


     
    2. The method of claim 1, wherein the first transmission line (101) is coupled to the ground (102) via a capacitor (104), and wherein the capacitor (104) has a capacitance selected to maintain signal integrity for the transmission of the first serial data at the first frequency.
     
    3. The method of claim 1, wherein the second frequency is multiple orders of magnitudes greater than the first frequency.
     
    4. The method of claim 1, wherein the serialization is performed by a FPGA (field-programmable gate array).
     
    5. The method of claim 1, wherein the transmission is performed by an LVDS (low-voltage differential signaling) driver.
     
    6. An apparatus for transmitting data between the inside and outside of a hermetically sealed chamber, comprising:

    a processor configured to serialize first data into a first serial data for transmission; and

    a transmitter configured to transmit the first serial data at a first frequency using a first transmission line (101) that connects the inside and outside of the hermetically sealed chamber;

    wherein the processor is further configured to serialize second data into a second serial data for transmission;

    wherein the transmitter is further configured to transmit the second serial data at a second frequency using a second transmission line that connects the inside and outside of the hermetically sealed chamber;

    wherein the second frequency greater than the first frequency;

    wherein the first transmission line (101) is coupled to a ground (102) via a frequency dependent impedance and

    wherein the first transmission line acting as a ground for the second transmission line.


     
    7. The apparatus of claim 6, wherein the first transmission line (101) is coupled to the ground (102) via a capacitor (104), and wherein the capacitor (104) has a capacitance selected to maintain signal integrity for the transmission of the first serial data at the first frequency.
     
    8. The apparatus of claim 6, wherein the second frequency is multiple orders of magnitudes greater than the first frequency.
     
    9. The apparatus of claim 6, wherein the processor comprises a FPGA (field-programmable gate array).
     
    10. The apparatus of claim 6, wherein the transmitter comprises an LVDS (low-voltage differential signaling) driver.
     


    Ansprüche

    1. Verfahren zum Übertragen von Daten zwischen dem Inneren und Äußeren einer hermetisch abgeschlossenen Kammer, das Folgendes aufweist:

    Serialisieren erster Daten in erste serielle Daten für Übertragung;

    Übertragen der ersten seriellen Daten mit einer ersten Frequenz unter Verwendung einer Übertragungsleitung (101), die das Innere und Äußere der hermetisch abgeschlossenen Kammer verbindet;

    Serialisieren von zweiten Daten in zweite serielle Daten für Übertragung; und

    Übertragen der zweiten seriellen Daten mit einer zweiten Frequenz unter Verwendung einer zweiten Übertragungsleitung (103), die das Innere und Äußere der hermetisch abgeschlossenen Kammer verbindet;

    wobei die zweite Frequenz größer als die erste Frequenz ist;

    wobei die erste Übertragungsleitung (101) über eine frequenzabhängige Impedanz mit Masse (102) gekoppelt ist; und

    wobei die erste Übertragungsleitung als Masse für die zweite Übertragungsleitung fungiert.


     
    2. Verfahren nach Anspruch 1, wobei die erste Übertragungsleitung (101) über einen Kondensator (104) mit der Masse (102) gekoppelt ist, und wobei der Kondensator (104) eine Kapazität aufweist, die dahingehend ausgewählt ist, Signalintegrität für die Übertragung der ersten seriellen Daten mit der ersten Frequenz aufrecht zu halten.
     
    3. Verfahren nach Anspruch 1, wobei die zweite Frequenz um mehrere Größenordnungen größer als die erste Frequenz ist.
     
    4. Verfahren nach Anspruch 1, wobei die Serialisierung durch ein FPGA (feldprogrammierbares Gate-Array) durchgeführt wird.
     
    5. Verfahren nach Anspruch 1, wobei die Übertragung durch einen LVDS(Low Voltage Differential Signaling)-Treiber durchgeführt wird.
     
    6. Gerät zum Übertragen von Daten zwischen dem Inneren und Äußeren einer hermetisch abgeschlossenen Kammer, das Folgendes aufweist:

    einen Prozessor, der dazu ausgelegt ist, erste Daten in erste serielle Daten für Übertragung zu serialisieren; und

    einen Transmitter, der dazu ausgelegt ist, die ersten seriellen Daten mit einer ersten Frequenz unter Verwendung einer Übertragungsleitung (101), die das Innere und Äußere der hermetisch abgeschlossenen Kammer verbindet, zu übertragen;

    wobei der Prozessor ferner dazu ausgelegt ist, zweite Daten in zweite serielle Daten für Übertragung zu serialisieren;

    wobei der Transmitter ferner dazu ausgelegt ist, die zweiten seriellen Daten mit einer zweiten Frequenz unter Verwendung einer zweiten Übertragungsleitung, die das Innere und Äußere der hermetisch abgeschlossenen Kammer verbindet, zu übertragen;

    wobei die zweite Frequenz größer als die erste Frequenz ist;

    wobei die erste Übertragungsleitung (101) über eine frequenzabhängige Impedanz mit Masse (102) gekoppelt ist; und

    wobei die erste Übertragungsleitung als Masse für die zweite Übertragungsleitung fungiert.


     
    7. Gerät nach Anspruch 6, wobei die erste Übertragungsleitung (101) über einen Kondensator (104) mit der Masse (102) gekoppelt ist, und wobei der Kondensator (104) eine Kapazität aufweist, die dahingehend ausgewählt ist, Signalintegrität für die Übertragung der ersten seriellen Daten mit der ersten Frequenz aufrecht zu halten.
     
    8. Gerät nach Anspruch 6, wobei die zweite Frequenz um mehrere Größenordnungen größer als die erste Frequenz ist.
     
    9. Gerät nach Anspruch 6, wobei der Prozessor ein FPGA (feldprogrammierbares Gate-Array) aufweist.
     
    10. Gerät nach Anspruch 6, wobei der Transmitter einen LVDS(Low Voltage Differential Signaling)-Treiber aufweist.
     


    Revendications

    1. Procédé pour la transmission de données entre l'intérieur et l'extérieur d'une chambre hermétiquement fermée, comprenant :

    la sérialisation de premières données en premières données sérielles pour la transmission ;

    la transmission des premières données sérielles à une première fréquence en utilisant une première ligne de transmission (101) qui relie l'intérieur et l'extérieur de la chambre hermétiquement fermée ;

    la sérialisation de deuxièmes données en deuxièmes données sérielles pour la transmission ; et

    la transmission des deuxièmes données sérielles à une deuxième fréquence en utilisant une deuxième ligne de transmission (103) qui relie l'intérieur et l'extérieur de la chambre hermétiquement fermée ;

    dans lequel la deuxième fréquence est supérieure à la première fréquence ;

    dans lequel la première ligne de transmission (101) est couplée à la terre (102) via une impédance dépendant de la fréquence ; et

    dans lequel la première ligne de transmission fait office d'une terre pour la deuxième ligne de transmission.


     
    2. Procédé selon la revendication 1, dans lequel la première ligne de transmission (101) est couplée à la terre (102) via un condensateur (104), et dans lequel le condensateur (104) a une capacité sélectionnée pour maintenir une intégrité de signal pour la transmission des premières données sérielles à la première fréquence.
     
    3. Procédé selon la revendication 1, dans lequel la deuxième fréquence est supérieure de plusieurs ordres de grandeur à la première fréquence.
     
    4. Procédé selon la revendication 1, dans lequel la sérialisation est réalisée par un réseau programmable de portes FPGA (field programmable gate array).
     
    5. Procédé selon la revendication 1, dans lequel la transmission est réalisée par un pilote de signalisation différentielle basse tension LVDS (low-voltage differential signaling).
     
    6. Appareil pour la transmission de données entre l'intérieur et l'extérieur d'une chambre hermétiquement fermée, comprenant :

    un processeur configuré pour sérialiser des premières données en premières données sérielles pour la transmission ; et

    un émetteur configuré pour transmettre les premières données sérielles à une première fréquence en utilisant une première ligne de transmission (101) qui relie l'intérieur et l'extérieur de la chambre hermétiquement fermée ;

    dans lequel le processeur est en outre configuré pour sérialiser des deuxièmes données en deuxièmes données sérielles pour la transmission ;

    dans lequel l'émetteur est en outre configuré pour transmettre les deuxièmes données sérielles à une deuxième fréquence en utilisant une deuxième ligne de transmission qui relie l'intérieur et l'extérieur de la chambre hermétiquement fermée ;

    dans lequel la deuxième fréquence est supérieure à la première fréquence ;

    dans lequel la première ligne de transmission (101) est couplée à la terre (102) via une impédance dépendant de la fréquence ; et

    dans lequel la première ligne de transmission fait office d'une terre pour la deuxième ligne de transmission.


     
    7. Appareil selon la revendication 6, dans lequel la première ligne de transmission (101) est couplée à la terre (102) via un condensateur (104), et dans lequel le condensateur (104) a une capacité sélectionnée pour maintenir une intégrité de signal pour la transmission des premières données sérielles à la première fréquence.
     
    8. Appareil selon la revendication 6, dans lequel la deuxième fréquence est supérieure de plusieurs ordres de grandeur à la première fréquence.
     
    9. Appareil selon la revendication 6, dans lequel le processeur comprend un réseau programmable de portes FPGA (field programmable gate array).
     
    10. Appareil selon la revendication 6, dans lequel l'émetteur comprend un pilote de signalisation différentielle basse tension LVDS (low-voltage differential signaling).
     




    Drawing








    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description