(19)
(11)EP 3 291 306 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
30.12.2020 Bulletin 2020/53

(21)Application number: 17180777.9

(22)Date of filing:  11.07.2017
(51)International Patent Classification (IPC): 
H01L 29/778(2006.01)
H01L 29/15(2006.01)
H01L 29/08(2006.01)
H01L 29/20(2006.01)

(54)

COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE COMPOUND SEMICONDUCTOR DEVICE

VERBUNDHALBLEITERBAUELEMENT UND VERFAHREN ZUR HERSTELLUNG EINES VERBUNDHALBLEITERBAUELEMENTS

DISPOSITIF SEMI-CONDUCTEUR COMPOSITE ET SON PROCÉDÉ DE FABRICATION


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 25.08.2016 JP 2016164679

(43)Date of publication of application:
07.03.2018 Bulletin 2018/10

(73)Proprietor: Fujitsu Limited
Kawasaki-shi, Kanagawa 211-8588 (JP)

(72)Inventor:
  • TAKAHASHI, Tsuyoshi
    Kawasaki-shi, Kanagawa 211-8588 (JP)

(74)Representative: Haseltine Lake Kempner LLP 
138 Cheapside
London EC2V 6BJ
London EC2V 6BJ (GB)


(56)References cited: : 
EP-A2- 0 565 054
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    FIELD



    [0001] The present invention relates to a compound semiconductor device and a method of manufacturing a compound semiconductor device.

    BACKGROUND



    [0002] Compound semiconductor devices are divided into various types. Among them, a high electron mobility transistor (HEMT) has advantages of low noise and high-speed operation, and is used in microwave and millimeter-wave amplifiers for these advantages.

    [0003] Since the channel layer of an HEMT is not doped with impurities, no impurity scattering occurs in the channel layer, whereby the mobility of two-dimensional electron gas in the channel layer increases.

    [0004] There are a variety of combinations of the materials for the channel layer and a compound semiconductor substrate.

    [0005] For example, there is a GaAs HEMT in which an i-type InxGa1-xAs (x = 0.1 to 0.2) layer is formed as a channel layer on a GaAs substrate. Such a GaAs HEMT is called a pseudomorphic HEMT (p-HEMT), because the GaAs substrate and the channel layer are pseudo-lattice-matched. In the p-HEMT, In in InxGa1-xAs of the channel layer contributes to further increase in the mobility of two-dimensional electron gas.

    [0006] There is also an InP HEMT, in which an InP substrate is used as a compound semiconductor substrate. The channel layer of an InP HEMT is, for example, an i-type In0.53Ga0.47As layer which is lattice-matched with the InP substrate. For the purpose of increasing the mobility of electrons, an i-type InxGa1-xAs (0.53<x) layer with a higher content ratio of In than the In0.53Ga0.47As layer is used as the channel layer of the InP HEMT in some cases.

    [0007] It was reported that, when an InGaAs layer is reduced in temperature, two-dimensional electron gas is less likely to suffer phonon scattering and therefore increases in mobility. For instance, it was reported that the mobility of two-dimensional electron gas in an In0.53Ga0.47As layer, which is 10,000 cm2/Vs at room temperature (300K), improves to 60,000 cm2/Vs at extremely low temperature (4K).

    [0008] Since mobility in the channel layer of the HEMT thus improves at low temperature, it is contemplated that the HEMT can be used to achieve an amplifier producing low noise at low temperature.

    [0009] Noted that the related techniques are disclosed in the following literature.

    [0010] Japanese Laid-open Patent Publication No. 2008-98674;
    Japanese Examined Laid-open Patent Publication No. Hei 5-4812;
    Matsuoka et al., "Temperature Dependence of Electron Mobility in InGaAs/InAlAs Heterostructures", Japanese Journal of Applied Physics. vol. 29, no. 10, pp. 2017-2025, 1990;
    Akazaki et al., "Kink Effect in an InAs-Inserted-Channel InAlAs/InGaAs Inverted HEMT at Low Temperature", IEEE Electron Device Letters., vol. 17, no. 7, pp. 378-380, 1996;
    Oliver et al., "ELECTRICAL CHARACTERIZATION AND ALLOY SCATTERING MEASUREMENTS OF LPE GaxIn1-xAs/InP FOR HIGH FREQUENCY DEVICE APPLICATIONS", Journal of Crystal Growth 54, pp. 64-68, 1981; and
    EP0565054 A2

    SUMMARY



    [0011] Even when the mobility in the channel layer improves as described above, however, the HEMT cannot exhibit superior amplification performance at low temperature unless low resistivity is achieved in areas other than the channel.

    [0012] The disclosed technique is made in view of the above circumstances, and its purpose is to provide a compound semiconductor device capable of achieving low resistivity and a method of manufacturing a compound semiconductor device.

    [0013] The invention is defined in the independent claims. Optional embodiments are set out in the dependent claims.

    [0014] According to the following disclosure, the n-type second compound semiconductor layer causes electrons to be induced in the first compound semiconductor layer. The electrons travel in the substrate's lateral direction in the i-type first compound semiconductor layers containing no impurities. Thus, the resistances in the first cap layer and the second cap layer do not increase due to impurity scattering, and the resistance of the compound semiconductor device can be maintained to be low.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0015] In the following, the term "example" is used to refer to unclaimed subject-matter whereas the term "embodiment" is used to refer to subject-matter covered by the claims.

    [0016] The invention is described, by way of example only, with reference to the following drawings, in which:

    Fig. 1 is a sectional view of a compound semiconductor device used for study;

    Fig. 2 is a diagram illustrating the energy band structure of the compound semiconductor device in Fig. 1;

    Fig. 3 is a sectional view schematically illustrating the resistances generated in the compound semiconductor device in Fig. 1;

    Fig. 4 is a graph illustrating the temperature dependency of the mobility of holes in InGaAs;

    Figs. 5A to 5M are sectional views of a compound semiconductor device in the course of manufacturing thereof according to a first example;

    Fig. 6 is a diagram illustrating the energy band structure of a first cap layer according to the first example;

    Fig. 7 is a diagram illustrating the band structure of the entire compound semiconductor device according to the first example, taken along the line II-II of Fig. 5M;

    Fig. 8 is a diagram illustrating calculated resistances of the first cap layer according to the first example;

    Figs. 9A to 9E are sectional views of a compound semiconductor device in the course of manufacturing thereof according to a second example;

    Fig. 10A is a diagram illustrating the energy band structure of the first cap layer according to the first example;

    Fig. 10B is a diagram illustrating the energy band structure of a first cap layer according to the second example;

    Figs. 11A to 11C are sectional views of a compound semiconductor device in the course of manufacturing thereof according to a first embodiment;

    Fig. 12 is a diagram illustrating the band structure of the entire compound semiconductor device according to the first embodiment, taken along the line III-III of Fig. 11C;

    Fig. 13 is a diagram illustrating another example of materials for the respective layers of an InP HEMT manufactured as a compound semiconductor device;

    Fig. 14 is a diagram illustrating an example of materials for the respective layers of a GaN HEMT manufactured as a compound semiconductor device; and

    Fig. 15 is a diagram illustrating an example of materials for the respective layers of a GaAs HEMT manufactured as a compound semiconductor device.


    DESCRIPTION OF EMBODIMENTS



    [0017] Prior to describing embodiments, a description is given of matters studied by the inventor of the present application.

    [0018] Fig. 1 is a sectional view of a compound semiconductor device used in this study.

    [0019] This compound semiconductor device 1 is an InP HEMT, and has a buffer layer 3, a channel layer 4, and an electron supply layer 5 formed in this order on an InP substrate 2.

    [0020] Among these layers, the buffer layer 3 plays a role of preventing a defect in the InP substrate 2 from affecting the channel layer 4, and is an i-type InAlAs layer in this example.

    [0021] The channel layer 4 is a layer in which electrons travel, and is an i-type InGaAs layer for example. Since the channel layer 4 is not doped with impurities, mobility of electrons travelling in the channel layer 4 is prevented from being decreased due to impurity scattering.

    [0022] The electron supply layer 5 is a compound semiconductor layer that supplies electrons to the channel layer 4. In this example, the electron supply layer 5 is formed by stacking a spacer layer 5a and a barrier layer 5c in this order, with a doped layer 5b of silicon as n-type impurity formed in their interface. The spacer layer 5a and the barrier layer 5c are both made of i-type InAlAs.

    [0023] According to this structure, two-dimensional electron gas is induced in the channel layer 4 due to the n-type impurities in the doped layer 5b.

    [0024] In addition, since the spacer layer 5a prevents the n-type impurities in the doped layer 5b from diffusing into the channel layer 4, impurity scattering due to the n-type impurities does not occur in the channel layer 4, allowing the mobility of the electrons in the channel layer 4 to be maintained at a high value.

    [0025] Moreover, the barrier layer 5c and a gate electrode to be described later form a Schottky barrier therebetween, by which the transistor's amplification operation is achieved.

    [0026] The electron supply layer 5 may be formed by, after stopping growing the spacer layer 5a, exposing the surface of the spacer layer 5a to a gas containing n-type impurities such as silicon to form the doped layer 5b, and then growing the barrier layer 5c. Such a method of forming the doped layer 5b is also called planar doping.

    [0027] On the electron supply layer 5, a first cap layer 6 and a second cap layer 7 are formed at a distance from each other. Moreover, a source electrode 8 is formed on the first cap layer 6, and a drain electrode 9 is formed on the second cap layer 7.

    [0028] The first cap layer 6 is an n-type compound semiconductor layer provided to reduce the resistance between the electron supply layer 5 and the source electrode 8. The higher the concentration of the n-type impurities in the first cap layer 6, the more the resistance between the electron supply layer 5 and the source electrode 8 is reduced. In this example, the first cap layer 6 is an InGaAs layer heavily doped with silicon as n-type impurities with a concentration of approximately 1×1019cm-3.

    [0029] Note that the second cap layer 7 is formed in the same step as the first cap layer 6, and is, like the first cap layer 6, an InGaAs layer heavily doped with silicon.

    [0030] Then, a gate electrode 10 is formed on the electron supply layer 5 in the area between the cap layers 6 and 7.

    [0031] Fig. 2 is a diagram illustrating the energy band structure of the compound semiconductor device 1.

    [0032] As illustrated in Fig. 2, since the first cap layer 6 is heavily doped with silicon as n-type impurities, carrier concentration of the first cap layer 6 becomes high. Therefore, a large quantity of electrons e can be generated in the first cap layer 6.

    [0033] In addition, the n-type impurities in the doped layer 5b cause two-dimensional electron gas 11 to be induced in the channel layer 4.

    [0034] According to the compound semiconductor device 1, since impurities are not doped in the channel layer 4 as described above, the mobility of the electrons in the channel layer 4 is expected to not decrease due to the impurity scattering. Thus, the noise of drain current is also expected to be reduced.

    [0035] However, Akazaki et al. cited above reported that the source resistance in the HEMT increases at low temperature. According to this report, the source resistance decreases from 1.02 Ωmm to 0.68 Ωmm when the temperature decreases from 300 K to 77 K, but then increases from 0.68 Ωmm to 0.82 Ωm when the temperature further decreases from 77 K to 4.2 K.

    [0036] The reason for this is considered as follows.

    [0037] Fig. 3 is a sectional view schematically illustrating the resistances generated in the compound semiconductor device 1.

    [0038] As depicted in Fig. 3, the compound semiconductor device 1 has a first resistance R1 to a fourth resistances R4, and the source resistance can approximate to the one obtained by connecting the first to fourth resistances R1 to R4 in series.

    [0039] The first resistance R1 is a contact resistance between the first cap layer 6 and the source electrode 8. The second resistance R2 is the resistance of the first cap layer 6 in the substrate's lateral direction.

    [0040] The third resistance R3 is the resistance that electrons experience when overriding a barrier formed by the electron supply layer 5. The fourth resistance R4 is the resistance of the channel layer 4 in the substrate's lateral direction.

    [0041] The inventor of the present application considers that the source resistance increases at extremely low temperature because the second resistance R2, out of the first to fourth resistances R1 to R4, increases at extremely low temperature.

    [0042] Fig. 4 illustrates a reason for this, which depicts a graph illustrating the temperature dependency of the mobility of holes in InGaAs.

    [0043] As illustrated in Fig. 4, factors for causing the mobility decrease include phonon scattering, alloy scattering, and impurity scattering. Among these factors, phonon scattering and alloy scattering decrease as temperature decreases, whereas impurity scattering is prominent at extremely low temperatures.

    [0044] Accordingly, as the temperature of InGaAs is reduced, the increase in mobility is saturated at temperatures around 77K and the mobility then decreases at temperatures below this.

    [0045] In view of this, it can be presumed that the cause for the decrease in the mobility at extremely low temperature is the impurities contained in the compound semiconductor. Among the first to fourth resistances R1 to R4, a resistance generated in an impurity-doped compound semiconductor layer is the second resistance R2, which is generated in the first cap layer 6 doped with n-type impurities.

    [0046] Therefore, it is considered that the increase in the source resistance at low temperature reported in Akazaki et al. is caused by an increase in the second resistance R2 at low temperature.

    [0047] Especially, the first cap layer 6 is heavily doped with n-type impurities with a concentration of approximately 1×1019cm-3 to reduce resistance as described earlier. Therefore, impurity scattering prominently occurs in the first cap layer 6 at extremely low temperature, which presumably increases the second resistance R2 at low temperature.

    [0048] In view of these findings, in the present example, the resistance of a cap layer is decreased so that the source resistance of an HEMT at low temperatures may be maintained to be low as follows.

    (First Example)



    [0049] A compound semiconductor device according to the present example is described while following its manufacturing process.

    [0050] Figs. 5A to 5M are sectional views of the compound semiconductor device in the course of manufacturing thereof according to the present example.

    [0051] In the present example, an InP HEMT is manufactured as a compound semiconductor device as follows.

    [0052] First, as illustrated in Fig. 5A, a compound semiconductor substrate such as an InP substrate is prepared as a substrate 20.

    [0053] Then, while placing the substrate 20 in an unillustrated chamber, an i-type InAlAs layer is formed as a buffer layer 21 to a thickness of about 300 nm on the substrate 20 by metal organic chemical vapor deposition (MOCVD) method.

    [0054] Growth gas used for the formation of the InAlAs layer is not particularly limited. For example, a material gas for In is trimethylindium ((CH3)3In) or triethylindium ((C2H5) 3In). A material gas for Al is trimethylaluminum ((CH3)3Al) or triethylaluminum ((C2H5)3Al). A material gas for As is arsine (AsH3).

    [0055] Moreover, the composition ratio of the InAlAs layer is not particularly limited. In the present example, an In0.52Al0.48As layer that lattice-matches with the InP substrate used as the substrate 20 is formed as the buffer layer 21.

    [0056] Such a composition ratio and material gas for the InAlAs layer described above also apply to other InAlAs layers to be formed in the subsequent steps.

    [0057] Then, while keeping the substrate 20 still in the chamber, an i-type InGaAs layer is formed on the buffer layer 21 to a thickness of about 15 nm by MOCVD method, and the InGaAs layer is used as a channel layer 22.

    [0058] Growth gas for this InGaAs layer is not particularly limited, ether. A material gas for In is trimethylindium or triethylindium, a material gas for Ga is trimethylgallium ((CH3)3Ga) or triethylgallium ((C2H5)3Ga). Also, a material gas for As is arsine.

    [0059] Also, the composition ratio of the InGaAs layer is In0.53Ga0.48As that lattice-matches with InP which is the material for the substrate 20.

    [0060] Such a composition ratio and material gas for the InGaAs layer described above also apply to other InGaAs layers to be formed in the subsequent steps.

    [0061] Next, a description is given of the step illustrated in Fig. 5B.

    [0062] First, while using the chamber used in the above, an i-type InAlAs layer is formed to a thickness of about 3 nm on the channel layer 22 by MOCVD method with the chamber being supplied with the same growth gas as used for the buffer layer 21. This i-type InAlAs layer is used as a spacer layer 23a.

    [0063] Then, the supply of the growth gas is temporally stopped, and the chamber is supplied with silane (SiH4) or disilane (Si2H6), which is a material gas for silicon. As a result, an n-type doped layer 23b is formed in the surface of the spacer layer 23a by planar doping. The doped layer 23b is doped with silicon as n-type impurities with a concentration of approximately 5×1012cm-2.

    [0064] Thereafter, while supplying the growth gas for an InAlAs layer to the above chamber again, an i-type InAlAs layer is formed as a barrier layer 23c to a thickness of about 10 nm on the doped layer 23b by MOCVD method.

    [0065] With the above steps, an electron supply layer 23 is formed by stacking the spacer layer 23a, the n-type doped layer 23b, and the barrier layer 23c in this order.

    [0066] According to the electron supply layer 23 with such a layered structure, like that in the example illustrated in Fig. 1, the spacer layer 23a can prevent the n-type impurities in the doped layer 23b from diffusing into the channel layer 22, and a Schottky barrier can be formed between the barrier layer 23c and a gate electrode to be described later.

    [0067] Note that when these advantages are not necessary, a single layered n-type InAlAs layer may be formed as the electron supply layer 23.

    [0068] Next, as illustrated in Fig. 5C, i-type first compound semiconductor layers 24 and n-type second compound semiconductor layers 25 are alternately stacked in this order on the electron supply layer 23 by MOCVD method in the above chamber to form a stacked film 26 of the first compound semiconductor layers 24 and the second compound semiconductor layers 25.

    [0069] In the present example, materials for the first compound semiconductor layers 24 and the second compound semiconductor layers 25 are selected so that the second compound semiconductor layers 25 have a wider bandgap than those of the first compound semiconductor layers 24.

    [0070] There exist several combinations of materials to achieve this. In the following example, the first compound semiconductor layers 24 are InGaAs layers, and the second compound semiconductor layers 25 are InAlAs layers that are uniformly doped with silicon as n-type impurities with a concentration of about 1×1019cm-2.

    [0071] To dope an InAlAs layer with silicon, a silane-based gas, such as silane or disilane, may be added to the aforementioned growth gas for InAlAs. To control the doping amount of silicon in the InAlAs layer, the flow rate of the silane-based gas may be adjusted.

    [0072] The bandgaps of the compound semiconductor layers 24 and 25 depend on their composition ratios. In the case where an i-type In0.53Ga0.48As layer is formed as the first compound semiconductor layer 24, the bandgap of the In0.53Ga0.48As layer is 0.74 eV. In the case where an n-type In0.52Al0.48As layer is formed as the second compound semiconductor layer 25, the bandgap of the In0.52Al0.48As layer is 1.46 eV.

    [0073] The film thicknesses of the compound semiconductor layers 24 and 25 are not particularly limited, either. In the present example, the compound semiconductor layers 24 and 25 are each approximately 5 nm thick. A structure in which the compound semiconductor layers 24 and 25 as thin as approximately 5 nm are stacked in this manner is also called a superlattice structure.

    [0074] The number of the compound semiconductor layers 24 and the number of the compound semiconductor layers 25 are not particularly limited, either. In this example, the stacked film 26 includes six first compound semiconductor layers 24 and five second compound semiconductor layers 25. Then, the first compound semiconductor layers 24 are disposed at the uppermost layer and the lowermost layer of the stacked film 26.

    [0075] Although the In0.53Ga0.48As layer of the first compound semiconductor layer 24 and the In0.52Al0.48As layer of the second compound semiconductor layer 25 are lattice-matched with each other, the lattice matching may be not needed when the first compound semiconductor layer 24 and the second compound semiconductor layer 25 have different bandgap.

    [0076] Next, as illustrated in Fig. 5D, a photoresist is applied to the stacked film 26 to form a first resist layer 30 by exposing and developing the photoresist.

    [0077] Then, as illustrated in Fig. 5E, while using the first resist layer 30 as a mask, the channel layer 22, the electron supply layer 23, and the stacked film 26 are wet-etched to form a device isolation trench 29 in these layers.

    [0078] Etching liquid used for this wet etching is not particularly limited. For example, a mixed solution of phosphoric acid and hydrogen peroxide solution may be used as the etching liquid.

    [0079] Thereafter, the first resist layer 30 is removed.

    [0080] Subsequently, as illustrated in Fig. 5F, a photoresist is applied to the entire upper surface of the substrate 20. Then, the photoresist is exposed and developed, thereby forming a second resist layer 31 including a first opening 31a and a second opening 31b.

    [0081] Next, as illustrated in Fig. 5G, a metal stacked film 33 is formed on the second resist layer 31 and in the openings 31a and 31b by vapor deposition. The metal stacked film 33 is formed by stacking, for example, a titanium layer of about 10 nm thickness, platinum layer of about 30 nm thickness, and a gold layer of about 300 nm thickness in this order.

    [0082] Next, as illustrated in Fig. 5H, the second resist layer 31 is removed with an organic solution, so that the metal stacked film 33 formed in the first opening 31a and the second opening 31b are left on the stacked film 26 as a source electrode 33a and a drain electrode 33b, respectively. Such a method of patterning the metal stacked film 33 is called liftoff process.

    [0083] Then, as illustrated in Fig. 5I, an electron beam resist is applied to the entire upper surface of the substrate 20. The resist is exposed to an electron beam, and then developed to be formed into a third resist layer 35 including a third opening 35a between the source electrode 33a and the drain electrode 33b.

    [0084] Then, as illustrated in Fig. 5J, the stacked film 26 is wet-etched through the third opening 35a to be patterned, thereby forming a groove 26x in the stacked film 26 under the third opening 35a.

    [0085] As a result of this patterning, the stacked film 26 under the source electrode 33a is left as a first cap layer 26a, and the stacked film 26 under the drain electrode 33b is left as a second cap layer 26b, with these cap layers 26a and 26b being separated by the groove 26x.

    [0086] Thereafter, the third resist layer 35 is removed.

    [0087] Next, a description is given of the step illustrated in Fig. 5K.

    [0088] First, fourth to sixth electron-beam resist layers 41 to 43 are formed in this order on the entire upper surface of the substrate 20.

    [0089] Then, the sixth resist layer 43 is exposed to an electron beam and then developed to form a fourth opening 43a. Furthermore, the fifth resist layer 42 is wet-etched through the fourth opening 43a, thereby forming a fifth opening 42a therein whose side surface is recessed than the fourth opening 43a.

    [0090] Then, a portion of the fourth resist layer 41 that is exposed through the fifth opening 42a is exposed to an electron beam and then developed, so that a hole 41a is formed in the fourth resist layer 41 in the groove 26x.

    [0091] Next, as illustrated in Fig. 5L, a metal stacked film 45 is formed on the sixth resist layer 43 by vapor deposition. The metal stacked film 45 is formed by stacking a titanium layer of about 10nm thickness, a platinum layer of about 30nm thickness, and a gold layer of about 300nm thickness.

    [0092] The metal laminated film 45 is also formed in the hole 41a and the openings 42a and 43a, whereby a T shaped gate electrode 45a is formed on the electron supply layer 23.

    [0093] Thereafter, as illustrated in Fig. 5M, the resist layers 41 to 43 are dissolved with an organic solution to be removed.

    [0094] With this, the basic structure of a compound semiconductor device 50 according to the present example is complete.

    [0095] In the compound semiconductor device 50, the first compound semiconductor layers 24 and the second compound semiconductor layers 25 having different bandgaps from each other are stacked to form the first cap layer 26a having a superlattice structure.

    [0096] Fig. 6 is a diagram illustrating the energy band structure of the first cap layer 26a.

    [0097] As illustrated in Fig. 6, the second compound semiconductor layer 25 is uniformly doped with silicon as n-type impurities 25x, and the n-type impurities 25x cause electrons e to be induced in the first compound semiconductor layer 24.

    [0098] Moreover, since the compound semiconductor layers 24 and 25 have different bandgaps from each other, a quantum well is formed in the first cap layer 26a.

    [0099] Most of the electrons e in the first cap layer 26a are trapped in the quantum well, and take discrete energy E in the quantum well. The electrons e travel freely in the first compound semiconductor layers 24 in the substrate's lateral direction by the momentum corresponding to the energy E.

    [0100] As a result, unlike the example in Fig. 1, most of the electrons travelling in the first cap layer 26a in the substrate's lateral direction are not scattered by the n-type impurities 25x. Therefore, the resistance of the first cap layer 26a can be prevented from increasing at low temperature due to impurity scattering.

    [0101] Moreover, by providing a plurality of n-type second compound semiconductor layers 25 in this manner, more electrons can be induced in the first compound semiconductor layers 24 than in the case of only one second compound semiconductor layer 25 is provided, thus making it possible to lower the sheet resistance of the first cap layer 26a.

    [0102] Still further, since film thickness of the second compound semiconductor layer 25 is thin, the electrons e can easily tunnel through the second compound semiconductor layer 25. Thus, the electrons e can also easily flow in the thickness direction of the first cap layer 26a. Moreover, since the tunneling current is not scattered by the n-type impurities 25x, the resistance of the first cap layer 26a in its thickness direction can also be maintained to be low.

    [0103] In order for the electrons e to be able to easily tunnel through the second compound semiconductor layer 25, it is preferable to thin the second compound semiconductor layer 25 to the thickness of about 5 nm to 10 nm.

    [0104] Moreover, in order for the electrons e to take the discrete energy E in the quantum well as described above, it is preferable to thin the first compound semiconductor layer 24 to the thickness of about 5 nm to 10 nm.

    [0105] Furthermore, for the same reason that the resistance of the first cap layer 26a can be reduced, resistance of the second cap layer 26b, which has the same structure as the first cap layer 26a, can also be reduced.

    [0106] Fig. 7 is a diagram illustrating the band structure of the entire compound semiconductor device 50, taken along the line II-II in Fig. 5M.

    [0107] As illustrated in Fig. 7, in the compound semiconductor device 50, two-dimensional electron gas 51 is generated in the channel layer 22 when the electrons e generated in the electron supply layer 23 reach the channel layer 22.

    [0108] Then, since the resistance of the first cap layer 26a is reduced at low temperature as described above, the source resistance generated between the source electrode 33a and the channel layer 22 can also be reduced at low temperature.

    [0109] Especially, in the present example, the first compound semiconductor layer 24, which has a narrower bandgap than the second compound semiconductor layer 25, is provided as the uppermost layer of the first cap layer 26a. Therefore, a barrier ΔE1 between the first cap layer 26a and the source electrode 33a can be lowered. This allows smooth supply of electrons from the source electrode 33a to the first cap layer 26a, enabling further decrease in the source resistance of the compound semiconductor device 50.

    [0110] Furthermore, the first compound semiconductor layer 24, which has the narrower bandgap, is provided as the lowermost layer of the first cap layer 26a. Therefore, electron injection from the first cap layer 26a to the electron supply layer 23 is not obstructed by the second compound semiconductor layer 25, which has the wider bandgap. This allows smooth supply of electrons from the first cap layer 26a to the electron supply layer 23, enabling further decrease in the source resistance of the compound semiconductor device 50.

    [0111] The inventor of the present invention calculated the resistance of the first cap layer 26a according to the present example.

    [0112] Fig. 8 illustrates the calculation results.

    [0113] Note that in this calculation, the first cap layer 6 in Fig. 1 was used as a comparative example, and the resistance of the first cap layer 6 was also calculated. As described with reference to Fig. 1, the first cap layer 6 is a single n-type InGaAs layer.

    [0114] Moreover, the number of the second compound semiconductor layers 25 of the present example is one for the calculation of mobility, and five for the calculation of sheet resistance.

    [0115] As illustrated in Fig. 8, electron mobility at room temperature (300K) is 2,000 cm2/Vs in the comparative example and is 10,000 cm2/Vs in the present example. Thus, it was revealed that the present example has higher mobility even at room temperature.

    [0116] Note that in the comparative example, electron mobility at extremely low temperature (4K) is 2,500 cm2/Vs, which is higher than the value 2,000 cm2/Vs at room temperature (300K).

    [0117] On the contrary, in the present example, electron mobility at extremely low temperature (4K) is 60,000 cm2/Vs. Thus, it was revealed that increase from the mobility at room temperature (10,000 cm2/Vs) greatly increases than that in the comparative example.

    [0118] The sheet resistance at room temperature (300K) is substantially the same in the present example and the comparative example.

    [0119] However, the sheet resistance at extremely low temperature (4K) is 10.4 Ω/square in the present example, which is lower than that in the comparative example (49.9 Ω/square).

    [0120] The percentage of the ratio of the sheet resistance at room temperature (300K) to the sheet resistance at extremely low temperature (4K) is approximately 80% in the comparative example, whereas it is 17% in the present example, which is markedly smaller than that of the comparative example.

    [0121] It was confirmed by the above results that the superlattice structure of the first cap layer 26a as in the present example is effective for reducing the resistance of the first cap layer 26a at extremely low temperatures such as 4K.

    [0122] Since resistance can be reduced at extremely low temperature in this manner, the compound semiconductor device 50 according to the present example produces low noise at extremely low temperature. Thus, when using the compound semiconductor device 50 for an amplifier of a radio telescope for example, observation results with very little noise can be obtained by cooling the compound semiconductor device 50 down to extremely low temperature.

    (Second Example)



    [0123] In the present example, the resistance of the first cap layer 26a is further reduced as follows.

    [0124] Figs. 9A to 9E are sectional views of a compound semiconductor device in the course of manufacturing thereof according to the present example. Note in Figs. 9A to 9E that the same elements as those in the first example are denoted by the same reference numerals as in the first example, and their explanations are omitted below.

    [0125] First, as illustrated in Fig. 9A, by performing the steps of Figs. 5A and 5B of the first example, a structure in which the buffer layer 21, the channel layer 22, and the electron supply layer 23 are stacked in this order on the substrate 20 is formed.

    [0126] Then, as illustrated in Fig. 9B, the i-type first compound semiconductor layer 24 is formed on the electron supply layer 23 to a thickness of about 5nm.

    [0127] The first compound semiconductor layer 24 is an i-type InGaAs layer formed by MOCVD method as in the first example.

    [0128] Next, a description is given of the step illustrated in Fig. 9C.

    [0129] First, growth gas for an InAlAs is supplied to the unillustrated chamber used for the formation of the first compound semiconductor layer 24. Thus, an i-type InAlAs layer is formed on the first compound semiconductor layer 24 by MOCVD method to a thickness of about 2.5 nm as a lower layer 25a of the second compound semiconductor layer 25.

    [0130] As described in the first example, the growth gas for the InAlAs layer includes trimethylindium or triethylindium as the material gas for In. The growth gas also includes trimethylaluminum or triethylaluminum as the material gas for Al. Further, the growth gas includes arsine for the material gas for As.

    [0131] Then, the supply of the growth gas to the chamber is temporally stopped, and then the chamber is supplied with a material gas for silicon such as silane and disilane, thereby exposing the surface of the lower layer 25a to the material gas for silicon. Thus, an n-type doped layer 25b is formed in the surface of the lower layer 25a by planar doping. The doped layer 25b is doped with silicon as n-type impurities with a concentration of about 5×1012cm-2.

    [0132] Thereafter, the growth gas for the InAlAs layer is again supplied to the chamber, thereby forming an i-type InAlAs layer on the doped layer 25b to a thickness of about 2.5nm as an upper layer 25c by MOCVD method.

    [0133] By these steps, the second compound semiconductor layer 25 in which the n-type impurities are localized in the doped layer 25b formed at the interface between the lower layer 25a and the upper layer 25c is obtained.

    [0134] Next, as illustrated in Fig. 9D, the above first compound semiconductor layers 24 and the second compound semiconductor layers 25 are alternately stacked to form the stacked film 26.

    [0135] After that, as illustrated in Fig. 9E, by performing the steps of Figs. 5D to 5M described in the first example, the basic structure of a compound semiconductor device 60 according to the present example is completed.

    [0136] According to the present example described above, as depicted in Fig. 9C, the second compound semiconductor layer 25 has a stacked structure of the lower layer 25a and the upper layer 25c which are both i-type, and the n-type impurities are localized in the doped layer 25b that are formed at the interface between the lower layer 25a and the upper layer 25c.

    [0137] Fig. 10A is a diagram illustrating the energy band structure of the first cap layer 26a according to the first example, and Fig. 10B is a diagram illustrating the energy band structure of the first cap layer 26a according to the present example.

    [0138] As illustrated in Fig. 10A, since the bandgap difference ΔEg between the compound semiconductor layers 24 and 25 is finite, the tails of the wave function ϕ of the electron e overlap with the second compound semiconductor layers 25. Thus, the electrons e exist in the second compound semiconductor layers 25 with a certain probability. In the first example, the electrons in the second compound semiconductor layer 25 are scattered due to the n-type impurities 25x uniformly distributed over the second compound semiconductor layer 25.

    [0139] On the contrary, in the present example as illustrated in Fig. 10B, the tail of the wave function ϕ of the electron e overlaps with the second compound semiconductor layers 25 as well for the aforementioned reason. Thus, the electrons e exist in the second compound semiconductor layers 25 with a certain probability.

    [0140] However, since the n-type impurities 25x are localized at the interface between the lower layer 25a and the upper layer 25c in the present example, the tail of the wave function ϕ of the electron e is less likely to overlap with the n-type impurities 25x

    [0141] Hence, the electrons e existing in the second compound semiconductor layer 25 are less likely to be scattered due to the n-type impurities 25x, which makes it possible to increase the mobility of the electrons in the first cap layer 26a than the first example.

    [0142] Especially, when the lower layer 25a and the upper layer 25c have the same film thickness, the n-type impurities 25x can be equally positioned away from the wave functions ϕ on both sides of the second compound semiconductor layer 25. As a result, the electrons e existing in both the upper surface and the lower surface of the second compound semiconductor layer 25 are less likely to be scattered due to the n-type impurities 25x, which makes it possible to further increase the electron mobility.

    (First Embodiment)



    [0143] In the present embodiment, the source resistance is further reduced as follows.

    [0144] Figs. 11A to 11C are sectional views of a compound semiconductor device in the course of manufacturing thereof according to the present embodiment. Note in Figs. 11A to 11C that the same elements as those in the first example are denoted by the same reference numerals as in the first example, and their explanations are omitted below.

    [0145] First, as illustrated in Fig. 11A, by performing the steps of Figs. 5A and 5B in the first example, a structure in which the buffer layer 21, the channel layer 22, and the electron supply layer 23 are stacked in this order on the substrate 20 is formed.

    [0146] Next, as illustrated in Fig. 11B, by alternately switching growth gases in the same chamber that is used for forming the electron supply layer 23, the i-type first compound semiconductor layers 24 and the n-type second compound semiconductor layers 25 are alternately stacked to form the stacked film 26.

    [0147] Of these compound semiconductor layers, the i-type first compound semiconductor layer 24 is InGaAs layer with the thickness of 5nm.

    [0148] Moreover, the n-type second compound semiconductor layer 25 is, as in the first example, InAlAs layer with the thickness of 5nm, in which silicon is doped with a concentration of about 1×1019cm-2 as n-type impurities.

    [0149] However, the Al composition ratio in the InAlAs layer is made lowered toward the uppermost layer of the stacked film 26 in the present embodiment, thereby making bandgap of the second compound semiconductor layer 25 narrower toward the uppermost layer of the stacked film 26. In order to reduce the Al composition ratio in this manner, the flow rate ratio of the material gas for Al, such as trimethylaluminum and triethylaluminum, in the growth gas for the second compound semiconductor layer 25 may be lowered.

    [0150] In this example, the stacked film 26 includes five second compound semiconductor layers 25. Among these layers, the first to third compound semiconductor layers 25 from the uppermost layer are made of In0.65Al0.35As, In0.60Al0.40As, and In0.55Al0.45As, respectively. Then, the remaining two second compound semiconductor layers 25 are all made of In0.52Al0.48As.

    [0151] Thereafter, by performing the steps of Figs. 5D to 5M described in the first example, the basic structure of a compound semiconductor device 70 according to the present embodiment is completed, as illustrated in Fig. 11C.

    [0152] According to the present embodiment described above, the bandgaps of the second compound semiconductor layers 25 in the first cap layer 26a are made narrower toward the uppermost layer of the first cap layer 26a.

    [0153] Fig. 12 is a diagram illustrating the band structure of the entire compound semiconductor device 70 taken along the line III-III in Fig. 11C.

    [0154] As illustrated in Fig. 12, as the result of making the bandgaps of the second compound semiconductor layers 25 in the first cap layer 26a narrower toward the uppermost layer of the first cap layer 26a, the height ΔE2 of the barrier between the source electrode 33a and the uppermost second compound semiconductor layer 25 can be reduced.

    [0155] As a result, the ohmic contact resistance generated between the source electrode 33a and the first cap layer 26a is reduced, thereby making it possible to further reduce the source resistance.

    [0156] Note that although the n-type second compound semiconductor layer 25 is uniformly doped with the n-type impurities in the above, the n-type second compound semiconductor layer 25 may be doped with n-type impurities by planar doping as in the second example.

    (Other Examples)



    [0157] In the first to second examples and the first embodiment, the InP HEMT is manufactured as the compound semiconductor device. However, the materials for the layers in the InP HEMT are not limited to the above. Further, the compound semiconductor device is not limited to the InP HEMT.

    [0158] Variations of the compound semiconductor device and the materials for its layers are described.

    <InP HEMT>



    [0159] Fig. 13 is a diagram illustrating another example of materials for the layers of an InP HEMT that is manufactured as the compound semiconductor device in the same process as in the first to second example and the first embodiment.

    [0160] As illustrated in Fig. 13, the first compound semiconductor layer 24 may be made of i-type InAs, instead of i-type InGaAs described in the first example. In this case, the second compound semiconductor layer 25 may be formed of either n-type InAlAs or n-type InGaAs.

    <GaN HEMT>



    [0161] Fig 14 is a diagram illustrating an example of materials for the layers of a GaN HEMT manufactured as the compound semiconductor device.

    [0162] A GaN HEMT is an HEMT having a GaN layer as the channel layer 22. In this case, a GaN substrate may be used as the substrate 20, and n-type AlGaN may be used as the material for the electron supply layer 23. Moreover, the first compound semiconductor layer 24 may be, for example, i-type InGaN, and the second compound semiconductor layer 25 may be n-type GaN or n-type AlGaN.

    <GaAs HEMT>



    [0163] Fig 15 is a diagram illustrating an example of materials for the layers of a GaAs HEMT manufactured as the compound semiconductor device.

    [0164] A GaAs HEMT is an HEMT having a GaAs layer as the channel layer 22. In this case, a GaAs substrate may be used as the substrate 20, and n-type AlGaAs may be used as the material for the electron supply layer 23. Moreover, the first compound semiconductor layer 24 may be, for example, i-type GaAs or i-type InGaAs, and the second compound semiconductor layer 25 may be n-type AlGaAs.


    Claims

    1. A compound semiconductor device comprising:

    a substrate (20);

    a channel layer (22) formed over the substrate (20);

    an electron supply layer (23) formed on the channel layer (22);

    a first cap layer (26a) and a second cap layer (26b) formed at a distance from each other on the electron supply layer (23);

    a source electrode (33a) formed on the first cap layer (26a) ;

    a drain electrode (33b) formed on the second cap layer (26b); and

    a gate electrode (45a) formed on the electron supply layer (23) between the first cap layer (26a) and the second cap layer (26b), wherein

    each of the first cap layer (26a) and the second cap layer (26b) is a stacked film formed by alternately stacking i-type first compound semiconductor layers (24) and n-type second compound semiconductor layers (25) having a wider bandgap than the first compound semiconductor layers (24), and characterized in that

    the bandgaps of the second compound semiconductor layers (25) become harrower toward an uppermost layer of the stacked film (26).


     
    2. The compound semiconductor device according to claim 1, wherein
    each of the second compound semiconductor layers (25) include:

    a lower layer (25a) made of an i-type compound semiconductor, and

    an upper layer (25c) formed on the lower layer (25c) and made of the i-type compound semiconductor, wherein

    n-type impurities are localized at an interface between the lower layer (25a) and the upper layer (25c).


     
    3. The compound semiconductor device according to claim 2, wherein
    the lower layer (25a) and the upper layer (25c) have the same thickness.
     
    4. The compound semiconductor device according to claim 1, wherein
    an uppermost layer of the stacked film (26) is the first compound semiconductor layer (24).
     
    5. The compound semiconductor device according to any preceding claim, wherein
    a lowermost layer of the stacked film (26) is the first compound semiconductor layer (24).
     
    6. A method of manufacturing a compound semiconductor device, the method comprising:

    forming a channel layer (22) over a substrate (20);

    forming an electron supply layer (23) on the channel layer (22);

    alternately forming i-type first compound semiconductor layers (24) and n-type second compound semiconductor layers (25) having a wider bandgap than the first compound semiconductor layers (24) on the electron supply layer (23) to form a stacked film (26) of the first compound semiconductor layers (24) and the second compound semiconductor layers (25);

    patterning the stacked film (26) to form a first cap layer (26a) and a second cap layer (26b) at a distance from each other;

    forming a source electrode (33a) on the first cap layer (26a) ;

    forming a drain electrode (33b) on the second cap layer (26b); and

    forming a gate electrode (45a) on the electron supply layer (23) between the first cap layer (26a) and the second cap layer (26b), characterized in that

    the bandgaps of the second compound semiconductor layers (25) become harrower toward an uppermost layer of the stacked film (26).


     
    7. The method of manufacturing a compound semiconductor device according to claim 6, wherein
    the forming of each of the second compound semiconductor layers (25) includes:

    forming a lower layer (25a) made of an i-type compound semiconductor,

    exposing a surface of the lower layer (25a) to a gas containing an n-type impurity, and

    after exposing the surface of the lower layer (25a) to the gas, forming an upper layer (25c) made of the i-type compound semiconductor on the surface to make the lower layer (25a) and the upper layer (25c) into the second compound semiconductor layer (25).


     
    8. The method of manufacturing the compound semiconductor device according to claim 7, wherein
    the lower layer (25a) and the upper layer (25c) have the same thickness.
     


    Ansprüche

    1. Verbundhalbleitervorrichtung umfassend:

    ein Substrat (20);

    eine Kanalschicht (22), die über dem Substrat (20) gebildet ist;

    eine Elektronenversorgungsschicht (23), die auf der Kanalschicht (22) gebildet ist;

    eine erste Abdeckschicht (26a) und eine zweite Abdeckschicht (26b), die in einer Distanz voneinander auf der Elektronenversorgungsschicht (23) gebildet sind;

    eine Source-Elektrode (33a), die auf der ersten Abdeckschicht (26a) gebildet ist;

    eine Drain-Elektrode (33b), die auf der zweiten Abdeckschicht (26b) gebildet ist; und

    eine Gate-Elektrode (45a), die auf der Elektronenversorgungsschicht (23) zwischen der ersten Abdeckschicht (26a) und der zweiten Abdeckschicht (26b) gebildet ist, wobei

    jede der ersten Abdeckschicht (26a) und der zweiten Abdeckschicht (26b) ein gestapelter Film ist, der durch abwechselndes Stapeln von ersten i-Typ-Verbundhalbleiterschichten (24) und zweiten n-Typ-Verbundhalbleiterschichten (25), die eine größere Bandlücke als die ersten Verbundhalbleiterschichten (24) aufweisen, gebildet wird, und dadurch gekennzeichnet, dass

    die Bandlücken der zweiten Verbundhalbleiterschichten (25) zu einer obersten Schicht des gestapelten Films (26) hin schmaler werden.


     
    2. Verbundhalbleitervorrichtung nach Anspruch 1, wobei jede der zweiten Verbundhalbleiterschichten (25) Folgendes aufweist:

    eine untere Schicht (25a), die aus einem i-Typ-Verbundhalbleiter hergestellt ist, und

    eine obere Schicht (25c), die auf der unteren Schicht (25c) gebildet ist und aus dem i-Typ-Verbundhalbleiter hergestellt ist, wobei

    n-Typ-Verunreinigungen an einer Schnittstelle zwischen der unteren Schicht (25a) und der oberen Schicht (25c) liegen.


     
    3. Verbundhalbleitervorrichtung nach Anspruch 2, wobei
    die untere Schicht (25a) und die obere Schicht (25c) dieselbe Dicke aufweisen.
     
    4. Verbundhalbleitervorrichtung nach Anspruch 1, wobei
    eine oberste Schicht des gestapelten Films (26) die erste Verbundhalbleiterschicht (24) ist.
     
    5. Verbundhalbleitervorrichtung nach einem der vorherigen Ansprüche, wobei eine unterste Schicht des gestapelten Films (26) die erste Verbundhalbleiterschicht (24) ist.
     
    6. Verfahren zur Herstellung einer Verbundhalbleitervorrichtung, wobei das Verfahren Folgendes umfasst:

    Bilden einer Kanalschicht (22) über einem Substrat (20);

    Bilden einer Elektronenversorgungsschicht (23) auf der Kanalschicht (22);

    abwechselndes Bilden von ersten i-Typ-Verbundhalbleiterschichten (24) und zweiten n-Typ-Verbundhalbleiterschichten (25), die eine größere Bandlücke als die ersten Verbundhalbleiterschichten (24) auf der Elektronenversorgungsschicht (23) aufweisen, um einen gestapelten Film (26) der ersten Verbundhalbleiterschichten (24) und der zweiten Verbundhalbleiterschichten (25) zu bilden;

    Strukturieren des gestapelten Films (26), um eine erste Abdeckschicht (26a) und eine zweite Abdeckschicht (26b) in einer Distanz voneinander zu bilden;

    Bilden einer Source-Elektrode (33a) auf der ersten Abdeckschicht (26a);

    Bilden einer Drain-Elektrode (33b) auf der zweiten Abdeckschicht (26b); und

    Bilden einer Gate-Elektrode (45a) auf der Elektronenversorgungsschicht (23) zwischen der ersten Abdeckschicht (26a) und der zweiten Abdeckschicht (26b), dadurch gekennzeichnet, dass

    die Bandlücken der zweiten Verbundhalbleiterschichten (25) zu einer obersten Schicht des gestapelten Films (26) hin schmaler werden.


     
    7. Verfahren zur Herstellung einer Verbundhalbleitervorrichtung nach Anspruch 6, wobei
    das Bilden von jeder der zweiten Verbundhalbleiterschichten (25) Folgendes umfasst:

    Bilden einer unteren Schicht (25a), die aus einem i-Typ-Verbundhalbleiter hergestellt ist,

    Aussetzen einer Fläche der unteren Schicht (25a) gegenüber einem Gas, das eine n-Typ-Verunreinigung enthält, und

    nach dem Aussetzen der Fläche der unteren Schicht (25a) gegenüber dem Gas, Bilden einer oberen Schicht (25c), die aus dem i-Typ-Verbundhalbleiter hergestellt ist, auf der Fläche, um die untere Schicht (25a) und die obere Schicht (25c) in die zweite Verbundhalbleiterschicht (25) umzuwandeln.


     
    8. Verfahren zur Herstellung der Verbundhalbleitervorrichtung nach Anspruch 7, wobei
    die untere Schicht (25a) und die obere Schicht (25c) dieselbe Dicke aufweisen.
     


    Revendications

    1. Dispositif à semi-conducteur composé comprenant :

    un substrat (20) ;

    une couche de canal (22) formée par-dessus le substrat (20) ;

    une couche d'alimentation en électrons (23) formée sur la couche de canal (22) ;

    une première couche de revêtement (26a) et une seconde couche de revêtement (26b) formées à une distance l'une de l'autre sur la couche d'alimentation en électrons (23) ;

    une électrode source (33a) formée sur la première couche de revêtement (26a) ;

    une électrode de drain (33b) formée sur la seconde couche de revêtement (26b) ; et

    une électrode de grille (45a) formée sur la couche d'alimentation en électrons (23) entre la première couche de revêtement (26a) et la seconde couche de revêtement (26b), dans lequel

    chacune de la première couche de revêtement (26a) et de la seconde couche de revêtement (26b) est un film empilé formé en empilant alternativement des premières couches de semi-conducteur composé de type i (24) des secondes couches de semi-conducteur composé de type n (25) ayant un intervalle de bande plus large que les premières couches de semi-conducteur composé (24), et caractérisé en ce que

    les intervalles de bande des secondes couches de semi-conducteur composé (25) deviennent plus étroits vers une couche supérieure du film empilé (26).


     
    2. Dispositif à semi-conducteur composé selon la revendication 1, dans lequel
    chacune des secondes couches de semi-conducteur composé (25) comprend :

    une couche inférieure (25a) composée d'un semi-conducteur composé de type i, et

    une couche supérieure (25c) formée sur la couche inférieure (25c) et composée du semi-conducteur composé de type i, dans lequel

    des impuretés de type n sont localisées au niveau d'une interface entre la couche inférieure (25a) et la couche supérieure (25c).


     
    3. Dispositif à semi-conducteur composé selon la revendication 2, dans lequel
    la couche inférieure (25a) et la couche supérieure (25c) possèdent la même épaisseur.
     
    4. Dispositif à semi-conducteur composé selon la revendication 1, dans lequel
    une couche supérieure du film empilé (26) est la première couche de semi-conducteur composé (24).
     
    5. Dispositif à semi-conducteur composé selon l'une quelconque des revendications précédentes, dans lequel
    une couche inférieure du film empilé (26) est la première couche de semi-conducteur composé (24).
     
    6. Procédé de fabrication d'un dispositif à semi-conducteur composé, le procédé comprenant :

    la formation d'une couche de canal (22) par-dessus un substrat (20) ;

    la formation d'une couche d'alimentation en électrons (23) sur la couche de canal (22) ;

    la formation alternée de premières couches de semi-conducteur composé de type i (24) et de secondes couches de semi-conducteur composé de type n (25) ayant un intervalle de bande plus large que les premières couches de semi-conducteur composé (24) sur la couche d'alimentation en électrons (23) afin de former un film empilé (26) des premières couches de semi-conducteur composé (24) et des secondes couches de semi-conducteur composé (25) ;

    la gravure du film empilé (26) afin de former une première couche de revêtement (26a) et une seconde couche de revêtement (26b) à une distance l'une de l'autre ;

    la formation d'une électrode source (33a) sur la première couche de revêtement (26a) ;

    la formation d'une électrode de drain (33b) sur la seconde couche de revêtement (26b) ; et

    la formation d'une électrode de grille (45a) sur la couche d'alimentation en électrons (23) entre la première couche de revêtement (26a) et la seconde couche de revêtement (26b), caractérisé en ce que

    les intervalles de bande des secondes couches de semi-conducteur composé (25) deviennent plus étroits vers une couche supérieure du film empilé (26).


     
    7. Procédé de fabrication d'un dispositif à semi-conducteur composé selon la revendication 6, dans lequel
    la formation de chacune des secondes couches de semi-conducteur composé (25) comprend :

    la formation d'une couche inférieure (25a) composée d'un semi-conducteur composé de type i,

    l'exposition d'une surface de la couche inférieure (25a) à un gaz qui contient une impureté de type n, et

    après l'exposition de la surface de la couche inférieure (25a) au gaz, la formation d'une couche supérieure (25c) composée du semi-conducteur composé de type i sur la surface afin de créer la couche inférieure (25a) et la couche supérieure (25c) dans la seconde couche de semi-conducteur composé (25).


     
    8. Procédé de fabrication du dispositif à semi-conducteur composé selon la revendication 7, dans lequel
    la couche inférieure (25a) et la couche supérieure (25c) possèdent la même épaisseur.
     




    Drawing













































































    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description




    Non-patent literature cited in the description