(19)
(11)EP 3 297 157 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
04.11.2020 Bulletin 2020/45

(21)Application number: 16188790.6

(22)Date of filing:  14.09.2016
(51)International Patent Classification (IPC): 
H03F 1/02(2006.01)
H03F 3/60(2006.01)
H03F 3/21(2006.01)

(54)

DESIGN METHODS FOR MULTI-PATH AMPLIFIERS AND MULTI-PATH AMPLIFIER

KONSTRUKTIONSVERFAHREN FÜR MEHRWEGEVERSTÄRKER SOWIE MEHRWEGEVERSTÄRKER

PROCÉDÉ DE CONCEPTION POUR AMPLIFICATEUR À TRAJETS MULTIPLES ET AMPLIFICATEUR À TRAJETS MULTIPLES


(84)Designated Contracting States:
AL AT BE BG CY CZ DE DK EE ES FI FR GB GR HR HU IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(43)Date of publication of application:
21.03.2018 Bulletin 2018/12

(73)Proprietor: Rohde & Schwarz GmbH & Co. KG
81671 München (DE)

(72)Inventor:
  • LLOYD, Gareth
    81827 München (DE)

(74)Representative: Isarpatent 
Patent- und Rechtsanwälte Behnisch Barth Charles Hassa Peckmann & Partner mbB Friedrichstrasse 31
80801 München
80801 München (DE)


(56)References cited: : 
EP-A2- 1 463 198
US-A1- 2014 159 808
US-A1- 2003 001 669
  
  • HORIGUCHI K ET AL: "EFFICIENCA ENHANCEMENT OF A DIGITAL PREDISTORION DOHERTY AMPLIFIER TRANSMITTER USING A VIRTUAL OPEN STUB TECHNIQUE", IEICE TRANSACTIONS ON ELECTRONICS, INSTITUTE OF ELECTRONICS, TOKYO, JP, vol. E90C, no. 9, 1 September 2007 (2007-09-01), pages 1670-1677, XP001508679, ISSN: 0916-8524, DOI: 10.1093/IETELE/E90-C.9.1670
  • TAKAYAMA Y ET AL: "Micro-Ha Doherty Zofukuki no Seikkeiho Oyobi SiMOSFET Denryoku Zofukuki/DESIGN METHOD OF MICROWAVE DOHERTY POWER AMPLIFIERS AND ITS APPLICATION TO SI POWER MOSFET AMPLIFI ERS", DENSHI JOHO TSUSHIN GAKKAI RONBUNSHI, C-2 - TRANSACTIONS OF THEINSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERSSECTION J-C-2, DENSHI JOHO TSUSHIN GAKKAI, TOKYO, JP, vol. J87-C, no. 10, 1 October 2004 (2004-10-01), pages 745-753, XP003021820, ISSN: 0915-1907
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

FIELD OF THE INVENTION



[0001] The present invention relates to design methods for multi-path amplifiers and multi-path amplifiers being designed according to such methods. The multi-path amplifiers may in particular be employed in Doherty or Chireix amplifier topologies, but may also be applicable to other amplifier types such as, but not limited to, push-pull amplifiers, balanced amplifieres or spatially combined amplifiers. Such multi-path amplifiers may in particular be implemented in transmit frontend (TxFE) devices, as for example employed in mobile communication devices or mobile computing devices.

BACKGROUND OF THE INVENTION



[0002] Doherty power amplifier architectures are increasingly used as replacement for more traditional Class B amplifier in base-station and broadcast applications. Doherty amplifiers are simple in construction and highly efficient in performance. However, despite of its success, practicable implementations of Doherty power amplifier architectures may be rather limited in RF bandwidth, a problem that tends to be exacerbated towards higher power levels.

[0003] With Doherty power amplifier architectures being widespread due to their increased efficiency performance, linearity and operating bandwidth are typically deteriorated. Class C biased peaking amplifiers may causes AM-PM distortion, thereby limiting the overall amplifier linearity. Additionally, combiner devices for the output power are often regarded as the constraining factor for achievable RF bandwidth. Doherty power amplifier architectures are typically used in narrowband scenarios and commonly accompanied by pre-distortion input circuitry.

[0004] Specifically in frontend applications Doherty power amplifier architectures have become the quasi-linear architecture of choice. As microwave or millimeter wave air interface become more common, particularly with the advent of 5G communication technologies, the conventionally used amplifier classes as constituents of the Doherty architecture impose severe restrictions to its applicability which have hitherto been tried to address with different approaches.

[0005] Document WO 2007/117189 A1 discloses a method and a system for compensating signal distortions in multiple transmitting branches of a composite amplifier. Document WO 2007/078217 A1 discloses a detuned composite amplifier with a nonlinear drive function having a phase that varies with the composite amplifier output voltage amplitude and being configured to transform the output voltage transition point into an extended output voltage transition region to increase the efficiency of the composite amplifier. Document US 2014/0085000 A1 discloses a Doherty-type amplifier with a main-amplifier circuit, an auxiliary-amplifier circuit and a signal-generating device. Document US 2015/0116039 A1 discloses a multi-path amplifier system with an adjustable power splitter. Document US 8,354,882 B2 discloses a Doherty amplifier with an optimized input network for MMIC integration. Documents EP 1 463 198 A2 and US 2003/0001669 A1 disclose Doherty amplifier topologies which are actively compensated for distortion by feeding pilot signals and using portions in the output signals corresponding to the fed pilot signals in an adaptation loop for actively controller pre-distorters. Document US 2014/0159808 A1 discloses an analysis technique for Doherty amplifiers for adjusting matching networks of the amplifier.

SUMMARY OF THE INVENTION



[0006] According to the disclosure of present invention a method for designing a multi-path amplifier in accordance with claim 1 is implemented.

[0007] Specifically, according to a first aspect of the invention, a method for designing a multi-path amplifier involves connecting an amplifier stage having at least two amplifier branches to a combiner stage; feeding a plurality of testing signals with one or more of a plurality of sweeping variables comprising one or more of frequency, differential input amplitude and differential input phase to the amplifier stage; measuring output signals at the output of the combiner stage depending on the plurality of testing signals; designing a structure of an input network stage for the amplifier stage on the basis of the measured output signals, the input network stage having at least one input terminal and at least two output terminals, the at least two output terminals being connected to respective amplifier branches of the multi-path amplifier and having power linear output with respect to each other; and combining the designed input network stage with the amplifier stage to create an efficiency-optimised multi-path amplifier. The input network stage includes an analog processing module comprising analog circuitry components comprising one or more of an attenuator, a differential phase shifter, a power splitter and a hybrid coupler, the analog circuitry components not being controllable or adjustable by a user input of by an adjustment unit.

[0008] The multi-path amplifier includes an input network having at least one input terminal and at least two output terminals, the at least two output terminals being connected to respective amplifier branches of the multi-path amplifier. The design of the input network stage includes an analog processing module comprising analog circuitry components which are configured to process signals, the analog processing module not being controllable or adjustable by a user input of by an adjustment unit. The input network has been designed according to the method of the first aspect of the invention.

[0009] In some embodiments, the measured output signals include one or more of current consumption, channel output power, adjacent channel power and output crest factor.

[0010] In some embodiments, measuring the output signals comprises checking the current output signals against a list of boundary conditions for the measured output signals in order to minimize time wasted performing measurements.

[0011] According to the first aspect of the invention, designing the structure of the input network stage includes one or more of a discrete filter component synthesis, a distributed filter component synthesis, a rat-race hybrid synthesis, a cascaded rat-race hybrid with a Schiffman phase shifter synthesis and a Schiffman phase shifter synthesis.

[0012] In some embodiments, the design of the input network stage includes a Wilkinson splitter.

[0013] One idea of the present invention is to provide hardware prototypes of the amplifier stage and the combiner stage of a multi-path amplifier early in the development phase. Those components necessarily suffer from imperfections and deviations from ideal parameters. The hardware prototypes of the amplifier stage and the combiner stage are
subject to extensive empirical multi-dimensional testing. The testing results are used to subequently compensate the imperfections during design of the input network stage.

[0014] Amongst others, there are several specific advantages associated with such design methods and the concomitantly designed multi-path amplifiers.

[0015] The input network stage may include various components such as power splitters, hybrid couplers, attenuators and/or phase shifters. Those components may be passive components, the design, specification and parameters of which may be chosen taking into account the obtained testing results. The input network stage may for example be synthesized to re-create optimum values for differential amplitude and phase over frequency at the output of the resulting multi-path amplifier. Advantageously, frequency-domain equalization may be achieved by adapting the input network stage design considerations to the imperfections of the amplifier stage and the combiner stage.

[0016] The extensive empirical multi-dimensional testing may be performed rapidly by using vector signal generators at the input end and signal and spectrum analyzers at the output end of the truncated prototype multi-path amplifier with the prototype amplifier stage and the prototype combiner stage only. A rapid measurement scheme may be driven by using a rapid test executive software.

[0017] Deliberately modifying the design of the input network stage to have a characteristic that is not constant over frequency may allow for a final design to be achieved that is tailored towards an optimum output under the given imperfections of the amplifier stage and/or the combiner stage. Performance improvements may be achieved by optimizing the input network stage to accommodate dispersions in the amplifier stage and combiner stage, effectively performing a frequency domain equalization.

[0018] This design technique becomes increasingly important as the Doherty concept rolls out in 5G and other millimeter wave frequency applications. At these higher frequencies, the sub-circuits have the potential to significantly increase in electrical size which, in turn, may cause increased frequency dispersion and degraded bandwidth.

[0019] The performance gain that may be achieved using the design methodology of the invention is in particular not limited by the model accuracy, the modelling methodology or dispersive effects in the sub-components of the amplifier and combiner stages, but instead maps the empirically gathered imperfections of the underlying hardware to obtain specifically designed hardware components of the input network stage. Thus, the finally obtained multi-path amplifier does not need any actively controlled elements and the complexity of the input network stage is accordingly reduced.

[0020] Specific embodiments of the invention are set forth in the dependent claims.

[0021] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS



[0022] Further details, aspects and embodiments of the invention will be described, by way of example only, with reference to the accompanying drawings. Elements in the drawings are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

FIG. 1 schematically illustrates a multi-path amplifier according to some embodiments of the invention.

FIG. 2 shows a flowchart of procedural stages of a method for designing a multi-path amplifier according to some other embodiments of the invention.



[0023] In all figures of the drawings elements, features and components which are the same or at least have the same functionality have been provided with the same reference symbols, unless explicitly stated otherwise.

DETAILED DESCRIPTION OF SOME EMBODIMENTS OF THE INVENTION



[0024] FIG. 1 schematically illustrates a multi-path amplifier 10. The multi-path amplifier 10 may be any type of amplifier that employs at least two amplifier branches in parallel. The multi-path amplifier 10 may for example comprise a Doherty amplifier, a balanced amplifier, a push-pull amplifier or a spatially combined amplifier. The general functionality of the multi-path amplifier 10 is to provide for an output current sourced by one of the amplifier branches which is discontinuous relative to its drive signal.

[0025] Doherty amplifiers have enjoyed a renaissance in recent years in transmitter frontend hardware. Its persistent presence in the literature, including conference proceedings and patent databases, are testament to its elegance and flexibility. To achieve operation as Doherty intended, two broad conditions should be met by the amplifiers and combiners: (i) The output current sourced by the auxiliary amplifier should have a specific characteristic, anyway discontinuous relative to the drive signal; and (ii) the combiner ("impedance inverter") should be 90 degrees length. Despite the efforts devoted to making each of the three sub-circuits, i.e. the input network stage 2, the amplifier stage with the amplifier branches 4a, 4b, 4c, and the combiner stage 6, less dispersive, neither of the two conditions as set out above can be fully met in practice. As a result, the load modulation process is not purely real.

[0026] The disclosed architectures for the multi-path amplifiers 10 are not mutually exclusive, i.e. a Doherty amplifier architecture may be constructed using one or more anti-phase amplifiers or push-pull amplifiers. Multiple anti-phase amplifiers may for example be balanced.

[0027] The multi-path amplifier 10 as shown in FIG. 1 includes an input network stage 2 having at least one input terminal 1 for receiving input signals and at least two output terminals 3a, 3b, 3c for outputting output signals. In FIG. 1 the number of output terminals 3a, 3b, 3c is exemplarily shown as three, however, it should be understood that another number greater than one may be equally possible for the number of output terminals of the input network stage 2. The input network stage 2 may in some embodiments be formed with passive electric circuitry, for example with resistors, connector lines, inductors and/or capacitors. The input network stage 2 may in some embodiments be formed to output output signals at the output terminals 3a, 3b, 3c which are power linear with respect to each other and with respect to the input signals at the input terminal 1. The input network stage 2 may in some embodiments include an analog processing module. The analog processing module may be formed with analog circuitry components and may be configured to process signals. Moreover, the analog processing module may be implemented in modular form. The input network stage 2 may in some embodiments comprise electric components such as attenuators, phase shifters and/or hybrid couplers. For example, the attenuators may be implemented as T-type or π-type attenuators. The phase shifters may for example be implemented as differential phase shifters, such as for example Schiffmann phase shifters. The analog processing module may in some embodiments be non-adjustable. In some embodiments the analog processing module may be not controllable by a user input or by an adjustment unit.

[0028] The output terminals 3a, 3b, 3c of the input network stage 2 are connected to an active load modulation amplifier block having a respective number of amplifier branches 4a, 4b, 4c which are each connected to one of the output terminals 3a, 3b, 3c of the input network stage 2. The number of amplifier branches 4a, 4b, 4c in FIG. 1 is exemplarily shown as three, however, it should be understood that another number greater than one may be equally possible for the number of amplifier branches. The amplifier branches 4a, 4b, 4c form, eventually together with additional components such as bandpass filters, attenuators, switches or similar components, an amplifier stage 4. The amplifier stage 4 may be arranged according to the desired amplifier functionality, such as for example in Doherty type arrangement, in cascaded arrangement of several amplifying modules or the like.

[0029] The design of components of the multi-path amplifier 10 of FIG. 1, specifically the input network 2, will be explained in conjunction with the design method M as depicted in FIG. 2, while resorting to the exemplary amplifier architecture of FIG. 1 for a better understanding of the underlying principles.

[0030] FIG. 2 schematically illustrates procedural stages of a design method M for designing a multi-path amplifier. The design method M may be advantageously used for designing a multi-path amplifier 10 as depicted in FIG. 1.

[0031] In the design method M, a first step M1 invloves connecting an amplifier stage having at least two amplifier branches 4a, 4b, 4c to a combiner stage 6. The amplifier stage and the combiner stage may be hardware prototypes having imperfections in their performance.

[0032] In a second step M2, a plurality of testing signals with one or more of a plurality of sweeping variables are fed to the amplifier stage. The sweeping variables may for example include one or more of frequency, differential input amplitude, differential input phase and absolute input power.

[0033] In a third step M3, output signals are measured at the output of the combiner stage depending on the plurality of testing signals. The measured output signals may for example include one or more of current consumption, channel output power, adjacent channel power and output crest factor. In order to minimize time wasted performing measurements, measuring the output signals may comprise checking the current output signals against a list of boundary conditions for the measured output signals.

[0034] In a fourth step M4, a structure of an input network stage 2 for the amplifier stage is deisgned on the basis of the measured output signals. This may includes one or more of a general filter construction technique, a discrete filter component synthetis, a distributed filter component synthesis, a rat-race hybrid, a cascaded rat-race hybrid with a Schiffman phase shifter and a Schiffman phase shifter. The input network stage 2 may in particular be designed to include at least two output terminals, an analog processing module, one or more of an attenuator, a differential phase shifter, a power splitter and a hybrid coupler, and/or a Wilkinson splitter.

[0035] In a fifth step, the designed input network stage 2 is combined with the amplifier stage to create an efficiency-optimised multi-path amplifier 10.

[0036] In order to provide the testing signals, signal libraries may be used. Within each signal library, there is a calibration signal and a plurality of test signals. The calibration signal comprises three 3GPP carriers, each separated by 80 MHz to occupy 160 MHz total. The test signals are single 3GPP carriers, with baseband offsets ranging from -80 MHz to +80 MHz in increments of 10 MHz. Using a baseband frequency sweep with the library of test signals enables a single phase coherence calibration of the two SMW channels for amplitude, phase and time delay. Performing an RF frequency sweep with fixed IF, will require a calibration (amplitude, phase, delay) at different associated LO (local oscillator) frequencies. For an RF frequency sweep, the user may pre-calibrate, store and recall these calibration values (delay, baseband phase and baseband amplitude) for each frequency, to support an even wider bandwidth. The user is, of course, free to create their own signal library and define their own experiment. Signals may be generated using Win-IQSIM2 software or using a vector signal analyzer. Alternatively, the signals may be generated in MATLAB or similar software.

[0037] In some embodiments, it may be useful to connect the amplifier stage and the combiner stage, for example by means of connectors that are designed to transfer data in signal form, such as LAN connectors. If the amplifier stage and the combiner stage are not connected by connectors it may prove difficult to transfer signals from the amplifier stage to the combiner stage. In some embodiments, it may also be helpful to connect the amplifier stage and/or the combiner stage to a power supply. This may advantageously aid in providing power to the amplifier stage and/or the combiner stage.

[0038] A calibration should be performed to ensure proper alignment in time, phase and amplitude of the output signals at the end of test cables connected to the combiner stage, i.e. that the effect of the test cables needs to be removed. The calibration procedure may already be embedded within QuickStep project files, if QuickStep is used for the measurement run. Within the QuickStep project, the calibration may be performed using a Forum script, enabling easy instrument control within a Phython scripting environment.

[0039] A rapid text executive software, such as aforementioned QuickStep may be used to drive the characterization process of the amplifier stage and the combiner stage. A broad, nested loop sweep characterization may be performed. Other characterization methodologies may for example involve searches for operating points of interest. Independently swept variables may for example include frequency, differential input amplitude, differential input phase, bias points and/or absolute input power. Measured dependent output quantities may for example involve current consumption, channel output power, adjacent channel power and/or output crest factor.

[0040] The measured values may for example be checked against a list of conditions intended to minimize time wasted performing measurements in operating regions that are unlikely to be of interest. Doing so also reduces the risk of entering potentially damaging operating conditions when applying the testing signals.

[0041] The characterization process of the design method M may be made easy by using a vector signal generator and a signal and spectrum analyzer, whilst rapid measurements may be enabled with Quickstep. The optimized input network stage may then designed using a high performance EM simulation tool, such as for example CST Studio Suite. Two different splitter syntheses may be used: A general filter contruction technique involving calculating and synthesizing discrete, distributed (or both) filter circuitry components being connected by a Wilkinson splitter, or a distributed method using a cascaded rat-race hybrid and Schiffman phase shifter.

[0042] In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the scope of the invention as set forth in the appended claims. For example, the connections between various elements as shown and described with respect to the drawings may be a type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise the connections may for example be direct connections or indirect connections.

[0043] Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits known to those skilled in the art, details of the circuitry and its components will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

[0044] Also, the invention is not limited to physical devices or units implemented in non-programmable hardware, but can also be applied in programmable devices or units able to perform the desired device functions by operating in accordance with suitable program code. Furthermore, the devices may be physically distributed over a number of apparatuses, while functionally operating as a single device. Devices functionally forming separate devices may be integrated in a single physical device. Those skilled in the art will recognize that the boundaries between logic or functional blocks are merely illustrative and that alternative embodiments may merge logic or functional blocks or impose an alternate decomposition of functionality upon various logic or functional blocks.

[0045] In the description, any reference signs shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms "a" or "an", as used herein, are defined as one or more than one. Also, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an." The same holds true for the use of definite articles. Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage. The order of method steps as presented in a claim does not prejudice the order in which the steps may actually be carried, unless specifically recited in the claim.

[0046] Skilled artisans will appreciate that the illustrations of chosen elements in the drawings are only used to help to improve the understanding of the functionality and the arrangements of these elements in various embodiments of the present invention. Also, common and well understood elements that are useful or necessary in a commercially feasible embodiment are generally not depicted in the drawings in order to facilitate the understanding of the technical concept of these various embodiments of the present invention. It will further be appreciated that certain procedural stages in the described methods may be described or depicted in a particular order of occurrence while those skilled in the art will understand that such specificity with respect to sequence is not actually required.


Claims

1. A method (M) for desigining a multi-path amplifier (10), the method (M) comprising:

connecting (M1) an amplifier stage having at least two amplifier branches (4a, 4b, 4c) to a combiner stage (6);

feeding (M2) a plurality of testing signals with one or more of a plurality of sweeping variables comprising one or more of frequency, differential input amplitude and differential input phase to the amplifier stage;

measuring (M3) output signals at the output of the combiner stage depending on the plurality of testing signals;

designing (M4) a structure of an input network stage (2) for the amplifier stage using a discrete filter component synthesis, a distributed filter component synthesis, a rat-race hybrid synthesis, a cascaded rat-race hybrid with a Schiffman phase shifter synthesis and a Schiffman phase shifter synthesis on the basis of the measured output signals, the input network stage (2) having at least one input terminal (1) and at least two output terminals (3a, 3b, 3c), the at least two output terminals (3a, 3b, 3c) being connected to respective amplifier branches (4a, 4b, 4c) of the multi-path amplifier (10) and having power linear output with respect to each other and with respect to the input signals at the input terminal; and

combining (M5) the designed input network stage (2) with the amplifier stage to create an efficiency-optimised multi-path amplifier (10),

wherein the input network stage (2) is an analog processing module comprising analog circuitry components comprising one or more of an attenuator, a differential phase shifter and a hybrid coupler, the analog circuitry components not being controllable or adjustable by a user input or by an adjustment unit.


 
2. The method (M) of claim 1, wherein the measured output signals include one or more of current consumption, channel output power, adjacent channel power and output crest factor.
 
3. The method (M) of one of the claims 1 to 2, wherein the input network stage (2) includes a Wilkinson splitter.
 


Ansprüche

1. Verfahren (M) zum Konstruieren eines Mehrwegeverstärkers (10), wobei das Verfahren (M) Folgendes umfasst:

Verbinden (M1) einer Verstärkerstufe mit mindestens zwei Verstärkerzweigen (4a, 4b, 4c) mit einer Kombiniererstufe (6);

Zuführen (M2) einer Vielzahl von Testsignalen mit einer oder mehreren einer Vielzahl von Wobbelvariablen, die eines oder mehreres von Frequenz, Differenzeingangsamplitude und Differenzeingangsphase umfassen, zur Verstärkerstufe;

Messen (M3) von Ausgangssignalen am Ausgang der Kombiniererstufe in Abhängigkeit von der Vielzahl von Testsignalen;

Konstruieren (M4) einer Struktur einer Eingangsnetzwerkstufe (2) für die Verstärkerstufe unter Verwendung einer diskreten Filterkomponentensynthese, einer verteilten Filterkomponentensynthese, einer Rat-Race-Hybridsynthese, eines kaskadierten Rat-Race-Hybrids mit einer Schiffman-Phasenverschiebersynthese und einer Schiffman-Phasenverschiebersynthese auf Basis der gemessenen Ausgangssignale, wobei die Eingangsnetzwerkstufe (2) mindestens einen Eingangsanschluss (1) und mindestens zwei Ausgangsanschlüsse (3a, 3b, 3c) aufweist, wobei die mindestens zwei Ausgangsanschlüsse (3a, 3b, 3c) mit jeweiligen Verstärkerzweigen (4a, 4b, 4c) des Mehrwegeverstärkers (10) verbunden sind und mit Bezug aufeinander und mit Bezug auf die Eingangssignale am Eingangsanschluss einen leistungslinearen Ausgang aufweisen; und

Kombinieren (M5) der konstruierten Eingangsnetzwerkstufe (2) mit der Verstärkerstufe, um einen effizienzoptimierten Mehrwegeverstärker (10) herzustellen,

wobei die Eingangsnetzwerkstufe (2) ein analoges Verarbeitungsmodul ist, das analoge Schaltungskomponenten umfasst, die eines oder mehreres von einem Dämpfer, einem Differenzphasenverschieber und einem Hybridkoppler umfassen, wobei die analogen Schaltungskomponenten durch eine Benutzereingabe oder durch eine Anpassungseinheit nicht steuerbar oder anpassbar sind.


 
2. Verfahren (M) nach Anspruch 1, wobei die gemessenen Ausgangssignale eines oder mehreres von Stromverbrauch, Kanalausgangsleistung, Nachbarkanalleistung und Ausgangsspitzenfaktor beinhalten.
 
3. Verfahren (M) nach einem der Ansprüche 1 bis 2, wobei die Eingangsnetzwerkstufe (2) einen Wilkinson-Splitter beinhaltet.
 


Revendications

1. Procédé (M) de conception d'un amplificateur à trajets multiples (10), le procédé (M) comprenant :

la connexion (M1) d'un étage d'amplificateur ayant au moins deux branches d'amplificateur (4a, 4b, 4c) à un étage de combineur (6) ;

la fourniture (M2) d'une pluralité de signaux de test, ayant une ou plusieurs variables parmi une pluralité de variables de balayage comprenant l'une ou plusieurs parmi la fréquence, l'amplitude d'entrée différentielle et la phase d'entrée différentielle, à l'étage d'amplificateur ;

la mesure (M3) de signaux de sortie à la sortie de l'étage de combineur en fonction de la pluralité de signaux de test ;

la conception (M4) d'une structure d'un étage de réseau d'entrée (2) pour l'étage d'amplificateur à l'aide d'une synthèse de composante de filtrage discrète, d'une synthèse de composante de filtrage distribuée, d'une synthèse à anneau hybride de type « rat-race », une synthèse à anneau hybride de type « rat-race » en cascade avec déphaseur de Schiffman et une synthèse à déphaseur de Schiffman sur la base des signaux de sortie mesurés, l'étage de réseau d'entrée (2) ayant au moins une borne d'entrée (1) et au moins deux bornes de sortie (3a, 3b, 3c), lesdites au moins deux bornes de sortie (3a, 3b, 3c) étant connectées à des branches d'amplificateur respectives (4a, 4b, 4c) de l'amplificateur à trajets multiples (10) et ayant une sortie linéaire de puissance les unes par rapport aux autres et par rapport aux signaux d'entrée au niveau de la borne d'entrée ; et

la combinaison (M5) de l'étage de réseau d'entrée conçu (2) avec l'étage d'amplificateur pour créer un amplificateur à trajets multiples à efficacité optimisée (10),

dans lequel l'étage de réseau d'entrée (2) est un module de traitement analogique comprenant des composants de circuit analogique comprenant l'un ou plusieurs parmi un atténuateur, un déphaseur différentiel et un coupleur hybride, les composants de circuit analogique ne pouvant pas être commandés ou réglés par une entrée utilisateur ou par une unité de réglage.


 
2. Procédé (M) selon la revendication 1, dans lequel les signaux de sortie mesurés incluent l'un ou plusieurs parmi une consommation de courant, une puissance de sortie de canal, une puissance de canal adjacent et un facteur de crête de sortie.
 
3. Procédé (M) selon l'une quelconque des revendications 1 à 2, dans lequel l'étage de réseau d'entrée (2) inclut un diviseur de Wilkinson.
 




Drawing








Cited references

REFERENCES CITED IN THE DESCRIPTION



This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description