(19)
(11)EP 3 300 118 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
06.05.2020 Bulletin 2020/19

(21)Application number: 17191834.5

(22)Date of filing:  19.09.2017
(51)Int. Cl.: 
H01L 29/786  (2006.01)
H01L 27/12  (2006.01)

(54)

FLEXIBLE DISPLAY

FLEXIBLE ANZEIGE

ÉCRAN SOUPLE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 23.09.2016 KR 20160122489

(43)Date of publication of application:
28.03.2018 Bulletin 2018/13

(73)Proprietor: LG Display Co., Ltd.
Seoul, 07336 (KR)

(72)Inventors:
  • YOUN, Sangcheon
    10845 Paju-si, Gyeonggi-do (KR)
  • KWON, Seyeoul
    10845 Paju-si, Gyeonggi-do (KR)
  • KWON, Hoiyong
    10845 Paju-si, Gyeonggi-do (KR)
  • KIM, Eunah
    10845 Paju-si, Gyeonggi-do (KR)

(74)Representative: Viering, Jentschura & Partner mbB Patent- und Rechtsanwälte 
Am Brauhaus 8
01099 Dresden
01099 Dresden (DE)


(56)References cited: : 
US-A1- 2004 018 674
US-A1- 2016 172 623
US-A1- 2016 141 310
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    BACKGROUND OF THE INVENTION


    Field of the Invention



    [0001] The present disclosure relates to a flexible display.

    Discussion of the Related Art



    [0002] With the development of information society, demands for display devices displaying an image are increasing in various ways. In a field of the display devices, a large-sized cathode ray tube (CRT) has been rapidly replaced by a flat panel display (FPD) having advantages of a thin profile, low weight, and a large-sized screen. Examples of the flat panel display include a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting diode (OLED) display, and an electrophoresis display (EPD).

    [0003] An OLED display includes self-emitting elements capable of emitting light by themselves and has advantages of a fast response time, a high emission efficiency, a high luminance, and a wide viewing angle. In particular, the OLED display may use a flexible plastic substrate. In addition, the OLED display has advantages of a lower driving voltage, lower power consumption, and better color tone as compared to a plasma display panel or an inorganic electroluminescent display.

    [0004] The OLED display may include a plurality of buffer layers on a flexible plastic substrate. The plurality of buffer layers blocks ions or impurities diffused from the plastic substrate underlying the buffer layers in a manufacturing process of the OLED display. Further, the plurality of buffer layers blocks the penetration of external moisture from the plastic substrate after the OLED display is completed, thereby preventing the degradation of thin film transistors and organic light emitting diodes.

    [0005] However, the buffer layer affects the component adjacent to the buffer layer due to the properties of a material constituting the buffer layer, thereby reducing characteristics of the component. For example, the buffer layer may include silicon nitride (SiNx). When the thin film transistor includes an oxide semiconductor, hydrogen existing in silicon nitride of the buffer layer is diffused and reduces electrical characteristics of the oxide semiconductor.

    [0006] US 2016/0141310 discloses a flexible display with a light shield and with buffer layers.

    SUMMARY OF THE INVENTION



    [0007] The present disclosure is to provide a display device capable of preventing moisture penetration through a plastic substrate.

    [0008] The present disclosure is to also provide a flexible display capable of preventing electrical characteristics of an oxide semiconductor from being reduced by a silicon nitride layer constituting a buffer layer.

    [0009] In one aspect, there is provided a flexible display according to the claims including an oxide semiconductor thin film transistor on a plastic substrate, the flexible display including a first buffer layer disposed on the plastic substrate, a second buffer layer disposed on the first buffer layer and formed of silicon oxide (SiOx), and an active layer disposed on the second buffer layer and formed of an oxide semiconductor, wherein the first buffer layer includes a lower layer directly contacting the plastic substrate and formed of silicon nitride (SiNx) and an upper layer disposed on the lower layer and formed of silicon oxide (SiOx).

    [0010] In one or more embodiments, a thickness of the lower layer is equal to or greater than a thickness of the upper layer.

    [0011] The lower layer includes a first lower layer and a second lower layer that are formed by separate deposition processes.

    [0012] In one or more embodiments, the first lower layer comprises first micro-sized pores and the second lower layer comprises second micro-sized pores, wherein the first micro-sized pores and the second micro-sized pores are separated from each other without being connected to each other.

    [0013] The first lower layer has a higher density than the second lower layer.

    [0014] In one or more embodiments, the second lower layer is formed on the first lower layer, wherein the first lower layer has dense characteristics and the second lower layer has porous characteristics.

    [0015] The flexible display further includes a light shielding layer disposed between the first buffer layer and the second buffer layer and overlapping the active layer.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0016] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate aspects of the disclosure and together with the description serve to explain the principles of the disclosure. In the drawings:

    [0017] FIG. 1 is a schematic block diagram of a flexible display according to an embodiment of the disclosure;

    [0018] FIG. 2 illustrates a first example of a circuit configuration of a subpixel;

    [0019] FIG. 3 illustrates a second example of a circuit configuration of a subpixel;

    [0020] FIG. 4 is a cross-sectional view of a flexible display according to an embodiment of the disclosure;

    [0021] FIG. 5 schematically illustrates configuration of a first buffer layer according to an embodiment of the disclosure;

    [0022] FIG. 6 schematically illustrates configuration of a first buffer layer according to the embodiment of the disclosure;

    [0023] FIG. 7 schematically illustrates a stacking structure of buffer layers according to a comparative example and an experimental example; and

    [0024] FIG. 8 is a graph illustrating a current-voltage characteristic of an oxide semiconductor thin film transistor according to a comparative example and an experimental example.

    DETAILED DESCRIPTION OF THE EMBODIMENTS



    [0025] Reference will now be made in detail to embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. It will be paid attention that detailed description of known arts will be omitted if it is determined that the arts can mislead the embodiments of the disclosure. Names of the respective elements used in the following explanations are selected only for convenience of writing the specification and may be thus different from those used in actual products.

    [0026] A display device according to an embodiment of the disclosure is a flexible display in which a display element is formed on a flexible plastic substrate. The flexible display according to the embodiment of the disclosure may be implemented based on a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting diode (OLED) display, an electrophoresis display (EPD), a quantum dot display (QDD), and the like. In the following description, for convenience of explanation, a case where the flexible display includes organic light emitting diodes will be described as an example.

    [0027] A flexible display includes a first electrode, a second electrode opposite the first electrode, and an emission layer between the first electrode and the second electrode. The first electrode may be an anode electrode, and the second electrode may be a cathode electrode. The flexible display is a self-emission display device configured to form hole-electron pairs, i.e., excitons by combining holes received from the first electrode and electrons received from the second electrode inside the emission layer and emit light by energy generated when the excitons return to a ground level.

    [0028] The flexible display according to the embodiment of the disclosure may be applied to both a top emission type display in which light is emitted upwardly, and a bottom emission type display in which light is emitted downwardly. In addition, the flexible display according to the embodiment of the disclosure may be applied to a transparent display in which an object on the back side can be seen through the flexible display.

    [0029] The flexible display according to the embodiment of the disclosure uses a plastic substrate, for example, a polyimide (PI) substrate, so as to secure the flexibility of the display device. Because barrier characteristics of the plastic substrate are very low, a buffer layer performing a barrier function has to be added to the plastic substrate. The buffer layer is positioned on the plastic substrate to block ions or impurities diffused from the plastic substrate and to prevent the moisture penetration from the outside.

    [0030] In general, the buffer layer includes a silicon oxide (SiOx) layer and a silicon nitride (SiNx) layer. Because the SiOx layer and the SiNx layer each have predetermined barrier characteristics, they can prevent the moisture penetration through the plastic substrate.

    [0031] Minimum thicknesses of the SiOx layer and the SiNx layer required to satisfy the predetermined barrier characteristics are different from each other. As a result of actually measuring the minimum thicknesses of the SiOx layer and the SiNx layer capable of satisfying a water vapor transmission rate (WVTR) of 10-2 to 10-4 g/m2/day, the minimum thickness of the SiNx layer was approximately 8 nm, and the minimum thickness of the SiOx layer was approximately 25 nm. Namely, assuming that the SiOx layer and the SiNx layer have the same thickness, it can be seen that the barrier characteristics of the SiNx layer are much better than the barrier characteristics of the SiOx layer.

    [0032] The embodiment of the disclosure uses the SiNx layer as the component constituting the buffer layer, considering that i) the SiOx layer has the minimum thickness larger than the SiNx layer so as to satisfy the predetermined barrier characteristics, and ii) the flexibility of the display device is reduced as a thickness of the buffer layer increases.

    [0033] However, because the display device according to the embodiment of the disclosure includes a thin film transistor (TFT) using an oxide semiconductor, the embodiment of the disclosure has to prevent hydrogen from entering the oxide semiconductor. Namely, a polycrystalline silicon semiconductor requires a hydrogenation process for filling vacancies of a polycrystalline silicon semiconductor material with hydrogen in consideration of a reduction in device characteristics resulting from the presence of vacancies. On the other hand, because a vacancy, in which a covalent bond is not formed, serves as a carrier in an oxide semiconductor material, the oxide semiconductor material needs to have a certain amount of vacancies. Thus, it is necessary to prevent a large amount of hydrogen from entering the oxide semiconductor.

    [0034] More specifically, when the buffer layer includes the SiNx layer, hydrogen existing in the SiNx layer may be diffused into the oxide semiconductor and may change a concentration of carriers inside a channel of the thin film transistor. Hence, a threshold voltage of an oxide semiconductor thin film transistor may be shifted in a negative direction, or the channel of the oxide semiconductor thin film transistor may become conductive, thereby reducing the image quality of the display device. Because of the above problems, a related art display device cannot use a SiNx layer as a buffer layer when including a thin film transistor using an oxide semiconductor.

    [0035] The embodiment of the disclosure describes an improved structure in which the SiNx layer can be used as the buffer layer in providing a display device including an oxide semiconductor thin film transistor.

    [0036] FIG. 1 is a schematic block diagram of a flexible display according to an embodiment of the disclosure. FIG. 2 illustrates a first example of a circuit configuration of a subpixel. FIG. 3 illustrates a second example of a circuit configuration of a subpixel.

    [0037] Referring to FIG. 1, a flexible display according to an embodiment of the disclosure includes an image processing unit 10, a timing controller 20, a data driver 30, a gate driver 40, and a display panel 50.

    [0038] The image processing unit 10 outputs a data signal DATA and a data enable signal DE supplied from the outside. The image processing unit 10 may output one or more of a vertical sync signal, a horizontal sync signal, and a clock signal in addition to the data enable signal DE. For the sake of brevity and ease of reading, these signals are not shown. The image processing unit 10 is formed on a system circuit board as an integrated circuit (IC).

    [0039] The timing controller 20 receives the data signal DATA and driving signals including the data enable signal DE or the vertical sync signal, the horizontal sync signal, the clock signal, etc. from the image processing unit 10.

    [0040] The timing controller 20 outputs a gate timing control signal GDC for controlling operation timing of the gate driver 40 and a data timing control signal DDC for controlling operation timing of the data driver 30 based on the driving signals. The timing controller 20 may be formed on a control circuit board as an IC.

    [0041] The data driver 30 samples and latches the data signal DATA received from the timing controller 20 in response to the data timing control signal DDC supplied from the timing controller 20 and converts the sampled and latched data signal DATA using gamma reference voltages. The data driver 30 outputs the converted data signal DATA to data lines DL1 to DLn. The data driver 30 is formed on a data circuit substrate as an IC.

    [0042] The gate driver 40 outputs a gate signal while shifting a level of a gate voltage in response to the gate timing control signal GDC supplied from the timing controller 20. The gate driver 40 outputs the gate signal to gate lines GL1 to GLm. The gate driver 40 is formed on a gate circuit board as an IC or is formed on the display panel 50 in a gate-in-panel (GIP) manner.

    [0043] The display panel 50 displays an image in response to the data signal DATA and the gate signal respectively received from the data driver 30 and the gate driver 40. The display panel 50 includes subpixels SP for displaying an image.

    [0044] As shown in FIG. 2, each subpixel may include a switching transistor SW, a driving transistor DR, a compensation circuit CC, and an organic light emitting diode (OLED). The organic light emitting diode operates to emit light based on a driving current generated by the driving transistor DR.

    [0045] The switching transistor SW performs a switching operation so that a data signal supplied through a first data line DL1 is stored in a capacitor Cst as a data voltage in response to a gate signal supplied through a first gate line GL1. The driving transistor DR enables a driving current to flow between a high potential power line VDD and a low potential power line GND based on the data voltage stored in the capacitor Cst. The compensation circuit CC is a circuit for compensating for a threshold voltage of the driving transistor DR. A capacitor connected to the switching transistor SW or the driving transistor DR may be mounted inside the compensation circuit CC.

    [0046] The compensation circuit CC includes one or more thin film transistors and a capacitor. Configuration of the compensation circuit CC may be variously changed depending on a compensation method. A brief description of the compensation circuit CC will be made.

    [0047] As shown in FIG. 3, a subpixel including the compensation circuit CC may further include a signal line and a power line for driving a compensation TFT and supplying a predetermined signal or electric power. The added signal line may be defined as a 1-2 gate line GL1b for driving the compensation TFT included in the subpixel. In FIG. 3, "GL1a" is a 1-1 gate line for driving the switching transistor SW. The added power line may be defined as an initialization power line INIT for initializing a predetermined node of the subpixel to a predetermined voltage. However, this is merely an example, and embodiments are not limited thereto.

    [0048] FIGS. 2 and 3 illustrate that one subpixel includes the compensation circuit CC by way of example. However, the compensation circuit CC may be omitted when an object (for example, the data driver 30) to be compensated is positioned outside the subpixel. The subpixel has a configuration of 2T(Transistor)1C(Capacitor) in which the switching transistor SW, the driving transistor DR, the capacitor, and the organic light emitting diode are provided. However, when the compensation circuit CC is added to the subpixel, the subpixel may have various configurations such as 3T1C, 4T2C, 5T2C, 6T2C, 7T1C, 7T2C, and the like.

    [0049] Also, FIGS. 2 and 3 illustrate that the compensation circuit CC is positioned between the switching transistor SW and the driving transistor DR by way of an example. However, the compensation circuit CC may be further positioned between the driving transistor DR and the organic light emitting diode. The position and the structure of the compensation circuit CC are not limited to the ones illustrated in FIGs. 2 and 3.

    [0050] FIG. 4 is a cross-sectional view of a flexible display according to an embodiment of the disclosure. FIG. 5 schematically illustrates configuration of a first buffer layer according to an embodiment of the disclosure. FIG. 6 schematically illustrates configuration of a first buffer layer according to another embodiment of the disclosure.

    [0051] Referring to FIGS. 4 and 5, a flexible display according to an embodiment of the disclosure includes a thin film transistor DT and an organic light emitting diode OLE on a plastic substrate SUB. For example, the plastic substrate SUB may be a polyimide (PI) substrate. Thus, the flexible display according to the embodiment of the disclosure may have flexible characteristic.

    [0052] A first buffer layer BF1 and a second buffer layer BF2 are positioned between the plastic substrate SUB and the thin film transistor DT. The first buffer layer BF1 may have a thickness of 100 Å to 11,000 Å, and the second buffer layer BF2 may have a thickness of 100 Å to 10,000 Å. A light shielding layer LS is positioned between the first buffer layer BF1 and the second buffer layer BF2. The light shielding layer LS may be disposed to overlap an active layer ACT, particularly, a channel of the thin film transistor DT and protects an oxide semiconductor element from external light.

    [0053] The first buffer layer BF1 blocks ions or impurities diffused from the plastic substrate SUB and prevents the moisture penetration from the outside. The first buffer layer BF1 includes a lower layer BL formed of silicon nitride (SiNx) and an upper layer TL formed of silicon oxide (SiOx). The lower layer BL and the upper layer TL are sequentially stacked and are positioned between the plastic substrate SUB and the active layer ACT of the thin film transistor DT.

    [0054] The lower layer BL is positioned on the plastic substrate SUB. The lower layer BL has a thickness capable of performing predetermined barrier characteristics and prevents the moisture penetration through the plastic substrate SUB. Because the lower layer BL is formed of silicon nitride (SiNx), the lower layer BL can satisfy the predetermined barrier characteristics with the thin thickness. Hence, the lower layer BL can prevent an increase in a thickness of the flexible display and secure predetermined flexibility of the flexible display. In other words, the lower layer BL may have a minimum thickness capable of satisfying the predetermined barrier characteristics. For example, the lower layer BL may have a thickness of 100 Å to 6,000 Å. The embodiment of the disclosure sets the SiNx layer (i.e., the lower layer BL), that has the better barrier characteristics than the SiOx layer under the condition of the same thickness, as a layer directly contacting the plastic substrate SUB, thereby simultaneously securing the predetermined barrier characteristics and the predetermined flexibility.

    [0055] Because the embodiment of the disclosure directly forms the lower layer BL on the plastic substrate SUB so as to prevent the moisture penetration through the plastic substrate SUB, interface characteristics between the plastic substrate SUB and the lower layer BL need to be considered.

    [0056] For example, when a SiOx layer is directly formed on the plastic substrate SUB, a peeling may occur at an interface between the plastic substrate SUB and the SiOx layer due to a difference between the properties of the plastic substrate SUB and the SiOx layer. The embodiment of the disclosure sets the SiNx layer having more similar surface characteristics to the plastic substrate SUB than the SiOx layer as a layer directly contacting the plastic substrate SUB, thereby preventing or minimizing a defective adhesion that may occur at an interface between the plastic substrate SUB and the lower layer BL.

    [0057] Because the embodiment of the disclosure uses not an existing glass substrate but the plastic substrate SUB having relatively low thermal conductivity, an auxiliary means for efficiently dissipating heat generated in an internal driving element, for example, the thin film transistor is necessary. The embodiment of the disclosure directly forms the lower layer BL formed of silicon nitride (SiNx) having high thermal conductivity on the plastic substrate SUB, in order to efficiently dissipate heat. Thermal conductivity of silicon nitride (SiNx) is approximately 15 times greater than thermal conductivity of silicon oxide (SiOx). The embodiment of the disclosure sets the SiNx layer having high thermal conductivity as a layer directly contacting the plastic substrate SUB, thereby efficiently dissipating heat without a separate auxiliary means.

    [0058] The upper layer TL is positioned on the lower layer BL. The upper layer TL may have a thickness of 100 Å to 5,000 Å. The embodiment of the disclosure can relatively increase a length of a moving path of hydrogen existing in the lower layer BL toward the active layer ACT by disposing the upper layer TL between the lower layer BL and the active layer ACT. Further, the embodiment of the disclosure can induce hydrogen diffused from the lower layer BL to move toward not the active layer ACT but the plastic substrate SUB by forming the upper layer TL serving as a barrier on the lower layer BL. Hence, hydrogen diffused from the lower layer BL can move toward the plastic substrate SUB underlying the lower layer BL and can be easily released to the outside. The embodiment of the disclosure brings the lower layer BL into contact with the plastic substrate SUB and stacks the upper layer TL on the lower layer BL, thereby preventing or reducing hydrogen from the lower layer BL from entering the active layer ACT. Hence, a reduction in electrical characteristics of the oxide semiconductor can be minimized.

    [0059] The thickness of the lower layer BL may be equal to or greater than the thickness of the upper layer TL. The lower layer BL may have enough thickness to block foreign substances from the outside. Further, the thickness of the upper layer TL may be equal or less than the thickness of the lower layer BL in consideration of the total thickness of the first buffer layer BF1 for the purpose of the flexibility of the flexible display.

    [0060] Because ions or impurities diffused from the plastic substrate SUB and moisture from the outside are mostly blocked by the lower layer BL formed of silicon nitride (SiNx), the upper layer TL formed of silicon oxide (SiOx) may have the relatively thin thickness. Namely, the embodiment of the disclosure can secure the reliability of water vapor transmission (or, water vapor permeation) with the thinner thickness, compared to when the lower layer BL is formed of only silicon oxide (SiOx). Namely, the embodiment of the disclosure can prevent an increase in the total thickness of the flexible display while securing the barrier characteristics and secure predetermined flexibility of the flexible display.

    [0061] Referring to FIG. 6, the lower layer BL constituting the first buffer layer BF1 is divided into a first lower layer BL1 and a second lower layer BL2 and dividedly deposited. That is, the first lower layer BL1 and the second lower layer BL2 may be deposited in separate processes. For example, the first lower layer BL1 and the second lower layer BL2 may be sequentially deposited in the same chamber at intervals of predetermined time. Both the first lower layer BL1 and the second lower layer BL2 are may be formed of silicon nitride (SiNx). The first lower layer BL1 may have a thickness of 100 Å to 3,000 Å, and the second lower layer BL2 may have a thickness of 100 Å to 3,000 Å.

    [0062] In a chemical vapor deposition (CVD) process, the lower layer BL is not uniformly deposited on the plastic substrate SUB, and thus a thickness variation depending on a position may occur in the lower layer BL. In this instance, surface characteristics of the lower layer BL may be reduced, and the upper layer TL on the lower layer BL may be peeled off.

    [0063] The embodiment of the disclosure dividedly deposits the lower BL (that is, the first lower layer BL1 and the second lower layer BL2 are deposited in separate processes), thereby reducing the thickness variation of the lower layer BL. Namely, when the lower layer BL is deposited through a single process, a corresponding material may be intensively deposited at a specific position during the process, resulting in an excessive thickness variation. On the other hand, when the lower layer BL is dividedly deposited, processes are performed in a temporally and/or spatially separated manner. Thus, even if a corresponding material is intensively deposited at a predetermined position during a first process, the position where the material is intensively deposited may be changed during a second process. Therefore, the thickness variation depending on the position can be reduced.

    [0064] Further, the embodiment of the disclosure can efficiently block a moisture penetration path, that may be formed in the lower layer BL during the process, by dividedly depositing lower layer BL (that is, the first lower layer BL1 and the second lower layer BL2 of the lower layer BL are deposited in separate processes). Namely, micro-sized pores (or fine cracks) may be formed inside the lower layer BL deposited through the CVD process. When the lower layer BL is deposited through a single process, the micro-sized pores formed inside the lower layer BL may be extended in a thickness direction to form a moisture penetration path. On the other hand, when the lower layer BL is dividedly deposited, processes are performed in a temporally and/or spatially separated manner. Thus, even if first micro-sized pores are generated in the first lower layer BL1 during a first process and second micro-sized pores are generated in the second lower layer BL2 during a second process, the first micro-sized pores and the second micro-sized pores may be separated from each other without being connected to each other. Therefore, the formation of the moisture penetration path in the thickness direction can be minimized.

    [0065] The first lower layer BL1 and the second lower layer BL2 have different densities. The first lower layer BL1 is formed of silicon nitride (SiNx) having a relatively higher density than the second lower layer BL2 and may have dense characteristics. The second lower layer BL2 is may be formed of silicon nitride (SiNx) having a relatively lower density than the first lower layer BL1 and may have porous characteristics. The embodiment of the disclosure can further improve characteristic of the water vapor permeation by bringing the first lower layer BL1 having the relatively high density into contact with the plastic substrate SUB.

    [0066] The second buffer layer BF2 is positioned on the first buffer layer BF1. The second buffer layer BF2 functions to prevent the active layer ACT of the thin film transistor DT from being contaminated by impurities and to insulate the light shielding layer LS from the active layer ACT. The second buffer layer BF2 is formed of silicon oxide (SiOx). The second buffer layer BF2 may have a minimum thickness capable of insulating the light shielding layer LS and the active layer ACT from each other.

    [0067] The embodiment of the disclosure can further increase a length of a moving path of hydrogen existing in the lower layer BL toward the active layer ACT by further including the second buffer layer BF2 between the lower layer BL and the active layer ACT. Hence, the embodiment of the disclosure can further reduce hydrogen of the lower layer BL from entering the active layer ACT and minimize a reduction in the electrical characteristics of the oxide semiconductor.

    [0068] The thin film transistor DT includes the active layer ACT, a gate electrode GA, a source electrode SE, and a drain electrode DE. More specifically, the active layer ACT is positioned on the second buffer layer BF2. The active layer ACT is formed of an oxide semiconductor. Examples of the oxide semiconductor include a zinc oxide semiconductor such as indium gallium zinc oxide (IGZO). The oxide semiconductor has advantages that it has higher mobility than amorphous silicon and polycrystalline silicon and can be manufactured in a low-temperature process. Because the oxide semiconductor has a low OFF-current, the oxide semiconductor may be suitable for a thin film transistor which has a short ON-time and a long OFF-time. Further, because the oxide semiconductor increases a voltage hold time of the pixel due to the low OFF-current, the oxide semiconductor may be suitable for a display device requiring a low-speed drive and/or low power consumption.

    [0069] A gate insulating layer GI is positioned on the active layer ACT. The gate insulating layer GI insulates the gate electrode GA and may be formed of silicon oxide (SiOx). The gate insulating layer GI may not include silicon nitride (SiNx), in order to prevent hydrogen from entering the active layer ACT. The gate electrode GA is positioned on the gate insulating layer GI. The gate electrode GA may be formed as a single layer or a multilayer formed of one of copper (Cu), molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), tantalum (Ta), and tungsten (W) or a combination thereof. The gate electrode GA is positioned corresponding to the channel of the active layer ACT. An interlayer dielectric layer ILD is positioned on the gate electrode GA.

    [0070] The interlayer dielectric layer ILD insulates the gate electrode GA and the active layer ACT underlying the interlayer dielectric layer ILD. The interlayer dielectric layer ILD may be formed as a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a multilayer thereof. However, the interlayer dielectric layer ILD may not include the SiNx layer, in order to prevent hydrogen from entering the active layer ACT.

    [0071] The interlayer dielectric layer ILD has contact holes CH exposing both sides (for example, a source region and a drain region) of the active layer ACT. The source electrode SE and the drain electrode DE are positioned on the interlayer dielectric layer ILD. Each of the source electrode SE and the drain electrode DE may be formed as a single layer or as a multilayer. When each of the source electrode SE and the drain electrode DE is formed as the single layer, each of the source electrode SE and the drain electrode DE may be formed of one of molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a combination thereof. When each of the source electrode SE and the drain electrode DE is formed as the multilayer, each of the source electrode SE and the drain electrode DE may be formed as a double layer of Mo/Al-Nd, Mo/Al, or Ti/Al or as a triple layer of Mo/Al-Nd/Mo, Mo/Al/Mo, or Ti/Al/Ti. The source electrode SE and the drain electrode DE are respectively connected to both sides of the active layer ACT through the contact holes CH of the interlayer dielectric layer ILD.

    [0072] A passivation layer PAS is positioned on the thin film transistor DT. The passivation layer PAS protects the thin film transistor DT and may be formed as a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a multilayer thereof. However, the passivation layer PAS may not include the SiNx layer, in order to prevent hydrogen from entering the active layer ACT.

    [0073] A planarization layer OC is positioned on the passivation layer PAS and reduces a height difference of an underlying structure. The planarization layer OC may be formed of an organic material such as photo acryl, polyimide, benzocyclobutene-based resin, and acrylate-based resin. One of the passivation layer PAS and the planarization layer OC may be omitted, if necessary or desired.

    [0074] The organic light emitting diode OLE is positioned on the planarization layer OC. The organic light emitting diode OLE includes a first electrode ANO, an organic light emitting layer OL, and a second electrode CAT. More specifically, the first electrode ANO is positioned on the planarization layer OC. The first electrode ANO is connected to the drain electrode DE of the thin film transistor DT through a contact hole penetrating the passivation layer PAS and the planarization layer OC. The first electrode ANO may serve as a transmissive electrode formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). Further, the first electrode ANO may further include a reflective layer and serve as a reflective electrode. The reflective layer may be formed of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), palladium (Pd) or a combination thereof. For example, the reflective layer may be formed of an Ag/Pd/Cu (APC) alloy.

    [0075] In addition, a bank layer BN defining the pixels is positioned on the plastic substrate SUB including the first electrode ANO. The bank layer BN may be formed of an organic material such as polyimide, benzocyclobutene-based resin, and acrylate. The organic light emitting layer OL is positioned on the first electrode ANO exposed by the bank layer BN. The organic light emitting layer OL is a layer, in which electrons and holes combine and emit light. The organic light emitting diode OLE may further include a hole injection layer and/or a hole transport layer between the organic light emitting layer OL and the first electrode ANO, and may further include an electron injection layer and/or an electron transport layer on the organic light emitting layer OL.

    [0076] The second electrode CAT is positioned on the organic light emitting layer OL. The second electrode CAT may be formed of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or a combination thereof each having a low work function. The second electrode CAT may be thin enough to transmit light and thus may serve as a transmissive electrode. Further, the second electrode CAT may be thick enough to reflect light and thus may serve as a reflective electrode.

    [0077] The flexible display according to the embodiment of the disclosure can block ions or impurities diffused from the plastic substrate and prevent the moisture penetration from the outside by forming the buffer layer including the SiNx layer.

    [0078] The flexible display according to the embodiment of the disclosure can implement the buffer layer having the thin thickness while securing the predetermined barrier characteristics by using the SiNx layer having a good water vapor transmission rate relative to a thickness. Thus, the embodiment of the disclosure can provide the flexible display capable of preventing the moisture penetration from the outside while securing the flexibility of the display device.

    [0079] The flexible display according to the embodiment of the disclosure can prevent hydrogen included in the SiNx layer from entering the oxide semiconductor by forming the buffer layer including the SiNx layer and the SiOx layer stacked on the SiNx layer. Thus, the embodiment of the disclosure can prevent a reduction in the electrical characteristics of the oxide semiconductor.

    [0080] Effects of the flexible display according to the embodiment of the disclosure will be described below through a comparative example and an experimental example. The experiments described below are only examples of the embodiment of the disclosure, and the embodiment of the disclosure is not limited to the following experimental examples. FIG. 7 schematically illustrates a stacking structure of buffer layers according to a comparative example and an experimental example. FIG. 8 is a graph illustrating a current-voltage characteristic of an oxide semiconductor thin film transistor according to a comparative example and an experimental example.

    [0081] The following experiments are to examine a change in characteristics of an oxide semiconductor depending on a difference in stacking order of a silicon oxide (SiOx) layer and a silicon nitride (SiNx) layer constituting a first buffer layer between a comparative example and an experimental example, when the first buffer layer according to the comparative example and the first buffer layer according to the experimental example have the same thickness.

    < Comparative example >



    [0082] As shown in (a) of FIG. 7, a silicon nitride (SiNx) layer, a silicon oxide (SiOx) layer, and a silicon nitride (SiNx) layer were sequentially stacked on a polyimide (PI) substrate, so that the comparative example was in contrast to the first buffer layer according to the embodiment of the disclosure. A thickness of the SiNx layer was 1,000 Å, and a thickness of the SiOx layer was 1,000 Å.

    [0083] Next, a silicon oxide (SiOx) layer was stacked on the SiNx layer, so that the comparative example was in contrast to the second buffer layer according to the embodiment of the disclosure. A thin film transistor including an IGZO active layer was manufactured on the SiOx layer. A thickness of the SiOx layer was 3,000 Å.

    < Experimental example>



    [0084] As shown in (b) of FIG. 7, a silicon nitride (SiNx) layer, a silicon nitride (SiNx) layer, and a silicon oxide (SiOx) layer constituting the first buffer layer according to the embodiment of the disclosure were sequentially stacked on a polyimide (PI) substrate. A thickness of the SiNx layer was 1,000 Å, and a thickness of the SiOx layer was 1,000 Å.

    [0085] Next, a silicon oxide (SiOx) layer constituting the second buffer layer according to the embodiment of the disclosure was stacked, and a thin film transistor including an IGZO active layer was manufactured on the SiOx layer. A thickness of the SiOx layer was 3,000 Å.

    [0086] FIG. 8 illustrates a result of measuring a current-voltage characteristic of an oxide semiconductor thin film transistor according to the comparative example and the experimental example.

    [0087] Referring to FIG. 8, a threshold voltage of an oxide semiconductor thin film transistor according to the comparative example was shifted by -4.69V in a negative direction and exceeded a normal range. Further, a threshold voltage of an oxide semiconductor thin film transistor according to the experimental example was shifted by -0.03V in the negative direction and was in the normal range.

    [0088] It can be seen from the comparative example that when the first buffer layer includes the SiNx layer, and the SiNx layer is disposed at an uppermost layer of the first buffer layer, hydrogen existing in the SiNx layer is diffused into the IGZO active layer and changes the device characteristics. On the other hand, when the first buffer layer includes the SiNx layer, and the SiOx layer is further formed on the SiNx layer as in the experimental example, an amount of hydrogen existing in the SiNx layer entering the IGZO active layer can decrease. Hence, change in the device characteristics can decrease. Thus, the embodiment of the invention includes the first buffer layer including the SiNx layer and the SiOx layer and disposes the SiOx layer on the SiNx layer in the first buffer layer, thereby securing the reliability of the oxide semiconductor thin film transistor even when the SiNx layer is used.

    [0089] Referring again to FIG. 8, a degree of scattering of the threshold voltage in the oxide semiconductor thin film transistor according to the comparative example was Δ7.22 which is beyond a normal range. Further, a degree of scattering of the threshold voltage in the oxide semiconductor thin film transistor according to the experimental example was Δ0.72 which is in the normal range.

    [0090] More specifically, when a thickness variation of the SiNx layer occurs depending on the position in the CVD process, an influence of the SiNx layer on the oxide semiconductor varies depending on the position. As a result, the degree of scattering of the threshold voltage of the oxide semiconductor increases.

    [0091] The embodiment of the invention can sufficiently secure a separation distance between the SiNx layer and the oxide semiconductor by disposing the SiOx layer on the SiNx layer in the first buffer layer. Hence, the embodiment of the invention can prevent an influence of the SiNx layer on the oxide semiconductor even when the SiNx layer is formed to have the thickness variation depending on the position, thereby securing the reliability of the components.


    Claims

    1. A flexible display including an oxide semiconductor thin film transistor (DT) on a plastic substrate (SUB), comprising:

    a first buffer layer (BF1) disposed on the plastic substrate (SUB);

    a second buffer layer (BF2) disposed on the first buffer layer (BF1) and formed of silicon oxide;

    an active layer (ACT) disposed on the second buffer layer (BF2) and formed of an oxide semiconductor; and

    a light shielding layer (LS) disposed between the first buffer layer (BF1) and the second buffer layer (BF2) and overlapping the active layer (ACT),

    wherein the first buffer layer (BF1) includes:

    a lower layer (BL) directly contacting the plastic substrate (SUB) and formed of silicon nitride; and

    an upper layer (TL) disposed on the lower layer (BL) and formed of silicon oxide,

    wherein the lower layer (BL) includes a first lower layer (BL1) formed on the plastic substrate (SUB) and a second lower layer (BL2) formed on the first lower layer (BL1), the first lower layer (BL1) having a higher density than the second lower layer (BL2).


     
    2. The flexible display of claim 1, wherein a thickness of the lower layer (BL) is equal to or greater than a thickness of the upper layer (TL).
     
    3. The flexible display of claim 1 or 2, wherein the first lower layer (BL1) and the second lower layer (BL2) are formed by temporally and/or spatially separate deposition processes.
     
    4. The flexible display of any one of claims 1 to 3, wherein the first lower layer (BL1) comprises first micro-sized cracks and the second lower layer (BL2) comprises second micro-sized cracks, wherein the first micro-sized cracks and the second micro-sized cracks are separated from each other without being connected to each other.
     
    5. The flexible display of any one of claims 1 to 3, wherein the first lower layer (BL1) has dense characteristics and the second lower layer (BL2) has porous characteristics.
     


    Ansprüche

    1. Flexible Anzeige, die einen Oxidhalbleiter-Dünnschichttransistor (DT) an einem Kunststoffsubstrat (SUB) aufweist, aufweisend:

    eine erste Pufferschicht (BF1), die an dem Kunststoffsubstrat (SUB) angeordnet ist;

    eine zweite Pufferschicht (BF2), die an der ersten Pufferschicht (BF1) angeordnet und aus Siliziumoxid gebildet ist;

    eine Aktivschicht (ACT), die an der zweiten Pufferschicht (BF2) angeordnet und aus einem Oxidhalbleiter gebildet ist; und

    eine Lichtabschirmungsschicht (LS), die zwischen der ersten Pufferschicht (BF1) und der zweiten Pufferschicht (BF2) angeordnet ist und die Aktivschicht (ACT) überlappt,

    wobei die erste Pufferschicht (BF1) aufweist:

    eine untere Schicht (BL), die das Kunststoffsubstrat (SUB) direkt kontaktiert und aus Siliziumnitrid gebildet ist; und

    eine obere Schicht (TL), die an der unteren Schicht (BL) angeordnet und aus Siliziumoxid gebildet ist,

    wobei die untere Schicht (BL) aufweist: eine erste untere Schicht (BL1), die auf dem Kunststoffsubstrat (SUB) gebildet ist, und eine zweite untere Schicht (BL2), die auf der ersten unteren Schicht (BL1) gebildet ist, wobei die erste untere Schicht (BL1) eine größere Dichte als die zweite untere Schicht (BL2) aufweist.


     
    2. Flexible Anzeige nach Anspruch 1, wobei eine Dicke der unteren Schicht (BL) gleich oder größer als eine Dicke der oberen Schicht (TL) ist.
     
    3. Flexible Anzeige nach Anspruch 1 oder 2, wobei die erste untere Schicht (BL1) und die zweite untere Schicht (BL2) durch zeitlich und/oder räumlich getrennte Abscheidungsprozesse gebildet sind.
     
    4. Flexible Anzeige nach einem der Ansprüche 1 bis 3, wobei die erste untere Schicht (BL1) erste Risse von Mikrogröße aufweist und die zweite untere Schicht (BL2) zweite Risse von Mikrogröße aufweist, wobei die ersten Risse von Mikrogröße und die zweiten Risse von Mikrogröße getrennt voneinander sind, ohne miteinander verbunden zu sein.
     
    5. Flexible Anzeige nach einem der Ansprüche 1 bis 3, wobei die erste untere Schicht (BL1) dichte Charakteristiken aufweist und die zweite untere Schicht (BL2) poröse Charakteristiken aufweist.
     


    Revendications

    1. Ecran souple incluant un transistor en couches minces semi-conducteur à oxyde (DT) sur un substrat en plastique (SUB), comprenant :

    une première couche tampon (BF1) disposée sur le substrat en plastique (SUB) ;

    une seconde couche tampon (BF2) disposée sur la première couche tampon (BF1) et formée d'oxyde de silicium ;

    une couche active (ACT) disposée sur la seconde couche tampon (BF2) et constituée d'un semi-conducteur à oxyde ; et

    une couche anti-éblouissement (LS) disposée entre la première couche tampon (BF1) et la seconde couche tampon (BF2) et recouvrant la couche active (ACT),

    dans lequel la première couche tampon (BF1) inclut :

    une couche inférieure (BL) en contact direct avec le substrat en plastique (SUB) et constituée de nitrure de silicium ; et

    une couche supérieure (TL) disposée sur la couche inférieure (BL) et formée d'oxyde de silicium,

    dans lequel la couche inférieure (BL) inclut une première couche inférieure (BL1) formée sur le substrat en plastique (SUB) et une seconde couche inférieure (BL2) formée sur la première couche inférieure (BL1), la première couche inférieure (BL1) ayant une densité supérieure à la seconde couche inférieure (BL2).


     
    2. Ecran souple selon la revendication 1, dans lequel une épaisseur de la couche inférieure (BL) est supérieure ou égale à une épaisseur de la couche supérieure (TL).
     
    3. Ecran souple selon la revendication 1 ou 2, dans lequel la première couche inférieure (BL1) et la seconde couche inférieure (BL2) sont formées par des procédés de dépôt séparés dans le temps et/ou dans l'espace.
     
    4. Ecran souple selon l'une quelconque des revendications 1 à 3, dans lequel la première couche inférieure (BL1) comprend des premières microfissures et la seconde couche inférieure (BL2) comprend des secondes microfissures, dans lequel les premières microfissures et les secondes microfissures sont séparées les unes des autres sans être reliées les unes aux autres.
     
    5. Ecran souple selon l'une quelconque des revendications 1 à 3, dans lequel la première couche inférieure (BL1) a des caractéristiques denses et la seconde couche inférieure (BL2) a des caractéristiques poreuses.
     




    Drawing
























    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description