(19)
(11)EP 3 300 121 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
15.04.2020 Bulletin 2020/16

(21)Application number: 17001494.8

(22)Date of filing:  06.09.2017
(51)International Patent Classification (IPC): 
H01L 29/861(2006.01)
H01L 29/167(2006.01)
H01L 21/329(2006.01)
H01L 29/36(2006.01)

(54)

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

VERFAHREN ZUR HERSTELLUNG EINES HALBLEITERBAUELEMENTS

PROCÉDÉ DE FABRICATION D'UN DISPOSITIF SEMI-CONDUCTEUR


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 27.09.2016 JP 2016187705

(43)Date of publication of application:
28.03.2018 Bulletin 2018/13

(73)Proprietor: Hitachi Power Semiconductor Device, Ltd.
Hitachi-shi, Ibaraki 319-1221 (JP)

(72)Inventors:
  • Wakagi, Masatoshi
    Tokyo, 100-8280 (JP)
  • Arai, Taiga
    Tokyo, 100-8280 (JP)
  • Mori, Mutsuhiro
    Tokyo, 100-8280 (JP)
  • Furukawa, Tomoyasu
    Tokyo, 100-8280 (JP)

(74)Representative: Strehl Schübel-Hopf & Partner 
Maximilianstrasse 54
80538 München
80538 München (DE)


(56)References cited: : 
EP-A2- 2 706 576
DE-C1- 4 013 626
US-A1- 2015 325 440
DE-A1- 4 336 663
JP-A- 2016 184 713
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    BACKGROUND OF THE INVENTION


    1. Field of the Invention



    [0001] The present invention relates to a semiconductor device, a method for manufacturing the same, and a power conversion system.

    2. Description of the Related Art



    [0002] The implementation of a deep n-buffer layer has been known as a technology to suppress an oscillation phenomenon due to a rapid decrease of a tail current (see, for example, JP-2008-251679-A).

    [0003] Also, the application of phosphorus (P) as a dopant of a deep n-buffer layer has been known as a technology to form a deep n-buffer layer to suppress the oscillation phenomenon due to a rapid decrease of a tail current (see, for example, JP-2014-146721-A).

    [0004] Also, the formation of several n-buffer layers generated by proton irradiation or local formation thereof in an n- layer center portion has been known as a technology to form a deep n-buffer layer to suppress the oscillation phenomenon due to a rapid decrease of a tail current (see, for example, WO-2011/052787-A1 or WO-2007/055352-A1).

    [0005] Also, the application of selenium (Se) as a dopant of a deep n-buffer layer has been known as a technology to form a deep n-buffer layer to suppress the oscillation phenomenon due to a rapid decrease of a tail current (see, for example, US-2012/0248576-A1).

    [0006] DE 43 36 663 A1 discloses a method of manufacturing a diode comprising the steps of diffusing oxygen into a n-doped Si substrate, forming a high n-doped cathode region in the substrate at one surface thereof, grinding the opposite surface of the substrate, forming a p-doped anode region in the substrate at the ground surface, forming anode and cathode contacts and annealing them at 450°C. The annealing step transforms the oxygen present in the substrate into thermal donors and increases the doping concentration in the portion of the substrate between anode and cathode regions, in particular in a region close to the cathode where the oxygen concentration is higher.

    [0007] JP 2016 184713 A is an earlier application of the present inventors which has been published after the priority date of the present application. That earlier application discloses a method similar to the one of DE 43 36 663 A.

    SUMMARY OF THE INVENTION



    [0008] A diode used as a freewheel diode by being connected in anti-parallel with an insulated gate bipolar transistor (IGBT) or metal-oxide-semiconductor (MOS) transistor in a power converter is further demanded to reduce recovery loss as a loss of diode during switching with an increasing drive frequency of the converter.

    [0009] The recovery loss can be reduced by making a wafer thinner, but carriers injected in an On state during recovery decrease rapidly and accordingly a tail current decreases rapidly, posing a problem that oscillation of frequencies of several MHz or more as shown in Fig. 8 occurs.

    [0010] To suppress the oscillation phenomenon, JP-2008-251679-A and JP-2014-146721-A disclose a configuration that implements a deep n-buffer layer. In this configuration, a decreasing speed of injected carriers during recovery is suppressed due to the deep n-buffer layer and the oscillation phenomenon can be suppressed by making a decrease of a tail current slower.

    [0011] Particularly, JP-2014-146721-A discloses the application of phosphorus (P) as a dopant of the n-buffer layer. Also, WO-2011/052787-A1 and WO-2007/055352-A1 disclose technologies to suppress the oscillation phenomenon by a configuration in which several n-buffer layers generated by proton irradiation are formed or a configuration in which an n-buffer layer is locally formed in an n- layer center portion. Further, US-2012/0248576-A1 discloses a configuration of a diode or the like in which a deep n-buffer layer using selenium (Se) as a dopant is applied.

    [0012] However, JP-2008-251679-A does not disclose a concrete dopant. JP-2014-146721-A discloses P, which is a V-group element, as a dopant, but in order to disperse P 30 µm or more as described in JP-2008-251679-A, it is necessary to disperse P for a long time at a high temperature of about 1300°C, posing a problem of low productivity. For V-group elements such as As and Sb applied ordinarily as n-type dopants, the diffusion constant is still smaller so that it is necessary to further extend the diffusion time.

    [0013]  WO-2011/052787-A1 and WO-2007/055352-A1 disclose the formation of an n-buffer layer by proton irradiation. However, in order to generate a donor to form an n-buffer layer in a deep position, irradiation of a large amount of high-energy protons is needed. Therefore, it is necessary to accelerate protons by a cyclotron for irradiation, positing a problem of increased costs.

    [0014] Further, WO-2011/052787-A1 and WO-2007/055352-A1 disclose a configuration in which an n-buffer layer is isolated and formed in a position relatively close to an anode. In this configuration, an electric field on the anode side becomes strong when a reverse bias is applied, inviting the degradation of withstand voltage and also posing a problem that a cosmic radiation ruggedness is deteriorated particularly in a high-voltage diode.

    [0015] In US-2012/0248576-A1, Se is applied as a dopant of the n-buffer layer. Se has a diffusion constant larger than that of P and so a deep n-buffer layer can be formed by diffusion in a short time at low temperature. However, it is normally necessary to newly introduce an Se material to the production line, which may cause a problem of line contamination. It is also necessary to install equipment of ion implantation of Se.

    [0016] In view of the above problems, it is preferable to provide a diode capable of suppressing the oscillation phenomenon at low cost. Alternatively, it is preferable to provide the configuration of a diode excellent in withstand voltage characteristics or cosmic radiation ruggedness. Alternatively, it is preferable to provide a device structure that is less likely to produce line contamination when diodes are manufactured.

    [0017] The present invention is made in view of the above circumstances and an object thereof is to provide a method for manufacturing a semiconductor device that is cost-effective and at the same time, capable of suppressing the oscillation phenomenon.

    [0018] In order to solve the above problem, the present invention provides a method for manufacturing a semiconductor device with the features defined in claim 1.

    [0019] Using he method of the present invention it is possible to cost-effectively suppress the oscillation phenomenon in a semiconductor device and a power conversion system comprising it.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0020] 

    Fig. 1A is a schematic sectional view of a diode according to a first example useful to understand the present invention in an active area and Fig. 1B is an n-type carrier concentration and oxygen concentration distribution chart;

    Fig. 2A is a schematic sectional view of a manufacturing process of the diode according to the first example in the active area and Fig. 2B is an oxygen concentration distribution chart;

    Fig. 3 is a schematic sectional view of another manufacturing process of the diode according to the first example in the active area;

    Fig. 4 is a schematic sectional view of still another manufacturing process of the diode according to the first example in the active area;

    Fig. 5 is a schematic sectional view of still another manufacturing process of the diode according to the first example in the active area;

    Fig. 6 is a diagram showing the relationship between an oxygen concentration and an oxygen thermal donor n-type carrier concentration;

    Fig. 7A is a schematic sectional view of a diode according to Comparative Example in an active area and Fig. 7B is an n-type carrier concentration and oxygen concentration distribution chart;

    Fig. 8 is a diagram showing voltage waveforms and current waveforms of the diodes according to the first example and Comparative Example during small-current recovery;

    Fig. 9 is a schematic sectional view of a diode according to a second example useful to understand the invention in the active area;

    Fig. 10A is a schematic sectional view of a diode according to a third example useful to understand the present invention in the active area and Fig. 10B is an n-type carrier concentration and oxygen concentration distribution chart;

    Fig. 11A is a schematic sectional view of a which can be manufactured by means of a method according to a first embodiment of the present invention in an active area and Fig. 11B is an n-type carrier concentration and oxygen concentration distribution chart;

    Fig. 12 is a diagram showing the relationship between yields and the thickness of a cathode n layer 104; and

    Fig. 13 is a block diagram of a power conversion system which can comprise a device manufactured by means of the method of the present invention.


    DESCRIPTION OF THE PREFERRED EMBODIMENTS AND EXAMPLES


    [Overview of the embodiments and the examples]



    [0021] The diode according to each embodiment or example described below includes an anode electrode on one side of a silicon (Si) semiconductor and a cathode electrode on the other side thereof and also includes a p-type layer (for example, an anode p layer 102 shown in Fig. 1A) adjacent to the anode electrode and an n-type layer (for example, the cathode n layer 104 shown in Fig. 1A) adjacent to the cathode electrode. The n-type layer is formed by containing a V-group element. As the V-group element, P (phosphorus), As (arsenic), and Sb (antimony) can be cited. These elements have a high activation rate of n-type carriers and so can form an n-type layer of high concentration.

    [0022] The diode includes an n-buffer layer (for example, an n-buffer layer 105 shown in Fig. 1A) containing oxygen continuously throughout an area adjacent to the n-type layer and having a thickness of 30 µm or more. The n-type carrier concentration of the n-buffer layer is higher than the carrier concentration of an n- layer (for example, an n- drift layer 101 in Fig. 1A) and is 1 x 1015 cm-3 or less. Further, the oxygen concentration in the area 30 µm away from the n-type layer is set to 1 x 1017 cm-3 or more and 1 x 1018 cm-3 or less, which is higher than the oxygen concentration of an area adjacent to the n-type layer. Further, the oxygen concentration of the n- layer adjacent to the p-type layer described above is set to less than 3 x 1017 cm-3.

    [0023] In the configuration of each embodiment or example described below, an oxygen thermal donor is generated to form an n-buffer layer. The diffusion coefficient of oxygen is larger than that of P, which is a V-group element, by two digits or more. Thus, oxygen can diffuse deeply in a short time. Oxygen is also used as an atmosphere of ordinary diffusion and can form an n-buffer layer configured for each embodiment or example by heat treatment in an oxygen atmosphere without using a special device. The oxygen thermal donor is eliminated by heat treatment at 800°C or more and is generated by heat treatment at 400 to 600°C. Thus, in a normal diode forming process, the n-type carrier concentration of the n-buffer can be adjusted by, after an oxygen thermal donor being eliminated by heat treatment at 800 to 1000°C, forming an oxygen thermal donor by annealing as, for example, activation annealing of an n-type layer or densify annealing of a boron phosphorus silicon glass (BPSG) film formed as an interlayer dielectric, at 400 to 500°C as a sinter after an electrode of Al or the like being formed.

    [0024] The carrier concentration of the oxygen thermal donor needs to be set larger than that of the n- layer. Further, the n-type carrier concentration is desirably set to 1 x 1015 cm-3 or less to ensure the life time of carriers.

    [0025] The n-type carrier concentration of the oxygen thermal donor is proportional to about 5-th power of the oxygen concentration from examinations by the present inventors and the n-type carrier concentration by the thermal donor can be made larger than that of the n- layer and set to 1 x 1015 cm-3 by setting the oxygen concentration in a position 30 µm away from the n-type layer to 1 x 1017 cm-3 to 1 x 1018 cm-3.

    [0026] An area of minimum n-type carrier concentration can be formed by making the oxygen concentration adjacent to the n-type layer lower than that of an area 30 µm away from the n-type layer. By storing holes in the area during recovery, a tail current component can be secured to reinforce an effect of suppressing the oscillation phenomenon.

    [0027] In each embodiment or example, the n-buffer layer is continuously formed up to an area of 30 µm or more. Also, the oxygen concentration near the p layer on the anode side is set to less than 3 x 1017 cm-3 and the n-type carrier concentration of the area is set to the level of the n- layer including low withstand voltage elements. Thus, the voltage of this portion when an inverse bias is applied can be reduced so that the withstand voltage can be ensured and also cosmic radiation ruggedness characteristics can be maintained in good condition.

    [0028] In the above configuration, the oxygen concentration on the cathode side is higher than that on the anode side. As described above, oxygen diffuses from both sides of a wafer after heat treatment in an oxygen atmosphere. Thus, the oxygen concentration can be reduced more on the anode side than on the cathode side by, for example, polishing the wafer from one side and setting the side as the anode side. Also, the oxygen concentration near the cathode surface can be reduced by out diffusion on the cathode side.

    [0029] Here, the configuration in which an area where the oxygen concentration is 5 x 1017 cm-3 or more and 1 x 1018 cm-3 or less and the concentration decreases toward the anode side is provided at least 10 µm becomes an effective structure to prevent the oscillation phenomenon, that is, ringing during recovery of a diode. With the oxygen concentration in the above range, an oxygen donor of 1 x 1012 cm-3 to 1 x 1015 cm-3 can be formed and further, by providing a carrier concentration gradient of the n-buffer layer 105 toward the anode side by the oxygen donor in the area of 10 µm or more, the speed of depletion during recovery can gradually be delayed so that the effect of ringing prevention by soft recovery can be increased.

    [0030] The configuration of each embodiment or example can be formed by producing a diode using the wafer. As described above, the configuration has an effect of suppressing the oscillation phenomenon. Also, the diffusion coefficient of oxygen is larger than that of P and thus, the configuration can be formed in a short time and so productivity can be improved and costs can be reduced. Also, with heat treatment in an oxygen atmosphere using a diffusion furnace, diodes can be manufactured without concerns about production line contamination.

    [0031] According to the invention, a structure in which an n layer is formed by diffusion of a V-group element such as P simultaneously with diffusion of oxygen that forms an n-buffer layer is effective. In this case, the n-buffer layer containing oxygen is continuously formed up to an area of 30 µm or more from the n layer. By setting the thickness of the n layer in this configuration to 50 µm or more, particularly a diode whose withstand voltage is 1.7 kV or less can maintain the whole wafer thick while maintaining the n- layer and the n-buffer layer thin. Accordingly, wafer damage during diode manufacturing process can be prevented and also yields can be improved. Also, by setting the oxygen concentration 30 µm away from the n layer to 1 x 1017 cm-3 to 1 x 1018 cm-3, the n-type carrier concentration by the thermal donor can be made larger than that of the n- layer and also set to 1 x 1015 cm-3 or less.

    [0032] Further, the oxygen concentration near the p layer on the anode side is set to less than 3 x 1017 cm-3 and the n-type carrier concentration of the area is set to the level of the n- layer. Also, this configuration is effective, like the above configuration, in suppressing the oscillation phenomenon during recovery so that the withstand voltage can be ensured and also cosmic radiation ruggedness characteristics can be maintained in good condition. Also with this configuration, the process can be reduced because the formation of the n layer and the oxygen diffusion are performed simultaneously.

    [0033] Hereinafter, each embodiment or example will be described in detail based on the drawings. In each diagram used to describe each embodiment or example, the same reference signs are attached to components having corresponding functions and a repeated description thereof is omitted when appropriate. Also in the description of each embodiment or example below, the description of the same portions or similar ones is omitted without being repeated when appropriate except when particularly needed.

    [First example]


    <Configuration of the first example>



    [0034] First, the configuration of a diode according to the first example useful to understand the present invention will be described with reference to Figs. 1A and 1B. Fig. 1A is a schematic sectional view of a diode 1 according to the first example in an active area and Fig. 1B is an n-type carrier concentration and oxygen concentration distribution chart thereof. In Fig. 1A, the illustration of a termination area is omitted and a known termination structure such as a field limiting ring (FLR) type in which a p-type well and an electrode are arranged in a ring shape may be applied to the termination area.

    [0035] As shown in Fig. 1A, the diode 1 according to the first example includes the n- drift layer 101, the anode p layer 102, an anode p- layer 103, the cathode n layer 104, the n-buffer layer 105 containing oxygen, an anode electrode 106, and a cathode electrode 107.

    [0036] In the description that follows, including intermediate steps of the manufacturing process, an entire semiconductor layer portion will be called an Si substrate 100. Oxygen is diffused beforehand into the Si substrate 100. A wafer of the oxygen concentration distribution as shown in Fig. 1B can be produced by, for example, diffusing oxygen at 1300°C for 15 h in an oxygen atmosphere and then polishing the wafer several hundred µm. Alternatively, a wafer into which oxygen has been diffused from both side may be cut in half to polish the cut surface.

    [0037] The n- drift layer 101 shown in Fig. 1A is a semiconductor layer made mainly of n-type Si and an n-type semiconductor layer made mainly of an n-type semiconductor area of an original n-type Si substrate before being denatured by ion implantation, diffusion or the like.

    [0038] The cathode n layer 104 is provided on the cathode side, which is the back side of the Si substrate 100, and is a n-type semiconductor layer made of an n-type impurity area of the concentration higher than that of the n- drift layer 101 and the n-buffer layer 105. As the n-type impurity of the cathode n layer 104, for example, a V-group element that is not oxygen is contained. As the V-group elements, P, As, and Sb can be cited. These elements can be made to have the activation rate of almost 100% and so are suitable for forming an n layer of high concentration.

    [0039] The n-buffer layer 105 is provided between the cathode n layer 104 and the n- drift layer 101 and is an n-type semiconductor layer made mainly of an oxygen thermal donor of the concentration lower than that of the cathode n layer 104 and higher than that of the n- drift layer 101. With such a configuration, the stretch of a depletion layer from a PN junction to the cathode side is suppressed and so ringing can be suppressed.

    [0040] The anode p layer 102 is locally provided on the anode side as a front side (upper side in Fig. 1A) of the Si substrate 100 and is a p-type semiconductor layer made mainly of a p-type impurity area. The anode p- layer 103 is provided on the anode side as the front side of the Si substrate 100 in an area where the anode p layer 102 is not provided and is a p-type semiconductor layer made mainly of a p-type impurity area of the concentration lower than that of the anode p layer 102.

    [0041] That is, the Si substrate 100 has a well structure on the front side in which the anode p- layer 103 as a thin p-type impurity area layer of low concentration is formed and the anode p layer 102 that is thick and made mainly of a locally high-concentration p-type impurity area.

    [0042] In the present example, the Si substrate 100 has a well structure in which the anode p layer 102 is locally arranged in the active area (area shown in Fig. 1A) and the well structure is configured to make recovery soft by suppressing the injection amount of holes from the anode electrode 106, that is, to reduce the rebound of voltage during recovery.

    [0043] The anode p layer 102 shown in Fig. 1A and arranged locally can be formed in a shape such as a dot (circular) shape or a stripe shape in a plane view when viewed from the front side of the Si substrate 100 as the anode side. For example, the anode p layer 102 can be formed in a circular shape of the diameter 10 to 100 µm and the circular shapes can be arranged by setting the distance therebetween to 10 to 200 µm. The depth of the anode p layer 102 can be set to about 3 to 10 µm and the peak concentration of p-type impurities can be set to about 1 x 1017 cm-3 to 1 x 1019 cm-3. Incidentally, the impurity concentration and dimensions of the anode p layer 102 can appropriately be set in accordance with the withstand voltage and specifications.

    [0044] On the front side of the Si substrate 100, the anode p- layer 103 of the concentration lower than that of the anode p layer 102 and made mainly of a p-type impurity area is formed in an area outside the area where the anode p layer 102 is provided. The peak concentration of p-type impurities of the anode p- layer 103 is preferably set to about 1 x 1015 cm-3 to 1 x 1017 cm-3. If the anode p- layer 103 is provided, a leak current flowing from the anode electrode 106 can be reduced when compared with a case when the anode p- layer 103 is not provided. If the leak current can be tolerated, the anode p layer 102 locally provided as a p-type semiconductor layer may be applied by omitting the anode p- layer 103. In that case, the process can be simplified by omitting an ion implantation process of p-type impurities to form the anode p- layer 103.

    [0045] The anode electrode 106 is an electrode ohmically connected to the anode p layer 102 and the cathode electrode 107 is an electrode ohmically connected to the cathode n layer 104.

    <Method for manufacturing diodes according to the first-example>



    [0046] Next, an example of the method for manufacturing the structure of an active area of the diode 1 according to the present example will be described. The structure of a termination area is also produced simultaneously with the structure of active area and the method for manufacturing the structure of the termination area is similar to that for manufacturing conventional diodes and so the description thereof is simplified.

    (Preparations of the substrate)



    [0047] First, an Si wafer into which oxygen has been diffused is prepared as the Si substrate 100 to produce the diode 1. Fig. 2B is an oxygen concentration distribution chart of the Si substrate 100. As the Si wafer, a floating zone (FZ) wafer having the specific resistance in accordance with the withstand voltage can be used. In the present example, a bulk of FZ wafer is used as the n- drift layer 101. The specific resistance of the FZ wafer is set to about 250 Ωcm for a diode having the withstand voltage of, for example, 3.3 kV.

    (Active area forming process)



    [0048] Next, an oxide film (not shown) is formed on the entire front side of the Si substrate 100 by thermal oxidation. Next, a photolithography process to form an active area as an area where the anode p- layer 103 (see Fig. 1A) is to be provided is performed. In the photolithography process, a resist in which the entire surface of the active area is open is formed by applying, exposing, and developing a resist material on the front side of the Si substrate 100. At this point, the resist is also opened as an area where a p-type well is to be formed in the termination area. Subsequently, an oxide film exposed through the opening of the resist is removed by wet etching and also the resist is removed. In this process, an oxide film in which the entire surface of the active area and an area where a p-type well of the termination area is to be formed are opened is formed on the front side of the Si substrate 100.

    (Anode p- layer forming process)



    [0049] Then, as shown in Fig. 2A, an implantation-through oxide film 108 is formed on the front side of the Si substrate 100 by thermal oxidation. An area where the oxide film (not shown) formed in the active area forming process and a thick film portion of the oxide film made of the implantation-through oxide film 108 overlap becomes a mask. Then, p-type impurities to form the anode p- layer 103 are implanted through the implantation-through oxide film 108 as a thin film portion. Accordingly, p-type impurities are implanted in the entire active area to entirely form the anode p- layer 103.

    (Anode p layer forming process)



    [0050] Next, as shown in Fig. 3, a photolithography process to form the anode p layer 102 is performed. In the photolithography process, a resist 109 having an opening in an area where the anode p layer 102 is to be formed of the active area is formed by applying, exposing, and developing a resist material on the front side of the Si substrate 100. At this point, an area where a p-type well is to be formed is also opened in the termination area (not shown). Then, the resist 109 is used as a mask to implant p-type impurities to form the anode p layer 102. At this point, p-type impurities are also implanted in the area where a p-type well is to be formed in the termination area (not shown) simultaneously.

    [0051] Next, the resist 109 is removed and then high-temperature annealing and oxidation are performed and at this point, the Si substrate 100 looks as shown in Fig. 4 (the anode electrode 106 shown in Fig. 4 is not yet generated at this stage) . Next, as shown in Fig. 4, implanted p-type impurities are diffused to form the anode p layer 102 and the anode p- layer 103 and also an oxide film (not shown) formed on the front side of the Si substrate 100 is allowed to grow.

    (Cathode n layer forming process)



    [0052] Then, n-type impurities to form the cathode n layer 104 are sequentially implanted entirely in the wafer from the back side (lower side in Fig. 4) of the Si substrate 100. As the n-type impurity, for example, a V-group element that is not oxygen is used. Next, the oxygen thermal donor can be eliminated by an impurity activation annealing process, that is, a process that activates implanted n-type impurities at 800 to 1000°C. Alternatively, prior to the impurity activation annealing process, an interlayer dielectric (not shown) such as BPSG may be formed. Also by performing densify annealing of the interlayer dielectric at 800 to 1000°C, n-type impurities can be activated and also the oxygen thermal donor can be eliminated.

    (Anode electrode/n-buffer layer forming process)



    [0053] Subsequently, a photolithography process to form a contact portion is performed. In the photolithography process, a resist (not shown) having an opening in the entire active area is formed by applying, exposing, and developing a resist material.

    [0054] Subsequently, an oxide film (not shown) exposed through the opening of the resist is removed by etching and also the resist is removed. Then, the film made of a conductive material to be the anode electrode 106, for example, an AlSi film is formed by sputtering or vapor deposition. The anode electrode is sintered at 400 to 500°C. By generating an oxygen thermal donor in this process, the n-type carrier concentration of the n-buffer layer 105 can be controlled with precision. Also by setting the treatment temperature after this process to 400°C or less, a thermal donor is prevented from being additionally generated.

    [0055] Then, a lithography process and an etching process to form an electrode provided on the p-type well in the termination area (not shown) are performed. Accordingly, the electrode on the p-type well is formed. At this point, as shown in Fig. 4, an AlSi film formed entirely in the active area becomes the anode electrode 106.

    [0056] Next, after the resist to process the electrode provided in the termination area (not shown) being removed, a protective film is formed in the termination area. As a method for forming a protective film, for example, a solution containing a precursor material of polyimide and a photosensitive material is applied and the termination area is exposed to light to change the precursor to polyimide to be able to form a polyimide protective film in the termination area.

    [0057] This completes the structure on the anode side.

    (Cathode electrode forming process)



    [0058] Next, as shown in Fig. 5, the structure on the cathode side is formed.

    [0059] First, the cathode electrode 107 is formed on the back side as the cathode side. The cathode electrode 107 can be formed by a method similar to that for forming the anode electrode 106 using an appropriate conductive material such as metal.

    [0060] Then, the entire wafer area is irradiated with an electron beam from the back side (lower side in Fig. 5) to adjust the life time of carriers and further, annealing may be performed for recovery of damage done by irradiation of the electron beam.

    [0061] Also, to reduce losses during recovery, the anode side may be irradiated with helium (He) proton to perform annealing at about 350°C. In this case, by making a local life time around an area where the oxygen concentration is 1 x 1017 cm-3 or more shorter, the amount of carriers remaining in the latter half of the recovery period can be reduced so that losses can be reduced effectively.

    (Division process)



    [0062] Lastly, chips of the diode 1 are completed by dividing the wafer by dicing or the like.

    <Production example>



    [0063] Next, a production example of producing the diode 1 according to the present example will be described.

    [0064] The diode of the present production example applies a wafer into which oxygen has been diffused as the Si substrate 100. Here, an anode electrode sinter to form an oxygen thermal donor is thermally treated at 450°C for only 0.5 to 8 h to examine the relationship between the oxygen concentration and the n-type carrier concentration. In Fig. 6, the relationship between the oxygen concentration and the oxygen thermal donor n-type carrier concentration is shown. It is evident from Fig. 6 that the gradient of log-log plotting is about 5 and the n-type carrier concentration is generated in proportion to approximately the fifth power of the oxygen concentration.

    [0065] It is also evident from Fig. 6 that the n-type carrier concentration is 1 x 1011 cm-3 or less when the oxygen concentration is less than 1 x 1017 cm-3. For an ordinary 3.3-kV diode, the n-type carrier concentration of the n- layer is 1.8 x 1013 cm-3 and thus, the n-type carrier concentration can be suppressed to 1/10 or less thereof by setting the oxygen concentration to less than 1 x 1017 cm-3. By setting the oxygen concentration near the anode p layer to less than 1 x 1017 cm-3, characteristics of the withstand voltage and the like can be ensured. In the present production example, the oxygen concentration near the anode p layer 102 in the case of a 3.3-kV diode is described and the case of a diode of low withstand voltage will be described in another example described below. It is also evident that when the oxygen concentration is 1 x 1018 cm-3 or less, the n-type carrier concentration can be made 1 x 1015 cm-3 or less. In the present production example, the peak value of the n-type carrier concentration of the n-buffer layer is set to 1 x 1014 cm-3 by producing a diode by heat treatment for 2 h. Diode characteristics were compared with those of Comparative Example described below.

    <Comparative Example>



    [0066] Here, Comparative Example to compare with the present example will be described.

    [0067] Fig. 7A is a schematic sectional view of the active area of a diode 1G according to Comparative Example and Fig. 7B is an n-type carrier concentration and oxygen concentration distribution chart thereof.

    [0068] The diode 1G according to Comparative Example is formed by a production method similar to that of the first example using an FZ wafer whose oxygen concentration is 1 x 1016 cm-3. Thus, no oxygen thermal donor is generated. The loss of the diode 1 in the above production example and that of the diode 1G in Comparative Example are equivalent.

    <Effect of the first example>



    [0069] In Fig. 8, current waveforms and voltage waveforms of small current (1/10 x rated current) recovery characteristics at room temperature of diodes of the production example (solid line) and Comparative Example (broken line) are shown.

    [0070] It is evident from Fig. 8 that while oscillation is observed from waveforms of Comparative Example, oscillation is not observed from waveforms of the production example.

    [0071] From the above result, it has been confirmed that the configuration of a diode including an n-buffer layer containing oxygen according to the present example is extremely effective in reducing noise. By applying the diode to a power conversion system according to an embodiment described below or the like, reliability of the power conversion system or the like can be improved so that electromagnetic interference (EMI) can be reduced.

    [0072] According to the present example, as described above, the oxygen concentration in an area of the width of at least 30 µm from a surface on the side of the n-type layer (104) of the cathode electrode (107) toward the anode electrode (106) is 1 x 1017 cm-3 or more and the oxygen concentration of the n- layer (101) in a position adjacent to the p-type layers (102, 103) is set to less than 3 x 1017 cm-3 and therefore, the oscillation phenomenon, that is, ringing can be suppressed cost-effectively.

    [Second example]



    [0073] Next, the configuration of a diode according to the second example useful to understand the present invention will be described with reference to Fig. 9.

    [0074] Fig. 9 is a schematic sectional view of a diode 1A according to the second example in the active area. The illustration of a termination area is omitted, but like in the first example, a termination structure such as FLR in which a p-type well and an electrode are arranged in a ring shape is used.

    [0075] As shown in Fig. 9, instead of the anode p layer 102 and the anode p- layer 103 of the diode 1 (see Fig. 1) in the first example, an anode p layer 112 having no well structure is applied to the diode 1A according to the second example. That is, the anode p layer 112 is formed entirely in the active area on the anode side. Other configurations are similar to those in the first example.

    [0076] Because the anode p layer 112 is formed entirely in the active area on the side of the anode electrode 106, the photolithography process to locally form the anode p layer 102 (see Fig. 1) like in the first example is not needed for the diode 1A according to the present example and also the process of ion implantation to form the anode p- layer 103 can be omitted. Accordingly, manufacturing costs can be reduced in the present example when compared with those in the first example. Other processes are similar to those in the first example.

    [Third example]



    [0077] Next, the configuration of a diode according to the third example useful to understand the present invention will be described with reference to Figs. 10A and 10B.

    [0078] Fig. 10A is a schematic sectional view of a diode 1B according to the third example in the active area. The illustration of a termination area is omitted, but like in the first example, a termination structure such as FLR in which a p-type well and an electrode are arranged is used. Fig. 10B is an n-type carrier concentration and oxygen concentration distribution chart thereof.

    [0079] As shown in Fig. 10A, the diode 1B according to the third example has a second n-buffer layer 110 between the cathode n layer 104 and the n-buffer layer 105 of the diode 1 (see Fig. 1) according to the first example. In other words, the cathode n layer can be considered to be formed in two stages by the cathode n layer 104 and the second n-buffer layer 110.

    [0080] When the diode 1B according to the present example is manufactured, a V-group element is implanted and diffused to the cathode side before the anode p layer 102 being formed. The diffusion may be simultaneous with the diffusion for the anode p layer 102. The second n-buffer layer 110 of 3 µm or more is formed by the diffusion. Next, processes after the anode p layer formation are performed, but these processes are similar to those in the first example and so the description thereof is omitted.

    [0081] According to the present example, as described above, the cathode n layer can be considered to be formed in two stages and so degradation of the withstand voltage against scratches on the back side can be prevented. Thus, diodes can be produced by setting the thickness of the n layer (the n layer formed in the cathode n layer 104 and the second n-buffer layer 110 in Fig. 10A) formed initially to 3 µm or more to improve yields.

    [0082] In this configuration, as shown in Fig. 10B, the n-type carrier concentration of the cathode n layer 104 is preferably set higher than the oxygen concentration. Accordingly, contact performance of the cathode electrode 107 and the cathode n layer 104 can be maintained in good condition. The maximum value of the n-type carrier concentration of the second n-buffer layer 110 is set lower than the n-type carrier concentration of the cathode n layer 104 and higher than the n-type carrier concentration of the n-buffer layer 105 containing oxygen. Accordingly, a decreasing speed of injected carriers during recovery can be suppressed and so that ringing can effectively be suppressed.

    [0083] Further, as shown in Fig. 10B, the n-type carrier concentration may be set lower than the oxygen concentration in the second n-buffer layer 110. The oxygen thermal donor is about 1 x 10-4 times the oxygen concentration and thus, by limiting the concentration of the second n-buffer layer 110 to the oxygen concentration or less, the difference of n-type carrier concentrations of the n-buffer layer 105 containing oxygen and the second n-buffer layer 110 can be reduced and therefore, the decrease of injected carriers during recovery becomes smooth and further, ringing can effectively be suppressed.

    [0084] To summarize the above description, the order of concentrations in the present example is as shown below:
    n-type carrier concentration of the cathode n layer 104 > oxygen concentration of the cathode n layer 104 > maximum value of the n-type carrier concentration of the second n-buffer layer 110 > n-type carrier concentration of the n-buffer layer 105 containing oxygen > n-type carrier concentration of the n- drift layer 101

    [0085] According to the present example, as described above, the second n-buffer layer (110) into which a V-group element is diffused is provided between the n-type layer (104) and the n-buffer layer (105), the oxygen concentration of the second n-buffer layer (110) is made higher than the n-type carrier concentration of the second n-buffer layer (110), the thermal donor concentration of the second n-buffer layer (110) is made higher than that of the n- layer (101), and the thermal donor concentration of the second n-buffer layer (110) is made lower than the n-type carrier concentration of a V-group element of the second n-buffer layer (110). Accordingly, the oscillation phenomenon, that is, ringing can effectively be suppressed.

    [First embodiment]


    <Configuration of the embodiment>



    [0086] Next, the configuration of a diode (semiconductor device) manufactured by means of a method to the first embodiment of the present invention will be described with reference to Figs. 11A and 11B.

    [0087] Fig. 11A is a schematic sectional view of a diode 1C (semiconductor device) in the active area. The illustration of a termination area is omitted, but like in the first example, a termination structure such as FLR in which a p-type well and an electrode are arranged in a ring shape is used. Fig. 11B is an n-type carrier concentration and oxygen concentration distribution chart thereof.

    [0088] In the present embodiment, the resistivity of the n- drift layer 101 (n- layer) formed in the Si substrate 100 (silicon semiconductor substrate) is set to 120 Ωcm and P diffusion of the cathode n layer 104 (n-type layer) is performed simultaneously with the diffusion of oxygen. As shown in Figs. 11A and 11B, the diode 1C has the cathode n layer 104 of high concentration formed 50 µm or more. Inside the n-buffer layer 105, the oxygen is 5 x 1017 cm-3 or more and 1 x 1018 cm-3 or less. The thickness of the n-buffer layer 105 containing oxygen is 30 µm or more.

    [0089]  The oxygen concentration on the anode side of the n- drift layer 101 is less than 3 x 1017 cm-3. The n-type carrier concentration of the n- drift layer 101 is 3.75 x 1013 cm-3. The amount of oxygen thermal donor near the anode p layer 102 (p-type layer) can be made 1/10 or less that of the n- drift layer 101 by setting, as described above, heat treatment conditions appropriately (see Fig. 6). Therefore, for a diode of low withstand voltage of 1.7 kV or less, the oxygen concentration near the anode p layer is suitably set to less than 3 x 1017 cm-3.

    [0090] When the diode 1C is formed, phosphorus glass is formed on a silicon (Si) wafer by the CVD method or the like prior to the diffusion of oxygen. Then, the wafer is thermally treated at 1300°C for 20 h in an oxygen atmosphere. An anode surface is formed by cutting and polishing one side of the wafer. Alternatively, phosphorus glass may be formed on both sides of the Si wafer before the wafer is thermally treated in an oxygen atmosphere and cut in the center, and the cut surface is polished. Next, like in the first example, the anode p- layer 103 (p-type layer) and the anode p layer 102 are formed. In this configuration, the cathode n layer 104 is already formed and thus, the next cathode n layer forming process is omitted and the forming process of the anode electrode 106 and the n-buffer layer 105 is performed. At this point, densify annealing of an interlayer film such as boron phosphorus silicon glass (BPSG) may well be applied to form the n-buffer layer 105. Processes after the cathode electrode formation are similar to those in the first example.

    [0091] According to the present embodiment, the cathode n layer 104 is implemented in the same process as that of the oxygen diffusion and thus, the process can be shortened.

    [0092] In a diode of the withstand voltage class of 1.7 kV or less like in the present embodiment, the sum of the thickness of the n- drift layer 101 and that of the n-buffer layer 105 is thin and so the configuration in which the cathode n layer is made thicker to ensure mechanical strength like in the present embodiment is effective. In a diode of the withstand voltage of 1.7 kV, the sum of the thickness of the n- drift layer 101 and that of the n-buffer layer 105 is appropriately set to about 180 µm from the viewpoint of ensuring the withstand voltage and reducing the switching loss.

    [0093] In Fig. 12, the relationship between the thickness of the cathode n layer 104 and upstream process yields when the cathode n layer 104 is formed in accordance with the thickness in the present embodiment is shown. It is evident from Fig. 12 that degradation of yields occurs when the thickness of the cathode n layer is less than 50 µm. Thus, it is effective to set the thickness of the cathode n layer 104 to 50 µm or more.

    <Effect of the embodiment>



    [0094] As described above, the semiconductor device (1C) of fig. 11A is characterized in that the n-type carrier concentration of the n-buffer layer (105) is higher than that of the n- layer (101) and is 1 x 1015 cm-3 or less, the oxygen concentration in the n-buffer layer (105) is 5 x 1017 cm-3 or more and 1 x 1018 cm-3 or less, and the oxygen concentration of the n- layer (101) in a position in contact with the p-type layers (102, 103) is less than 3 x 1017 cm-3.

    [0095] Accordingly, recovery characteristics (see Fig. 8) like in the first example can be implemented and the oscillation phenomenon can be suppressed cost-effectively.

    [0096] Throughout the whole n-buffer layer (105) the oxygen concentration decreases toward the anode side and the oxygen concentration in the n-buffer layer (105) is 5 x 1017 cm-3 or more and 1 x 1018 cm-3 or less.

    [0097] Accordingly, the oscillation phenomenon can further be suppressed.

    [0098] The method for manufacturing the diode 1C according to the present embodiment is characterized in that a step of removing an oxygen thermal donor by heat treatment at 800°C or higher, a step of forming the anode electrode (106), and a step of generating an oxygen thermal donor by heat treatment at 400°C or higher are sequentially performed.

    [0099] Accordingly, the n-type carrier concentration of the n-buffer can be adjusted with precision.

    [0100] The method for manufacturing the diode 1C according to the present embodiment is also characterized in that a step of forming a layer containing a V-group element on the silicon semiconductor substrate (100), a step of thermally treating the silicon semiconductor substrate (100) in an atmosphere containing oxygen, a step of diffusing the V-group element and oxygen into the silicon semiconductor substrate (100) simultaneously, and a step of cutting the other surface of the silicon semiconductor substrate (100) are sequentially performed.

    [0101] Accordingly, the diffusion of the V-group element and the diffusion of oxygen are carried out in the same process so that the process can be shortened.

    [0102] Next, a power conversion system will be described with reference to Fig. 13.

    [0103] Fig. 13 is a block diagram of a power conversion system 10.

    [0104] As shown in Fig. 13, the power conversion system 10 includes a rectifier circuit 12, an upper arm driving circuit 14U, a lower arm driving circuit 14D, and an inverter 16.

    [0105] The rectifier circuit 12 converts an AC voltage supplied from an AC power supply 202 into a DC voltage. The inverter 16 performs the pulse width modulation (PWM) of the DC voltage before applying the modulated voltage to a motor 206 of an induction machine or synchronous machine. The upper/lower arm driving circuits 14U, 14D drive an insulated gate bipolar transistor (IGBT) included in the inverter 16. The inverter 16 includes IGBT 200a to 200f as semiconductor switching elements and these IGBT 200a to 200f have diodes 201a to 201f connected in anti-parallel therewith. These diodes 201a to 201f operate as freewheel diodes.

    [0106] Diodes manufactured by means of the method of the present invention are applied as the diodes 201a to 201f. In the inverter 16, one of the IGBT 200a to 200c (first semiconductor switching elements) and one of the diodes 201d to 201f (second semiconductor switching elements) are combined and two such pairs are connected in series. Therefore, two anti-parallel circuits of IGBT and diodes are connected in series to constitute a half bridge circuit for one phase.

    [0107] As many half bridge circuits as the number of phases of AC, three phases in the present embodiment, are included. An AC voltage of a U phase is output from a series connection point of the two IGBT 200a, 200d, that is, a series connection point of the two anti-parallel circuits. Similarly, AC voltages of a V phase and a W phase are output from series connection points of other half bridge circuits and these AC voltages are applied to the motor 206 as a 3-phase AC voltage and the motor 206 is thereby driven.

    [0108] Collectors of the IGBT 200a to 200c on the upper arm side are connected in common and connected to a DC high potential side of the rectifier circuit 12. Also, emitters of the IGBT 200d to 200f on the lower arm side are connected in common and connected to a ground side of the rectifier circuit 12. The upper/lower arm driving circuits 14U, 14D control the On/Off state of the IGBT 200a to 200f by providing driving signals to gates of the IGBT 200a to 200f to cause the inverter 16 to output an AC voltage.

    [0109] Diodes manufactured by means of the method of the invention are connected in anti-parallel with the IGBT 200a to 200f as freewheel diodes and therefore, recovery losses during switching can be reduced. Accordingly, energy efficiency of the power conversion system 10 as a whole can be improved. In addition, diodes manufactured by means of the method of the present invention suppress noise and therefore, the switching operation is stable and also EMI can be reduced.

    [Modifications]



    [0110] The present invention is not limited to the above embodiments and various modifications thereof can be made, within the scope of the appended claims. Possible modifications to the above embodiments are, for example, the following:
    1. (1) The present invention is not limited to separate diodes and the present invention may be applied to, for example, a diode contained in a semiconductor switching element of reverse conducting type. Also, in place of the IGBT 200a to 200f in the power conversion system 10 shown in Fig. 13, a semiconductor switching element such as a metal oxide semiconductor field effect transistor (MOSFET), junction type bipolar transistor, junction type FET, static induction transistor, and gate turn off thyristor (GTO thyristor) may be used.



    Claims

    1. A method for manufacturing a semiconductor device comprising:

    an anode electrode (106) formed on one side of a silicon semiconductor substrate (100);

    a cathode electrode (107) formed on the opposite side of the silicon semiconductor substrate (100);

    a p-type layer (102, 103) formed in the substrate (100) next to the anode electrode (106);

    an n-type layer (104) formed in the substrate (100) next to the cathode electrode (107) by diffusing a group V element, wherein a thickness of the n-type layer (104) is 50 µm or more;

    an n- layer (101) formed in the substrate (100) between the p-type layer (102, 103) and the n-type layer (104); and

    an n-buffer layer (105) formed in the substrate (100) between the n- layer (101) and the n-type layer (104) and having a thickness of 30 µm or more,

    wherein the substrate (100) has the following oxygen concentration profile:

    the oxygen concentration of the n- layer (101) in a position in contact with the p-type layer (102, 103) is less than 3 x 1017 cm-3,

    the oxygen concentration in the n-buffer layer (105) decreases from a cathode side toward an anode side throughout the whole n-buffer layer (105), and

    the oxygen concentration in the n-buffer layer (105) is 5 x 1017 cm-3 or more and 1 x 1018 cm-3 or less,

    wherein the method comprises the steps of:

    a) providing the substrate (100) having the two opposite sides;

    b) diffusing the group V element into the substrate (100) to form the n-type layer (104) and, simultaneously, diffusing oxygen into the substrate (100);

    c) cutting the substrate (100) along a direction parallel to said sides;

    d) polishing the cut surface; and

    e) forming the p-type layer (102, 103) at the polished surface,

    wherein said steps a) to e) lead to the substrate (100) having said oxygen concentration profile,

    the method further comprising, after said steps a) to e), the steps of removing oxygen thermal donors by heat treatment at 800°C or higher, then forming the anode electrode (106), and then generating by heat treatment at 400°C or more oxygen thermal donors from the oxygen present in the substrate (100) so as to set the n-type carrier concentration of the n-buffer layer (105) to a value of 1 x 1015 cm-3 or less which is higher than that of the n- layer (101) but smaller than that of the n-type layer (104).


     


    Ansprüche

    1. Verfahren zum Herstellen eines Halbleiterbauelements mit
    einer Anodenelektrode (106), die auf einer Seite eines Silizium-Halbleitersubstrats (100) gebildet ist,
    einer Kathodenelektrode (107), die auf der entgegengesetzten Seite des Silizium-Halbleitersubstrats (100) gebildet ist,
    einer p-Schicht (102, 103), die in dem Substrat (100) neben der Anodenelektrode (106) gebildet ist,
    einer n-Schicht (104), die in dem Substrat (100) neben der Kathodenelektrode (107) gebildet ist, indem ein Gruppe-V-Element diffundiert wird, wobei eine Dicke der n-Schicht (104) mindestens 50 µm beträgt,
    einer n--Schicht (101), die in dem Substrat (100) zwischen der p-Schicht (102, 103) und der n-Schicht (104) gebildet ist, und
    einer n-Puffer-Schicht (105), die in dem Substrat (100) zwischen der n--Schicht (101) und der n-Schicht (104) gebildet ist und eine Dicke von mindestens 30 µm aufweist,
    wobei das Substrat (100) das folgende Sauerstoffkonzentrationsprofil aufweist:

    die Sauerstoffkonzentration der n--Schicht (101) in einer Position in Kontakt mit der p-Schicht (102, 103) beträgt weniger als 3 x 1017 cm-3,

    die Sauerstoffkonzentration in der n-Puffer-Schicht (105) verringert sich von einer Kathodenseite zu einer Anodenseite über die gesamte n-Puffer-Schicht (105), und

    die Sauerstoffkonzentration in der n-Puffer-Schicht (105) beträgt mindestens 5 x 1017 cm-3 und höchstens 1 x 1018 cm-3,

    wobei in den Schritten des Verfahrens:

    a) das Substrat (100) mit den zwei entgegengesetzten Seiten bereitgestellt wird,

    b) das Gruppe-V-Element in das Substrat (100) diffundiert wird, um die n-Schicht (104) zu bilden, und gleichzeitig Sauerstoff in das Substrat (100) diffundiert wird,

    c) das Substrat (100) längs einer Richtung parallel zu den Seiten geschnitten wird,

    d) die Schnittfläche poliert wird, und

    e) die p-Schicht (102, 103) an der polierten Fläche gebildet wird,

    wobei die Schritte a) bis e) zu dem Substrat (100) mit dem Sauerstoffkonzentrationsprofil führen,

    wobei in dem Verfahren ferner nach den Schritten a) bis e) Schritte durchgeführt werden, in denen thermische Sauerstoffdonatoren durch eine Wärmebehandlung bei mindestens 800°C entfernt werden, dann die Anodenelektrode (106) gebildet wird, und dann durch Wärmebehandlung bei mindestens 400°C thermische Sauerstoffdonatoren aus dem in dem Substrat (100) vorhandenen Sauerstoff erzeugt werden, um die n-Typ-Ladungsträgerkonzentration der n-Puffer-Schicht (105) auf einen Wert von höchstens 1 x 1015 cm-3 einzustellen, der größer ist als der der n--Schicht (101) aber kleiner als der der n-Schicht (104).


     


    Revendications

    1. Procédé de fabrication d'un dispositif à semi-conducteur comprenant :

    une électrode d'anode (106) formée sur un côté d'un substrat (100) semi-conducteur de silicium ;

    une électrode de cathode (107) formée sur le côté opposé du substrat (100) semi-conducteur de silicium ;

    une couche de type p (102, 103) formée dans le substrat (100) à côté de l'électrode d'anode (106) ;

    une couche de type n (104) formée dans le substrat (100) à côté de l'électrode de cathode (107) par diffusion d'un élément du groupe V, dans lequel une épaisseur de la couche de type n (104) est 50 µm ou plus ;

    une couche n- (101) formée dans le substrat (100) entre la couche de type p (102, 103) et la couche de type n (104) ; et

    une couche tampon n (105) formée dans le substrat (100) entre la couche n- (101) et la couche de type n (104) et ayant une épaisseur de 30 µm ou plus,

    dans lequel le substrat (100) a le profil de concentration en oxygène suivant :

    la concentration en oxygène de la couche n- (101) dans une position en contact avec la couche de type p (102, 103) est inférieure à 3 x 1017 cm-3,

    la concentration en oxygène dans la couche tampon n (105) diminue d'un côté de cathode vers un côté d'anode sur la totalité de la couche tampon n (105), et

    la concentration en oxygène dans la couche tampon n (105) est 5 x 1017 cm-3 ou plus et 1 x 1018 cm-3 ou moins,

    dans lequel le procédé comprend les étapes de :

    a) prévision du substrat (100) ayant les deux côtés opposés ;

    b) diffusion de l'élément du groupe V dans le substrat (100) pour former la couche de type n (104) et, simultanément, diffusion d'oxygène dans le substrat (100) ;

    c) découpe du substrat (100) le long d'un sens parallèle auxdits côtés ;

    d) polissage de la surface de découpe ; et

    e) formation de la couche de type p (102, 103) au niveau de la surface polie,

    dans lequel lesdites étapes a) à e) conduisent au substrat (100) ayant ledit profil de concentration en oxygène,

    le procédé comprenant en outre, après lesdites étapes a) à e), les étapes d'élimination de donneurs thermiques d'oxygène par traitement thermique à 800°C ou plus, ensuite de formation de l'électrode d'anode (106), et ensuite de génération par traitement thermique à 400°C ou plus de donneurs thermiques d'oxygène à partir de l'oxygène présent dans le substrat (100) de façon à fixer la concentration de support de type n de la couche tampon n (105) à une valeur de 1 x 1015 cm-3 ou moins qui est supérieure à celle de la couche n- (101) mais inférieure à celle de la couche de type n (104).


     




    Drawing












































    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description