(19)
(11)EP 3 316 289 A3

(12)EUROPEAN PATENT APPLICATION

(88)Date of publication A3:
18.07.2018 Bulletin 2018/29

(43)Date of publication A2:
02.05.2018 Bulletin 2018/18

(21)Application number: 17199137.5

(22)Date of filing:  30.10.2017
(51)Int. Cl.: 
H01L 21/8238  (2006.01)
H01L 21/28  (2006.01)
H01L 27/092  (2006.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
MA MD

(30)Priority: 31.10.2016 CN 201610927451

(71)Applicants:
  • Semiconductor Manufacturing International Corporation (Shanghai)
    Shanghai 201203 (CN)
  • Semiconductor Manufacturing International Corporation (Beijing)
    Beijing 100176 (CN)

(72)Inventor:
  • LI, Yong
    Shanghai, 201203 (CN)

(74)Representative: Klunker IP Patentanwälte PartG mbB 
Destouchesstraße 68
80796 München
80796 München (DE)

  


(54)METHOD TO IMPROVE THE HIGH K QUALITY


(57) A method of manufacturing a semiconductor device includes providing a substrate structure including PMOS and NMOS regions having respective first and second trenches, a high-k dielectric layer (203) in the first and second trenches, and a first P-type work function adjustment layer (204) on the high-k dielectric layer, sequentially forming first (301) and second (302) protective layers and a mask layer (401) on the substrate structure; removing a portion of the mask layer exposing a portion of the second protective layer (302) on the NMOS region; removing the exposed portion of the second protective layer (302) on the NMOS region exposing a portion of the first protective layer (301) on the NMOS region; removing the mask layer exposing the second protective layer on the PMOS region; removing portions of the first protective layer and first P-type work function adjustment layer on the NMOS region; and removing the second and first protective layers on the PMOS region.