(19)
(11)EP 3 320 561 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
26.08.2020 Bulletin 2020/35

(21)Application number: 16741416.8

(22)Date of filing:  17.06.2016
(51)Int. Cl.: 
H01L 29/423  (2006.01)
H01L 29/788  (2006.01)
H01L 29/66  (2006.01)
H01L 27/115  (2017.01)
(86)International application number:
PCT/US2016/038241
(87)International publication number:
WO 2017/011139 (19.01.2017 Gazette  2017/03)

(54)

SPLIT GATE NON-VOLATILE MEMORY CELL HAVING A FLOATING GATE, WORD LINE AND ERASE GATE

NICHTFLÜCHTIGE SPLIT-GATE-SPEICHERZELLE MIT FLOATING-GATE, WORTZEILE UND ERASE-GATE

CELLULE DE MÉMOIRE NON VOLATILE À GRILLE FRACTIONNÉE AYANT UNE GRILLE FLOTTANTE, UNE LIGNE DE MOTS ET UNE GRILLE D'EFFACEMENT


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 10.07.2015 US 201562191047 P
14.06.2016 US 201615182527

(43)Date of publication of application:
16.05.2018 Bulletin 2018/20

(73)Proprietor: Silicon Storage Technology, Inc.
San Jose, CA 95134 (US)

(72)Inventors:
  • YANG, Jeng-Wei
    Hsinchu County, Zhubei City (TW)
  • WU, Man-Tang
    Hsinchu 305 (TW)
  • CHEN, Chun-Ming
    New Taipei City 220 (TW)
  • TADAYONI, Mandana
    Cupertino, CA 95014 (US)
  • SU, Chien-Sheng
    Saratoga, CA 95070 (US)
  • DO, Nhan
    Saratoga, CA 95070 (US)

(74)Representative: Betten & Resch 
Patent- und Rechtsanwälte PartGmbB Maximiliansplatz 14
80333 München
80333 München (DE)


(56)References cited: : 
JP-A- 2000 286 348
US-A1- 2014 126 299
US-A1- 2009 207 662
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    RELATED APPLICATIONS



    [0001] This application claims the benefit of U.S. Provisional Application No. 62/191,047, filed July 10, 2015, and which is incorporated herein by reference.

    FIELD OF THE INVENTION



    [0002] The present invention relates to split gate flash memory cell design and operation.

    BACKGROUND OF THE INVENTION



    [0003] Split gate non-volatile flash memory devices are known. Figure 1 illustrates a 2-Gate Cell that includes two gates (word line gate WL and floating gate FG), and thus includes three terminals (word line WL, source S, and drain D). Drain D can alternately be referred to as bit line BL, and word line WL can alternately be referred to as the control gate. The floating gate FG is partially over and insulated from the source S and a portion of the channel region CR (which extends between the source S and drain D), and the word line WL is over and insulated from the other portion of the channel region CR. The floating gate FG has an upper surface terminating in a sharp edge that faces the word line WL (to facilitate erase operation). U.S. Patent 5,029,130 discloses such a memory cell, which is incorporated herein by reference for all purposes.

    [0004] Figure 2 illustrates an extended source 2-Gate Cell, which is similar to the memory device of Fig. 1, except that it further includes an extended source line ESL formed over and in contact with source S. The extended source line ESL provides enhanced voltage coupling from the source S to the floating gate FG via the extended source line ESL.

    [0005] Figure 3 illustrates a 4-Gate, 5-terminal Cell, which is similar to the memory device of Fig. 1, except that it further includes an erase gate EG over and insulated from source region S, and a coupling gate CG over and insulated from the floating gate FG. The erase operation uses the upper surface edge of the floating gate FG that faces the erase gate EG. Thus, this memory cell has four gates (WL, CG, FG, EG) and 5 terminals (S, D, WL, CG, EG). U.S. Patents 6,747,310 and 7,868,375 disclose such a memory cell.

    [0006] JP 2000 286348 A discloses how to provide a nonvolatile semiconductor memory device which is superior in device characteristics and advantageous micronized in size. SOLUTION: This device is equipped with a first and a second gate oxide film formed on a P-type silicon substrate 51, provided with a source and a drain region, 61 and 74,floating gates 67 formed on the first oxide film so as to be each adjacent to the edges of the source region 61, control gates 70 formed on the second gate oxide film so as to be each adjacent to the floating gates 67 and the drain regions 74, and an erasing gate 64 formed on the source region 61 to be adjacent to the floating gates 67 through the intermediary of a tunnel oxide film 62B and brought into contact with the source region 61 which is distant from it by a certain space. US 2014/126299 A1 discloses a semiconductor device having a semiconductor layer, a floating gate electrode provided over the semiconductor layer via a first insulation film, and an erase gate electrode to which an erase voltage is applied. The floating gate electrode has an opposing region that opposes via a second insulation film to the erase gate electrode. The opposing region has such a shape that multiple electric field concentrating portions are formed when the erase voltage is applied to the erase gate electrode. US 2009/207662 A1 discloses The present disclosure provides a multi-transistorelement including a substrate, a first floating gate disposed on the substrate, a second floating gate disposed on the substrate and coupled to the first floating gate, and a first active region disposed in the substrate and coupled to the first and second floating gates.

    [0007] It is desirable to achieve the functionality and performance advantages of the 4-gate device, but with smaller device geometries and fewer masking steps during manufacturing.

    BRIEF SUMMARY OF THE INVENTION



    [0008] The present invention is defined in independent claims. The dependent claims define embodiments of the invention.

    [0009] The aforementioned needs are addressed by a memory device that includes a silicon semiconductor substrate, spaced apart source and drain regions formed in the silicon semiconductor substrate with a channel region there between, a conductive floating gate disposed over and insulated from a first portion of the channel region and a first portion of the source region, and a conductive erase gate. The erase gate includes a first portion that is laterally adjacent to and insulated from the floating gate, and is over and insulated from the source region, and a second portion that extends up and over, and is insulated from, the floating gate. A conductive word line gate is disposed over and insulated from a second portion of the channel region. The word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate. A thickness of insulation separating the word line gate from the second portion of the channel region is less than a thickness of insulation separating the floating gate from the erase gate.

    [0010] A method of reading a memory cell that includes spaced apart source and drain regions formed in a silicon semiconductor substrate with a channel region there between, a floating gate disposed over and insulated from a first portion of the channel region and partially over the source region, an erase gate disposed over and insulated from the source region, and a word line gate disposed over and insulated from a second portion of the channel region, wherein the erase gate includes a first portion laterally adjacent to the floating gate and a second portion that extends up and over the floating gate, and wherein the word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate. The method includes applying a positive voltage to the word line gate, applying a positive voltage to the drain region, applying a zero voltage to the erase gate, and applying a zero voltage to the source region.

    [0011] Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0012] 

    Fig. 1 is a side cross sectional view of a conventional two gate, three terminal non-volatile memory device.

    Fig. 2 is a side cross sectional view of a conventional two gate, three terminal non-volatile memory device with an extended source line.

    Fig. 3 is a side cross sectional view of a conventional four gate, five terminal non-volatile memory device.

    Fig. 4 is a side cross sectional view of a three gate, four terminal non-volatile memory device.

    Fig. 5 is a side cross sectional view of a three gate, four terminal non-volatile memory device with metal word line gates and high K dielectric.

    Fig. 6 is a table showing the operational voltages of the memory cell in a first example.

    Fig. 7 is a table showing the operational voltages of the memory cell in a second example.

    Fig. 8 is a table showing the operational voltages of the memory cell in a third example.

    Figs. 9A-9F are side cross sectional views illustrating the steps in forming the non-volatile memory cell.

    Fig. 10 is a side cross sectional view illustrating an alternate embodiment of the non-volatile memory cell.


    DETAILED DESCRIPTION OF THE INVENTION



    [0013] As shown in Figure 4, source region 12 and drain region 14 are formed in a silicon substrate 10, with a channel region 16 of the substrate therebetween. A floating gate 18 is preferably polysilicon and is formed over and insulated from the source region 12 and a first portion of the channel region 16. A word line gate 20 can be polysilicon and is formed over and insulated from a second portion of the channel region 16. An erase gate 22 is preferably polysilicon and is formed over and insulated from the source region 12. The erase gate 22 has a first portion laterally adjacent the floating gate 18, and a second portion that extends up and over the floating gate 18. Unlike the four gate device described above, the memory cell in Figure 4 does not have a coupling gate. The memory cell device of Figure 5 is the same as that of Figure 4, except the polysilicon word line gates 20 are replaced with metal gates 21, and are surrounded by a high K dielectric 24 (i.e. having a dielectric constant K greater than that of oxide, such as HfO2, ZrO2, TiO2, Ta2O5, or other adequate materials, etc.).

    [0014] The three-gate memory cell configurations of Figures 4 and 5 have many advantages. Specifically, they utilize capacitive coupling between the erase gate 22 and floating gate 18 during programming, so that a separate coupling gate is not needed. The length of the word line gate 20, and the thickness of the oxide layer 26 between the word line gate 20 and the substrate 10, can be shrunk while maintaining high cell current and speed. The tunneling oxide layer 28 between the floating gate 18 and erase gate 22 is protected by the erase gate 22 (which wraps around the tunnel oxide), to prevent degradation during subsequent chip processing to ensure good erase capability and endurance. The total cell height, as well as erase gate and word line gate height, can be adjusted to meet the height of logic gates formed on the same chip. The width and length of the floating gate 18, and the source line 12, can be formed by a self-aligned process. Process, strap layout and layout of metal connections will be simpler since the coupling gate is eliminated. Metal connections will be easier to fill in small Y-pitch in advance technology such as 40nm, 28 and 20 nm technology nodes.

    [0015] Figure 6 illustrates cell operation voltages for selected and unselected lines of an array of the 3-gate memory cell, according to a first example. Selected lines (Sel.) include the memory cell(s) being operated on, and unselected lines (Uns.) are those that do not include the memory cell(s) being operated on.

    [0016] Figure 7 illustrates cell operation voltages for selected and unselected lines of an array of the 3-gate memory cell, according to a second example. In this example, a positive voltage on the erase gate is used for the erase operation.

    [0017] Figure 8 illustrates cell operation voltages for selected and unselected lines of an array of the 3-gate memory cell, according to a third example. In this example, a negative voltage on the source line is used for the erase operation.

    [0018] Figures 9A-9F illustrate the steps in forming the 3-gate memory device. After forming STI isolation regions between the active regions, the following layers are formed: silicon dioxide (oxide) 40 on the substrate 10, polysilicon (poly) 42 on oxide 40, oxide 44 on poly 42, and silicon nitride (nitride) 46 on oxide 44. The nitride 46 is patterned (e.g. photolithography masking process) with a trench 48. Oxide spacers 50 are formed inside the trench 48 and over the poly layer 42. The exposed portion of poly layer 42 between the spacers 50 is removed by poly etch, exposing oxide layer 40. The exposed portion of oxide layer 40 is removed by oxide etch. The resulting structure is shown in Fig. 9A. The etched sidewalls of poly layer 42 are inwardly slanted (see slanted portion 42a), to create sharper upper edges to the poly layer 42.

    [0019] An implantation is performed to form source region 12 in the substrate underneath trench 48. Oxide etch and formation are performed to form a tunnel oxide 28 that extends along and over the top of slanted portions 42a (i.e. on the exposed end portions of poly 42). A poly deposition and etch are used to form polysilicon in the bottom of trench 48, which constitutes erase gate 22. An oxide and etch back are used to fill the trench 48 with oxide (over erase gate 22). The resulting structure is shown in Fig. 9B.

    [0020] Nitride 46 is removed, and an oxide etch is used to expose outer portions of poly layer 42, which are removed by poly etch to define the outer edges of floating gates 18. The outer edges of floating gates 18 are covered with oxide, as shown in Fig. 9C. An oxide etch removes the oxide layer on the substrate, and a thin layer of oxide 52 is formed on the removes the oxide layer on the substrate, and a thin layer of oxide 52 is formed on the substrate adjacent the outer edges of the floating gates 18. Oxide layer 52 can be much thinner than the tunnel oxide layer 28. A layer of nitride oxide (SiON) can be formed instead of oxide layer 52 or additionally on oxide layer 52. The memory cell portion is covered with a poly layer 54, and an oxide layer 56 on the poly layer 54, while the logic portion of the device includes SiN (silicon nitride) 58 embedded in the poly layer 54, with that portion of the poly layer 54 under the SiN 58 serving as a logic gate poly and that portion above serving as a dummy poly, as shown in Fig. 9D. Poly etching is then used leaving word line WL poly gates 20 and logic device poly gate 60, as shown in Fig. 9E. Processing continues, including an implantation which forms drain regions 14, and protective oxide 62, as shown in Fig. 9F.

    [0021] In an alternate embodiment, a poly etch can be used to remove the poly word line gates 20, and replace them with metal word line gates 21 surrounded by a high K dielectric 24 on at least two sides, as shown in Fig. 10.

    [0022] With either embodiment, the total cell height, i.e. erase gate 22 and WL gate 20 height, can be adjusted to meet the logic gate height requirement. The floating gate width, floating gate length and source line are defined by self-aligned process. Process, strap layout and layout of metal connection will be simpler compared to 4-gate devices because the control gate is eliminated. Metal connection will be easier to fill in small Y-pitch advanced device technologies. Fewer photolithography masking steps are needed compared to the conventional 2 and 4 gate devices discussed above. The cell height can be significantly reduced, given the thin oxide layer 52 relative to the tunnel oxide 28 (because the erase gate 22 is being used to high voltage erasing, and the word line gate is only being used as a select gate), the planar upper surfaces of the word line gates 20 and erase gates 22, and that the word line gate 20 need not be formed with any vertical overlap with the floating gate 18.

    [0023] It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of the appended claims. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps need be performed in the exact order illustrated or claimed, but rather in any order that allows the proper formation of the memory cell of the present invention. Lastly, single layers of material could be formed as multiple layers of such or similar materials, and vice versa.

    [0024] It should be noted that, as used herein, the terms "over" and "on" both inclusively include "directly on" (no intermediate materials, elements or space disposed therebetween) and "indirectly on" (intermediate materials, elements or space disposed therebetween). Likewise, the term "adjacent" includes "directly adjacent" (no intermediate materials, elements or space disposed therebetween) and "indirectly adjacent" (intermediate materials, elements or space disposed there between), "mounted to" includes "directly mounted to" (no intermediate materials, elements or space disposed there between) and "indirectly mounted to" (intermediate materials, elements or spaced disposed there between), and "electrically coupled" includes "directly electrically coupled to" (no intermediate materials or elements there between that electrically connect the elements together) and "indirectly electrically coupled to" (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements therebetween.


    Claims

    1. A memory device, comprising:

    a silicon semiconductor substrate (10);

    spaced apart source and drain regions (12, 14) formed in the silicon semiconductor substrate with a channel region (16) there between;

    a conductive floating gate (18) disposed over and insulated from a first portion of the channel region (16) and a first portion of the source region, wherein the floating gate (18) includes lower and upper surface and an inwardly slanted sidewall (42a) terminating at the upper surface in a sharp edge such that a width of the floating gate (18) at the lower surface is less than a width of the floating gate (18) at the upper surface;

    a conductive erase gate (22) that includes:

    a first portion that is laterally adjacent to and insulated from the floating gate (18), and is over and insulated from the source region, and

    a second portion that extends up and over, and is insulated from, the floating gate (18),

    wherein the second portion of the erase gate (22) wraps around the sharp edge, and wherein a tunneling oxide layer (28) is positioned between the floating gate (18) and the second portion of the erase gate (22) so that the tunneling oxide (28) is protected;

    a conductive word line gate (20) disposed over and insulated from a second portion of the channel region (16), wherein the word line gate (20) is disposed laterally adjacent to the floating gate (18) and includes no portion disposed over the floating gate;

    wherein a thickness of insulation (52) separating the word line gate (20) from the second portion of the channel region (16) is less than a thickness of insulation (40) separating the floating gate (18) from the erase gate (22);

    wherein the erase gate (22) is the only conductive gate disposed over the floating gate (18) and the erase gate (22) second portion among the first portion of the erase gate (22) and the second portion of the erase gate (22) is the only gate portion disposed over the floating gate (18);

    wherein the word line gate (20) comprises:

    a bottom surface facing the second portion of the channel region (16), wherein the bottom surface is planar, and

    a top surface opposite the bottom surface, wherein the top surface is planar;

    wherein the erase gate (22) comprises:

    a second bottom surface facing the source region; and

    a second top surface opposite the second bottom surface that is planar.


     
    2. The memory device of claim 1, wherein the word line gate (20) comprises:

    metal material; and

    a layer of high K dielectric material disposed between the metal material and the second portion of the channel region (16).


     
    3. The memory device of claim 1, wherein the word line gate (20) comprises:

    polysilicon; and

    a layer of nitride oxide, SiON, disposed between the polysilicon and the second portion of the channel region (16).


     


    Ansprüche

    1. Speichervorrichtung, umfassend:

    ein Siliziumhalbleitersubstrat (10);

    voneinander beabstandete Source- und Drain-Regionen (12, 14), die in dem Siliziumhalbleitersubstrat mit einer dazwischenliegenden Kanal-Region (16) gebildet sind;

    ein leitfähiges Floating-Gate (18), das über einem ersten Bereich der Kanal-Region (16) und einem ersten Bereich der Source-Region angeordnet und davon isoliert ist, wobei das Floating-Gate (18) eine untere und eine obere Oberfläche und eine nach innen geneigte Seitenwand (42a) beinhaltet, die an der oberen Oberfläche in einer scharfen Kante endet, so dass eine Breite des Floating-Gates (18) an der unteren Oberfläche geringer ist als eine Breite des Floating-Gates (18) an der oberen Oberfläche;

    ein leitfähiges Lösch-Gate (22), beinhaltend:

    einen ersten Bereich, der lateral benachbart zu dem Floating-Gate (18) und davon isoliert ist, und der über der Source-Region angeordnet und davon isoliert ist, und

    einen zweiten Bereich, der sich nach oben und über das Floating-Gate (18) erstreckt und davon isoliert ist,

    wobei der zweite Bereich des Lösch-Gates (22) sich um die scharfe Kante wickelt, und wobei eine tunnelnde Oxidschicht (28) zwischen dem Floating-Gate (18) und dem zweiten Bereich des Lösch-Gates (22) positioniert ist, so dass das tunnelnde Oxid (28) geschützt ist;

    ein leitfähiges Wortleitungs-Gate (20), das über einem zweiten Bereich der Kanal-Region (16) angeordnet ist und davon isoliert ist, wobei das Wortleitungs-Gate (20) lateral benachbart zu dem Floating-Gate (18) angeordnet ist und keinen Bereich beinhaltet, der über dem Floating-Gate angeordnet ist;

    wobei eine Isolationsdicke (52), die das Wortleitungs-Gate (20) von dem zweiten Bereich der Kanal-Region (16) separiert, geringer ist als eine Isolationsdicke (40), die das Floating-Gate (18) von dem Lösch-Gate (22) separiert;

    wobei das Lösch-Gate (22) das einzige leitfähige Gate ist, das über dem Floating-Gate (18) angeordnet ist und der zweite Bereich des Lösch-Gates (22) unter dem ersten Bereich des Lösch-Gates (22) und dem zweiten Bereich des Lösch-Gates (22) der einzige Gate-Bereich ist, der über dem Floating-Gate (18) angeordnet ist;

    wobei das Wortleitungs-Gate (20) umfasst:

    eine untere Oberfläche, die dem zweiten Bereich der Kanal-Region (16) zugewandt ist, wobei die untere Oberfläche planar ist, und

    eine obere Oberfläche, die der unteren Oberfläche gegenüberliegt, wobei die obere Oberfläche planar ist;

    wobei das Lösch-Gate (22) umfasst:

    eine zweite untere Oberfläche, die der Source-Region zugewandt ist; und

    eine zweite obere Oberfläche, die der zweiten unteren Oberfläche gegenüberliegt, die planar ist.


     
    2. Speichervorrichtung nach Anspruch 1, wobei das Wortleitungs-Gate (20) umfasst:

    einen metallischen Werkstoff; und

    eine Schicht eines Werkstoffes mit hoher Dielektrizitätskonstante, die zwischen dem metallischen Werkstoff und dem zweiten Bereich der Kanal-Region (16) angeordnet ist.


     
    3. Speichervorrichtung nach Anspruch 1, wobei das Wortleitungs-Gate (20) umfasst:

    Polysilizium; und

    eine Schicht von Nitritoxid, SiON, die zwischen dem Polysilizium und dem zweiten Bereich der Kanal-Region (16) angeordnet ist.


     


    Revendications

    1. Dispositif mémoire, comprenant :

    un substrat semi-conducteur en silicium (10) ;

    une zone drain et une zone source (12, 14) espacées l'une de l'autre et formées dans le substrat semi-conducteur en silicium avec une zone canal (16) entre elles ;

    une grille flottante conductrice (18) disposée au-dessus et isolée d'une première portion de la zone canal (16) et d'une première portion de la zone source, la grille flottante (18) comprenant une surface inférieure et une surface supérieure et une paroi latérale (42a) inclinée vers l'intérieur se terminant au niveau de la surface supérieure en un bord effilé de sorte qu'une largeur de la grille flottante (18) au niveau de la surface inférieure est inférieure à une largeur de la grille flottante (18) au niveau de la surface supérieure ;

    une grille d'effacement conductrice (22) qui comprend :

    une première portion qui est latéralement adjacente à et isolée de la grille flottante (18), et est au-dessus et isolée de la zone source, et

    une deuxième portion qui s'étend vers le haut et au-dessus, et est isolée de la grille flottante (18),

    la deuxième portion de la grille d'effacement (22) s'enroulant autour du bord effilé, et une couche d'oxyde à effet tunnel (28) étant positionnée entre la grille flottante (18) et la deuxième portion de la grille d'effacement (22) de sorte que l'oxyde à effet tunnel (28) est protégé ;

    une grille de ligne de mots conductrice (20) disposée au-dessus et isolée d'une deuxième portion de la zone canal (16), la grille de ligne de mots (20) étant disposée latéralement de façon adjacente à la grille flottante (18) et ne comprenant aucune portion disposée au-dessus de la grille flottante ;

    dans lequel une épaisseur d'isolation (52) séparant la grille de ligne de mots (20) de la deuxième portion de la zone canal (16) est inférieure à une épaisseur d'isolation (40) séparant la grille flottante (18) de la grille d'effacement (22) ;

    dans lequel la grille d'effacement (22) est la seule grille conductrice disposée au-dessus de la grille flottante (18) et la deuxième portion de la grille d'effacement (22) parmi la première portion de la grille d'effacement (22) et la deuxième portion de la grille d'effacement (22) est la seule portion de grille disposée au-dessus de la grille flottante (18) ;

    dans lequel la grille de ligne de mots (20) comprend :

    une surface inférieure faisant face à la deuxième portion de la zone canal (16), la surface de fond étant plane, et

    une surface supérieure opposée à la surface inférieure, la surface supérieure étant plane ;

    dans lequel la grille d'effacement (22) comprend :

    une deuxième surface inférieure faisant face à la zone source ; et

    une deuxième surface supérieure opposée à la deuxième surface inférieure qui est plane.


     
    2. Dispositif mémoire selon la revendication 1, dans lequel la grille de ligne de mots (20) comprend :

    un matériau en métal ; et

    une couche de matériau avec une constante diélectrique K élevée disposée entre le matériau en métal et la deuxième portion de la zone canal (16).


     
    3. Dispositif mémoire selon la revendication 1, dans lequel la grille de ligne de mots (20) comprend :

    du polysilicium ; et

    une couche d'oxyde de nitrure, SiON, disposée entre le polysilicium et la deuxième portion de la zone canal (16) .


     




    Drawing
















































    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description