(19)
(11)EP 3 324 439 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
02.09.2020 Bulletin 2020/36

(21)Application number: 17794646.4

(22)Date of filing:  22.02.2017
(51)International Patent Classification (IPC): 
H01L 27/02(2006.01)
H02H 9/04(2006.01)
(86)International application number:
PCT/CN2017/074450
(87)International publication number:
WO 2018/053991 (29.03.2018 Gazette  2018/13)

(54)

ELECTROSTATIC-DISCHARGE PROTECTION CIRCUIT APPLIED TO INTEGRATED CIRCUIT

SCHALTUNG ZUM SCHUTZ VOR ELEKTROSTATISCHEN ENTLADUNGEN FÜR EINE INTEGRIERTE SCHALTUNG

CIRCUIT DE PROTECTION CONTRE LES DÉCHARGES ÉLECTROSTATIQUES APPLIQUÉ À UN CIRCUIT INTÉGRÉ


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 26.09.2016 WO PCT/CN2016/100109

(43)Date of publication of application:
23.05.2018 Bulletin 2018/21

(73)Proprietor: Shenzhen Goodix Technology Co., Ltd.
Shenzhen, Guangdong 518045 (CN)

(72)Inventor:
  • LEE, Tsung-Lung
    Taipei City (TW)

(74)Representative: Straus, Alexander et al
2K Patent- und Rechtsanwälte - München Keltenring 9
82041 Oberhaching
82041 Oberhaching (DE)


(56)References cited: : 
CN-A- 1 649 142
CN-A- 101 030 574
CN-A- 101 192 753
US-A1- 2009 086 394
US-A1- 2011 176 245
US-B1- 6 399 990
CN-A- 1 805 142
CN-A- 101 192 606
US-A1- 2006 065 932
US-A1- 2010 148 266
US-A1- 2013 099 297
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    Field of the Invention



    [0001] The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly, to an ESD protection circuit capable of preventing leakage current.

    Background



    [0002] As electronic technology evolves, electronic devices are applied in a wider area. Electronic devices are not only applied in high technology area such as aerospace equipment, but also applied in consumer electronic products, such as home appliances, communication devices, medical equipment, etc. Electro static discharge (ESD) is everywhere, and ESD problem is a threat for normal operation of equipment. It is an issue of engineer thinking about how to prevent ESD such that the device operates normally. ESD happens usually in real life, especially when the electronic device is manufactured, transported, stored and in usage. When the electrostatic is accumulated to a certain level, energy of a certain degree would be released, which causes irreversible damage on the electronic device.

    [0003] The ESD protection circuits in the art, e.g., the ESD circuits disclosed in D1 (US 2006/065932 A1) and D2 (US2011/176245 A1), have unavoidable leakage current, which increases over all power consumption of the integrated circuit (IC) .

    [0004] Specifically, the ESD circuit of D1 comprises a first transistor formed on a substrate with its gate and a first diffusion region coupled to the first node for receiving the ESD current, and a second transistor coupled in series with the first transistor at its second diffusion region and with the second transistor's gate coupled to the second node for dissipating the ESD current therethrough.

    [0005] The ESD circuit of D2 comprises a diode network, coupled between an IC pad of the IC and a drain of the cascode grounded gate NFET, where the diode network sets the turn-on voltage of the device at a desired level; and a precharge circuit, to set the bias voltage at the drain of the cascode grounded gate NFET at a desired level in order to reduce the capacitive loading at the IC pad.

    [0006] Both D1 and D2 face the leakage current problem. Therefore, how to prevent leakage current is a significant objective in the field.

    Summary



    [0007] It is therefore a primary objective of embodiments of the present application to provide an ESD protection circuit capable of preventing leakage current.

    [0008] To solve the problem stated in the above, the present application provides an ESD protection circuit as defined in claim 1, including a first N-type transistor including a first gate terminal, coupled to a ground terminal; a first electrode terminal, coupled to the first gate terminal; and a second electrode terminal; a second N-type transistor including a second gate terminal, coupled to a metal pad; a third electrode terminal, coupled to the second gate terminal; a fourth electrode terminal, coupled to the second electrode terminal; and a fifth electrode terminal; and a high-voltage tracing circuit including a first input terminal, coupled to the metal pad, receiving a metal pad voltage; a second input terminal, receiving a supply voltage; and an output terminal, coupled to the fifth electrode terminal, configured to output a high-voltage tracing voltage, wherein the high-voltage tracing voltage is larger than or equal to the metal pad voltage.

    [0009] For example, the high-voltage tracing circuit includes a first transistor including a first control terminal, coupled to the second input terminal; a first terminal, coupled to the first input terminal; and a second terminal, coupled to the output terminal; and a second transistor including a second control terminal, coupled to the first input terminal; a third terminal, coupled to the second input terminal; and a fourth terminal, coupled to the output terminal.

    [0010] For example, when the metal pad voltage is larger than the supply voltage, the first transistor is conducted and the second transistor is cutoff.

    [0011] For example, when the metal pad voltage is less than the supply voltage, the first transistor is cutoff and the second transistor is conducted.

    [0012] For example, the high-voltage tracing circuit further includes a diode, coupled between the first input terminal and the first terminal of the first transistor.

    [0013] For example, the first N-type transistor further includes a first base terminal, coupled to the first electrode terminal.

    [0014] For example, the second N-type transistor includes a first deep N-well, disposed under the third electrode terminal, the fourth electrode terminal and the fifth electrode terminal.

    [0015] For example, the second N-type transistor further includes a first P-well, disposed between the third electrode terminal, the fourth electrode terminal and the first deep N-well.

    [0016] For example, the second N-type transistor further includes a first N-well, and the first N-well is disposed by a side of the first P-well.

    [0017] For example, the N-type region is formed as the fifth electrode terminal.

    [0018] For example, when a metal pad voltage of the metal pad is a positive ESD voltage, a first current flows to the ground terminal through the first N-type transistor.

    [0019] For example, when a metal pad voltage of the metal pad is a positive ESD voltage, the first N-type transistor is formed as a first bipolar transistor.

    [0020] For example, when a metal pad voltage of the metal pad is a negative ESD voltage, a second current flows to the metal pad through the second N-type transistor.

    [0021] For example, when a metal pad voltage of the metal pad is a negative ESD voltage, the second N-type transistor is formed as a second bipolar transistor.

    [0022] For example, the high-voltage tracing voltage is a maximum voltage of the metal pad voltage and the supply voltage.

    [0023] For example, the ESD protection circuit further includes a diode, coupled between the fifth electrode terminal of the second N-type transistor and the output terminal of the high-voltage tracing circuit.

    [0024] For example, the diode includes a first terminal, coupled to the fifth electrode terminal of the second N-type transistor; and a second terminal, coupled to the output terminal of the high-voltage tracing circuit.

    [0025] For example, the diode includes a second N-well, disposed under the first terminal and the second terminal.

    [0026] For example, the diode includes a second P-well, disposed under the first terminal and the second terminal.

    [0027] For example, the diode further includes a second deep N-well, disposed under the second P-well.

    [0028] For example, the ESD protection circuit further includes a plurality of diodes, formed as a diode series; wherein the diode series is coupled between the fifth electrode terminal of the second N-type transistor and the output terminal of the high-voltage tracing circuit.

    [0029] The ESD protection circuit provided by the present application utilizes the high-voltage tracing circuit to avoid the leakage current, and has advantages of small circuit area and low power consumption.

    Brief Description of the Drawings



    [0030] One or more exemplary embodiments illustrated by the drawings of the corresponding images, which illustrate exemplary embodiments does not constitute a limited, elements the same reference numerals in the figures of the drawings denote like elements having, unless otherwise stated, the accompanying drawings do not constitute a limit thereon.

    FIG. 1 is a schematic diagram of an electrostatic discharge (ESD) protection circuit according to an embodiment of the present application.

    FIG. 2 is a sectional side view of circuit layout regarding a first N-type transistor and a second N-type transistor within the ESD protection circuit illustrated in FIG. 1.

    FIG. 3 is a schematic diagram of an ESD protection circuit according to an embodiment of the present application.

    FIG. 4 is a sectional side view of circuit layout regarding a second N-type transistor and a diode within the ESD protection circuit illustrated in FIG. 3.

    FIG. 5 is a sectional side view of circuit layout regarding the second N-type transistor and a diode within the ESD protection circuit illustrated in FIG. 3.

    FIG. 6 is a schematic diagram of an ESD protection circuit according to an embodiment of the present application.

    FIG. 7 is a schematic diagram of an ESD protection circuit according to an embodiment of the present application.


    Detailed Description



    [0031] In order to make the objects, technical solutions and advantages of the present invention become more apparent, the following relies on the accompanying drawings and embodiments to describe the present invention in further detail. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.

    [0032] Please refer to FIG. 1 and FIG. 2. FIG. 1 is a schematic diagram of an electrostatic discharge (ESD) protection circuit 10 according to an embodiment of the present invention. FIG. 2 is a sectional side view of circuit layout regarding a first N-type transistor Q1 and a second N-type transistor Q2. The ESD protection circuit 10 includes the first N-type transistor Q1, the second N-type transistor Q2 and a high-voltage tracing circuit TH. The first N-type transistor Q1 includes a gate terminal G1 and electrode terminals S1 and D1. The second N-type transistor Q2 includes a gate terminal G2 and electrode terminals S2, D2 and E2. The gate terminal G1 and the electrode terminal S1 are coupled to a ground terminal GND. The gate terminal G2 and the electrode terminal S2 are coupled to a metal pad PAD. The electrode terminal D1 of the first N-type transistor Q1 is coupled to the electrode terminal D2 of the second N-type transistor. The high-voltage tracing circuit TH has input terminals In_1 and In_2 and an output terminal Out. The input terminal In_1 is coupled to the metal pad PAD, configured to receive a metal pad voltage VPAD. The input terminal In_2 is configured to receive a supply voltage VDDIO. The output terminal Out is coupled to the electrode terminal E2 of the second N-type transistor Q2, configured to output a high-voltage tracing voltage VE2, wherein the high-voltage tracing voltage VE2 is larger than or equal to the metal pad voltage VPAD.

    [0033] Specifically, as shown in FIG. 2, the first N-type transistor Q1 is formed on a P-type substrate PSUB. That is, the N-type regions 200, 202 and the P-type regions 204, 206 are formed on the P-type substrate PSUB. The N-type region 200 may be formed as the electrode terminal D1 of the first N-type transistor Q1. The N-type region 202 may be formed as the electrode terminal S1 of the first N-type transistor Q1. An oxide layer and a poly silicon layer, disposed between the N-type region 200 and the N-type region 202, are formed as the gate terminal G1 of the first N-type transistor Q1. In addition, the P-type region 204 may be formed as a base terminal B1 of the first N-type transistor Q1. The gate terminal G1, the electrode terminal S1 and the base terminal B1 of the first N-type transistor Q1 are all coupled to the ground terminal GND.

    [0034] In addition, the second N-type transistor Q2 includes a deep N-well DNW, a P-well PW, N-wells NW, N-type regions 220, 222, 227 and 228 and P-type regions 224 and 226. The P-well PW and the N-wells NW are both formed on the deep N-well DNW. The N-wells NW are disposed by two sides of the P-well PW. The N-type regions 220, 222 and the P-type regions 224 and 226 are formed on the P-well PW. The N-type regions 227 and 228 are formed on the N-wells NW. Similarly, the N-type region 220 may be formed as the electrode terminal S2 of the second N-type transistor Q2, and the N-type region 222 may be formed as the electrode terminal D2 of the second N-type transistor Q2. An oxide layer and a poly silicon layer, disposed between the N-type region 220 and the N-type region 222, are formed as the gate terminal G2 of the second N-type transistor Q2. In addition, the P-type region 226 may be formed as a base terminal B2 of the second N-type transistor Q2. The gate terminal G2, the electrode terminal S2 and the base terminal B2 of the second N-type transistor Q2 are all coupled to the metal pad PAD. In addition, the N-type regions 227 and 228 are formed as the electrode terminal E2 of the second N-type transistor Q2, and coupled to the output terminal Out of the high-voltage tracing circuit TH.

    [0035] Notably, junctions between the P-well PW of the second N-type transistor Q2 and the N-well NW would form parasitic diodes Dpar. When the forward bias between the P-well PW and the N-wells NW is too large, it is equivalent that the parasitic diodes Dpar are conducted, and leakage current from the P-well PW to the N-wells NW is generated.

    [0036] To solve the leakage current problem, the high-voltage tracing circuit TH may output the high-voltage tracing voltage VE2 which is larger than or equal to the metal pad voltage VPAD, to prevent the leakage current. Specifically, the high-voltage tracing circuit TH includes a first transistor P1 and a second transistor P2. In an embodiment, the first transistor P1 and the second transistor P2 are all PMOS. A gate PG1 of the first transistor P1 is coupled to the input terminal In_2 to receive the supply voltage VDDIO. A source PS1 of the first transistor P1 is coupled to the input terminal In_1 to receive the metal pad voltage VPAD. A gate PG2 of the second transistor P2 is coupled to the input terminal In_1 to receive the metal pad voltage VPAD. A source PS2 of the second transistor P2 is coupled to the input terminal In_2 to receive the supply voltage VDDIO, a drain PD1 of the first transistor P1 and a drain PD2 of the second transistor P2 are both coupled to the electrode terminal E2 of the second N-type transistor Q2. Ignoring a threshold voltage Vth of the first transistor P1 and the second transistor P2, when the metal pad voltage VPAD is larger than the supply voltage VDDIO, the first transistor P1 is conducted and the second transistor P2 is cutoff. At this time, the high-voltage tracing circuit TH outputs the high-voltage tracing voltage VE2 as the metal pad voltage VPAD to the electrode terminal E2 of the second N-type transistor Q2. On the other hand, when the metal pad voltage VPAD is less than the supply voltage VDDIO, the first transistor P1 is cutoff and the second transistor P2 is conducted. At this time, the high-voltage tracing circuit TH outputs the high-voltage tracing voltage VE2 as the supply voltage VDDIO to the electrode terminal E2 of the second N-type transistor Q2. In other words, the high-voltage tracing voltage VE2 outputted by the high-voltage tracing circuit TH is a maximum voltage of the metal pad voltage VPAD and the supply voltage VDDIO, i.e., VE2 = max (VPAD, VDDIO) . It implies that, the high-voltage tracing voltage VE2 outputted by the high-voltage tracing circuit TH is larger than or equal to the metal pad voltage VPAD. In this case, the junctions between the P-well PW of the second N-type transistor Q2 and the N-wells NW would hardly have sufficient forward bias, or the forward bias is insufficient. The parasitic diodes Dpar are rarely conducted, which solves the leakage current problem between the P-well PW and the N-wells NW.

    [0037] In addition, an internal circuit 12, protected by the ESD protection circuit 10, is coupled to the metal pad PAD, where the metal pad PAD, the ESD protection circuit 10 and the internal circuit 12 may be integrated in an integrated circuit (IC) . Under a normal operation condition, i.e., when a voltage difference between the metal pad PAD and the ground terminal GND is substantially the supply voltage VDDIO of the IC, a loop from the metal pad PAD to the ground terminal GND is cutoff. When an extremely high voltage exists between the metal pad PAD and the ground terminal GND, e.g., ESD Zap, or during ESD testing, a current path within the ESD protection circuit 10 from the metal pad PAD to the ground terminal GND may be formed, which means that the loop from the metal pad PAD to the ground terminal GND is conducted, so as to prevent the extremely high voltage and its current has impact on the internal circuit 12, e.g., damages the internal circuit 12.

    [0038] Specifically, under a normal operation condition, when the metal pad voltage VPAD of the metal pad PAD is substantially the supply voltage VDDIO, the second N-type transistor Q2 is conducted and the first N-type transistor Q1 is cutoff. When the metal pad voltage VPAD is substantially negative of the supply voltage, i.e., -VDDIO, the second N-type transistor Q2 is cutoff and the first N-type transistor Q1 is conducted. In other words, under the normal operation condition, the loop between the metal pad PAD and the ground terminal GND is cutoff.

    [0039] On the other hand, when ESD Zap occurs or it is during ESD testing, the first N-type transistor Q1 (or the second N-type transistor Q2) is equivalent to a bipolar transistor and the current path is formed, which is to prevent the internal circuit 12 from being damaged. Specifically, when the metal pad voltage VPAD receives a positive ESD voltage, e.g., VPAD=2 kilovolt (KV), the second N-type transistor Q2 is conducted, and the P-type substrate PSUB of the first N-type transistor Q1 and the N-type regions 200, 202 form a bipolar transistor Bsub and an equivalent resistance Rsub. Hence, a current may flow from the metal pad PAD to the ground terminal GND. On the other hand, when the metal pad voltage VPAD receives a negative ESD voltage, e.g., VPAD=-2KV, the first N-type transistor Q1 is conducted, and the P-well PW of the second N-type transistor Q2 and the N-type regions 220, 222 forms a bipolar transistor BPW and an equivalent resistance RPW. Hence, a current may flow from the ground terminal GND to the metal pad PAD. In other words, when there is an extremely high voltage existing between the metal pad PAD and the ground terminal GND, the originally cutoff first N-type transistor Q1 (or the originally cutoff second N-type transistor Q2) may form as the bipolar transistor Bsub (or the bipolar transistor BPW), and the current path between the metal pad PAD and the ground terminal GND is formed, such that the loop through the metal pad PAD and the ground terminal GND is conducted in time, so as to prevent excessive current from flowing to the internal circuit 12 and damaging the internal circuit 12.

    [0040] As can be seen, the ESD protection circuit 10 utilizes the high-voltage tracing circuit TH to provide the high-voltage tracing voltage VE2 which is larger than the metal pad voltage VPAD to the electrode terminal E2 of the second N-type transistor Q2. Hence, the ESD protection circuit 10 would not have the leakage current flowing from the P-well PW to the N-well NW.

    [0041] Notably, the embodiments stated in the above are utilized for illustrating the concept of the present application. Those skilled in the art may make modifications and alterations accordingly, and not limited herein. For example, please refer to FIG. 3, which is a schematic diagram of an ESD protection circuit 30 according to an embodiment of the present application. The ESD protection circuit 30 is similar to the ESD protection circuit 10, and thus, the same components are denoted by the same notations. Different from the ESD protection circuit 10, the ESD protection circuit 30 further includes a diode DP. The diode DP is coupled between the electrode terminal E2 of the second N-type transistor Q2 and the output terminal Out of the high-voltage tracing circuit TH. When the metal pad voltage VPAD is negative, the diode DP may be utilized to prevent junction breakdown between the N-well NW and the P-well PW (or the deep N-well DNW and the P-well PW) within the second N-type transistor Q2. Please refer to FIG. 4 to see the detail connection between the second N-type transistor Q2 and the diode DP. FIG. 4 is a sectional side view of circuit layout regarding the second N-type transistor Q2 and a diode DP4. The diode DP4 may be utilized to realize the diode DP in FIG. 3. As FIG. 4 shows, the diode DP4 may be formed in the P-type substrate PSUB. The diode DP4 includes an N-well NW4, an N-type region 400 and a P-type region 402, where the N-type region 400 and the P-type region 402 are formed in the N-well NW4. The N-type region 400 is coupled to the output terminal Out of the high-voltage tracing circuit TH, and the P-type region 402 is coupled to the N-type region 227/the electrode terminal E2 of the second N-type transistor Q2. In addition, the diode DP in FIG. 3 is not limited to be realized by using the diode DP4 in FIG. 4. For example, please refer to FIG. 5, which is a sectional side view of circuit layout regarding the second N-type transistor Q2 and a diode DP5. The diode DP5 may also be utilized to realize the diode DP in FIG. 3. Different from the diode DP4, the diode DP5 includes a deep N-well DNW5, a P-well PW5, N-wells NW5, N-type regions 500, 504, 506 and a P-type region 502. The P-well PW5 and the N-wells NW5 are both formed on the deep N-well DNW5. The N-wells NW5 are disposed by two sides of the P-well PW5. In addition, the N-type region 500 and the P-type region 502 are formed on the P-well PW5. The N-type regions 504 and 506 are formed on the N-well NW5. The N-type regions 504, 506 and the P-type region 502 are coupled to the N-type region 227/the electrode terminal E2 of the second N-type transistor Q2. The N-type region 500 is coupled to the output terminal Out of the high-voltage tracing circuit TH.

    [0042] In addition, please refer to FIG. 6, which is a schematic diagram of an ESD protection circuit 60 according to an embodiment of the present application. The ESD protection circuit 60 is similar to the ESD protection circuit 30, and thus, the same components are denoted by the same notations. Different from the ESD protection circuit 30, the ESD protection circuit 60 comprises a plurality of diodes DP6. The plurality of diodes DP6 are connected in series to form as a diode series, and the diode series is coupled between the electrode terminal E2 of the second N-type transistor Q2 and the output terminal Out of the high-voltage tracing circuit TH, which is also within the scope of the present application.

    [0043] In addition, please refer to FIG. 7, which is a schematic diagram of an ESD protection circuit 70 according to an embodiment of the present application. The ESD protection circuit 70 is similar to the ESD protection circuit 10, and thus, the same components are denoted by the same notations. Different from the ESD protection circuit 10, the high-voltage tracing circuit TH of the ESD protection circuit 70 further includes a diode D1. The diode D1 is configured to protect the first transistor P1, so as to prevent the first transistor P1 from damage caused by excessive voltage, especially when the metal pad voltage VPAD is negative of the supply voltage VDDIO, i.e., VPAD = - VDDIO.

    [0044] In summary, the ESD protection circuit of the present application utilizes the high-voltage tracing circuit to provide the high-voltage tracing voltage larger than the metal pad voltage to the electrode terminal of the second N-type transistor Q2. Thus, the ESD protection circuit may avoid the leakage current from the P-well to the N-wells.


    Claims

    1. An electrostatic discharge (ESD) protection circuit, comprising:

    a first N-type transistor (Q1), comprising:

    a first gate terminal (G1), coupled to a ground terminal (GND);

    a first source electrode terminal (S1), coupled to the first gate terminal (G1); and

    a first drain electrode terminal (D1); and

    a first base terminal (B1), wherein the first gate terminal (G1), the first source electrode terminal (S1), and the first base terminal (B1) of the N-type first transistor (Q1) are all coupled to the ground terminal (GND);

    the ESD protection circuit further comprising a second N-type transistor (Q2), comprising:

    a second gate terminal (G2), coupled to a metal pad (PAD);

    a second source electrode terminal (S2), coupled to the second gate terminal (G2);

    a second drain electrode terminal (D2), coupled to the first drain electrode terminal (D1);

    a second base terminal (B2), wherein the second gate termnal (G2), the second source electrode terminal (S2), and the second base terminal (B2) are coupled to the metal pad (PAD); and

    a fifth electrode terminal (E2), coupled to an isolation region (227, 228) of the second N-type transistor (Q2);

    and the ESD protection circuit further comprising a high-voltage tracing circuit (TH), comprising:

    a first input terminal (In_1), coupled to the metal pad (PAD) and configured to receive a metal pad voltage (VPAD);

    a second input terminal (In_2), configured to receive a supply voltage (VDDIO); and

    an output terminal (Out), coupled to the fifth electrode terminal (E2), configured to output a high-voltage tracing voltage, wherein the high-voltage tracing voltage is larger than or equal to the metal pad voltage.


     
    2. The ESD protection circuit as claim 1, characterised in that, the high-voltage tracing circuit comprises:

    a first transistor (P1), comprising:

    a first control terminal (PG1), coupled to the second input terminal (In_2);

    a first terminal (PS1), coupled to the first input terminal (In_1); and

    a second terminal (PD1), coupled to the output terminal (Out); and

    a second transistor (P2), comprising:

    a second control terminal (PG2), coupled to the first input terminal (In_1);

    a third terminal (PS2), coupled to the second input terminal (In_2); and

    a fourth terminal (PD2), coupled to the output terminal (Out).


     
    3. The ESD protection circuit as claim 2, characterised in that, when the metal pad voltage is larger than the supply voltage, the first transistor is conducted and the second transistor is cutoff ; or when the metal pad voltage is less than the supply voltage, the first transistor is cutoff and the second transistor is conducted.
     
    4. The ESD protection circuit as claim 2, characterised in that, the high-voltage tracing circuit (TH) further comprises:
    a diode (D1), coupled between the first input terminal (In_1) and the first terminal (PS1) of the first transistor (P1).
     
    5. The ESD protection circuit as any one of claims 1 to 4, characterised in that, the second N-type transistor (Q2) comprises:
    a first deep N-well (DNW), disposed under the second source electrode terminal (S2), the second drain electrode terminal (D2) and the fifth electrode terminal (E2).
     
    6. The ESD protection circuit as claim 5, characterised in that, the second N-type transistor (Q2) further comprises a first P-well (PW), disposed between the second source electrode terminal (S2), the second drain electrode terminal (D2) and the first deep N-well (DNW).
     
    7. The ESD protection circuit as claim 6, characterised in that, the second N-type transistor (Q2) further comprises a first N-well (NW), and the first N-well (NW) is disposed by a side of the first P-well (PW).
     
    8. The ESD protection circuit as claim 7, characterised in that, the second N-type transistor further comprises an N-type region (227, 228), the N-type region (227, 228) is disposed in the first N-well (NW) and is formed as the fifth electrode terminal (E2).
     
    9. The ESD protection circuit as any one of claims 1 to 8, characterised in that,
    when a metal pad voltage of the metal pad is a positive ESD voltage, a first current flows to the ground terminal through the first N-type transistor or the first N-type transistor is formed as a first bipolar transistor; or
    when a metal pad voltage of the metal pad is a negative ESD voltage, a second current flows to the metal pad through the second N-type transistor, or the second N-type transistor is formed as a second bipolar transistor.
     
    10. The ESD protection circuit as claim 9, characterised in that, the positive ESD voltage is larger than 1 kilovolt, or the negative ESD voltage is less than negative 1 kilovolt.
     
    11. The ESD protection circuit as any one of claims 1 to 10, characterised in that, the high-voltage tracing voltage is a maximum voltage between the metal pad voltage and the supply voltage.
     
    12. The ESD protection circuit as any one of claims 1 to 11, characterised by, further comprising:
    a diode (DP, DP4, DP5) or a plurality of diodes (DP6) formed as a diode series, coupled between the fifth electrode terminal (E2) of the second N-type transistor (Q2) and the output terminal (Out) of the high-voltage tracing circuit (TH).
     
    13. The ESD protection circuit as claim 12, characterised in that, the diode comprises:

    a first terminal, coupled to the fifth electrode terminal (E2) of the second N-type transistor (Q2); and

    a second terminal, coupled to the output terminal (Out) of the high-voltage tracing circuit (TH).


     
    14. The ESD protection circuit as claim 13, characterised in that, the diode (DP5) comprises:

    a second N-well (NW5), disposed under the first terminal and the second terminal; or

    a second P-well (PW5), disposed under the first terminal and the second terminal.


     
    15. The ESD protection circuit as claim 14, characterised in that, the diode further comprises:
    a second deep N-well (DNW5), disposed under the second P-well.
     


    Ansprüche

    1. Elektrostatische Entladungs- (ESD) Schutzschaltung, dadurch gekennzeichnet, dass diese umfasst:

    einen ersten N-Typ-Transistor (Q1), der umfasst:

    einen ersten Gatteranschluss (G1), der mit einem Erdungsanschluss (GND) gekoppelt ist;

    einen ersten Quellenelektrodenanschluss (S1), der mit dem ersten Gatteranschluss (G1) gekoppelt ist;

    einen ersten Abflusselektrodenanschluss (D1); und

    einen ersten Basisanschluss (B1), worin der erste Gatteranschluss (G1), der erste Quellenelektrodenanschluss (S1), und der erste Basisanschluss (B1) des ersten N-Typ-Transistors (Q1) alle mit dem Erdungsanschluss (GND) gekoppelt sind;

    worin die ESD-Schutzschaltung weiter einen zweiten N-Typ-Transistor (Q2) umfasst, der umfasst:

    einen zweiten Gatteranschluss (G2), der mit einem Metall-Pad (PAD) gekoppelt ist;

    einen zweiten Quellenelektrodenanschluss (S2), der mit dem zweiten Gatteranschluss (G2) gekoppelt ist;

    einen zweiten Abflusselektrodenanschluss (D2), der mit dem ersten Abflusselektrodenanschluss (D1) gekoppelt ist;

    einen zweiten Basisanschluss (B2), worin der zweite Gatteranschluss (G2), der zweite Quellenelektrodenanschluss (S2), und der zweite Basisanschluss (B2) mit dem Metall-Pad (PAD) gekoppelt sind; und

    einen fünften Elektrodenanschluss (E2), der mit einem Isolierbereich (227, 228) des zweiten N-Typ-Transistors (Q2) gekoppelt ist; und

    worin die ESD-Schutzschaltung weiter einen Hochspannungs-Ablaufverfolgungsschaltkreis (TH) umfasst, der umfasst:

    einen ersten Eingangsanschluss (In_1), der mit dem Metall-Pad (PAD) gekoppelt und ausgestaltet ist, eine Metall-Pad-Spannung (VPAD) zu empfangen;

    einen zweiten Eingangsanschluss (In_2), der ausgestaltet ist, eine Versorgungsspannung (VDDIO) zu empfangen; und

    einen Ausgangsanschluss (Out), der mit dem fünften Elektrodenanschluss (E2) gekoppelt und ausgestaltet ist, eine Hochspannungs-Ablaufverfolgungsspannung auszugeben, wobei die Hochspannungs-Ablaufverfolgungsspannung größer oder gleich der Metall-Pad-Spannung ist.


     
    2. ESD-Schutzschaltung nach Anspruch 1, dadurch gekennzeichnet, dass der Hochspannungs-Ablaufverfolgungsschaltkreis umfasst:

    einen ersten Transistor (P1), der umfasst:

    einen ersten Steueranschluss (PG1), der mit dem zweiten Eingangsanschluss (In_2) gekoppelt ist;

    einen ersten Anschluss (PS1), der mit dem ersten Eingangsanschluss (In_1) gekoppelt ist; und

    einen zweiten Anschluss (PD1), der mit dem Ausgangsanschluss (Out) gekoppelt ist; und

    einen zweiten Transistor (P2), der umfasst:

    einen zweiten Steueranschluss (PG2), der mit dem ersten Eingangsanschluss (In_1) gekoppelt ist;

    einen dritten Anschluss (PS2), der mit dem zweiten Eingangsanschluss (In_2) gekoppelt ist; und

    einen vierten Anschluss (PD2), der mit dem Ausgangsanschluss (Out) gekoppelt ist.


     
    3. ESD-Schutzschaltung nach Anspruch 2, dadurch gekennzeichnet, dass wenn die Metall-Pad-Spannung größer ist als die Versorgungsspannung, der erste Transistor leitet und der zweite Transistor abgeschaltet ist; oder wenn die Metall-Pad-Spannung kleiner als die Versorgungsspannung ist, der erste Transistor abgeschaltet ist und der zweite Transistor leitet.
     
    4. ESD-Schutzschaltung nach Anspruch 2, dadurch gekennzeichnet, dass der Hochspannungs-Ablaufverfolgungsschaltkreis (TH) weiter umfasst:
    eine Diode (D1), die zwischen dem ersten Eingangsanschluss (In_1) und dem ersten Anschluss (PS1) des ersten Transistors (P1) gekoppelt ist.
     
    5. ESD-Schutzschaltung nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, dass, der zweite N-Typ-Transistor (Q2) umfasst:
    eine erste tiefe N-Wanne (DNW), die unter dem zweiten Quellenelektrodenanschluss (S2), dem zweiten Abflusselektrodenanschluss (D2) und dem fünften Elektrodenanschluss (E2) angeordnet ist.
     
    6. ESD-Schutzschaltung nach Anspruch 5, dadurch gekennzeichnet, dass der zweite N-Typ-Transistor (Q2) weiter eine erste P-Wanne (PW) umfasst, die zwischen dem zweiten Quellenelektrodenanschluss (S2), dem zweiten Abflusselektrodenanschluss (D2) und der ersten tiefen N-Wanne (DNW) angeordnet ist.
     
    7. ESD-Schutzschaltung nach Anspruch 6, dadurch gekennzeichnet, dass der zweite N-Typ-Transistor (Q2) weiter eine erste N-Wanne (NW) umfasst, worin die erste N-Wanne (NW) an einer Seite der ersten P-Wanne (PW) angeordnet ist.
     
    8. ESD-Schutzschaltung nach Anspruch 7, dadurch gekennzeichnet, dass der zweite N-Typ-Transistor weiter einen N-Typ-Bereich (227, 228) umfasst, worin der N-Typ-Bereich (227, 228) in der ersten N-Wanne (NW) angeordnet und als der fünfte Elektrodenanschluss (E2) ausgebildet ist.
     
    9. ESD-Schutzschaltung nach einem der Ansprüche 1 bis 8, dadurch gekennzeichnet, dass,
    wenn eine Metall-Pad-Spannung des Metall-Pads eine positive ESD-Spannung ist, ein erster Strom durch den ersten N-Typ-Transistor zu dem Erdungsanschluss fließt oder der erste N-Typ-Transistor als ein erster bipolarer Transistor ausgebildet ist; oder
    wenn eine Metall-Pad-Spannung des Metall-Pads eine negative ESD-Spannung ist, ein zweiter Strom durch den zweiten N-Typ-Transistor zu dem Metall-Pad fließt, oder der zweite N-Typ-Transistor als ein zweiter bipolarer Transistor ausgebildet ist.
     
    10. ESD-Schutzschaltung nach Anspruch 9, dadurch gekennzeichnet, dass die positive ESD-Spannung größer als 1 Kilovolt ist, oder die negative ESD-Spannung kleiner als 1 negatives Kilovolt ist.
     
    11. ESD-Schutzschaltung nach einem der Ansprüche 1 bis 10, dadurch gekennzeichnet, dass die Hochspannungs-Ablaufverfolgungsspannung eine Maximalspannung zwischen der Metall-Pad-Spannung und der Versorgungsspannung ist.
     
    12. ESD-Schutzschaltung nach einem der Ansprüche 1 bis 11, dadurch gekennzeichnet, dass sie weiter umfasst:
    eine Diode (DP, DP4, DP5) oder mehrere als eine Diodenreihe ausgebildete Dioden (DP6), die zwischen dem fünften Elektrodenanschluss (E2) des zweiten N-Typ-Transistors (Q2) und dem Ausgangsanschluss (Out) des Hochspannungs-Ablaufverfolgungsschaltkreises (TH) gekoppelt sind.
     
    13. ESD-Schutzschaltung nach Anspruch 12, dadurch gekennzeichnet, dass die Diode umfasst:

    einen ersten Anschluss, der mit dem fünften Elektrodenanschluss (E2) des zweiten N-Typ-Transistors (Q2) gekoppelt ist; und

    einen zweiten Anschluss, der mit dem Ausgangsanschluss (Out) des Hochspannungs-Ablaufverfolgungsschaltkreises (TH) gekoppelt ist.


     
    14. ESD-Schutzschaltung nach Anspruch 13, dadurch gekennzeichnet, dass die Diode (DP5) umfasst:

    eine zweite N-Wanne (NW5), die unter dem ersten Anschluss und dem zweiten Anschluss angeordnet ist; oder

    eine zweite P-Wanne (PW5), die unter dem ersten Anschluss und dem zweiten Anschluss angeordnet ist.


     
    15. ESD-Schutzschaltung nach Anspruch 14, dadurch gekennzeichnet, dass die Diode weiter umfasst:
    eine zweite tiefe N-Wanne (DNW5), die unter der zweiten P-Wanne angeordnet ist.
     


    Revendications

    1. Circuit de protection contre les décharges électrostatiques (DES) comprenant :

    un premier transistor de type N (Q1), comprenant :

    une première borne de grille (G1), couplée à une borne de masse (GND) ;

    une première borne d'électrode source (S1), couplée à la première borne de grille (G1) ; et

    une première borne d'électrode de drain (D1) ; et

    une première borne de base (B1) ; la première borne de grille (G1), la première borne d'électrode source (S1) et la première borne de base (B1) du premier transistor de type N (Q1) étant toutes couplées à la borne de masse (GND) ;

    le circuit de protection contre les DES comprenant en outre un deuxième transistor de type N (Q2), comprenant :

    une deuxième borne de grille (G2), couplée à un plot métallique (PAD) ;

    une deuxième borne d'électrode source (S2), couplée à la deuxième borne de grille (G2) ;

    une deuxième borne d'électrode de drain (D2), couplée à la première borne d'électrode de drain (D1) ;

    une deuxième borne de base (B2) ; la deuxième borne de grille (G2), la deuxième borne d'électrode source (S2) et la deuxième borne de base (B2) étant couplées au plot métallique (PAD) ; et

    une cinquième borne d'électrode (E2), couplée à une région d'isolation (227, 228) du deuxième transistor de type N (Q2) ;

    et

    le circuit de protection contre les DES comprenant en outre un circuit de repérage haute tension (TH), comprenant :

    une première borne d'entrée (In_1), couplée au plot métallique (PAD) et conçue pour recevoir une tension de plot métallique (VPAD) ;

    une deuxième borne d'entrée (In_2), conçue pour recevoir une tension d'alimentation (VDDIO) ; et

    une borne de sortie (Out), couplée à la cinquième borne d'électrode (E2), conçue pour délivrer une tension de repérage haute tension, la tension de repérage haute tension étant supérieure ou égale à la tension de plot métallique.


     
    2. Circuit de protection contre les DES selon la revendication 1, caractérisé en ce que le circuit de repérage haute tension comprend :

    un premier transistor (P1), comprenant :

    une première borne de commande (PG1), couplée à la deuxième borne d'entrée (In_2) ;

    une première borne (PS1), couplée à la première borne d'entrée (In_1) ; et

    une deuxième borne (PD1), couplée à la borne de sortie (Out) ; et

    un deuxième transistor (P2) comprenant :

    une deuxième borne de commande (PG2), couplée à la première borne d'entrée (In_1) ;

    une troisième borne (PS2), couplée à la deuxième borne d'entrée (In_2) ; et

    une quatrième borne (PD2), couplée à la borne de sortie (Out).


     
    3. Circuit de protection contre les DES selon la revendication 2, caractérisé en ce que, lorsque la tension de plot métallique est supérieure à la tension d'alimentation, le premier transistor est mis à l'état conducteur et le deuxième transistor est coupé ; ou lorsque la tension de plot métallique est inférieure à la tension d'alimentation, le premier transistor est coupé et le deuxième transistor est mis à l'état conducteur.
     
    4. Circuit de protection contre les DES selon la revendication 2, caractérisé en ce que le circuit de repérage haute tension (TH) comprend en outre :
    une diode (D1), couplée entre la première borne d'entrée (In_1) et la première borne (PS1) du premier transistor (P1).
     
    5. Circuit de protection contre les DES selon l'une quelconque des revendications 1 à 4, caractérisé en ce que le deuxième transistor de type N (Q2) comprend :
    un premier puits N profond (DNW), disposé sous la deuxième borne d'électrode source (S2), la deuxième borne d'électrode de drain (D2) et la cinquième borne d'électrode (E2).
     
    6. Circuit de protection contre les DES selon la revendication 5, caractérisé en ce que le deuxième transistor de type N (Q2) comprend en outre un premier puits P (PW), disposé entre la deuxième borne d'électrode source (S2), la deuxième borne d'électrode de drain (D2) et le premier puits N profond (DNW).
     
    7. Circuit de protection contre les DES selon la revendication 6, caractérisé en ce que le deuxième transistor de type N (Q2) comprend en outre un premier puits N (NW) et le premier puits N (NW) est disposé sur un côté du premier puits P (PW).
     
    8. Circuit de protection contre les DES selon la revendication 7, caractérisé en ce que le deuxième transistor de type N comprend en outre une région de type N (227, 228), la région de type N (227, 228) étant disposée dans le premier puits N (NW) et étant formée en tant que cinquième borne d'électrode (E2).
     
    9. Circuit de protection contre les DES selon l'une quelconque des revendications 1 à 8, caractérisé en ce que,
    lorsqu'une tension de plot métallique du plot métallique est une tension de DES positive, un premier courant s'écoule vers la borne de masse à travers le premier transistor de type N ou le premier transistor de type N est formé en tant que premier transistor bipolaire ; ou
    lorsqu'une tension de plot métallique du plot métallique est une tension de DES négative, un deuxième courant s'écoule vers le plot métallique à travers le deuxième transistor de type N ou le deuxième transistor de type N est formé en tant que deuxième transistor bipolaire.
     
    10. Circuit de protection contre les DES selon la revendication 9, caractérisé en ce que la tension de DES positive est supérieure à 1 kilovolt ou la tension de DES négative est inférieure à 1 kilovolt négatif.
     
    11. Circuit de protection contre les DES selon l'une quelconque des revendications 1 à 10, caractérisé en ce que la tension de repérage haute tension est une tension maximale entre la tension de plot métallique et la tension d'alimentation.
     
    12. Circuit de protection contre les DES selon l'une quelconque des revendications 1 à 11, caractérisé en ce qu'il comprend en outre :
    une diode (DP, DP4, DP5) ou une pluralité de diodes (DP6) formées en série de diodes, couplée entre la cinquième borne d'électrode (E2) du deuxième transistor de type N (Q2) et la borne de sortie (Out) du circuit de repérage haute tension (TH).
     
    13. Circuit de protection contre les DES selon la revendication 12, caractérisé en ce que la diode comprend :

    une première borne, couplée à la cinquième borne d'électrode (E2) du deuxième transistor de type N (Q2) ; et

    une deuxième borne, couplée à la borne de sortie (Out) du circuit de repérage haute tension (TH).


     
    14. Circuit de protection contre les DES selon la revendication 13, caractérisé en ce que la diode (DP5) comprend :

    un deuxième puits N (NW5), disposé sous la première borne et la deuxième borne ; ou

    un deuxième puits P (PW5), disposé sous la première borne et la deuxième borne.


     
    15. Circuit de protection contre les DES selon la revendication 14, caractérisé en ce que la diode comprend en outre :
    un deuxième puits N profond (DNW5), disposé sous le deuxième puits P.
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description