(19)
(11)EP 3 327 709 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
27.11.2019 Bulletin 2019/48

(21)Application number: 17204289.7

(22)Date of filing:  29.11.2017
(51)International Patent Classification (IPC): 
G09G 3/20(2006.01)
G09G 3/3233(2016.01)
G09G 3/3225(2016.01)
H01L 27/32(2006.01)

(54)

ULTRA HIGH DENSITY TRANSPARENT FLAT PANEL DISPLAY

TRANSPARENTE FLACHBILDSCHIRMANZEIGE MIT ULTRAHOHER DICHTE

ÉCRAN PLAT TRANSPARENT ULTRA-HAUTE DENSITÉ


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 29.11.2016 KR 20160160843

(43)Date of publication of application:
30.05.2018 Bulletin 2018/22

(73)Proprietor: LG Display Co., Ltd.
Seoul, 07336 (KR)

(72)Inventors:
  • HAN, Sungman
    10845 Gyeonggi-do (KR)
  • PARK, Eunji
    10845 Gyeonggi-do (KR)
  • LEE, Kihyung
    10845 Gyeonggi-do (KR)

(74)Representative: Morrall, Jonathan Ian McLachlan 
Kilburn & Strode LLP Lacon London 84 Theobalds Road
London WC1X 8NL
London WC1X 8NL (GB)


(56)References cited: : 
EP-A1- 3 057 085
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    Technical Field



    [0001] The present disclosure relates to an ultra high density transparent flat panel display. Especially, the present disclosure relates to a transparent organic light emitting diode display having ultra high pixel density.

    Description of the Related Art



    [0002] Nowadays, various flat panel displays (or "FPD") are being developed for overcoming many drawbacks of cathode ray tubes (or "CRT") which are heavy and bulky. Flat panel display devices include liquid crystal display devices (or "LCD"), field emission displays (or "FED"), plasma display panels (or "PDP"), electro-luminescence devices (or "EL") and so on.

    [0003] As a self-emitting display device, an electro-luminescence device has the following merits: the response speed is very fast, the brightness is very high and the view angle is large. An electro-luminescence device can be categorized as an inorganic light emitting diode display or an organic light emitting diode display (or "OLED"). Owing to good energy efficiency, lower leakage current and the possibility of representing color and brightness by controlling current, development of OLED displays using organic light emitting diodes is required.

    [0004] FIG. 1 is a diagram illustrating the structure of an organic light emitting diode. As shown in FIG. 1, an organic light emitting diode comprises an organic light emitting material layer, and a cathode and anode facing each other with an organic light emitting material layer therebetween. The organic light emitting material layer comprises a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL and an electron injection layer EIL. The organic light emitting diode radiates light due to the energy released from the exciton formed in an excitation state in which a hole and an electron are recombined in the emission layer EML.

    [0005] The organic light emitting diode radiates light due to the energy released from the exciton formed in an excitation state in which a hole from the anode and an electron from the cathode are recombined in the emission layer EML. The organic light emitting diode display can show video data by controlling the amount (or 'brightness') of the light generated and radiated from the emission layer ELM of the organic light emitting diode as shown in FIG. 1.

    [0006] An OLED using organic light emitting diodes having good energy efficiency can be categorized into passive matrix type organic light emitting diode displays (or PMOLED) and active matrix type organic light emitting diode displays (or AMOLED).

    [0007] The active matrix type organic light emitting diode display (or AMOLED) shows video data by controlling the current applied to an organic light emitting diode using a thin film transistor (or TFT). Hereinafter, referring to FIGs. 2 and 3, an organic light emitting diode display according to the related art will be explained.

    [0008] FIG. 2 is an exemplary circuit diagram illustrating the structure of one pixel in an active matrix organic light emitting diode display (or AMOLED). FIG. 3 is a plan view illustrating the structure of the AMOLED according to the related art. FIG. 4 is a cross sectional view along the cutting line I-I' for illustrating the structure of a bottom emission type AMOLED according to the related art.

    [0009] Referring to FIGs. 2 and 3, the active matrix organic light emitting diode display comprises a switching thin film transistor ST, a driving thin film transistor DT connected to the switching thin film transistor ST, and an organic light emitting diode OLE connected to the driving thin film transistor DT. By depositing a scan line SL, a data line DL and a driving current line VDD on a substrate, a pixel area is defined. As an organic light emitting diode is disposed within the pixel area, it defines an emission area.

    [0010] The switching thin film transistor ST is formed where the scan line SL and the data line DL cross. The switching thin film transistor ST selects the pixel which is connected to the switching thin film transistor ST. The switching thin film transistor ST includes a gate electrode SG branching from the gate line GL, a semiconductor channel layer SA overlapping with the gate electrode SG, a source electrode SS and a drain electrode SD. The driving thin film transistor DT drives an anode electrode ANO of the organic light emitting diode OLE disposed at the pixel selected by the switching thin film transistor ST.

    [0011] The driving thin film transistor DT includes a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a semiconductor channel layer DA, a source electrode DS connected to the driving current line VDD, and a drain electrode DD. The drain electrode DD of the driving thin film transistor DT is connected to the anode electrode ANO of the organic light emitting diode OLE. Between the anode electrode ANO and the cathode electrode CAT, an organic light emitting layer OL is disposed. The base (or low) voltage line VSS is connected to the cathode electrode CAT. A storage capacitor Cst is formed between the gate electrode DG of the driving thin film transistor DT and the driving current line VDD or between the gate electrode DG of the driving thin film transistor DT and the drain electrode DD of the driving thin film transistor DT.

    [0012] Referring to FIG. 4, a bottom emission type organic light emitting diode display will be explained. On the substrate SUB of the active matrix organic light emitting diode display, the gate electrodes SG and DG of the switching thin film transistor ST and the driving thin film transistor DT, respectively are formed. On the gate electrodes SG and DG, the gate insulator GI is deposited. On the gate insulator GI overlapping with the gate electrodes SG and DG, the semiconductor layers SA and DA are formed, respectively. On the semiconductor layer SA and DA, the source electrode SS and DS and the drain electrode SD and DD facing and separating from each other are formed. The drain electrode SD of the switching thin film transistor ST is connected to the gate electrode DG of the driving thin film transistor DT via the gate contact hole GH penetrating the gate insulator GI. The passivation layer PAS is deposited on the substrate SUB having the switching thin film transistor ST and the driving thin film transistor DT.

    [0013] The upper surface of the substrate having these thin film transistors ST and DT is not in even and/or smooth condition, but in uneven and/or rough condition having many steps. In order to get the best light emitting efficiency, the organic light emitting layer OL should be deposited on an even or planar surface. So, to make the upper surface planar and even, an over coat layer OC is deposited on the whole surface of the substrate SUB.

    [0014] Then, on the over coat layer OC, the anode electrode ANO of the organic light emitting diode OLE is formed. Here, the anode electrode ANO is connected to the drain electrode DD of the driving thin film transistor DT through the pixel contact hole PH penetrating the over coat layer OC and the passivation layer PAS.

    [0015] On the substrate SUB having the anode electrode ANO, a bank BN is formed over the area having the switching thin film transistor ST, the driving thin film transistor DT and the various lines DL, SL and VDD, for defining the light emitting area. The exposed portion of the anode electrode ANO by the bank BN would be the light emitting area. The organic light emitting layer OL is deposited on the anode electrode ANO exposed by the bank BN. On the organic light emitting layer OL, a cathode electrode CAT is deposited.

    [0016] A spacer (not shown) is disposed on the substrate SUB having the cathode electrode CAT. It is preferable that the spacer is disposed on the bank BN, non-emission area. With the spacer, an en-cap may be joined on the lower substrate SUB. For attaching the en-cap and the lower substrate SUB, an adhesive layer or adhesion material (not shown) would be deposited there-between.

    [0017] For a bottom emission type organic light emitting diode display, the light emitted from the organic light emitting layer OL would be radiated to the lower substrate SUB. Therefore, it is preferable that a color filter CF is disposed between the overcoat layer OC and the passivation layer PAS and the anode electrode ANO include a transparent conductive material. Further, the cathode electrode CAT preferably includes a metal material such as a metal having high reflectivity for reflecting light from the organic light emitting layer OL to the bottom side. In addition, the organic light emitting layer OL and the cathode electrode CAT would be deposited to cover the whole surface of the substrate.

    [0018] The cathode electrode CAT is supplied with the reference voltage of the organic light emitting diode OLE. For ensuring stable operation of the organic light emitting diode OLE, the reference voltage should be kept stable without flickering. To do so, it is preferable that the cathode electrode CAT comprises a low resistance metal material such as a metal and is deposited over the whole surface of the substrate SUB.

    [0019] When an organic light emitting diode display according to the related art is used for a long time, video quality may degrade due to a change of the electric characteristics of the pixels. Compensation elements for measuring these defects detect changes in electric characteristics.

    [0020] When these compensation elements or circuits are installed into the pixel area, they may cause a reduction in the aperture ratio, which is the ratio of the emission area to the pixel area. For ultra-high resolution displays, including UHD or 4K displays, the pixel area includes the switching thin film transistor, the driving thin film transistor and the compensation thin film transistor and so the aperture ratio is significantly reduced. A new structure of an organic light emitting diode display which ensures a high aperture ratio with ultra high-density resolution is therefore required.

    [0021] In addition, an organic light emitting diode display may be applied to specific displays with unique functions such as transparent displays in which images and/or information are effectively superimposed onto objects behind the display. However, special use displays should have more unique features than general purpose organic light emitting diode displays for realizing their specific purposes. For example, a transparent organic light emitting diode display having an ultra high pixel density is needed.

    SUMMARY



    [0022] In order to overcome the above-mentioned drawbacks, a purpose of the present disclosure is to provide an ultra-high pixel density transparent organic light emitting diode display. Another purpose of the present disclosure is to provide an ultra-high pixel density transparent organic light emitting diode display having a high aperture ratio. Still another purpose of the present disclosure is to provide a transparent organic light emitting diode display providing better video quality by minimizing the effects between lines even though the gaps between lines are smaller.

    [0023] In order to accomplish the above, the present disclosure provides a transparent flat panel display according to the claims.

    [0024] The organic light emitting diode display according to the present disclosure includes a compensation thin film transistor for controlling the conditions of the driving thin film transistor and/or the organic light emitting diode by detecting the degradation of the pixel. Under demanding conditions causing the deterioration of the pixel, the video quality can be kept in superior condition. The transparent organic light emitting diode display according to the present disclosure relates to the top emission type organic light emitting diode display in which the emission area is defined as occupying the majorityof the pixel area. The transparent area is disposed as being separated from the pixel area. Therefore, for ultra high pixel density, the emission area can be maximized so that a high aperture ratio can be obtained. In addition, as the gaps between lines are smaller as the pixel density increases, the sensing line can be disposed far away from the data lines. As a result, the sensing signal is not affected by the data voltage which is frequently changed and superior video quality can be ensured.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0025] The accompanying drawings, which are included to provide further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain the principles of the disclosure.

    [0026] In the drawings:

    FIG. 1 is a diagram illustrating the structure of an organic light emitting diode according to the related art.

    FIG. 2 is an exemplary circuit diagram illustrating the structure of one pixel in an active matrix organic light emitting diode display (or AMOLED) according to the related art.

    FIG. 3 is a plan view illustrating the structure of one pixel in an AMOLED according to the related art.

    FIG. 4 is a cross sectional view along line I-I' for illustrating the structure of a bottom emission type AMOLED according to the related art.

    FIG. 5 is an equivalent circuit diagram illustrating the structure of one pixel in an organic light emitting diode display having a compensation element according to the present disclosure.

    FIG. 6 is a plan view illustrating thr structure of a transparent organic light emitting diode display having a compensation element.

    FIG. 7 is a plan view illustrating the structure of a transparent organic light emitting diode display according to the embodiment of the present disclosure.


    DETAILED DESCRIPTION



    [0027] Referring to the attached figures, preferred embodiments of the present disclosure will be explained. Like reference numerals designate like elements throughout the detailed description. However, the present disclosure is not restricted by these embodiments and can be applied to various changes or modifications without changing the technical scope. In the following embodiments, the names of the elements are selected for ease of explanation such that they may be different from actual names.

    [0028] Next, referring to FIG. 5, part of the present disclosure will be explained. FIG. 5 is an equivalent circuit diagram illustrating the structure of one pixel in an organic light emitting diode display having a compensation element according to the present disclosure.

    [0029] Referring to FIG. 5, one pixel of the organic light emitting diode display comprises a switching thin film transistor ST, a driving thin film transistor DT, a storage capacitor Cst, a compensation element and an organic light emitting diode OLE. The compensation element may be configured in various ways. Here, the case in which the compensation element includes a sensing thin film transistor ET and a sensing line REF will be explained.

    [0030] Responding to the scan signal supplied from the scan line SL, the switching thin film transistor ST works as a switching operation for storing the data signal from the data line DL in the storage capacitor Cst as the data voltage. According to the data voltage in the storage capacitor Cst, the driving thin film transistor DT supplies the driving current between the driving current line VDD (supplying the variable high level voltage) and the base voltage line VSS (supplying the constant low level voltage). The organic light emitting diode OLE generates light according to the driving current supplied by the driving thin film transistor DT.

    [0031] The sensing thin film transistor ET is an additional element disposed within the pixel area for compensating for the threshold voltage of the driving thin film transistor DT. The sensing thin film transistor ET is connected between the drain electrode of the driving thin film transistor DT and the anode electrode (or the sensing node) of the organic light emitting diode OLE. The sensing thin film transistor ET supplies the initial voltage (or the sensing voltage) from the sensing line REF to the sensing node or detects (or senses) the voltage or current at the sensing node.

    [0032] The switching thin film transistor ST includes a source electrode connected to the data line DL, and a drain electrode connected to the gate electrode of the driving thin film transistor DT. The driving thin film transistor DT includes a source electrode connected to the driving current line VDD, and a drain electrode connected to anode electrode of the organic light emitting diode OLE. The storage capacitor Cst includes a first electrode connected to the gate electrode of the driving thin film transistor DT, and a second electrode connected to the anode electrode of the organic light emitting diode OLE.

    [0033] The organic light emitting diode OLE includes an anode electrode connected to the drain electrode of the driving thin film transistor DT, and a cathode electrode connected to the base (or low) voltage line VSS. The sensing transistor ET includes a source electrode connected to the sensing line REF, and a drain electrode connected to the sensing node (the anode electrode of the organic light emitting diode OLE).

    [0034] The operating timing of the sensing thin film transistor ET may be related to that of the switching thin film transistor ST according to a compensation algorithm. For example, as shown in FIG. 5, the gate electrodes of the switching thin film transistor ST and the sensing thin film transistor ET may be connected to the scan line SL commonly. Otherwise, the gate electrode of the switching thin film transistor ST is connected to one scan line SL and the gate electrode of the sensing thin film transistor ET is connected to the other scan line (not shown).

    [0035] According to the sensing results, the digital type data signal, the analog type data signal or gamma signal may be compensated. The compensation elements for generating the compensating signal (or the compensating voltage) based on the sensing results may be configured as the internal circuits embedded into the data driver or timing controller or the external circuits.

    [0036] FIG. 5 shows a pixel with a 3T1C structure (three thin film transistor and one capacitor) including a switching thin film transistor ST, driving thin film transistor DT, sensing thin film transistor ET, storage capacitor Cst and organic light emitting diode OLE. Otherwise, the pixel may include additional compensation elements as seen in, for example, 3T2C, 4T2C, 5T1C, 6T2C etc. structures.

    [0037] Hereinafter, the structural features of the transparent organic light emitting diode display configured with the circuit diagram shown in FIG. 5 according to the present disclosure will be explained. In accordance with the actual structure of the pixel, the aperture ratio may be different. As well as the resolution, the aperture ratio is very important for deciding the quality of the display. As the resolution of the display is increased, the unit pixel area gets smaller for a given display size. The size of the thin film transistors and the width of the lines cannot be made smaller indefinitely. If the pixel area is smaller, the ratio of the emission area to the pixel area is also smaller.

    [0038] Further, when the compensation element is included in the pixel area, the aperture ratio, the ratio of the emission area to the pixel area, is even smaller. In addition, as the number of pixels increases, the probability of pixels having defects also increases. Pixels with defects are the main cause of deterioration of video quality. Therefore, it is preferable that pixels with defects are darkened or turn off so that normal pixels are not affected by the defects. To darken or turn off defective pixels, it is preferable to cut the connecting part between the thin film transistor and the organic light emitting diode. Hereinafter, various structures of an organic light emitting diode display according to the present disclosure will be explained.

    [0039] FIG. 6 is a plan view illustrating a structure of a transparent organic light emitting diode display having a compensation element.

    [0040] The transparent organic light emitting diode display comprises a sensing line REF, a data line DL, a driving current line VDD, a horizontal sensing line REFh, a horizontal current line VDDh and a scan line SL on a substrate SUB. These lines define a pixel area. In detail, a unit pixel area is defined as an area surrounded by two neighboring horizontal sensing lines REFh, one data line DL and one driving current line VDD. These lines may be made of an opaque metal material such as a metal.

    [0041] A transparent organic light emitting diode display comprises a transparent (or transmissive) area TRA and an emission area LEA. The transparent area TRA is an area through which the background behind the display is transmitted. That is to say that objects behind the display may be seen through the transparent area TRA. For example, it is an area that transparently transmits the background views beyond the display, like a glass window, to an observer located in front of the display. The emission area LEA is an area for representing the image information or data provided by the display. For a transparent organic light emitting diode display, the emission area includes an organic light emitting diode.

    [0042] The scan line SL, the horizontal sensing line REFh and the horizontal current line VDDh run in a horizontal direction on the substrate SUB. The data line DL, the driving current line VDD and the sensing line REF run in a vertical direction on the substrate SUB. The horizontal sensing line REFh is connected to the sensing line REF via a sensing contact hole RH. The horizontal current line VDDh is connected to the driving current line VDD via the current contact hole VH.

    [0043] Between two neighboring horizontal sensing lines REFh, the horizontal current line VDDh and the scan line SL are disposed. The area between the upper horizontal sensing line REFh and the horizontal current line VDDh is defined as an image area having the transparent area TRA and the emission area LEA. The area between the horizontal current line VDDh and the lower horizontal sensing line REFh is defined as the non-emission area. In the emission area LEA, an organic light emitting diode OLE is disposed. In the non-emission area, the thin film transistors ST, DT and ET and the storage capacitor Cst are disposed.

    [0044] The switching thin film transistor ST includes a switching source electrode SS connected to the data line DL, a switching gate electrode SG defined at a part of the scan line SL, a switching semiconductor layer SA and a switching drain electrode SD. A channel area is defined at the overlapped area of the switching semiconductor layer SA with the switching gate electrode SG. As the switching semiconductor layer SA crosses the scan line SL, for example from the lower side to the upper side of the scan line as illustrated in FIG. 6, the switching thin film transistor ST is formed.

    [0045] The sensing thin film transistor ET includes a sensing source electrode ES connected to the horizontal sensing line REFh, a sensing gate electrode EG defined at a part of the scan line SL, a sensing semiconductor layer EA and a sensing drain electrode ED. A channel area is defined at the overlapped area of the sensing semiconductor layer EA with the sensing gate electrode EG. As the sensing semiconductor layer EA crosses the scan line SL, for example from the lower side to the upper side of the scan line as illustrated in FIG. 6, the sensing thin film transistor ET is formed.

    [0046] The driving thin film transistor DT includes a driving source electrode DS defined at a part of the horizontal current line VDDh, a driving gate electrode DG connected to the switching drain electrode SD, a driving semiconductor layer DA and a driving drain electrode DD. A channel area is defined at the overlapped area of the driving semiconductor layer DA with the driving gate electrode DG. The driving semiconductor layer DA crosses the driving gate electrode DG between the horizontal current line VDDh and the scan line SL. The driving drain electrode DD is connected to a portion of the driving semiconductor layer DA and a portion of the sensing semiconductor layer EA.

    [0047] The storage capacitor Cst includes a first electrode and a second electrode. The first electrode comprises an expanded portion of the switching drain electrode SD. The second electrode comprises an expanded portion of the driving semiconductor layer DA to the scan line SL over the driving gate electrode DG. The driving thin film transistor DT and the storage capacitor Cst are disposed between the horizontal current line VDDh and the scan line SL. The driving elements are disposed between the horizontal current line VDDh and the horizontal sensing line REFh. This area is defined as the non-emission area.

    [0048] The anode electrode ANO of the organic light emitting diode OLE is connected to the driving drain electrode DG through the pixel contact hole PH. The anode electrode ANO covers the emission area LEA in the image area but doesn't cover the transparent area TRA. The open area of the bank BA is exposes a maximum area of the anode electrode ANO within the emission area LEA.

    [0049] To ensure the maximum possible area, the anode electrode ANO occupies the greatest area of the emission area LEA and some portions extend to the non-emission area. Specifically, it is preferable that the anode electrode ANO extends to the driving drain electrode DG. Further, the anode electrode ANO may overlap with the storage capacitor Cst. As it may be difficult to form the second electrode of the storage capacitor Cst from the driving semiconductor layer DA, the second electrode of the storage capacitor Cst may be formed by expanding the anode electrode ANO to overlap with the first electrode of the storage capacitor Cst.

    [0050] Most parts of the anode electrode ANO are exposed by the bank BN. The organic light emitting diode OLE is formed by stacking the organic light emitting layer and the cathode electrode on the bank BN. It is preferable that the organic light emitting diode OLE is formed to have the maximum possible emission area within the pixel area. In addition, at the transparent area TRA, it is preferable that the organic light emitting layer OL and the cathode electrode CAT are not disposed. However, when the cathode electrode is made of a transparent conductive material, the cathode electrode CAT may be disposed in the transparent area TRA.

    [0051] The transparent organic light emitting diode display with sensing thin film transistor ET has a very complex structure. Therefore, the ratio of the image area within a pixel area is very low. The image area is divided into two areas: a transparent area TRA and an emission area LEA. Therefore, the aperture ratio for representing a video image is much lower than without a sensing thin film transistor. Therefore, a new structure is needed for a transparent organic light emitting diode display having an ultra high aperture ratio.

    [0052] Further, the organic light emitting diode display shown in FIG. 6 has a sensing line REF for the compensation elements. Specifically, the sensing line REF is disposed as close to or adjacent to the data lines DL. The data lines DL are for providing data voltages which are frequently changed or varied according to the video image data. Therefore, the sensing line REF may be affected by these frequently varying voltages. A structure in which the sensing line REF is electrically isolated or insulated from the data lines DL is therefore desirable.

    [0053] In realizing an ultra-high density display, the size of the pixel area gets smaller and gaps between lines get smaller. Consequently, for an ultra-high pixel density transparent organic light emitting diode display, the structure for electrically isolating or insulating the sensing line REF from the data lines DL is even more important.

    <First Embodiment>



    [0054] Hereinafter, referring to FIG. 7, a first embodiment will be explained. FIG. 7 is a plan view illustrating the structure of a transparent organic light emitting diode display according to the first embodiment of the present disclosure. The first embodiment provides a structure in which the gap between a sensing line and a data line is minimized to realize an ultra-high pixel density transparent organic light emitting diode display.

    [0055] Referring to FIG. 7, a transparent organic light emitting diode display according to the first embodiment of the present disclosure comprises a driving current line VDD, a first data line DL1, a second data line DL2, a third data line DL3, a fourth data line DL4, a base (or low) voltage line VSS and a sensing line REF, which run in a vertical direction on a substrate, for example as illustrated in FIG. 7. The transparent organic light emitting diode display further comprises a first scan line SL1, a second scan line SL2 and a horizontal sensing line REFh which run in a horizontal direction on the substrate. These lines may be made of an opaque metal material such as a metal.

    [0056] The first data line DL1 to the fourth data line DL4 are disposed between the driving current line VDD and the base (or low) voltage line VSS. The sensing line REF is disposed between the base voltage line VSS and a next driving current line VDD.

    [0057] Between the driving current line VDD and the base voltage line VSS, the emission area LEA is disposed. Between the base voltage line VSS and the sensing line REF, the transparent area TRA is disposed. In another case, the base voltage line VSS is not disposed on the substrate. In this instance, the emission area LEA may be disposed between the driving current line VDD and the fourth (last) data line DL4. The transparent area TRA may be disposed between the fourth data line DL4 and the sensing line REF.

    [0058] The first scan line SL1 and the second scan line SL2 cross the driving current line VDD, the data lines DL1 to DL4 and the sensing line REF. The first scan line SL1 and the second scan line SL2 are disposed as close to or adjacent to each other. Between the first scan line SL1 and the second scan line SL2, the horizontal sensing line REFh is disposed.

    [0059] The transparent organic light emitting diode display according to the first embodiment of the present disclosure includes a unit pixel area having four sub pixel areas and two transparent areas. The unit pixel area is disposed between two neighboring sensing lines REF. Between the two neighboring sensing lines REF, the driving current line VDD, the four data lines DL1 to DL4 and the base voltage line VSS are disposed.

    [0060] Between the first data line DL1 and the second data line DL2, a first pixel area P1 and a second pixel area P2 are disposed. Between the third data line DL3 and the fourth data line DL4, a third pixel area P3 and a fourth pixel area P4 are disposed. The first pixel area P1 is defined as being surrounded by the first data line DL1, the second data line DL2, the first scan line SL1 and the horizontal driving line VDDh. The second pixel area P2 is defined as being surrounded by the first data line DL1, the second data line DL2, the second scan line SL2 and the horizontal driving line VDDh. The third pixel area P3 is defined as being surrounded by the third data line DL3, the fourth data line DL4, the first scan line SL1 and the horizontal driving line VDDh. The fourth pixel area P4 is defined as being surrounded by the third data line DL3, the fourth data line DL4, the second scan line SL2 and the horizontal driving line VDDh.

    [0061] A red sub pixel R may be allocated as the first pixel area P1, a green sub pixel G may be allocated as the second pixel area P2, a white sub pixel W may be allocated as the third pixel area P3 and a blue sub pixel B may be allocated as the fourth pixel area P4. Here, the case in which one unit pixel includes one red sub pixel R, one white sub pixel W, one green sub pixel G and one blue sub pixel B will be explained. However, one unit pixel is not restricted in this manner; various sub pixel color arrangements may be used.

    [0062] At each pixel area P1 to P4, the thin film transistors ST, DT and ET, the storage capacitor STG and the organic light emitting diode OLE are disposed. The transparent organic light emitting diode display according to the first embodiment is of the top emission type so that the thin film transistors ST, DT and ET are disposed under the organic light emitting diode OLE. The organic light emitting diode OLE includes an anode electrode ANO, an organic light emitting layer and a cathode electrode. The anode electrode is connected to the driving thin film transistor DT and includes an opaque reflective metal material such as a metal. The organic light layer is deposited on the anode electrode ANO. The cathode electrode includes a transparent conductive material and is deposited on the organic emitting layer. In order to ensure the emission area LEA is maximized, some of the lines may overlap with the organic light emitting diode OLE.

    [0063] Here, the first pixel area P1 will be explaied. The switching thin film transistor ST includes a switching source electrode SS connected to the first data line DL1, a switching gate electrode SG defined at a part of the first scan line SL1, a switching semiconductor layer SA and a switching drain electrode SD. The area of the switching semiconductor layer SA overlapping with the switching gate electrode SG is defined as the channel area. As the switching semiconductor layer SA crosses the first scan line SL1, for example from the lower side to the upper side of the first scan line SL1 as illustrated, the switching thin film transistor ST is formed.

    [0064] The sensing thin film transistor ET includes a sensing source electrode ES connected to the horizontal sensing line REFh, a sensing gate electrode EG defined at another part of the first scan line SL1, a sensing semiconductor layer EA and a sensing drain electrode ED. A channel area is defined at the area of the sensing semiconductor layer EA overlapping with the sensing gate electrode EG. As the sensing semiconductor layer EA crosses the first scan line SL1, for example from the lower side to the upper side of the first scan line SL1 as illustrated, the sensing thin film transistor ET is formed.

    [0065] The driving thin film transistor DT includes a driving source electrode DS defined at a part of the horizontal current line VDDh branched from the driving current line VDD, a driving gate electrode DG connected to the switching drain electrode SD, a driving semiconductor layer DA and a driving drain electrode DD. A channel area is defined at the area of the driving semiconductor layer DA overlapping with the driving gate electrode DG. The driving semiconductor layer DA crosses the driving gate electrode DG between the horizontal current line VDDh and the first scan line SL1. The driving drain electrode DD is connected to the one portion of the driving semiconductor layer DA and one portion of the sensing semiconductor layer EA.

    [0066] The storage capacitor Cst includes a first electrode and a second electrode. The first electrode comprises an expanded portion of the switching gate electrode SG. The second electrode comprises an expanded portion of the driving gate electrode DG. The first pixel area P1, including the thin film transistors ST, DT and ET and the storage capacitor Cst, is disposed between the first scan line SL1 and the horizontal current line VDDh.

    [0067] An anode electrode ANO is disposed at the first pixel area P1. Even though it is not shown in the figure, a planar layer is deposited on the surface of the substrate having the thin film transistors ST, DT and ET and the storage capacitor Cst, and then the anode electrode ANO is formed on the planar layer. The anode electrode ANO is connected to the driving drain electrode DD of the driving thin film transistor DT. The anode electrode ANO may have a rectangular shape covering the first pixel area P1.

    [0068] On the anode electrode ANO, a bank BN is formed for defining the emission area LEA. The open area formed at the bank BN defines the emission area LEA of the anode electrode ANO. On the emission area LEA, an organic light emitting layer is deposited. On the organic light emitting layer, a cathode electrode covering the whole surface of the substrate is deposited. At the emission area LEA, the organic light emitting diode OLE is formed, as the anode electrode ANO, the organic light emitting layer and the cathode electrode are stacked sequentially.

    [0069] In the transparent organic light emitting diode display according to the first embodiment, most of all areas of the pixel area would be defined as the emission area LEA. The transparent area TRA is disposed as being separated from the pixel area which is the emission area LEA. In detail, two transparent areas TRA are disposed next to the four pixel areas P1 to P4, as shown in FIG. 7. The emission area may comprise first, second, third and fourth emission areas. The four pixel areas P1, P2, P3 and P4 may comprise the first, second, third and fourth emission areas, respectively.

    [0070] In FIG. 7, the sensing line REF is disposed as being apart from the data line DL1 to DL4. For example, based on the driving current line VDD, the data lines DL1 to DL4 are disposed at one side from the driving current line VDD, and the sensing line REF is disposed at another side from the driving current line VDD. The sensing line REF is closer to the driving current line VDD than the data lines DL1 to DL4. The driving current line VDD supplies a constant voltage, so that the voltage of the driving current line VDD is not affected by the sensing line REF. Further, the transparent area TRA is disposed between the sensing line REF and the data lines DL1 to DL4,. Therefore, the sensing line REF is not affected by the data lines DL1 to DL4.

    [0071] The transparent organic light emitting diode display according to the first embodiment of the present disclosure provides a structure in which the sensing line REF is disposed as being apart from the data lines DL1 to DL4, even though the gaps between lines are much closer, to realize an ultra-high density pixel structure. As a result, the sensing signal is not affected by the data voltages which are frequently changed, and superior video quality can be ensured.

    [0072] While the embodiments of the present disclosure have been described in detail with reference to the drawings, it will be understood by those skilled in the art that the disclosure can be implemented in other specific forms without changing the essential features of the disclosure. Therefore, it should be noted that the forgoing embodiment are merely illustrative in all aspects and are not to be construed as limiting the disclosure. The scope of the disclosure is defined by the appended claims rather than the detailed description of the disclosure.


    Claims

    1. A transparent flat panel display device comprising:

    a substrate (SUB),

    a plurality of data lines (DL1-DL4) arranged in a first direction on the substrate, a plurality of scan lines (SL1, SL2) arranged in a second direction on the substrate, and a plurality of pixels at the intersection of the data lines and scan lines;

    a plurality of sensing lines (REF) arranged in the first direction on the substrate; wherein each pixel area, comprising four sub-pixel areas (P1-P4) and two transparent areas (TRA), is disposed between two neighbouring sensing lines (REF);

    wherein each pixel comprises a switching thin film transistor (ST), a driving thin film transistor (DT), a storage capacitor (Cst), a compensation element and an organic light emitting diode (OLE), the compensation element comprising a sensing thin film transistor (ET);

    a driving current line (VDD) arranged in the first direction and connected to each driving thin film transistor (DT), each data line (DL) connected to a switching thin film transistor (ST) of a respective pixel;

    each sensing line (REF) being connected to a sensing thin film transistor (ET) of a respective pixel;

    a plurality of second sensing lines (REFh) running in the second direction on the substrate, the first direction being perpendicular to the second direction, the second sensing lines (REFh) being connected to the first sensing line (REF) via a sensing contact hole (RH);

    wherein each pixel area comprises a first, second, third and fourth emission area corresponding respectively to the four sub-pixel areas (P1-P4);

    wherein the two transparent areas (TRA) of each pixel are arranged in the second direction and are both disposed between the data lines (DL) connected to the pixel and the neighbouring sensing line (REF) on one side of the pixel area;

    a constant voltage supply means configured to supply a constant voltage to the driving current line (VDD);

    wherein the driving current line (VDD) is disposed between the data lines (DL) connected to the pixel and the neighbouring sensing line (REF) on the other side of the pixel area.


     
    2. The device according to claim 1, wherein the data lines include a first data line (DL1), a second data line (DL2), a third data line (DL3) and a fourth data line (DL4),
    wherein the first emission area and the second emission area are disposed between the first data line and the second data line, and
    wherein the third emission area and the fourth emission area are disposed between the third data line and the fourth data line.
     
    3. The device according to the claim 1 or 2, further comprising:
    a base voltage line (VSS) disposed between the one or more data lines and the transparent area.
     
    4. The device according to any preceding claim, wherein the low voltage line includes an opaque metal material and is connected to a cathode electrode (CAT).
     
    5. The device according to the claim 2 or any of claims 3 to 4 when dependent on claim 2,
    wherein the scan lines includes a first scan line (SL1) and a second scan line (SL2) disposed as being close to each other, and
    the second sensing line is branched from the sensing line and disposed between the first scan line and the second scan line.
     
    6. The device according to the claim 5, wherein the first emission area is disposed at a first sub-pixel area (P1) defined by the first data line, the second data line and the first scan line, wherein the second emission area is disposed at a second sub-pixel area (P2) defined by the first data line, the second data line and the second scan line,
    wherein the third emission area is disposed at a third sub-pixel area (P3) defined by the third data line, the fourth data line and the first scan line, and
    wherein the fourth emission area is disposed at a fourth sub-pixel area (P4) defined by the third data line, the fourth data line and the second scan line.
     
    7. The device according to any preceding claim, wherein the switching thin film transistor, the driving thin film transistor, the sensing thin film transistor and the storage capacitor are disposed under the organic light emitting diode.
     
    8. The device according to claim 7, wherein the organic light emitting diode includes:

    an anode electrode (ANO) connected to the driving thin film transistor and including an opaque reflective metal material;

    an organic light emitting layer (OL) deposited on the anode electrode; and

    a cathode electrode (CAT) including a transparent conductive material and deposited on the organic light emitting layer.


     


    Ansprüche

    1. Transparente Flachbildschirmvorrichtung, die Folgendes umfasst:

    ein Substrat (SUB),

    eine Vielzahl von Datenleitungen (DL1-DL4), die in einer ersten Richtung auf dem Substrat angeordnet sind, eine Vielzahl von Abtastleitungen (SL1, SL2), die in einer zweiten Richtung auf dem Substrat angeordnet sind, und eine Vielzahl von Pixeln an dem Schnittpunkt der Datenleitungen und Abtastleitungen;

    eine Vielzahl von Erfassungsleitungen (REF), die in der ersten Richtung auf dem Substrat angeordnet sind; wobei jeder Pixelbereich, der vier Subpixelbereiche (P1-P4) und zwei transparente Bereiche (TRA) umfasst, zwischen zwei benachbarten Erfassungsleitungen (REF) angeordnet ist;

    wobei jedes Pixel einen schaltenden Dünnfilmtransistor (ST), einen antreibenden Dünnfilmtransistor (DT), einen Speicherkondensator (Cst), ein Kompensationselement und eine organische Leuchtdiode (OLE) aufweist, wobei das Kompensationselement einen erfassenden Dünnfilmtransistor (ET) aufweist;

    eine Antriebsstromleitung (VDD), die in der ersten Richtung angeordnet und mit jedem antreibenden Dünnfilmtransistor (DT) verbunden ist, wobei jede Datenleitung (DL) mit einem schaltenden Dünnfilmtransistor (ST) eines entsprechenden Pixels verbunden ist;

    jede Erfassungsleitung (REF) mit einem erfassenden Dünnfilmtransistor (ET) eines entsprechenden Pixels verbunden ist; eine Vielzahl von zweiten Erfassungsleitungen (REFh) in der zweiten Richtung auf dem Substrat verlaufen, wobei die erste Richtung senkrecht zu der zweiten Richtung ist und die zweiten Erfassungsleitungen (REFh) über ein erfassendes Kontaktloch (RH) mit der ersten Erfassungsleitung (REF) verbunden sind;

    wobei jeder Pixelbereich einen ersten, zweiten, dritten und vierten Emissionsbereich aufweist, die jeweils den vier Subpixelbereichen (P1-P4) entsprechen;

    wobei die zwei transparenten Bereiche (TRA) jedes Pixels in der zweiten Richtung ausgerichtet und beide zwischen den Datenleitungen (DL) angeordnet sind, die mit dem Pixel und der benachbarten Erfassungsleitung (REF) auf einer Seite des Pixelbereichs verbunden sind;

    eine Konstantspannungs-Versorgungseinrichtung, die dazu ausgelegt ist, die Antriebsstromleitung (VDD) mit einer Konstantspannung zu versorgen;

    wobei die Antriebsstromleitung (VDD) zwischen den Datenleitungen (DL), die mit dem Pixel verbunden sind, und der benachbarten Erfassungsleitung (REF) auf der anderen Seite des Pixelbereichs angeordnet ist.


     
    2. Vorrichtung gemäß Anspruch 1, wobei die Datenleitungen eine erste Datenleitung (DL1), eine zweite Datenleitung (DL2), eine dritte Datenleitung (DL3) und eine vierte Datenleitung (DL4) einschließen,
    wobei der erste Emissionsbereich und der zweite Emissionsbereich zwischen der ersten Datenleitung und der zweiten Datenleitung angeordnet sind, und
    wobei der dritte Emissionsbereich und der vierte Emissionsbereich zwischen der dritten Datenleitung und der vierten Datenleitung angeordnet sind.
     
    3. Vorrichtung gemäß Anspruch 1 oder 2, die ferner Folgendes umfasst:
    eine Basisspannungsleitung (VSS), die zwischen der einen oder den mehreren Datenleitungen und dem transparenten Bereich angeordnet ist.
     
    4. Vorrichtung gemäß einem der vorhergehenden Ansprüche, wobei die Niederspannungsleitung ein undurchsichtiges Metallmaterial enthält und mit einer Kathodenelektrode (CAT) verbunden ist.
     
    5. Vorrichtung gemäß Anspruch 2 oder einem der Ansprüche 3 bis 4, wenn von Anspruch 2 abhängig,
    wobei die Abtastleitungen eine erste Abtastleitung (SL1) und eine zweite Abtastleitung (SL2) einschließen, die als nah beieinander angeordnet sind, und
    die zweite Erfassungsleitung von der Erfassungsleitung abzweigt und zwischen der ersten Abtastleitung und der zweiten Abtastleitung angeordnet ist.
     
    6. Vorrichtung gemäß Anspruch 5, wobei der erste Emissionsbereich an einem ersten Subpixelbereich (P1) angeordnet ist, der durch die erste Datenleitung, die zweite Datenleitung und die erste Abtastleitung definiert wird,
    wobei der zweite Emissionsbereich an einem zweiten Subpixelbereich (P2) angeordnet ist, der durch die erste Datenleitung, die zweite Datenleitung und die zweite Abtastleitung definiert wird,
    wobei der dritte Emissionsbereich an einem dritten Subpixelbereich (P3) angeordnet ist, der durch die dritte Datenleitung, die vierte Datenleitung und die erste Abtastleitung definiert wird, und
    wobei der vierte Emissionsbereich an einem vierten Subpixelbereich (P4) angeordnet ist, der durch die dritte Datenleitung, die vierte Datenleitung und die zweite Abtastleitung definiert wird.
     
    7. Vorrichtung gemäß einem der vorhergehenden Ansprüche, wobei der schaltende Dünnfilmtransistor, der antreibende Dünnfilmtransistor, der erfassende Dünnfilmtransistor und der Speicherkondensator unter der organischen Leuchtdiode angeordnet sind.
     
    8. Vorrichtung gemäß Anspruch 7, wobei die organische Leuchtdiode Folgendes einschließt:

    eine Anodenelektrode (ANO), die mit dem antreibenden Dünnfilmtransistor verbunden ist und ein undurchsichtiges reflektierendes Metallmaterial enthält;

    eine organische lichtemittierende Schicht (OL), die auf die Anodenelektrode aufgebracht ist; und

    eine Kathodenelektrode (CAT), die ein transparentes leitfähiges Material aufweist und auf die organische lichtemittierende Schicht aufgebracht ist.


     


    Revendications

    1. Dispositif d'affichage à panneau plat transparent comprenant :

    un substrat (SUB) ;

    une pluralité de lignes de données (DL1-DL4) agencées dans une première direction sur le substrat, une pluralité de lignes de balayage (SL1, SL2) agencées dans une deuxième direction sur le substrat, et une pluralité de pixels à l'intersection des lignes de données et des lignes de balayage ;

    une pluralité de lignes de détection (REF) agencées dans la première direction sur le substrat ; chaque zone de pixel, comprenant quatre sous-zones de pixel (P1-P4) et deux zones transparentes (TRA), étant disposée entre deux lignes de détection (REF) voisines ;

    chaque pixel comprenant un transistor en couche mince de commutation (ST), un transistor en couche mince d'excitation (DT), un condensateur de stockage (Cst), un élément de compensation et une diode électroluminescente organique (OLE), l'élément de compensation comprenant un transistor en couche mince de détection (ET) ;

    une ligne de courant d'excitation (VDD) étant agencée dans la première direction et raccordée à chaque transistor en couche mince d'excitation (DT), chaque ligne de données (DL) raccordée à un transistor en couche mince de commutation (ST) d'un pixel respectif ;

    chaque ligne de détection (REF) étant raccordée à un transistor en couche mince de détection (ET) d'un pixel respectif ;

    une pluralité de deuxièmes lignes de détection (REFh) s'étendant dans la deuxième direction sur le substrat, la première direction étant perpendiculaire à la deuxième direction, les deuxièmes lignes de détection (REFh) étant raccordées à la première ligne de détection (REF) par le biais d'un trou de contact de détection (RH) ;

    chaque zone de pixel comprenant une première, une deuxième, une troisième et une quatrième zone d'émission correspondant respectivement aux quatre sous-zones de pixel (P1-P4) ;

    les deux zones transparentes (TRA) de chaque pixel étant agencées dans la deuxième direction et étant toutes deux disposées entre les lignes de données (DL) raccordées au pixel et la ligne de détection (REF) voisine sur un côté de la zone de pixel ;

    un moyen de fourniture de tension constante configuré pour fournir une tension constante à la ligne de courant d'excitation (VDD) ;

    la ligne de courant d'excitation (VDD) étant disposée entre les lignes de données (DL) raccordées au pixel et la ligne de détection (REF) voisine sur l'autre côté de la zone de pixel.


     
    2. Dispositif selon la revendication 1, dans lequel les lignes de données comportent une première ligne de données (DL1), une deuxième ligne de données (DL2), une troisième ligne de données (DL3) et une quatrième ligne de données (DL4),
    dans lequel la première zone d'émission et la deuxième zone d'émission sont disposées entre la première ligne de données et la deuxième ligne de données, et
    dans lequel la troisième zone d'émission et la quatrième zone d'émission sont disposées entre la troisième ligne de données et la quatrième ligne de données.
     
    3. Dispositif selon la revendication 1 ou 2, comprenant en outre :
    une ligne de tension de base (VSS) disposée entre la ou les lignes de données et la zone transparente.
     
    4. Dispositif selon une quelconque revendication précédente, dans lequel la ligne basse tension comporte un matériau métallique opaque et est raccordée à une électrode cathodique (CAT).
     
    5. Dispositif selon la revendication 2 ou l'une quelconque des revendications 3 à 4 lorsqu'elles sont dépendantes de la revendication 2, dans lequel les lignes de balayage comportent une première ligne de balayage (SL1) et une deuxième ligne de balayage (SL2) disposées pour être proches l'une de l'autre, et
    la deuxième ligne de détection est dérivée depuis la ligne de détection et disposée entre la première ligne de balayage et la deuxième ligne de balayage.
     
    6. Dispositif selon la revendication 5, dans lequel la première zone d'émission est disposée au niveau d'une première sous-zone de pixel (P1) définie par la première ligne de données, la deuxième ligne de données et la première ligne de balayage,
    dans lequel la deuxième zone d'émission est disposée au niveau d'une deuxième sous-zone de pixel (P2) définie par la première ligne de données, la deuxième ligne de données et la deuxième ligne de balayage,
    dans lequel la troisième zone d'émission est disposée au niveau d'une troisième sous-zone de pixel (P3) définie par la troisième ligne de données, la quatrième ligne de données et la première ligne de balayage, et
    dans lequel la quatrième zone d'émission est disposée au niveau d'une quatrième sous-zone de pixel (P4) définie par la troisième ligne de données, la quatrième ligne de données et la deuxième ligne de balayage.
     
    7. Dispositif selon une quelconque revendication précédente, dans lequel le transistor en couche mince de commutation, le transistor en couche mince d'excitation, le transistor en couche mince de détection et le condensateur de stockage sont disposés sous la diode électroluminescente organique.
     
    8. Dispositif selon la revendication 7, dans lequel la diode électroluminescente organique comporte :

    une électrode anodique (ANO) raccordée au transistor en couche mince d'excitation et comportant un matériau métallique opaque réfléchissant ;

    une couche électroluminescente organique (OL) déposée sur l'électrode anodique ; et

    une électrode cathodique (CAT) comportant un matériau conducteur transparent et déposée sur la couche électroluminescente organique.


     




    Drawing