(19)
(11)EP 3 345 216 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
13.10.2021 Bulletin 2021/41

(21)Application number: 15903220.0

(22)Date of filing:  31.08.2015
(51)International Patent Classification (IPC): 
H01L 27/092(2006.01)
H01L 29/51(2006.01)
H01L 29/78(2006.01)
H01L 27/06(2006.01)
H01L 29/423(2006.01)
H01L 21/8252(2006.01)
H01L 29/778(2006.01)
H01L 29/20(2006.01)
H01L 21/8238(2006.01)
H01L 29/66(2006.01)
(52)Cooperative Patent Classification (CPC):
H01L 29/66462; H01L 29/7786; H01L 29/513; H01L 29/4236; H01L 29/2003; H01L 21/823807; H01L 29/78; H01L 29/66522; H01L 21/8252; H01L 27/0605; H01L 27/092
(86)International application number:
PCT/US2015/047835
(87)International publication number:
WO 2017/039635 (09.03.2017 Gazette  2017/10)

(54)

III NITRIDE COMPLEMENTARY TRANSISTORS

III-NITRID-KOMPLEMENTÄRTRANSISTOREN

TRANSISTORS COMPLÉMENTAIRES AU NITRURE DU GROUPE III


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(43)Date of publication of application:
11.07.2018 Bulletin 2018/28

(73)Proprietor: HRL Laboratories, LLC
Malibu, CA 90265-4799 (US)

(72)Inventors:
  • CHU, Rongming
    Agoura Hills, California 91301 (US)
  • CAO, Yu
    Agoura Hills, California 91301 (US)

(74)Representative: Richards, John et al
Ladas & Parry LLP
Temple Chambers 3-7 Temple Avenue London EC4Y 0DA
Temple Chambers 3-7 Temple Avenue London EC4Y 0DA (GB)


(56)References cited: : 
EP-A2- 2 846 353
US-A1- 2006 113 564
US-A1- 2012 126 291
US-A1- 2013 043 485
US-A1- 2005 179 096
US-A1- 2011 024 798
US-A1- 2013 026 495
US-A1- 2014 264 380
  
  • H. HAHN ET AL: "First monolithic integration of GaN-based enhancement mode n-channel and p-channel heterostructure field effect transistors", 72ND DEVICE RESEARCH CONFERENCE, June 2014 (2014-06), pages 259-260, XP055155997, DOI: 10.1109/DRC.2014.6872396 ISBN: 978-1-47-995405-6
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

TECHNICAL FIELD



[0001] This disclosure relates to a method for providing a semiconductor device in III-nitride complementary metal-oxide-semiconductor (CMOS) technology.

BACKGROUND



[0002] GaN N-channel transistors are known in the prior art to have excellent high-power and high-frequency performance. However, there are applications in which it is desirable to have a P-channel GaN transistor that can work with a GaN N-channel transistor on the same integrated circuit or substrate so that a high performance complementary metal-oxide-semiconductor (CMOS) integrated-circuit (IC) can be realized. The embodiments of the present disclosure answer these and other needs.

SUMMARY



[0003] According to the invention, a method for providing a semiconductor device comprises forming a III-nitride (III-N) layer buffer layer on a substrate, forming a III-N N-channel layer on the buffer layer, forming a III-N N-barrier layer on the N-channel layer, forming a first dielectric layer on top of the N-barrier layer, etching the first dielectric layer, the N-barrier layer, and the N-channel layer to form a first mesa for an N-channel transistor and to expose a portion of the buffer layer, forming a second dielectric layer over the first mesa and over a first area of the exposed portion of the buffer layer, wherein the first area is adjacent the first mesa, and wherein a remaining portion of the buffer layer is exposed, forming on top of the remaining exposed portion of the buffer layer a III-N P-barrier layer, forming on top

[0004] US 2013/043485 discloses a p-type GaN-based semiconductor device including: a first channel layer which is formed from a GaN-based semiconductor, and in which a carrier gas of a first conductivity type occurs; a barrier layer formed on the first channel layer from a GaN-based semiconductor having a higher bandgap than the first channel layer; and a second channel layer which is formed on the barrier layer from a GaN-based semiconductor having a lower bandgap than the barrier layer, and in which a carrier gas of a second conductivity type occurs, wherein the carrier concentration of the carrier gas of the second conductivity type is lower in a region below a first gate electrode than in other regions between a first source electrode and a first drain electrode, and is controlled by the first gate electrode. An embodiment comprising complementary transistors is also disclosed. The n-type transistor is formed by removing the second channel layer.

[0005] US 2006/113564 discloses a field effect transistor having heterostructure with a buffer layer or substrate. A channel is arranged on the buffer layer or on the substrate, and a capping layer is arranged on the channel. The channel consists of a piezopolar material and either the region around the boundary interface between the buffer layer or substrate and channel or the region around the boundary interface between the channel and capping layer is doped in a manner such that the piezocharges occurring at the respective boundary interface are compensated.

[0006] The document "first monolithic integration of GaN-based enhancement mode n-channel and p-channel heterostructure field effect transistors" by H. Hahn (72nd Device Research Conference, June 2014, pages 259-260, ISBN: 978-1-47-995405-6) discloses that GaN-based devices have shown to be promising alternatives to Si - based devices in a wide range of applications. After covering several frequency bands in RF power amplification, GaN -based devices also penetrate into the power-switching market. Owing to the high carrier density and the high mobility in a 2-D electron gas (2DEG) and a large bandgap, GaN-based devices have shown great performance. These properties may also be exploited in digital logic applications, for which complementary logic offers the lowest power consumption. Hence, p-channel devices which employ a 2-D hole gas (2DHG) have attracted increasing research interest lately. The recent progress of p-channel device characteristics [1] finally enables the monolithic integration of p- and n-channel transistors. Hence, complementary logic on basis of GaN (C-GaN) is within reach. As a first step towards C-GaN, the first report on the integration of enhancement mode (e-mode) n- and p-channel devices on a single wafer is presented. Challenges encountered are discussed and a first voltage transfer characteristic of art inverter structure is shown. For formation of the complementary devices, a stack comprising a sapphire substrate, a 0.3 µm AlN layer, a 2.0 µm GaN layer, a 35 nm Al0.42In0.03Ga0.55N layer, a 3 nm uid-GaN layer, a 23 nm GaN:Mg layer and a 7 nm graded GaN:Mg++ layer is formed. The p-GaN stack is removed in the designated n-region. of the III-N P-barrier layer a III-N P-channel layer, forming on top of the III-N P-channel layer a III-N P-cap layer, wherein the III-N P-barrier layer, the III-N P-channel layer, and the III-N P-cap layer form a second mesa for a P-channel transistor, and wherein the first and second mesa are separated by the first area on the buffer layer, removing the second dielectric, and implanting ions in the buffer layer between the first mesa and the second mesa for providing isolation between the N-channel transistor and the P-channel transistor.

[0007] These and other features and advantages will become further apparent from the detailed description and accompanying figures that follow. In the figures and description, numerals indicate the various features, like numerals referring to like features throughout both the drawings and the description.

BRIEF DESCRIPTION OF THE DRAWINGS



[0008] FIG. 1 shows a cross-section of a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors, the device as such not forming part of the claimed invention.

[0009] FIGs. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J, 2K, 2L, 2M, 2N, and 2O show a process flow for fabrication a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors in accordance with the claimed invention.

DETAILED DESCRIPTION



[0010] In the following description, numerous specific details are set forth to clearly describe various specific embodiments disclosed herein. One skilled in the art, however, will understand that the presently claimed invention may be practiced without all of the specific details discussed below. In other instances, well known features have not been described so as not to obscure the invention.

[0011] The present disclosure describes a GaN CMOS technology which integrates N-channel and P-channel GaN transistors on the same wafer. The result is a high performance GaN-based complementary metal-oxide-semiconductor (CMOS) integrated circuit which does not form part of the claimed invention. CMOS IC is the preferred topology for many circuit applications, due to its high noise immunity and low power consumption.

[0012] U.S. Patent Application No. 14/838,958 filed August 28, 2015, published as US patent 9,812,532 B1, describes a P-channel transistor. The GaN ICs of the present disclosure integrate N-channel and P-channel transistors on a common substrate and have better performance than a circuit with discrete GaN N-channel and/or P-channel transistors because more functionality can be achieved with less power consumption. An advantage of the GaN ICs of the present disclosure is that their performance is better than what can be attained with Si CMOS, because high performance N-channel and P-channel GaN transistors are used.

[0013] FIG. 1 shows a cross-section of a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors, the device not forming part of the claimed invention. The substrate 10 can be GaN, AlN, Sapphire, SiC, Si or any other suitable substrate material. FIG. 1 is further described below with reference to FIG. 2O.

[0014] FIGs. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J, 2K, 2L, 2M, 2N, and 2O show a process flow for fabrication a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors in accordance with the present invention. FIG. 2O is the same as FIG. 1, but is also shown in the process flow for completeness.

[0015] Referring now to FIG. 2A, a III-N layer buffer layer 12 is on the substrate 10, and may be grown by chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The buffer layer 12 may be GaN. On top of the buffer layer 12 is III-N N-channel layer 14, which may be GaN, and which may be grown by MOCVD or MBE. On top of the III-N N-channel layer 14 is a III-N N-barrier layer 16, which may be grown by MOCVD or MBE. The barrier layer 16 can be AlGaN, AlInN, AlInGaN, AlN, or a combination of these layers. The barrier layer 16 has a wider bandgap than the N-channel layer 14, and the thickness of the barrier layer 16 is typically in the range of 1~100nm.

[0016] A layer of dielectric 18 is deposited on top of the N-barrier layer 16. The dielectric 18 may be SiN, SiO2, SiON, AlN, or any combination of those, and may have a thickness of 1~500nm.

[0017] Next with reference to FIG. 2B, the dielectric 18, the barrier layer 16, and the channel layer 14 are etched to create a mesa 52 of the channel layer 14, the barrier layer 16 and the dielectric 18 and to expose a portion of the buffer layer 12.

[0018] Then as shown in FIG. 2C, a dielectric 60 is formed over the mesa 52 and over an area 54 of the exposed portion of the buffer layer 12.

[0019] Next with reference to FIG. 2D, on top of the remaining portion 56 of the buffer layer 12, a III-N P-barrier layer 20 may be grown by MOCVD or MBE. The P-barrier layer 20 can be AlGaN, AlInN, AlInGaN, AlN, or a combination of these. The thickness of the P-barrier layer 20 is typically in the range of 1~100nm. The P-barrier layer 20 assists in the accumulation of holes. On top of the III-N P-barrier layer 20, a III-N P-channel layer 22 may be grown by MOCVD or MBE. The P-channel layer 22 is typically GaN, with a narrower bandgap than the P-barrier layer 20. The thickness of the P-channel layer 22 is typically in the range of 1∼100nm.

[0020] On top of the III-N P-channel layer 22, a III-N P-cap layer 24 may be grown by MOCVD or MBE. The III-N P-cap layer 24 is typically GaN doped with Mg. The Mg concentration can vary across the P-cap layer 24. The thickness of the P-cap layer 24 is typically 1~100nm.

[0021] Then, as shown in FIG. 2E, the dielectric 60, which masked the mesa 52 and the area 54 of the buffer layer 12 while forming the P-barrier layer, the P-channel layer, and the P-cap layer, is removed. The result, as shown in FIG. 2E is the mesa 52 for an N-channel transistor, and a mesa 58 for a P-channel transistor.

[0022] Next, as shown in FIG. 2F, the mesa 52 is isolated from the mesa 58 by ion implantation 50 in the area 54 and on the sides of mesas 52 and 58.

[0023] Then, as shown in FIG. 2G, a dielectric 26 is deposited over the P-cap layer 24 of mesa 58, and over a portion of area 54 between the mesa 52 and the mesa 58.

[0024] Next, as shown in FIG. 2H, a P-gate trench 62 is formed in dielectric 26. The bottom of the P-gate trench 62 may extend partially or entirely through the P-cap layer 24, and may also extend partially through the P-channel layer 22.

[0025] Then, as shown in FIG. 2I, a N-gate trench 64 is formed in dielectric 18. The bottom of the trench 64 may extend partially or entirely through the dielectric 18, partially or entirely through the barrier layer 16, and partially or entirely through the N-channel layer 14, so that the N-gate trench stops anywhere between the top surface of dielectric 18 and the top surface of the buffer layer 12.

[0026] Next, as shown in FIG. 2J, a dielectric 28 is formed over the device, so that the dielectric 28 is on top of dielectric 18, covering the bottom and sides of N-gate trench 64, on top of dielectric 26, and covering the bottom and sides of P-gate trench 62. The dielectric 28 is typically a stack of AIN/SiN layer, grown by MOCVD. The dielectric 28 may also be only deposited in the N-gate trench 64 and the P-gate trench 62 to insulate the N-gate electrode 32 and the P-gate electrode 42, respectively, for low gate leakage current.

[0027] Then, as shown in FIG. 2K, N-ohmic openings 70 and 72 are made on opposite sides of the N-gate trench 64.

[0028] The openings 70 and 72 are made through the dielectric 28, and may be made partially or entirely through the dielectric 18, and in some cases partially or entirely through the N-barrier layer 16.

[0029] Next, as shown in FIG. 2L, the openings 70 and 72 are filled with metal to form N-ohmic electrodes 74 and 76, forming source and drain contacts, respectively, for the N-channel transistor.

[0030] Then, as shown in FIG. 2M, P-ohmic openings 80 and 82 are formed on opposite sides of the P-gate trench 62. The openings 80 and 82 are made through the dielectric 28, through the dielectric 26, and in some cases partially or entirely through the P-cap layer 24.

[0031] Next, as shown in FIG. 2N, the openings 80 and 82 are filled with metal to form P-ohmic electrodes 84 and 86, forming source and drain contacts, respectively, for the P-channel transistor.

[0032] Finally, as shown in FIG. 2O, the N-gate trench 64 is filled with metal 32 to form a gate contact for the N-channel transistor, and the P-gate trench 62 is filled with metal 42 to form a gate contact for the P-channel transistor.

[0033] The result is a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors, as shown in FIG. 1, which is the same as FIG. 2O.

[0034] Referring now to FIG. 1, the substrate 10 may be but is not limited to GaN, AlN, Sapphire, SiC, or Si. The III-N buffer layer 12 is on the substrate 10. As shown in FIG. 1, on top of one portion of the buffer layer 12, is the III-N N-channel layer 14 on the buffer layer 12, and the III-N N-barrier layer 16 on the N-channel layer 14. On top of another portion of the buffer layer 12, is the III-N P-barrier layer 20 on the buffer layer 12, the III-N P-channel layer 22 on the P-barrier layer 20, and the III-N P-Cap layer 24 on the P-channel layer 22.

[0035] The dielectric 28 covers the bottom and sides of N-gate trench 64, and the bottom and sides of P-gate trench 62, as described above. Metal 32 fills gate trench 64 to form a gate contact for the N-channel transistor, and metal 42 fills gate trench 62 to form a gate contact for the P-channel transistor.

[0036] N-ohmic electrodes 74 and 76 provide source and drain contacts, respectively, for the N-channel transistor, and P-ohmic electrodes 84 and 86 provide source and drain contacts, respectively, for the P-channel transistor.

[0037] Ion implantation 50 in the area 54 between the N-channel transistor and the P-channel transistor provides isolation of the N-channel transistor from the P-channel transistor.

[0038] A person skilled in the art will understand that well known steps of patterning and etching may be used in the process flow, such as for example to remove a layer or portion of a layer. Such well known processes are not described in detail, because they are widely used in semiconductor processing.

[0039] The foregoing Detailed Description of exemplary and preferred embodiments is presented for purposes of illustration and disclosure in accordance with the requirements of the law. It is not intended to be exhaustive nor to limit the invention to the precise form(s) described, but only to enable others skilled in the art to understand how the invention may be suited for a particular use or implementation. The possibility of modifications and variations will be apparent to practitioners skilled in the art. No limitation is intended by the description of exemplary embodiments which may have included tolerances, feature dimensions, specific operating conditions, engineering specifications, or the like, and which may vary between implementations or with changes to the state of the art, and no limitation should be implied therefrom. Applicant has made this disclosure with respect to the current state of the art, but also contemplates advancements and that adaptations in the future may take into consideration of those advancements, namely in accordance with the then current state of the art. It is intended that the scope of the invention be defined by the Claims as written. Reference to a claim element in the singular is not intended to mean "one and only one" unless explicitly so stated.


Claims

1. A method for providing a semiconductor device comprising :

forming a III-nitride layer buffer layer (12) on a substrate (10);

forming a III-nitride N-channel layer (14) on the buffer layer (12);

forming a III-nitride N-barrier layer (16) on the N-channel layer (14);

forming a first dielectric layer (18) on top of the N-barrier layer (16);

etching the first dielectric layer (18), the N-barrier layer (16), and the N-channel layer (14) to form a first mesa (52) for an N-channel transistor and to expose a portion of the buffer layer (12);

forming a second dielectric layer (60) over the first mesa (52) and over a first area (54) of the exposed portion of the buffer layer (12), wherein the first area (54) is adjacent the first mesa (52), and wherein a remaining portion of the buffer layer (12) is exposed;

forming on top of the remaining exposed portion of the buffer layer (12) a III-nitride P-barrier layer (20);

forming on top of the III-nitride P-barrier layer (20) a III-nitride P-channel layer (22);

forming on top of the III-nitride P-channel layer (22) a III-nitride P-cap layer (24), wherein the III-nitride P-barrier layer (20), the III-nitride P-channel layer (22), and the III-N P-cap layer (24) form a second mesa (58) for a P-channel transistor, and wherein the first (52) and second mesa (58) are separated by the first area (54) on the buffer layer;

removing the second dielectric (60); and

implanting ions in the buffer layer between the first mesa (52) and the second mesa (58) for providing isolation (50) between the N-channel transistor and the P-channel transistor.


 
2. The method of claim 1 further comprising:

forming a third dielectric (26) over the P-cap layer (24) and over a portion of the first area (54) between the first (52) and second (58) mesas;

forming a P-gate trench (62) in the third dielectric (26), wherein a bottom of the P-gate trench (62) extends partially or entirely through the P-cap layer (24), or extends partially through the P-channel layer (22); and

forming an N-gate trench (64) in the first dielectric (18), wherein the bottom of the N-gate trench (64) extends partially or entirely through the first dielectric (18), or partially or entirely through the N-barrier layer (16), or partially or entirely through the N-channel layer (14), so that the N-gate trench (64) stops anywhere between a top surface of the first dielectric (18) and a top surface of the buffer layer (12); and

forming a fourth dielectric (28) on top of the first dielectric (18), over the bottom and sides of the N-gate trench (64), on top of the third dielectric (26), and over the bottom and sides of the P-gate trench (62).


 
3. The method of claim 2 further comprising:

etching first (70) and second (72) openings on opposite sides of the N-gate trench (64);

filling the first (70) and second (72) openings with metal to form N-ohmic electrodes for source (74) and drain (76) contacts, respectively, for the N-channel transistor;

etching third (80) and fourth (82) openings on opposite sides of the P-gate trench (62); and

filling the third (80) and fourth (82) openings with metal to form P-ohmic electrodes for source (84) and drain (86) contacts, respectively, for the P-channel transistor.


 
4. The method of claim 2 further comprising:

filling the N-gate trench (64) with metal to form a gate contact (32) for the N-channel transistor;

filing the P-gate trench (62) with metal to form a gate contact (42) for the P-channel transistor.


 
5. The method of claim 1, wherein:
the substrate (10) comprises GaN, AIN, Sapphire, SiC, or Si .
 
6. The method of claim 1, wherein:
the III-nitride buffer layer (12) comprises GaN.
 
7. The method of claim 1, wherein:
the III-nitride N-channel layer (14) comprises GaN.
 
8. The method of claim 1, wherein:
the III-nitride N-barrier layer (16) comprises one of more of AIGaN, AlInN, AlInGaN, or AIN; and the N-barrier layer (16) has a wider bandgap than the N-channel layer (14).
 
9. The method claim 1, wherein:
the P-barrier layer (20) comprises one or more of AIGaN, AlInN, AlInGaN, or AIN.
 
10. The method of claim 1, wherein:
the P-channel layer (22) comprises GaN; and wherein the P-channel layer (22) has a narrower bandgap than the P-barrier layer (20).
 
11. The method of claim 1, wherein:
the P-cap layer (24) comprises Mg .
 


Ansprüche

1. Verfahren zur Bereitstellung einer Halbleitervorrichtung, wobei das Verfahren folgendes umfasst:

Ausbilden einer III-Nitridschicht-Pufferschicht (12) auf einem Substrat (10);

Ausbilden einer III-Nitrid-N-Kanalschicht (14) auf der Pufferschicht (12);

Ausbilden einer III-Nitrid-N-Sperrschicht (16) auf der N-Kanalschicht (14);

Ausbilden einer ersten dielektrischen Schicht (18) über der N-Sperrschicht (16);

Ätzen der ersten dielektrischen Schicht (18), der N-Sperrschicht (16) und der N-Kanalschicht (14), um ein erstes Mesa (52) für einen N-Kanal-Transistor auszubilden und um einen Teil der Pufferschicht (12) freizulegen;

Ausbilden einer zweiten dielektrischen Schicht (60) über dem ersten Mesa (52) und über einem ersten Bereich (54) des freiliegenden Teils der Pufferschicht (12), wobei der erste Bereich (54) angrenzend an das erste Mesa (52) angeordnet ist, und wobei ein verbleibender Teil der Pufferschicht (12) frei liegt;

Ausbilden einer III-Nitrid-P-Sperrschicht (20) über dem verbleibenden frei liegenden Teil der Pufferschicht (12);

Ausbilden einer III-Nitrid-P-Kanalschicht (22) über der III-Nitrid-P-Sperrschicht (20);

Ausbilden einer III-Nitrid-P-Deckschicht (24) über der III-Nitrid-P-Kanalschicht (22), wobei die III-Nitrid-P-Sperrschicht (20), die III-Nitrid-P-Kanalschicht (22) und die III-Nitrid-P-Deckschicht (24) ein zweites Mesa (58) für einen P-Kanal-Transistor bilden, und wobei das erste (52) und das zweite Mesa (58) durch den ersten Bereich (54) auf der Pufferschicht getrennt sind;

Entfernen der zweiten Dielektrikums (60); und

Implantieren von Ionen in die Pufferschicht zwischen dem ersten Mesa (52) und dem zweiten Mesa (58), um eine Isolation (50) zwischen dem N-Kanal-Transistor und dem P-Kanal-Transistor bereitzustellen.


 
2. Verfahren nach Anspruch 1, wobei das Verfahren ferner folgendes umfasst:

Ausbilden eines dritten Dielektrikums (26) über der P-Deckschicht (24) und über einem Teil des ersten Bereichs (54) zwischen dem ersten (52) und dem zweiten (58) Mesa;

Ausbilden eines P-Gate-Trenchs (62) in dem dritten Dielektrikum (26), wobei sich ein Boden des P-Gate-Trenchs (62) teilweise oder vollständig durch die P-Deckschicht (24) erstreckt, oder wobei er sich teilweise durch die P-Kanalschicht (22) erstreckt; und

Ausbilden eines N-Gate-Trenchs (64) in dem ersten Dielektrikum (18), wobei sich der Boden des N-Gate-Trenchs (64) teilweise oder vollständig durch das erste Dielektrikum (18) erstreckt, oder wobei er sich teilweise oder vollständig durch die N-Sperrschicht (16) oder erstreckt, oder wobei er sich teilweise oder vollständig durch die N-Kanalschicht (14) erstreckt, so dass der N-Gate-Trench (64) an beliebiger Stelle zwischen einer oberen Oberfläche des ersten Dielektrikums (18) und einer oberen Oberfläche der Pufferschicht (12) endet; und

Ausbilden eines vierten Dielektrikums (28) über dem ersten Dielektrikum (18), über dem Boden und den Seiten des N-Gate-Trenchs (64), über dem dritten Dielektrikum (26) und über dem Boden und den Seiten des P-Gate-Trenchs (62).


 
3. Verfahren nach Anspruch 2, wobei das Verfahren ferner folgendes umfasst:

Ätzen erster (70) und zweiter (72) Öffnungen auf entgegengesetzten Seiten des N-Gate-Trench (64);

Füllen der ersten (70) und zweiten (72) Öffnungen mit Metall, um entsprechende N-ohmsche Elektroden für Source- (74) und Drain- (76) Kontakte für den N-Kanal-Transistor auszubilden;

Ätzen dritter (80) und vierter (82) Öffnungen auf entgegengesetzten Seiten des P-Gate-Trench (62); und

Füllen der dritten (80) und vierten (82) Öffnungen mit Metall, um entsprechende N-ohmsche Elektroden für Source- (84) und Drain- (86) Kontakte für den P-Kanal-Transistor auszubilden.


 
4. Verfahren nach Anspruch 2, wobei das Verfahren ferner folgendes umfasst:

Füllen des N-Gate-Trench (64) mit Metall, um einen Gate-Kontakt (32) für den N-Kanal-Transistor auszubilden;

Füllen des P-Gate-Trench (62) mit Metall, um einen Gate-Kontakt (42) für den P-Kanal-Transistor auszubilden.


 
5. Verfahren nach Anspruch 1, wobei:
das Substrat (10) GaN, AlN, Saphir, SiC oder Si umfasst.
 
6. Verfahren nach Anspruch 1, wobei:
die III-Nitrid-Pufferschicht (12) GaN umfasst.
 
7. Verfahren nach Anspruch 1, wobei:
die III-Nitrid-N-Kanalschicht (14) GaN umfasst.
 
8. Verfahren nach Anspruch 1, wobei:

wobei die III-Nitrid-N-Sperrschicht (16) eines oder mehrere der folgenden umfasst: AlGaN, AlInN, AlInGaN oder AlN; und

wobei die N-Sperrschicht (16) einen breiteren Bandabstand als die N-Kanalschicht (14) aufweist.


 
9. Verfahren nach Anspruch 1, wobei:
die P-Sperrschicht (20) eines oder mehrere der folgenden umfasst: AlGaN, AlInN, AlInGaN oder Aln.
 
10. Verfahren nach Anspruch 1, wobei:
die P-Kanalschicht (22) GaN umfasst; und wobei die P-Kanalschicht (22) einen schmaleren Bandabstand als die P-Sperrschicht (20) aufweist.
 
11. Verfahren nach Anspruch 1, wobei:
die P-Deckschicht (24) Mg umfasst.
 


Revendications

1. Procédé permettant de produire un dispositif semi-conducteur comprenant les étapes consistant à :

former une couche tampon de couche de nitrure du groupe III (12) sur un substrat (10) ;

former une couche de canal N de nitrure du groupe III (14) sur la couche tampon (12) ;

former une couche barrière N de nitrure du groupe III (16) sur la couche de canal N (14) ;

former une première couche diélectrique (18) sur la couche barrière N (16) ;

graver la première couche diélectrique (18), la couche barrière N (16) et la couche de canal N (14) pour former une première mesa (52) pour un transistor à canal N et pour exposer une partie de la couche tampon (12) ;

former une deuxième couche diélectrique (60) sur la première mesa (52) et sur une première zone (54) de la partie exposée de la couche tampon (12), la première zone (54) étant adjacente à la première mesa (52), et une partie restante de la couche tampon (12) étant exposée ;

former sur le dessus de la partie exposée restante de la couche tampon (12) une couche barrière P de nitrure du groupe III (20) ;

former sur le dessus de la couche barrière P de nitrure du groupe III (20) une couche de canal P de nitrure du groupe III (22) ;

former sur le dessus de la couche de canal P de nitrure du groupe III (22) une couche superficielle P de nitrure du groupe III (24), la couche barrière P de nitrure du groupe III (20), la couche de canal P de nitrure du groupe III (22) et la couche superficielle P de nitrure du groupe III (24) formant une deuxième mesa (58) pour un transistor à canal P, et la première (52) et la deuxième mesa (58) étant séparées par la première zone (54) sur la couche tampon ;

retirer le deuxième diélectrique (60) ; et

implanter des ions dans la couche tampon entre la première mesa (52) et la deuxième mesa (58) pour fournir une isolation (50) entre le transistor à canal N et le transistor à canal P.


 
2. Procédé selon la revendication 1 comprenant en outre les étapes consistant à :

former un troisième diélectrique (26) sur la couche superficielle P (24) et sur une partie de la première zone (54) entre les première (52) et deuxième (58) mesas ;

former une tranchée de grille P (62) dans le troisième diélectrique (26), un fond de la tranchée de grille P (62) s'étendant partiellement ou entièrement à travers la couche superficielle P (24), ou s'étendant partiellement à travers la couche de canal P (22) ; et

former une tranchée de grille N (64) dans le premier diélectrique (18), le fond de la tranchée de grille N (64) s'étendant partiellement ou entièrement à travers le premier diélectrique (18), ou partiellement ou entièrement à travers la couche barrière N (16), ou partiellement ou entièrement à travers la couche de canal N (14), de sorte que la tranchée de grille N (64) s'arrête n'importe où entre une surface supérieure du premier diélectrique (18) et une surface supérieure de la couche tampon (12) ; et

former un quatrième diélectrique (28) sur le dessus du premier diélectrique (18), sur le fond et les côtés de la tranchée de grille N (64), sur le dessus du troisième diélectrique (26), et sur le fond et les côtés de la tranchée de grille P (62).


 
3. Procédé selon la revendication 2 comprenant en outre les étapes consistant à :

graver des première (70) et deuxième (72) ouvertures sur les côtés opposés de la tranchée de grille N (64) ;

remplir les première (70) et deuxième (72) ouvertures avec du métal pour former des électrodes N-ohmiques pour des contacts de source (74) et de drain (76), respectivement, pour le transistor à canal N ;

graver des troisième (80) et quatrième (82) ouvertures sur des côtés opposés de la tranchée de grille P (62) ; et

remplir les troisième (80) et quatrième (82) ouvertures avec du métal pour former des électrodes P-ohmiques pour des contacts de source (84) et de drain (86), respectivement, pour le transistor à canal P.


 
4. Procédé selon la revendication 2 comprenant en outre les étapes consistant à :

remplir la tranchée de grille N (64) avec du métal pour former un contact de grille (32) pour le transistor à canal N ;

remplir la tranchée de grille P (62) avec du métal pour former un contact de grille (42) pour le transistor à canal P.


 
5. Procédé selon la revendication 1 :
le substrat (10) comprenant du GaN, de l'AIN, du saphir, du SiC ou du Si.
 
6. Procédé selon la revendication 1 :
la couche tampon de nitrure du groupe III (12) comprenant du GaN.
 
7. Procédé selon la revendication 1 :
la couche de canal N de nitrure du groupe III (14) comprenant du GaN.
 
8. Procédé selon la revendication 1 :

la couche barrière N de nitrure du groupe III (16) comprenant de l'AlGaN, de l'AlInN, de l'AlInGaN et/ou de l'AIN ; et

la couche barrière N (16) ayant une bande interdite plus large que la couche de canal N (14).


 
9. Procédé selon la revendication 1 :
la couche barrière P (20) comprenant de l'AlGaN, de l'AlInN, de l'AlInGaN ou de l'AIN.
 
10. Procédé selon la revendication 1 :
la couche de canal P (22) comprenant du GaN ; et la couche de canal P (22) ayant une bande interdite plus étroite que la couche barrière P (20).
 
11. Procédé selon la revendication 1, la couche superficielle P (24) comprenant du Mg.
 




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Cited references

REFERENCES CITED IN THE DESCRIPTION



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Patent documents cited in the description




Non-patent literature cited in the description