(19)
(11)EP 3 355 360 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
04.11.2020 Bulletin 2020/45

(21)Application number: 16790255.0

(22)Date of filing:  14.02.2016
(51)International Patent Classification (IPC): 
H01L 29/786(2006.01)
H01L 29/66(2006.01)
H01L 27/12(2006.01)
H01L 21/3213(2006.01)
(86)International application number:
PCT/CN2016/073760
(87)International publication number:
WO 2017/049845 (30.03.2017 Gazette  2017/13)

(54)

MANUFACTURING METHOD FOR THIN FILM TRANSISTOR

HERSTELLUNGSVERFAHREN FÜR DÜNNSCHICHTTRANSISTOR

PROCÉDÉ DE FABRICATION D'UN TRANSISTOR À COUCHE MINCE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 22.09.2015 CN 201510609039

(43)Date of publication of application:
01.08.2018 Bulletin 2018/31

(73)Proprietor: BOE Technology Group Co., Ltd.
Beijing 100015 (CN)

(72)Inventors:
  • SHU, Shi
    Beijing 100176 (CN)
  • ZHANG, Bin
    Beijing 100176 (CN)
  • XU, Chuanxiang
    Beijing 100176 (CN)
  • QI, Yonglian
    Beijing 100176 (CN)

(74)Representative: Gesthuysen Patent- und Rechtsanwälte 
Patentanwälte Huyssenallee 100
45128 Essen
45128 Essen (DE)


(56)References cited: : 
CN-A- 101 345 261
CN-A- 103 268 855
CN-A- 105 185 714
US-A1- 2003 232 456
CN-A- 101 345 261
CN-A- 103 268 855
US-A- 5 624 861
US-A1- 2012 171 822
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    TECHNICAL FIELD



    [0001] The present invention relates to a method for fabricating a thin film transistor.

    BACKGROUND



    [0002] High PPI (Pixels Per Inch) products have currently become a main developing trend for display devices with a small or medium size. A top-gate structure is generally adopted in products, for purpose of realizing a TFT (thin film transistor) with improved characteristics to meet the charging demand of high PPI products.

    [0003] However, the process for the top-gate structure is generally complicated, and there are numerous masking processes. Therefore, the cost and yield have become the concerns of the panel manufacturers. To prevent the strong light from a backlight from directly irradiating a back channel which would lead to leakage current, a light shielding layer is generally formed prior to the semiconductor layer. The light shielding layer is usually made from metal Mo, and a pattern is formed by a separate masking process.

    [0004] US 2009/0014721 discloses a TFT with a light shield.

    [0005] In some products, the light shielding layer is omitted to decrease the number of masking processes and thus reduce the cost. Instead, the performance of these products is ensured by improving the process capacity of other portions in TFT and optimizing the pixel design. However, this solution is abandoned soon during upgrade of products, because a large leakage current is not acceptable for a high performance product. Thus, there is still a need for arranging the light shielding layer in the top gate structure.

    SUMMARY



    [0006] The present invention intends to solve the technical problem of simplifying a process for fabricating a thin film transistor with a light shielding layer.

    [0007] To this end, the present invention provides a method for fabricating a thin film transistor, comprising:

    forming in sequence a light shielding layer, an insulating layer, and a semiconductor layer; and forming a pattern of the light shielding layer, the insulating layer, and the semiconductor layer in a patterning process,

    wherein only one mask is used in the patterning process, the forming the pattern of the light shielding layer, the insulating layer, and the semiconductor layer in the patterning process comprises: forming photoresist in a first region of the semiconductor layer; etching the semiconductor layer to remove the semiconductor layer outside the first region; etching the insulating layer for a first time to remove the insulating layer outside the first region; treating the photoresist, so that the photoresist has a width which is smaller than a width of the first region, the treated photoresist corresponding to a second region; etching the light shielding layer and the semiconductor layer, to remove the light shielding layer outside the first region and the semiconductor layer outside the second region, and etching the insulating layer for a second time, so that the insulating layer has a width which is larger than a width of the second region and smaller than the width of the first region. Preferably, etching the semiconductor layer comprises:
    etching the semiconductor layer for 110-120 seconds under conditions in which a flow ratio between SF6 and Cl2 is 10/400-40/400, and a RF generator inputs a power of 600-1000 W to plasma in a processing chamber.



    [0008] Preferably, etching the insulating layer for the first time comprises:
    etching the insulating layer for 250-350 seconds under conditions in which a flow ratio between CF4 and O2 is 200/40-200/20, and a RF generator inputs a power of 600-1000 W to plasma in a processing chamber.

    [0009] Preferably, treating the photoresist comprises:
    ashing the photoresist.

    [0010] Preferably, ashing the photoresist comprises:
    ashing the photoresist for 40-60 seconds under conditions in which a flow ratio between SF6 and O2 is 20/400-40/400, and a RF generator inputs a power of 350W-450 W to plasma in a processing chamber.

    [0011] Preferably, etching the light shielding layer and the semiconductor layer comprises:
    etching the light shielding layer and the semiconductor layer for 110-120 seconds under conditions in which a flow ratio between SF6 and Cl2 is 10/400-40/400, and a RF generator inputs a power of 600-1000 W to plasma in a processing chamber.

    [0012] Preferably, etching the insulating layer for the second time comprises:

    etching the insulating layer for 35-45 seconds under conditions in which a flow ratio between CF4 and O2 is 200/50-200/30, and a RF generator inputs a power of 600-1000 W to plasma in a processing chamber; and

    etching the insulating layer for 18-22 seconds under conditions in which a flow ratio between SF6 and O2 is 10/200-30/200, and the RF generator inputs a power of 300-500 W to plasma in the processing chamber.



    [0013] Preferably, prior to forming the photoresist in the first region of the semiconductor layer, the method further comprises:

    forming a first amorphous silicon layer on a buffer layer as the light shielding layer;

    forming the insulating layer on the light shielding layer;

    forming a second amorphous silicon layer on the insulating layer;

    annealing the second amorphous silicon layer, to convert the second amorphous silicon layer into a the polycrystalline silicon layer as the semiconductor layer.



    [0014] Preferably, the buffer layer is made from SiNx, and the insulating layer is made from SiOy, wherein 1<x<2, and 1<y<3.

    [0015] Preferably, after etching the insulating layer for the second time, the method further comprises:

    peeling off the photoresist on the semiconductor layer;

    forming a gate insulating layer on the semiconductor layer;

    forming a gate on the gate insulating layer;

    forming an interlayer dielectric layer on the gate; and

    forming a source and a drain on the interlayer dielectric layer, wherein the source and the drain are electrically connected with the semiconductor layer by via holes in the interlayer dielectric layer and the gate insulating layer.



    [0016] Preferably, the amorphous silicon layer has a width which is larger than a width of the insulating layer, and the width of the insulating layer is larger than a width of the polycrystalline silicon layer.

    [0017] Preferably, the method further comprises:

    a gate insulating layer arranged on the semiconductor layer;

    a gate arranged on the gate insulating layer;

    an interlayer dielectric layer arranged on the gate; and

    a source and a drain arranged on the interlayer dielectric layer, wherein the source and the drain are electrically connected with the semiconductor layer by via holes in the interlayer dielectric layer and the gate insulating layer.



    [0018] According to the above technical solutions, a polycrystalline silicon layer can be formed into an active layer and an amorphous silicon layer into the light shielding layer, by using only one mask. As compared with the existing method in which a light shielding layer is formed from a metal below the active layer by using an additional mask, the number of masking processes is reduced by one, which simplifies a fabricating process of the thin film transistor.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0019] These and other aspects of the invention are apparent from and will be further elucidated, by way of example, with reference to the drawings, in which:

    Fig. 1 is a schematic flow chart illustrating a method for fabricating a thin film transistor;

    Fig. 2 is a schematic flow chart illustrating a method for fabricating a thin film transistor in an embodiment of the present invention; and

    Figs. 3, 4, 5, 6, 7, 8, 9, and 10 are schematic flow charts illustrating a method for fabricating a thin film transistor in an embodiment of the present invention.


    DETAILED DESCRIPTION OF EMBODIMENTS



    [0020] The above objects, features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings and specific embodiments. It is noted that embodiments and features in embodiments of the present application can be combined in case no conflict occurs.

    [0021] In the following description, details will be presented for fully understanding the present invention, but the following embodiments are only used for explaining more clearly the technical solution of the present invention rather than limiting the protection scope of the present invention.

    [0022] Reference numerals: 1 light shielding layer; 2 insulating layer; 3 semiconductor layer; 4 photoresist; 5 buffer layer; 6 gate insulating layer; 7 gate; 8 interlayer dielectric layer; 9 substrate; 10 first region; 11 source; 12 drain; 20 second region.

    [0023] As shown in Fig. 1, a method for fabricating a thin film transistor comprises the following steps:

    S1, forming in sequence a light shielding layer 1, an insulating layer 2, and a semiconductor layer 3, as shown in Fig. 3; and

    S2, forming a pattern of the light shielding layer 1, the insulating layer 2 and the semiconductor layer 3 in one patterning process.



    [0024] As shown in Fig. 3, the structure of the thin film transistor is arranged on a substrate 9. For simplicity, the reference numeral for the substrate 9 is not shown in Figs. 4-10.

    [0025] As shown in Fig. 2, forming the pattern of the light shielding layer 1, the insulating layer 2, and the semiconductor layer 3 in a patterning process comprises the following steps:

    S21, forming photoresist 4 in a first region 10 of the semiconductor layer 3, as shown in Fig. 4;

    S22, etching the semiconductor layer 3 to remove the semiconductor layer outside the first region 10, as shown in Fig. 5;

    S23, etching the insulating layer 2 for a first time to remove the insulating layer outside the first region 10, as shown in Fig. 6;

    S24, treating the photoresist 4, so that the photoresist 4 has a width which is smaller than a width of the first region 10, wherein the treated photoresist corresponds to a second region 20, as shown in Fig. 7; and S25, etching the light shielding layer 1 and the semiconductor layer 3, to remove the light shielding layer 1 outside the first region 10 and the semiconductor layer 3 outside the second region 20, as shown in Fig. 8.



    [0026] In the present embodiment, the light shielding layer, the insulating layer, and the semiconductor layer are retained on the photoresist after the etching process. As a result, etching of the light shielding layer, the insulating layer, and the semiconductor layer can be performed by using a mask corrsesponding to the photoresist.

    [0027] The resulting semiconductor layer can function as an active layer, and the insulating layer can prevent the light shielding layer from affecting electrical performance of the polycrystalline silicon layer. In the present embodiment, a polycrystalline silicon layer can be formed into the active layer and an amorphous silicon layer into the light shielding layer, by using only one mask. As compared with the existing method in which a light shielding layer is formed from a metal below the active layer by using an additional mask, the number of masking processes is reduced by one, which simplifies a fabricating process of the thin film transistor.

    [0028] The method further comprises the following steps: S26, etching the insulating layer 2 for a second time, so that the insulating layer 2 has a width which is larger than a width of the second region 20 and smaller than the width of the first region 10, as shown in Fig. 9.

    [0029] In the present embodiment, a structure in which the light shielding layer, the insulating layer, and the semiconductor layer decrease successively in width can be formed. Such a structure ensures electrical performance of the active layer made from the three-layer structure. The light shielding layer in the lowest layer can provide an enhanced light shielding effect for the semiconductor layer, so that the light from the bottom side is prevented from irradiating the semiconductor layer. Preferably, step S22 of etching the semiconductor layer 3 comprises: etching the semiconductor layer 3 for 110-120 seconds under conditions in which a flow ratio between SF6 and Cl2 is 10/400-40/400, and a RF generator inputs a power of 600-1000 W to plasma in a processing chamber.

    [0030] Preferably, in step S22, the semiconductor layer 3 can be etched for 115 seconds under conditions in which the flow ratio between SF6 and Cl2 is 20/400, and the RF generator inputs a power of 800 W to plasma in the processing chamber.

    [0031] The semiconductor layer 3 can be made from polycrystalline silicon, Cl2 can provide Cl element for etching polycrystalline silicon, and SF6 can provide F element for etching polycrystalline silicon. Cl2 can effectively etch polycrystalline silicon. SF6 doped in Cl2 facilitates etching, and thus increases the etching rate.

    [0032] Preferably, etching the insulating layer 2 for the first time in step S23 comprises: etching the insulating layer 2 for 250-350 seconds under conditions in which a flow ratio between CF4 and O2 is 200/40-200/20, and the RF generator inputs a power of 600-1000 W to plasma in the processing chamber.

    [0033] Preferably, in step S23, the insulating layer 2 can be etched for 200 seconds under conditions in which the flow ratio between CF4 and O2 is 200/40, and the RF generator inputs a power of 800 W to plasma in the processing chamber.

    [0034] The insulating layer 2 can be made from SiOy, wherein 1<y<3. CF4 can provide F element during etching. Adding O2 in the etching gas facilitates forming a tapering angle during etching.

    [0035] Preferably, treating the photoresist 4 in step S24 comprises: ashing the photoresist 4.

    [0036] In addition, after ashing, the photoresist has a decreased width to expose a portion of the polycrystalline silicon layer below the photoresist. Thus, during etching the amorphous silicon layer, the exposed portion of the polycrystalline silicon layer below the photoresist can be etched at the same time, so that the width of the polycrystalline silicon layer is decreased. Thus, it is not necessary to etch the polycrystalline silicon layer separately, which decreases the times of arranging a mask and simplifies the fabricating process.

    [0037] Preferably, in step S24, ashing the photoresist 4 comprises:
    ashing the photoresist for 40-60 seconds under conditions in which a flow ratio between SF6 and O2 is 20/400-40/400, and the RF generator inputs a power of 350W-450 W to plasma in the processing chamber.

    [0038] Preferably, in step S24, the photoresist 4 can be ashed for 50 seconds under conditions in which the flow ratio between SF6 and O2 is 30/400, and the RF generator inputs a power of 400 W to plasma in the processing chamber.

    [0039] Preferably, etching the light shielding layer 1 and the semiconductor layer 3 in step S25 comprises:
    etching the light shielding layer 1 and the semiconductor layer 3 for 110-120 seconds under conditions in which the flow ratio between SF6 and Cl2 is 10/400-40/400, and the RF generator inputs a power of 600-1000 W to plasma in the processing chamber.

    [0040] Preferably, in step S25, the light shielding layer 1 and the semiconductor layer 3 can be etched for 115 seconds under conditions in which the flow ratio between SF6 and Cl2 is 20/400, and the RF generator inputs a power of 800 W to plasma in the processing chamber.

    [0041] Preferably, etching the insulating layer 2 for the second time in step S26 comprises:

    etching the insulating layer 2 for 35-45 seconds under conditions in which the flow ratio between CF4 and O2 is 200/50-200/30, and the RF generator inputs a power of 600-1000 W to plasma in the processing chamber; and

    etching the insulating layer 2 for 18-22 seconds under conditions in which the flow ratio between SF6 and O2 is 10/200-30/200, and the RF generator inputs a power of 300-500 W to plasma in the processing chamber.



    [0042] Preferably, in step S26, the insulating layer 2 is firstly etched for 40 seconds under conditions in which the flow ratio between CF4 and O2 is 200/40, and the RF generator inputs a power of 800 W to plasma in the processing chamber; and the insulating layer 2 is then etched for 20 seconds under conditions in which the flow ratio between SF6 and O2 is 20/200, and the RF generator inputs a power of 400 W to plasma in the processing chamber.

    [0043] According to the pattern of the light shielding layer, the insulating layer, and the semiconductor layer formed under the above etching conditions, a structure in which the light shielding layer has a width larger than that of the insulating layer and the insulating layer has a width larger than that of the semiconductor layer, i.e., the light shielding layer, the insulating layer, and the semiconductor layer gradually decrease in width in a upward direction, can be formed conveniently. As a result, the light shielding layer can completely block the light from the bottom side which otherwise would irradiate the semiconductor layer.

    [0044] By etching under the above conditions, the resulting light shielding layer, insulating layer and semiconductor layer have a dense structure and smooth surface. It is ensured that the semiconductor layer has excellent electrical performance, and the insulating layer can insulate the light shielding layer from the semiconductor layer in a satisfactory way.

    [0045] In the present embodiment, etching the insulating layer for the second time can also be divided into two steps, wherein a first etching step can reduce the width of the insulating layer, and a second etching step mainly etch the photoresist. The polycrystalline silicon layer, the insulating layer, and the amorphous silicon layer are subject to several etching processes, so that the photoresist is prone to be modified. The second etching step can etch away the modified photoresist at the surface. In this way, the photoresist can be conveniently removed subsequently.

    [0046] Preferably, prior to forming the photoresist 4 in the first region 10 of the semiconductor layer 3 in step S21, the method further comprises:

    forming a first amorphous silicon layer on a buffer layer 5 as the light shielding layer 1;

    forming the insulating layer 2 on the light shielding layer 1;

    forming a second amorphous silicon layer on the insulating layer 2; and

    annealing the second amorphous silicon layer, to convert the second amorphous silicon layer into a polycrystalline silicon layer which acts as the semiconductor layer 3.



    [0047] Preferably, the buffer layer 5 is made from SiNx, wherein 1<x<2. For example, in case x=4/3, SiNx is Si3N4. The insulating layer 2 is made from SiOy, wherein 1<y<3. For example, in case y=2, SiOy can be SiO2. SiOy shows excellent insulating performance, and is easy to etch, which can ensure the etching effect.

    [0048] As shown in Fig. 10, preferably, after etching the insulating layer 2 for the second time in step S26, the method further comprises:

    peeling off the photoresist 4 on the semiconductor layer 3;

    forming a gate insulating layer 6 on the semiconductor layer 3;

    form a gate 7 on the gate insulating layer 6;

    forming an interlayer dielectric layer 8 on the gate 7; and

    forming a source 11 and a drain 12 on the interlayer dielectric layer 8, which are electrically connected with the semiconductor layer 3 by via holes in the interlayer dielectric layer 8 and the gate insulating layer 6.



    [0049] The forming process in the flow chart for example can comprise a film-forming process like depositing, sputtering, and a patterning process like etching.

    [0050] In the present embodiment, after the source and the drain are formed, conventional structures in the display substrate such as a passivation layer, a common electrode, and a pixel electrode can be formed, and description thereof is omitted.

    [0051] As shown in Fig. 10, the thin film transistor comprises:

    the light shielding layer 1;

    the insulating layer 2 which is arranged on the light shielding layer 1; and

    the semiconductor layer 3 which is arranged on the insulating layer 2. Preferably, the light shielding layer 1 has a width larger than that of the insulating layer 2, and the width of the insulating layer 2 is larger than that of the semiconductor layer 3.



    [0052] Preferably, the thin film transistor further comprises:

    the gate insulating layer 6 which is arranged on the semiconductor layer 3;

    the gate 7 which is arranged on the gate insulating layer 6;

    the interlayer dielectric layer 8 which is arranged on the gate 7; and

    the source 11 and the drain 12, which are arranged on the interlayer dielectric layer 8, and electrically connected with the semiconductor layer 3 by via holes in the interlayer dielectric layer 8 and the gate insulating layer 6.



    [0053] A display further comprises the thin film transistor as described above.

    [0054] It is noted that the display device can be any product or component with a display function, e.g., a display panel, a electronic paper, a mobile paper, a tablet computer, a TV set, a notebook computer, a digital photo frame, a navigator.

    [0055] The technical solutions of the present invention have been described above with reference to the accompanying drawings. In the existing technique, a top-gate thin film transistor needs a separate masking process to form the light shielding layer, so that the whole process is relatively tedious. According to technical solutions of the present invention, the polycrystalline silicon layer can be formed into the active layer and the amorphous silicon layer into the light shielding layer, by using only one mask. As compared with the existing method in which the light shielding layer is formed from a metal below the active layer by using an additional mask, the number of masking processes is reduced by one, which simplifies a fabricating process of the thin film transistor. In the drawings, sizes of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer, or an intervening layer may be present. It will be understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element or layer, or one or more intervening layer may be present. It will further be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the unique element or layer between these elements or layers, or one or more intervening layer may be present. Like reference numerals refer to like parts throughout the specification.

    [0056] In the present invention, the terms "first", "second" are used for purpose of describing, instead of indicating or implying relative importance.


    Claims

    1. A method for fabricating a thin film transistor, comprising:

    forming in sequence a light shielding layer (1), an insulating layer (2), and a semiconductor layer (3); and

    forming a pattern of the light shielding layer (1), the insulating layer (2), and the semiconductor layer (3) in a patterning process,

    wherein only one mask is used in the patterning process, the forming the pattern of the light shielding layer (1), the insulating layer (2), and the semiconductor layer (3) in the patterning process comprises:

    forming photoresist (4) in a first region (10) of the semiconductor layer (3);

    etching the semiconductor layer (3) to remove the semiconductor layer (3) outside the first region (10);

    etching the insulating (2) layer for a first time to remove the insulating layer (2) outside the first region (10);

    treating the photoresist (4), so that the photoresist (4) has a width which is smaller than a width of the first region (10), the treated photoresist (4) corresponding to a second region (20);

    etching the light shielding layer (1) and the semiconductor layer (3), to remove the light shielding layer (1) outside the first region (10) and the semiconductor layer (3) outside the second region (20), and

    etching the insulating layer (2) for a second time, so that the insulating layer (2) has a width which is larger than a width of the second region (20) and smaller than the width of the first region (10).


     
    2. The method of claim 1, characterized in that, etching the semiconductor layer (3) comprises:
    etching the semiconductor layer (3) for 110-120 seconds under conditions in which a flow ratio between SF6 and Cl2 is 10/400-40/400, and a RF generator inputs a power of 600-1000 W to plasma in a processing chamber.
     
    3. The method of claim 1, characterized in that, etching the insulating layer (2) for the first time comprises:
    etching the insulating layer (2) for 250-350 seconds under conditions in which a flow ratio between CF4 and O2 is 200/40-200/20, and a RF generator inputs a power of 600-1000 W to plasma in a processing chamber.
     
    4. The method of claim 1, characterized in that, treating the photoresist (4) comprises:
    ashing the photoresist (4).
     
    5. The method of claim 4, characterized in that, ashing the photoresist (4) comprises:
    ashing the photoresist (4) for 40-60 seconds under conditions in which a flow ratio between SF6 and O2 is 20/400-40/400, and a RF generator inputs a power of 350W-450 W to plasma in a processing chamber.
     
    6. The method of claim 1, characterized in that, etching the light shielding layer (1) and the semiconductor layer (3) comprises:
    etching the light shielding layer (1) and the semiconductor layer (3) for 110-120 seconds under conditions in which a flow ratio between SF6 and Cl2 is 10/400-40/400, and a RF generator inputs a power of 600-1000 W to plasma in a processing chamber.
     
    7. The method of claim 1, characterized in that, etching the insulating layer (2) for the second time comprises:

    etching the insulating layer (2) for 35-45 seconds under conditions in which a flow ratio between CF4 and O2 is 200/50-200/30, and a RF generator inputs a power of 600-1000 W to plasma in a processing chamber; and

    etching the insulating layer (2) for 18-22 seconds under conditions in which a flow ratio between SF6 and O2 is 10/200-30/200, and the RF generator inputs a power of 300-500 W to plasma in the processing chamber.


     
    8. The method of any one of claims 2-7, characterized in that, prior to forming the photoresist (4) in the first region (10) of the semiconductor layer (3), the method further comprises:

    forming a first amorphous silicon layer on a buffer layer (5) as the light shielding layer (1);

    forming the insulating layer (2) on the light shielding layer (1);

    forming a second amorphous silicon layer on the insulating layer (2); and

    annealing the second amorphous silicon layer, to convert the second amorphous silicon layer into a polycrystalline silicon layer as the semiconductor layer (3).


     
    9. The method of claim 8, characterized in that, the buffer layer (4) is made from SiNx, and the insulating layer (2) is made from SiOy, wherein 1<x<2 and 1<y<3.
     
    10. The method of claim 1, characterized in that, after etching the insulating layer (2) for the second time, the method further comprises:

    peeling off the photoresist (4) on the semiconductor layer (3);

    forming a gate insulating layer (6) on the semiconductor layer (3);

    forming a gate (7) on the gate insulating layer (6);

    forming an interlayer dielectric layer (8) on the gate (7); and

    forming a source (11) and a drain (12) on the interlayer dielectric layer (8), wherein the source (11) and the drain (12) are electrically connected with the semiconductor layer (3) by via holes in the interlayer dielectric layer (8) and the gate insulating layer (6).


     


    Ansprüche

    1. Verfahren zur Herstellung eines Dünnschichttransistors, umfassend:

    nacheinander Bilden einer Lichtabschirmschicht (1), einer Isolatorschicht (2) und einer Halbleiterschicht (3); und

    Bilden einer Struktur der Lichtabschirmschicht (1), der Isolatorschicht (2) und der Halbleiterschicht (3) durch ein Strukturierungsverfahren,

    wobei

    bei dem Strukturierungsverfahren nur eine Maske verwendet wird, wobei das Bilden der Struktur der Lichtabschirmschicht (1), der Isolatorschicht (2) und der Halbleiterschicht (3) durch das Strukturierungsverfahren umfasst:

    Bilden von Photoresist (4) in einem ersten Bereich (10) der Halbleiterschicht (3);

    Ätzen der Halbleiterschicht (3), um die Halbleiterschicht (3) außerhalb des ersten Bereichs (10) zu entfernen;

    erstmaliges Ätzen der Isolatorschicht (2), um die Isolatorschicht (2) außerhalb des ersten Bereichs (10) zu entfernen;

    Behandeln des Photoresists (4), so dass der Photoresist (4) eine Breite aufweist, die kleiner als eine Breite des ersten Bereichs (10) ist, wobei der behandelte Photoresist (4) einem zweiten Bereich (20) entspricht;

    Ätzen der Lichtabschirmschicht (1) und der Halbleiterschicht (3), um die Lichtabschirmschicht (1) außerhalb des ersten Bereichs (10) und die Halbleiterschicht (3) außerhalb des zweiten Bereichs (20) zu entfernen; und

    zweitmaliges Ätzen der Isolatorschicht (2), so dass die Isolatorschicht (2) eine Breite aufweist, die größer als eine Breite des zweiten Bereichs (20) und kleiner als die Breite des ersten Bereichs (10) ist.


     
    2. Verfahren gemäß Anspruch 1, dadurch gekennzeichnet, dass Ätzen der Halbleiterschicht (3) umfasst:
    Ätzen der Halbleiterschicht (3) für 110-120 Sekunden unter Bedingungen, bei denen ein Flussverhältnis zwischen SF6 und Cl2 10/400-40/400 beträgt und ein RF-Generator eine Leistung von 600-1000 W in Plasma in einer Verarbeitungskammer einspeist.
     
    3. Verfahren gemäß Anspruch 1, dadurch gekennzeichnet, dass erstmaliges Ätzen der Isolatorschicht (2) umfasst:
    Ätzen der Isolatorschicht (2) für 250-350 Sekunden unter Bedingungen, bei denen ein Flussverhältnis zwischen CF4 und O2 200/40-200/20 beträgt und ein RF-Generator eine Leistung von 600-1000 W in Plasma in einer Verarbeitungskammer einspeist.
     
    4. Verfahren gemäß Anspruch 1, dadurch gekennzeichnet, dass Behandeln des Photoresists (4) umfasst:
    Veraschen des Photoresists (4).
     
    5. Verfahren gemäß Anspruch 4, dadurch gekennzeichnet, dass Veraschen des Photoresists (4) umfasst:
    Veraschen des Photoresists (4) für 40-60 Sekunden unter Bedingungen, bei denen ein Flussverhältnis zwischen SF6 und O2 20/400-40/400 beträgt und ein RF-Generator eine Leistung von 350-450 W in Plasma in einer Verarbeitungskammer einspeist.
     
    6. Verfahren gemäß Anspruch 1, dadurch gekennzeichnet, dass Ätzen der Lichtabschirmschicht (1) und der Halbleiterschicht (3) umfasst:
    Ätzen der Lichtabschirmschicht (1) und der Halbleiterschicht (3) für 110-120 Sekunden unter Bedingungen, bei denen ein Flussverhältnis zwischen SF6 und Cl2 10/400-40/400 beträgt und ein RF-Generator eine Leistung von 600-1000 W in Plasma in einer Verarbeitungskammer einspeist.
     
    7. Verfahren gemäß Anspruch 1, dadurch gekennzeichnet, dass zweitmaliges Ätzen der Isolatorschicht (2) umfasst:

    Ätzen der Isolatorschicht (2) für 35-45 Sekunden unter Bedingungen, bei denen ein Flussverhältnis zwischen CF4 und O2 200/50-200/30 beträgt und ein RF-Generator eine Leistung von 600-1000 W in Plasma in einer Verarbeitungskammer einspeist; und

    Ätzen der Isolatorschicht (2) für 18-22 Sekunden unter Bedingungen, bei denen ein Flussverhältnis zwischen SF6 und O2 10/200-30/200 beträgt und der RF-Generator eine Leistung von 300-500 W in Plasma in der Verarbeitungskammer einspeist.


     
    8. Verfahren gemäß einem der Ansprüche 2-7, dadurch gekennzeichnet, dass das Verfahren vor dem Bilden des Photoresists (4) in dem ersten Bereich (10) der Halbleiterschicht (3) ferner umfasst:

    Bilden einer ersten amorphen Siliciumschicht auf einer Pufferschicht (5) als die Lichtabschirmschicht (1);

    Bilden der Isolatorschicht (2) auf der Lichtabschirmschicht (1);

    Bilden einer zweiten amorphen Siliciumschicht auf der Isolatorschicht (2); und

    Tempern der zweiten amorphen Siliciumschicht, um die zweite amorphe Siliciumschicht in eine polykristalline Siliciumschicht als die Halbleiterschicht (3) umzuwandeln.


     
    9. Verfahren gemäß Anspruch 8, dadurch gekennzeichnet, dass die Pufferschicht (4) aus SiNx besteht und die Isolatorschicht (2) aus SiOy besteht, wobei 1 < x < 2 und 1 < y < 3.
     
    10. Verfahren gemäß Anspruch 1, dadurch gekennzeichnet, dass das Verfahren nach dem zweitmaligen Ätzen der Isolatorschicht (2) ferner umfasst:

    Abziehen des Photoresists (4) auf der Halbleiterschicht (3);

    Bilden einer Gate-Isolatorschicht (6) auf der Halbleiterschicht (3);

    Bilden eines Gates (7) auf der Gate-Isolatorschicht (6);

    Bilden einer Zwischenschichtdielektrikumschicht (8) auf dem Gate (7); und

    Bilden einer Source (11) und einer Drain (12) auf der Zwischenschichtdielektrikumschicht (8), wobei die Source (11) und die Drain (12) durch Kontaktlöcher in der Zwischenschichtdielektrikumschicht (8) und der Gate-Isolatorschicht (6) elektrisch mit der Halbleiterschicht (3) verbunden sind.


     


    Revendications

    1. Procédé de fabrication d'un transistor à couche mince, comprenant :

    la formation, l'une après l'autre, d'une couche de blocage de la lumière (1), d'une couche isolante (2), et d'une couche de semi-conducteur (3) ; et

    la formation d'un motif constitué de la couche de blocage de la lumière (1), de la couche isolante (2), et de la couche de semi-conducteur (3), dans un processus de formation de motif,

    dans lequel un seul masque est utilisé dans le processus de formation de motif, la formation du motif constitué de la couche de blocage de la lumière (1), de la couche isolante (2), et de la couche de semi-conducteur (3) dans le processus de formation de motif comprenant :

    la formation d'un photorésist (4) dans une première région (10) de la couche de semi-conducteur (3) ;

    la gravure de la couche de semi-conducteur (3) pour enlever la couche de semi-conducteur (3) située en dehors de la première région (10) ;

    la gravure de la couche isolante (2) une première fois, pour enlever la couche isolante (2) située en dehors de la première région (10) ;

    le traitement du photorésist (4), de telle sorte que le photorésist (4) ait une largeur qui est inférieure à une largeur de la première région (10), le photorésist traité (4) correspondant à une deuxième région (20) ;

    la gravure de la couche de blocage de la lumière (1) et de la couche de semi-conducteur (3), pour enlever la couche de blocage de la lumière (1) située en dehors de la première région (10) et la couche de semi-conducteur (3) située en dehors de la deuxième région (20), et

    la gravure de la couche isolante (2) une deuxième fois, de telle sorte que la couche isolante (2) ait une largeur qui est supérieure à une largeur de la deuxième région (20) et inférieure à la largeur de la première région (10).


     
    2. Procédé selon la revendication 1, caractérisé en ce que la gravure de la couche de semi-conducteur (3) comprend :
    la gravure de la couche de semi-conducteur (3) pendant 110 à 120 secondes dans des conditions dans lesquelles un rapport de débit entre SF6 et Cl2 est de 10/400 à 40/400, et un générateur RF apporte une puissance de 600 à 1 000 W à un plasma dans une chambre de traitement.
     
    3. Procédé selon la revendication 1, caractérisé en ce que la gravure de la couche isolante (2) une première fois comprend :
    la gravure de la couche isolante (2) pendant 250 à 350 secondes dans des conditions dans lesquelles un rapport de débit entre CF4 et O2 est de 200/40 à 200/20, et un générateur RF apporte une puissance de 600 à 1 000 W à un plasma dans une chambre de traitement.
     
    4. Procédé selon la revendication 1, caractérisé en ce que le traitement du photorésist (4) comprend :
    la calcination du photorésist (4).
     
    5. Procédé selon la revendication 4, caractérisé en ce que la calcination du photorésist (4) comprend :
    la calcination du photorésist (4) pendant 40 à 60 secondes dans des conditions dans lesquelles un rapport de débit entre SF6 et O2 est de 20/400 à 40/400, et un générateur RF apporte une puissance de 350 à 450 W à un plasma dans une chambre de traitement.
     
    6. Procédé selon la revendication 1, caractérisé en ce que la gravure de la couche de blocage de la lumière (1) et de la couche de semi-conducteur (3) comprend :
    la gravure de la couche de blocage de la lumière (1) et de la couche de semi-conducteur (3) pendant 110 à 120 secondes dans des conditions dans lesquelles un rapport de débit entre SF6 et Cl2 est de 10/400 à 40/400, et un générateur RF apporte une puissance de 600 à 1 000 W à un plasma dans une chambre de traitement.
     
    7. Procédé selon la revendication 1, caractérisé en ce que la gravure de la couche isolante (2) une deuxième fois comprend :

    la gravure de la couche isolante (2) pendant 35 à 45 secondes dans des conditions dans lesquelles un rapport de débit entre CF4 et O2 est de 200/50 à 200/30, et un générateur RF apporte une puissance de 600 à 1 000 W à un plasma dans une chambre de traitement ; et

    la gravure de la couche isolante (2) pendant 18 à 22 secondes dans des conditions dans lesquelles un rapport de débit entre SF6 et O2 est de 10/200 à 30/200, et le générateur RF apporte une puissance de 300 à 500 W à un plasma dans la chambre de traitement.


     
    8. Procédé selon l'une quelconque des revendications 2 à 7, caractérisé en ce que, avant la formation du photorésist (4) dans la première région (10) de la couche de semi-conducteur (3), le procédé comprend en outre :

    la formation d'une première couche de silicium amorphe sur une couche tampon (5) comme couche de blocage de la lumière (1) ;

    la formation de la couche isolante (2) sur la couche de blocage de la lumière (1) ;

    la formation d'une deuxième couche de silicium amorphe sur la couche isolante (2) ; et

    le recuit de la deuxième couche de silicium amorphe, pour convertir la deuxième couche de silicium amorphe en une couche de silicium polycristallin comme couche de semi-conducteur (3).


     
    9. Procédé selon la revendication 8, caractérisé en ce que la couche tampon (4) se compose de SiNx, et la couche isolante (2) se compose de SiOy, avec 1 < x < 2 et 1 < y < 3.
     
    10. Procédé selon la revendication 1, caractérisé en ce que, après la gravure de la couche isolante (2) une deuxième fois, le procédé comprend en outre :

    le décollement du photorésist (4) présent sur la couche de semi-conducteur (3) ;

    la formation d'une couche isolante de grille (6) sur la couche de semi-conducteur (3) ;

    la formation d'une grille (7) sur la couche isolante de grille (6) ;

    la formation d'une couche diélectrique intercalaire (8) sur la grille (7) ; et

    la formation d'une source (11) et d'un drain (12) sur la couche diélectrique intercalaire (8), la source (11) et le drain (12) étant connectés électriquement à la couche de semi-conducteur (3) par des trous traversants dans la couche diélectrique intercalaire (8) et la couche isolante de grille (6).


     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description