(19)
(11)EP 3 389 051 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
09.09.2020 Bulletin 2020/37

(21)Application number: 16885510.4

(22)Date of filing:  18.01.2016
(51)International Patent Classification (IPC): 
G06N 3/063(2006.01)
G06F 9/30(2018.01)
G11C 13/00(2006.01)
G06F 13/00(2006.01)
G11C 5/02(2006.01)
G11C 7/10(2006.01)
G06F 17/16(2006.01)
G06F 7/00(2006.01)
G06J 1/00(2006.01)
(86)International application number:
PCT/CN2016/071254
(87)International publication number:
WO 2017/124237 (27.07.2017 Gazette  2017/30)

(54)

MEMORY DEVICE AND DATA-PROCESSING METHOD BASED ON MULTI-LAYER RRAM CROSSBAR ARRAY

SPEICHERVORRICHTUNG UND DATENVERARBEITUNGSVERFAHREN BASIEREND AUF EINER MEHRSCHICHTIGEN RRAM-CROSSBAR-ANORDNUNG

DISPOSITIF DE MÉMOIRE ET PROCÉDÉ DE TRAITEMENT DE DONNÉES SUR LA BASE DE RÉSEAU CROSSBAR MULTICOUCHE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(43)Date of publication of application:
17.10.2018 Bulletin 2018/42

(73)Proprietors:
  • Huawei Technologies Co., Ltd.
    Longgang Shenzhen, Guangdong 518129 (CN)
  • Nanyang Technological University
    Singapore 639798 (SG)

(72)Inventors:
  • YU, Hao
    Singapore 639798 (SG)
  • WANG, Yuhao
    Singapore 639798 (SG)
  • ZHAO, Junfeng
    Shenzhen Guangdong 518129 (CN)
  • YANG, Wei
    Shenzhen Guangdong 518129 (CN)
  • XIAO, Shihai
    Shenzhen Guangdong 518129 (CN)
  • NI, Leibin
    Singapore 639798 (SG)

(74)Representative: Kreuz, Georg Maria 
Huawei Technologies Duesseldorf GmbH Riesstraße 25
80992 München
80992 München (DE)


(56)References cited: : 
WO-A1-2011/133139
CN-A- 1 138 719
CN-A- 102 169 720
US-B2- 7 835 174
WO-A1-2014/109771
CN-A- 101 840 995
US-A1- 2010 046 275
  
  • Ping Chi ET AL: "SEAL-lab Processing-in-Memory in ReRAM-based Main Memory", , 30 November 2015 (2015-11-30), XP055524308, Retrieved from the Internet: URL:https://pdfs.semanticscholar.org/ef4e/ bf4effc38ddebe1f87b8bfe0ed68fca88bac.pdf [retrieved on 2018-11-15]
  • LEIBIN NI ET AL: "An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar", 2016 21ST ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), IEEE, 25 January 2016 (2016-01-25), pages 280-285, XP032877600, DOI: 10.1109/ASPDAC.2016.7428024 [retrieved on 2016-03-07]
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

TECHNICAL FIELD



[0001] The present invention relates to the storage field, and more specifically, to a memory device, and a data processing method based on a multilayer RRAM crossbar array.

BACKGROUND



[0002] Currently, many applications are related to complex big data computing such as fingerprint recognition and machine learning. For current big data computing, performance bottlenecks of a computing system mainly lie in the following two aspects:
Memory wall (memory wall): With development of technologies, processor performance is continuously improving. However, memory performance improves quite slowly. Consequently, memory performance becomes a "short slab" for improving overall system performance, and this is referred to as a memory wall. Specifically, connection and communication between a processor and a memory are implemented by using an input/output (Input/Output, I/O) bus. Limited by hardware, the I/O bus has limited bandwidth. Consequently, in most time, the processor is in an idle state of waiting for memory.

[0003] Power wall (power wall): Currently, most memories are volatile memories. Therefore, to prevent a data loss, the volatile memories need to be energized all along. This leads to high dynamic power consumption and high static power consumption of the memories.

[0004] Generally, the following solutions are provided to the foregoing two problems.

[0005] A solution to the memory wall: A logic unit (or logic circuit) may be added to a memory, so that data is directly computed in the memory, that is, in-memory computing. Using summation of 10 numbers as an example, if the memory has only a data storage function, the processor needs to read the 10 numbers from the memory through an I/O bus, and sum the 10 numbers. If the memory has a logic operation function, the memory can directly compute the sum of the 10 numbers, and then send a computing result to the processor through the I/O bus. It may be found, from a comparison between the foregoing two implementations, that a memory with the logic operation function reduces transmission pressure of the I/O bus by 90%, so that memory wall restriction can be effectively mitigated.

[0006] A solution to the power wall: A non-volatile memory may be used to replace the volatile memory. Because the memory is non-volatile, a loss of data in the memory caused by power interruption does not occur. Therefore, in a data processing process, the entire memory does not need to be energized all along. In this way, power consumption is effectively reduced.

[0007] Development of a resistive random access memory (Resistive Random Access Memory, RRAM) technology makes it possible to resolve the foregoing two problems at the same time. First, a core device of an RRAM is a memristor (that is, a resistor in the RRAM is a memristor). The RRAM is non-volatile and can reduce power consumption. Further, as shown in FIG. 1, the RRAM has a crossbar array structure (therefore, the RRAM is generally referred to as an RRAM crossbar array, or an RRAM crossbar). The RRAM crossbar may be single-layer or multilayer. In a multilayer RRAM crossbar, an output of a layer may be used as an input of a next layer. A resistor array is disposed at each layer of the RRAM crossbar. If the resistor in the RRAM is considered as a neuron in a neural network, it may be found that the RRAM crossbar is structurally very similar to the neural network. Such a structure is very suitable for logic operation. Specifically, various logic operations may be implemented by configuring a quantity of layers of the RRAM crossbar, a size of a resistor array at each layer of RRAM crossbar, and a resistance value of each resistor.

[0008] In the prior art, a logic operation capability of the RRAM crossbar is already developed and used to some extent. FIG. 2 shows a conventional circuit structure of an RRAM crossbar that can perform a logic operation. First, a resistance value of a resistor in the RRAM crossbar needs to be configured according to a desired logic operation function (such as summation, exclusive OR, and matrix multiplication). Using matrix multiplication Y = ΦX as an example, first, each element in a matrix Φ may be stored in the RRAM crossbar. For example, a resistor Gij in FIG. 2 corresponds to an element in the ith row and the jth column of Φ, and a resistance value of Gij represents a value of the corresponding element. Then, in actual matrix multiplication, elements of a matrix X are first converted from digital parameters x1...xn into analog parameters (analog voltage signals), and are then input into rows of the RRAM. Then a point multiplication operation is performed on the elements in the matrix by using voltage, current, and resistance relationships between rows and columns in the RRAM crossbar, so as to obtain computing results V1 to Vm. Finally, the computing results (analog voltage parameters) are converted into digital parameters (such as y1 and y2) and are then output.

[0009] It may be learned, from the description above, that a conventional RRAM crossbar uses an analog parameter to perform a logic operation, and such an operation manner mainly has the following two disadvantages:
First, a large quantity of digital-to-analog converters (Digital to Analog Converter, DAC) and analog-to-digital converters (Analog to Digital Converter, ADC) are required for DA and AD conversion operations on signals. The converters and the conversion operations are time-consuming and power-consuming.

[0010] Second, to implement specific operation logic, the resistor in the RRAM needs to be configured or programmed in advance. In practice, the resistance value of the resistor in the RRAM is determined according to an integral of a current that flows through the resistor. However, characteristics of resistor elements in the RRAM are not constant and may fluctuate to some extent. Consequently, resistance values obtained by an integral operation on a same current may be different. Specifically, as shown in (a) in FIG. 3, affected by fluctuation of element characteristics, a resistor has different state conversion curves (from an Ron state (also referred to as a low resistance state, or an on-state) to an intermediate state (intermediate state) and then to an Roff state (also referred to as a high resistance state, or an off-state), resulting in inaccuracy of resistance programming. In addition, it may be learned, from (b) in FIG. 3, that such inaccuracy is especially apparent in the intermediate state of the resistor.

[0011] WO 2014-109771 relates to a method for implementing nonvolatile memory array logic includes configuring a crosspoint memory array in a first configuration and applying an input voltage to the crosspoint array in the first configuration to produce a setup voltage.

[0012] XP055524308, "Processing-in-Memory in ReRAM-based Main Memory", relates to a novel process in memory (PIM) system, utilizing metal-oxide resistive random access memory (ReRAM) as main memory and also for computation. This document shows a ReRAM memory device comprising a controller and memory units, each comprising a logic module including a FF sub-array, wherein each memristor in the FF subarray stores a 6 bit data, wherein the memory unit is configured to perform a dot product: 6 bits input data are multiplied by a 6 bit stored data.

[0013] WO 2011-133139 relates to a method for operating a circuit (100) containing memristive devices (130) senses respective states of a plurality of memristive devices (130) and refreshes the respective states of the memristive devices (130) according to the states sensed. This document discloses a RRAM crossbar memory comprising an array storing 0s and 1s and configured to provide a dot product of an input vector associated to voltages of the row lines and a vector of state values stored in the memristors column.

SUMMARY



[0014] This application provides a memory device, to improve accuracy of a logic operation of a conventional RRAM crossbar. The present invention is as defined in the appended independent claims. Further implementations are disclosed in the appended dependent claims, description, and figures.

[0015] This application improves accuracy of the logic operation of the RRAM crossbar.

BRIEF DESCRIPTION OF DRAWINGS



[0016] To describe the technical solutions of the present invention more clearly, the following briefly describes the accompanying drawings describing preferred embodiments of the present invention.

FIG. 1 is a schematic diagram of a physical structure of an RRAM crossbar;

FIG. 2 is a structural diagram of a conventional logic circuit based on an RRAM crossbar;

FIG. 3 is a curve of a resistance characteristic of a resistor in an RRAM crossbar;

FIG. 4 is a schematic structural diagram of a memory device according to an embodiment of the present invention;

FIG. 5 shows an example of a bus design manner of a control module 45;

FIG. 6 is a schematic structural diagram of a layer of an RRAM crossbar;

FIG. 7 is a circuit diagram of the first layer of RRAM crossbar in a three-layer RRAM crossbar used to implement Boolean matrix multiplication;

FIG. 8 is a circuit diagram of the second layer of RRAM crossbar in a three-layer RRAM crossbar used to implement Boolean matrix multiplication; and

FIG. 9 is a circuit diagram of the third layer of RRAM crossbar in a three-layer RRAM crossbar used to implement Boolean matrix multiplication.


DESCRIPTION OF EMBODIMENTS



[0017] FIG. 4 is a schematic structural diagram of a memory device according to an embodiment of the present invention. It may be learned, from FIG. 4, that the memory device 40 is in an H-tree structure on the whole. In this structure, a storage module 43 (or referred to as a data module, a data array, or the like) is paired with a logic module 44 (or referred to as a logic circuit, a logic operation circuit, an in-memory logic, or the like).

[0018] Optionally, in an embodiment, both the storage module 43 and the logic module 44 may be RRAM crossbars. Further, the storage module 43 may be a single-layer RRAM crossbar, and the logic module 44 is a multilayer RRAM crossbar. Certainly, a type of the storage module 43 is not specifically limited in this embodiment of the present invention, and another type of storage medium may be used. In addition, even if both the storage module 43 and the logic module 44 are RRAM crossbars, a quantity of layers of the RRAM crossbar is not specifically limited in this embodiment of the present invention. For example, the storage module 43 may be designed as a multilayer RRAM crossbar (it has to be noted that a single-layer RRAM crossbar can also implement a simple logic operation). Still referring to FIG. 4, the memory device 40 mainly includes four parts: a block decoder 41 (Block decoder), a storage module 43, a logic module 44, and a control module 45. The control module 45 may be a CMOS-based control module. The storage module 43, the logic module 44, and the control module 45 may be included in a memory unit 42 (or referred to as a data/logic pair). In FIG. 4, the control module 45 is separately connected to the storage module 43, the logic module 44, and the block decoder 41, and is connected to the processor 47 (such as a CPU) through the block decoder 41. The control module 45 is configured to receive and parse an instruction of the processor 47, and may further be responsible for data exchange or transmission between the storage module 43 and the logic module 44. The block decoder 41 may transfer the instruction delivered by the processor 47 to a control module 45 of a memory unit 42 corresponding to the instruction. In addition, in an embodiment, an address search function of the memory unit 42 may be integrated in the block decoder 41, and remaining control functions are all integrated in the control module 45.

[0019] It may be learned, from the foregoing description, that the control module 45 may be connected to the block decoder 41, but the block decoder 41 may be responsible only for transferring the instruction delivered by the processor 47 to the control module 45 of the corresponding memory unit 42. Therefore, from another perspective, the control module 45 may be considered as a main body for receiving and parsing the instruction of the processor. Using FIG. 5 as an example, the following describes, in detail, an internal structure of the control module and how the control module processes an instruction.

[0020] FIG. 5 shows an example of a bus design manner of a control module. The control module 45 may include an instruction queue 451, an instruction decoder 452, an address decoder 453, and an SRAM array 454, and a connection manner therebetween may be shown in FIG. 5. Considering that an operating frequency of the memory device may be lower than an operating frequency of the processor, the instruction queue 451 may be disposed in the control module 45 to buffer the instruction delivered by the processor 47, so as to reduce a wait time of the processor 47. The instruction decoder 452 parses a to-be-executed instruction (which may be, for example, an instruction of data reading, data storage, or memory computing, and is described in detail in the following), and then performs a corresponding operation. The address decoder 453 may decompose address information in the instruction into row/column information of the storage module 43 or row/column information of the logic module 44. The SRAM array 454 may be configured to temporarily store data that is read from the storage module 43 or the logic module 44, and according to the instruction, write the data into the storage module 43 or the logic module 44, or transfer the data back to the external processor 47.

[0021] A format and a type of the instruction delivered by the processor 47 to the memory device 40 are not specifically limited in this embodiment of the present invention. For example, the type of the instruction delivered by the processor 47 to the memory device 40 or a type of an instruction that needs to be parsed by the control module 45 may include 4 types of instructions listed in Table 1.
Table 1 Types and parameters of instructions needing to be parsed by a control module 45
InstructionOperand 1Operand 2OperationApplication requiring this operation
SW (Store Word) Data Address Store data in an address Write (ordinary write) in a storage module, write (logic configuration) in a logic module, data input configuration in a logic module, write-back after memory computing
Address 1 Address 2 Read data from the address 1 and store the data into the address 2
LW (Load Word) Address - Read data from an address to a processor Ordinary read
ST (Start) Memory unit serial number - Turn on all row/column switches of a logic module in a memory unit corresponding to this serial number Performing memory computing
WT (Wait) - - Wait for a completion signal of memory computing of a logic module Preventing an instruction in an instruction queue from being operated during memory computing


[0022] Using a memory computing process as an example, first, logic configuration is performed on the logic module 44, that is, a resistance value of a resistor in the logic module 44 is configured so that the logic module 44 can implement particular operation logic. Then an input signal is provided to the logic module 44. That is, data requiring a logic operation is input into the logic module 44. Then, memory computing may be performed in the logic module 44 according to the input signal and configured operation logic. The following describes in detail a memory computing process with reference to the instructions in Table 1.

[0023] When memory computing is needed, the processor 47 may deliver the following instructions to the memory device 40.

Instruction 1: an SW instruction, which is used to write data in the processor 47 or the storage module 43 into the logic module 44 to configure a resistance value of the RRAM in the logic module 44, so that the logic module can implement particular logic such as summation, exclusive OR, and multiplication.

Instruction 2: an SW instruction, which is used to write data in the processor 47 or the storage module 43 into an input column (a voltage

input by a word line (word line) in FIG. 6) of the logic module 44. A particular logic operation on input data can be implemented in the logic module based on previously configured operation logic. For example, the logic module 44 implements a+b summation logic. b may be stored into the logic module by using the instruction 1, then a is input by using the instruction 2, and then a and b are summed.

Instruction 3: an ST instruction, which is used to turn on all row/column switches of the logic module 44, so that a current flows through all rows/columns of the logic module 44.

Instruction 4: a WT instruction. When a complex logic operation is implemented by using an RRAM crossbar, multiple layers of RRAM crossbars are needed in the logic module 44. In this case, it takes a time to complete computing of the RRAM crossbars. Therefore, the ST instruction may be used to instruct the control module 45 to wait for completion of memory computing of the logic module 44, and then execute a subsequent instruction.

Instruction 5: an SW instruction, which may be used to: after memory computing is completed, write data obtained by means of operation by the logic module 44 back into the storage module 43. It should be noted that for particular logic, logic configuration needs to be performed on the logic module 44 only once, and the instruction 1 may not be necessarily executed each time before memory computing is performed. That is, a same logic operation can be implemented for different data by changing data in an input column of the logic module 44.



[0024] A process in which the control module 45 performs memory computing according to the instruction is described above in detail. It should be noted that the control module 45 may also perform ordinary data read/write according to an instruction. This process is similar to that in the prior art, and is not described herein in detail. Using FIG. 6 as an example, the following briefly describes a logic operation process of the logic module 44 based on an RRAM crossbar.

[0025] In FIG. 6, a comparator circuit is disposed at the bottom of each bit line (bit line). In practice, the comparator circuit may be a sense amplifier (Sense Amplifier, SA). The SA includes a constant resistor Rs (for example, Rs<Ron<Roff) with a relatively small resistance value, and an operational amplifier, so as to convert a current signal in a column (that is, a bit line) into a voltage, and compare the voltage with a voltage threshold at the first layer of RRAM crossbar to obtain a computing result of this column. Computing formulas for each column are as follows:



In a formula (1),

indicates a voltage of a word line (word line) of the ith row,

indicates a voltage of a bit line (bit line) of the jth column, gij indicates an admittance (a reciprocal of Rij) corresponding to a resistor Rij,

indicates a voltage threshold corresponding to the jth column, and

indicates an output voltage of the jth column. In addition, FIG. 6 merely shows a circuit structure of a single-layer RRAM crossbar. If the logic module 44 includes a multilayer RRAM crossbar, a column output

of a layer may be used as a row input of a next layer. All layers may have a same structure or different structures. A column output

of a last layer may be used as a final output of the logic module 44.

[0026] In order to use the RRAM crossbar to implement a particular logic operation (or function), the following steps may be performed to configure the resistance value of the resistor in the RRAM crossbar and a voltage threshold of each column (that is, the resistance value in the RRAM crossbar and the voltage threshold of each column determine logic actually implemented by the RRAM crossbar):

Step 1: In software (such as MatLab and Octave), determine a quantity of layers of the RRAM crossbar required for implementing the particular logic, and a size of rows and columns of each layer.

Step 2: Compute a resistance value of a resistor at each layer of RRAM crossbar, and a voltage threshold of the comparator circuit.

Step 3: Use an instruction to store the computed resistance value of the resistor in the RRAM crossbar into a corresponding resistor, and set the voltage threshold of the comparator circuit.

Step 4: Implement the particular logic computing by using hardware (a circuit of the logic module 44).



[0027] Disadvantages of the RRAM crossbar based on an analog signal are described above in detail with reference to FIG. 2 and FIG. 3, for example, excessive AD and DA conversion operations, and errors existing in a resistance value configuration process. To overcome the disadvantages, the following describes, with reference to specific embodiments, specific implementations of an RRAM crossbar based on a digital signal.

[0028] First, it may be learned, from (b) in FIG. 3, that in comparison with an intermediate state, reliability is higher if the resistor in the RRAM crossbar is set to Ron or Roff (a process of configuring the resistor in the RRAM crossbar may be referred to as RRAM programming). That is, if only the resistor in the RRAM crossbar is set to Ron or Roff, resistor configuration errors can be reduced, and logic operation reliability can be improved. Therefore, the resistor in the RRAM crossbar in this embodiment of the present invention is either set to an Ron state or set to an Roff state. Roff indicates a Boolean value "0" (or digit "0"), and Ron indicates a Boolean value "1" (or digit "1").

[0029] Then a row input interface of the RRAM crossbar may be designed as a pure digital interface, without a need for AD conversion (it may be learned, from FIG. 6, that a row input of the RRAM crossbar is a voltage signal, provided that the input voltage signal includes a high level and a low level, where the high level corresponds to the Boolean value 1, and the low level corresponds to the Boolean value 0; however, voltage values of the high level and the low level are not specifically limited in this embodiment of the present invention). By means of the foregoing settings, the logic module based on an analog signal shown in FIG. 2 may be converted into a logic module based on a digital signal.

[0030] Referring to FIG. 6, a resistor Rs in an SA of each column may be a small resistor with a constant resistance value, and Roff » Ron » Rs may be satisfied for Roff, Ron, and RS. A comparator circuit (using an SA as an example in the figure) is connected to an end of each column. Referring to a formula (2), the SA compares a voltage of this column with a voltage threshold of the column to obtain an output voltage of this column. The output voltage is either a voltage (low level) corresponding to the Boolean value 0 or a voltage (high level) corresponding to the Boolean value 1.

[0031] It should be understood that particular logic can be implemented by configuring the resistor in the RRAM crossbar and the voltage threshold in each column of the word line.

[0032] Using Boolean matrix (elements in the matrix are all 0 and 1) multiplication the following describes in detail how to configure the resistance value of the resistor in the RRAM crossbar and configure the voltage threshold of the word line in the RRAM crossbar to implement the Boolean matrix multiplication.

[0033] For ease of understanding, a computing process of matrix multiplication Y = ΦX is described first. General forms and vector forms of matrices X and Φ are as follows:





[0034] A product of the matrix Φ and the matrix X may alternatively be considered as a product of a column vector

and a row vector [X1 X2X3 K]. For details, refer to a formula (4):



[0035] It may be learned, from formulas (3) and (4), that each element of the matrix Y is a result of point multiplication of a row of the matrix Φ and a column of the matrix X (that is, computing an inner product).

[0036] In this embodiment of the present invention, first, a logic module is provided. The logic module may implement, based on a multilayer RRAM crossbar, point multiplication operation logic of a Boolean vector (the Boolean vector is a vector whose elements are 0 or 1). Based on this, a memory device is configured to implement a Boolean matrix (the Boolean matrix is a matrix whose elements are 0 or 1) multiplication operation is further provided in this embodiment of the present invention. The memory device may include one or more logic modules that can implement Boolean vector multiplication. Because a Boolean matrix multiplication operation may be decomposed into multiple point multiplication operations of Boolean vectors, the memory device may decompose the Boolean matrix multiplication operation into multiple point multiplication operations of Boolean vectors, and then distribute the multiple point multiplication operations of Boolean vectors to the one or more logic modules. The one or more logic modules jointly implement the Boolean matrix multiplication operation.

[0037] The following describes, in detail, a structure and functions of a multilayer RRAM crossbar for implementing a Boolean vector point multiplication operation by using a Boolean vector [φ0,j, φ1,j,...φN-1,j] (which may be considered as a vector formed by elements of any row in the Boolean matrix Φ, and corresponds to the Boolean vector A mentioned above) and a Boolean vector [xi,0, xi,1,...xi,N-1] (which may be considered as a Boolean vector formed by elements of any column in the matrix X, and corresponds to the Boolean vector B mentioned above) as an example.

[0038] The multilayer RRAM crossbar may specifically include three layers of RRAM crossbars. A circuit shown in FIG. 7 is used at the first layer of RRAM crossbar in the three-layer RRAM crossbar.

[0039] In FIG. 7, the first layer of RRAM crossbar includes an N×N resistor array. N resistors in each column of the N×N resistor array respectively indicate the Boolean vector [φ0,j, φ1,j,...φN-1,j]. For example, it is assumed that N is 8, and 8 elements of [φ0,j, φ1,j,...φN-1,j] are 10101010 sequentially. Therefore, resistance values of the first column in the N×N resistor array of the first layer of RRAM crossbar are Ron (corresponding to 1), Roff (corresponding to 0), Ron, Roff, Ron, Roff, Ron, and Roff sequentially, and a resistance configuration of each column in the N×N resistor array is the same as a resistance configuration of the first column.

[0040] A comparator circuit is disposed at the bottom of each column (bit line) of the N×N resistor array (an SA is used as an example of the comparator circuit in the following). The comparator circuit may include a constant resistor Rs with a relatively small resistance value. The comparator circuit includes a comparator. A

[0041] function of the comparator circuit is converting a current signal in each column into a voltage signal, and comparing the voltage signal with a voltage threshold Vth1 of the column, so as to determine whether a computing result of this column is 0 or 1. The voltage threshold of each column in the N×N resistor array may be set to VrgonRs(2j+1)/2 sequentially, where j is a positive integer ranging from 0 to N-1. Vr indicates an actual voltage (that is, a high level) when an input of X is 1, gon indicates an admittance corresponding to a resistor Ron, and Rs indicates a resistance value of a sampling resistor. It may be learned, from this formula, that thresholds of columns in the N×N resistor array increase sequentially and are step-shaped on the whole (as shown in FIG. 7).

[0042] The following describes logic functions which are implemented by the first layer of RRAM crossbar.

[0043] A voltage signal corresponding to the Boolean vector [xi,0, xi,1,...xi,N-1] is input into the first layer of RRAM crossbar (that is, a high level is input into a word line corresponding to an element 1 in the Boolean vector [xi,0, xi,1,...xi,N-1], and a low level is input into a word line corresponding to an element 0 in the Boolean vector [xi,0, xi,1,...xi,N-1] ). As described above, a resistance value of a resistor in each column at the first layer of RRAM crossbar is a resistance value corresponding to the Boolean vector [φ0,j, φ1,j,...φN-1,j]. When all row/column switches of the first layer of RRAM crossbar are turned on, point multiplication logic of the Boolean vector [φ0,j, φ1,j,...φN-1,j] and the Boolean vector [xi,0, xi,1,...xi,N-1] is implemented on each bit line of the first layer of RRAM crossbar based on a relationship between a voltage and a current. A result of the point multiplication logic may be represented by a current on each word line. Then, at an output end of the bit line, an SA connected to the word line of the first layer of RRAM crossbar outputs a voltage signal corresponding to a first computing result by setting the step-shaped voltage thresholds described above. The first computing result is an N-dimensional Boolean vector, first K elements of the first computing result is 1, remaining elements are 0, and K is a result of a point multiplication operation on the Boolean vector [φ0,j, φ1,j,...φN-1,j] and the Boolean vector [xi,0, xi,1,...xi,N-1]. For example, it is assumed that N=8 and K=3. By means of a logic operation of the first layer of RRAM crossbar, an output O1,j (0≤j≤N-1) result of the first layer of RRAM crossbar is 11100000. It may be understood as follows: all comparison results of SAs in columns 0 to 3 are that column voltages are greater than voltage thresholds, and all comparison results of SAs in columns 4 to 7 are that column voltages are less than voltage thresholds.

[0044] Next, a logic task of the second layer of RRAM crossbar and the third layer of RRAM crossbar in the three-layer RRAM crossbar is converting an output result of the first layer of RRAM crossbar into a binary representation of K. Still using K=3 as an example, the output result of the first layer of RRAM crossbar is 11100000, and the logic task of the second layer of RRAM crossbar and the third layer of RRAM crossbar is converting 11100000 into 11, that is, 3 in binary. The following further describes structures and logic functions of the second layer of RRAM crossbar and the third layer of RRAM crossbar (herein, the second layer of RRAM crossbar and the third layer of RRAM crossbar jointly complete the foregoing logic task, but this is not limited in this embodiment of the present invention; and the foregoing logic task may alternatively be implemented by one layer of RRAM crossbar or more than three layers of RRAM crossbars).

[0045] To implement the foregoing logic task, a structure shown in FIG. 8 may be used for the second layer of RRAM crossbar. In FIG. 8, the second layer of RRAM crossbar includes a (2N-1)×N resistor array. Resistance values of the (2j)th and (2j+1)th resistors in the jth column of resistors of the second layer of RRAM crossbar are Ron, and resistance values of remaining resistors are Roff, where 0≤j≤N-2. A resistance value of the (2N-1)th resistor in the (N-1)th column of resistors of the second layer of RRAM crossbar is Ron, and resistance values of remaining resistors are Roff. 2N-1 word lines of the second layer of RRAM crossbar may be connected to the bit line output end O1,j of the first layer of RRAM crossbar according to a connection relationship shown in FIG. 8. It should be noted that output ends of some bit lines of the first layer of RRAM crossbar require a negation operation before being connected to word lines of the second layer of RRAM crossbar. Referring to O1,j shown in FIG. 7, such a negation operation may be implemented by connecting to a device such as a comparator or a phase inverter. This is not specifically limited in this embodiment of the present invention. An end of each bit line at the second layer of RRAM crossbar is connected to a comparator circuit. A voltage threshold Vth2 of the comparator circuit may be set to VrgonRs/2. In addition, a positive pole and a negative pole of a comparator in an operation circuit need to be swapped (that is, the voltage threshold Vth2 is set at an in-phase input end of the comparator, and a reverse-phase input end is connected to the resistor Rs and the bit line) to obtain an output O2,j of the second layer, where 0≤j≤N-1.

[0046] A relationship between the output O2,j of the second layer of RRAM crossbar and the output of the first layer of RRAM crossbar may be expressed by a formula (5). That is, the formula (5) is a logic function to be implemented by the second layer of the RRAM crossbar.

Logic expressed by the formula (5) is actually exclusive-OR logic. That is, an exclusive-OR operation is performed pairwise on the first computing result output by the first layer of RRAM crossbar to obtain an intermediate computing result. The intermediate computing result is an N-dimensional vector. The (K-1)th element of the N-dimensional vector is 1, and remaining elements are 0. K is a result of a point multiplication operation on the Boolean vector [φ0,j, φ1,j,...φN-1,j] and the Boolean vector [xi,0, xi,1,...xi,N-1]. That an output result of the first layer of RRAM crossbar is 11100000 is used as an example. An obtained result is 00100000 after the logic operation of the second layer is performed. However, it should be noted that a structure of the RRAM crossbar for implementing the exclusive-OR logic is not specifically limited in this embodiment of the present invention, and FIG. 8 is merely an example. In practice, the exclusive-OR logic may alternatively be implemented by configuring resistance values of resistors and voltage thresholds in another manner.

[0047] The second layer of RRAM crossbar transfers the voltage signal corresponding to the intermediate computing result to the word lines of the second layer of RRAM crossbar. The output end O2,j of the jth bit line of the second layer of RRAM crossbar is connected to the input end of the jth word line of the third layer of RRAM crossbar. A logic circuit of the third layer of RRAM crossbar is shown in FIG. 9. The third layer of RRAM crossbar includes an N×n resistor array, where n is greater than or equal to a minimum quantity of bits required for expressing the integer N in binary (for example, N=8, a binary representation of 8 is 1000, that is, the binary representation of 8 requires 4 bits, and therefore, n is greater than or equal to 4). Resistance values of N rows of resistors are set so that the resistors indicate binary 1 to N sequentially from top to bottom. In this way, when the voltage signal corresponding to the intermediate operation result output by the second layer of RRAM crossbar is used as an input voltage signal of the third layer of RRAM crossbar, because the (K-1)th element of the intermediate operation result is a Boolean value 1 and remaining elements are a Boolean value 0, the (K-1)th bit line of the third layer of RRAM crossbar inputs a voltage signal (high level) corresponding to the Boolean value 1, and remaining bit lines each input a voltage signal (low level) corresponding to the Boolean value 0. From a logic perspective, by means of such a configuration, an operation result (corresponding to the second operation result described above) finally output by the third layer of RRAM crossbar is a binary representation of K. That is, a binary representation of an integer corresponding to resistors in the (K-1)th row of the third layer of RRAM crossbar (it may be learned, as described above, that the resistors in the (K-1)th row correspond to the binary representation of the integer K) is selected as a final operation result. An output of the third layer of RRAM crossbar is a voltage signal corresponding to the final operation result.

[0048] Still using N=8 and K=3 as an example, a logic output of the second layer of RRAM crossbar is 00100000. A logic correspondence between an input and an output of the third layer of RRAM crossbar is shown in the following table.
Table 2 Input and output comparison table of a third layer of RRAM crossbar
Logic input of a third layer of RRAM crossbarRow serial numberLogic output of a third layer of RRAM crossbar
00000000 None  
10000000 0 0001
01000000 1 0010
00100000 2 0011
00010000 3 0100
00001000 4 0101
00000100 5 0110
00000010 6 0111
00000001 7 1000


[0049] It may be learned, from the foregoing table, that an output corresponding to 00100000 is 0011, that is, a binary representation of 3.

[0050] It should be noted that if an input matrix is a non-Boolean matrix (for example, the input matrix is a positive real matrix), the matrix may be decomposed into a linear combination of multiple Boolean matrices by means of linear algebra. Then, operations are performed on the multiple Boolean matrices in the foregoing manner, and then results of the operations on the multiple Boolean matrices are linearly combined to obtain a matrix multiplication result corresponding to the real matrix. Details are not described again in this embodiment of the present invention.

[0051] A person of ordinary skill in the art may be aware that, in combination with the examples described in the embodiments disclosed in this specification, units and algorithm steps may be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed by hardware or software depends on particular applications and design constraint conditions of the technical solutions.


Claims

1. A memory device (40), wherein the memory device (40) comprises a control bus and multiple memory units (42), the multiple memory units (42) are connected to each other through the control bus, and each of the multiple memory units (42) comprises:

a control module (45), wherein the control module is connectable to a processor (47) through the control bus, and configured to receive and parse an instruction of the processor through the control bus, and the instruction of the processor comprises a logic operation instruction; and

a logic module (44), wherein the logic module (44) is connected to the control module (45), the logic module (44) comprises a multilayer of resistive random access memory, RRAM, crossbar array, for each memristor of the multilayer of RRAM crossbar array the corresponding resistance value is Ron or Roff, Ron indicates a Boolean value 1, Roff indicates a Boolean value 0, and the logic module (44) is a storage module configured to perform a Boolean operation by using the multilayer of RRAM crossbar array according to the logic operation instruction.

wherein the logic module (44) is configured to, according to the logic operation instruction, perform a dot product operation of a Boolean vector A and a Boolean vector B, A and B each indicates an N-dimensional Boolean vector, and N is a positive integer not less than 2;

wherein the first layer of RRAM crossbar array of the multilayer of RRAM crossbar array comprises a memristor array having N rows × N columns, for each row of the first layer of RRAM crossbar array, an input end of the memristors of the row are connected to a corresponding word line, for each column of the first layer of RRAM crossbar array, an output end of the memristors of the column are connected to a corresponding bit line, the N word lines of the first layer of RRAM crossbar array are connected to the control module (45), and the N bit lines of the first layer of RRAM crossbar array are respectively connected to other layers of RRAM crossbar array of the multilayer of RRAM crossbar array through N comparator circuits; wherein the logic module (44) comprises said N comparator circuits,

the first layer of RRAM crossbar array is configured to generate N current signals on the N bit lines, each of the currents on the corresponding bit line being generated according to voltage signals input by the N word lines , the resistance values of the corresponding memristors of the first layer of RRAM crossbar array and a corresponding resistor (Rs), a voltage value of the voltage signal input by the jth word line of the N word lines is a voltage value corresponding to Bj, the resistance value of each memristors of the jth row of the first layer of RRAM crossbar array is a resistance value corresponding to Aj, Bj is the jth element of the Boolean vector B, Aj is the jth element of the Boolean vector A, and a value of j ranges from 0 to N-1;

the N comparator circuits respectively configured to convert the N current signals into N voltage signals, and configured to compare the N voltage signals with voltage thresholds respectively corresponding to the N comparator circuits, so that output ends of the N bit lines which correspond to output ends of the N comparator circuits output a voltage signal corresponding to a first computing result, wherein the first computing result is an N-dimensional Boolean vector, first K elements of the first computing result are 1, remaining elements are 0, and K is an operation result of the dot product of A and B; and

the other layers of RRAM crossbar array are configured to receive the voltage signal corresponding to the first computing result from the output ends of the N bit lines, and configured to generate, according to the voltage signal corresponding to the first computing result and the resistance values of the plurality of memristors of the other layers of RRAM crossbar array, a voltage signal (O3,0....O3,n) corresponding to a second computing result, wherein the second computing result is a binary representation of K.


 
2. The memory device (40) according to claim 1, wherein the jth comparator circuit of the N comparator circuits comprises the corresponding resistor Rs of a constant resistance value and a comparator, one end of the resistor Rs is connected to the jth bit line in the N bit lines and the comparator, the other end of the resistor Rs is grounded, the corresponding voltage threshold of the jth comparator circuit is VrgonRs(2j+1)/2, Vr indicates a voltage value corresponding to a Boolean value 1, and gon indicates a reciprocal of Ron.
 
3. The memory device (40) according to claim 2, wherein the logic module (44) comprises at least three layers of RRAM crossbar array and the other layers of RRAM crossbar array comprise the second layer of RRAM crossbar array and the third layer of RRAM crossbar array;
the second layer of RRAM crossbar array comprises a (2N-1) rows × N columns memristors array, for each row of the second layer of RRAM crossbar array, an input end of the memristors of the row are connected to a corresponding word line, for each column of the second layer of RRAM crossbar array, an output end of the memristors of the column are connected to a corresponding bit line, and word lines of the second layer of RRAM crossbar array are connected to the output ends of the bit lines of the first layer of RRAM crossbar array;
the second layer of RRAM crossbar array configured to receive the voltage signal corresponding to the first computing result from the output ends of the bit lines of the first layer of RRAMs through the 2N-1 word lines, and perform a logic operation according to the voltage signal corresponding to the first computing result and the resistance values of the memristors of the second layer of RRAM crossbar array so as to obtain a voltage signal corresponding to an intermediate computing result:

wherein O1,j is a negation of a Boolean value corresponding to the voltage signal output by the jth bit line of the first layer of RRAM crossbar array, O1,j+1 is a Boolean value corresponding to the voltage signal output by the (j+1)th bit line of the first layer of RRAM crossbar array, and O2,j is a negation of a Boolean value corresponding to the voltage signal output by the jth bit line of the second layer of RRAM crossbar array;

the third layer of RRAM crossbar array comprises an N rows × n columns memristor array, for each row of the third layer of RRAM crossbar array, an input end of the memristors of the row are connected to a corresponding word line, for each column of the third layer of RRAM crossbar array, an output end of the memristors of the column are connected to a corresponding bit line, and n is greater than or equal to a minimum quantity of bits required for expressing the integer N in binary; and

the third layer of RRAM crossbar array configured to receive the voltage signal corresponding to the intermediate computing result from the N bit lines of the second layer of RRAM crossbar array through the N word lines of the third layer of RRAM crossbar array, and encode the intermediate computing result according to the voltage signal corresponding to the intermediate computing result and the resistance values of the memristors of the third layer of RRAM crossbar array, so as to obtain the voltage signal (O3,0....O3,n) corresponding to the second computing result.


 
4. The memory device (40) according to claim 3, wherein the jth word line of the third layer of RRAM crossbar array is connected to the jth bit line of the second layer of RRAM crossbar array, and the resistance values of the memristors of the jth row of the third layer of RRAM crossbar array correspond to a binary representation of the integer j+1.
 
5. The memory device (40) according to any one of claims 1 to 4, wherein the Boolean vector A is any row vector of a Boolean matrix Φ, the Boolean vector B is any column vector of a Boolean matrix X, each of multiple logic modules in the memory device is responsible for dot product operations of some row vectors of the Boolean matrix Φ and some column vectors of the Boolean matrix X, and the multiple logic modules jointly implement a Boolean matrix multiplication operation of the Boolean matrix Φ and the Boolean matrix X.
 
6. The memory device (40) according to any one of claims 1 to 5, wherein the instruction of the processor further comprises a data read/write instruction, and each memory unit further comprises:
a storage module (43), wherein the storage module (43) is connectable to the control module (45), and the control module (45) is configured to perform data reading/writing by using the storage module (43) according to the data read/write instruction.
 
7. A data processing method based on a multilayer of resistive random access memory, RRAM, crossbar array, wherein for each memristor of the multilayer RRAM crossbar array a corresponding resistance value is Ron or Roff, Ron indicates a Boolean value 1, Roff indicates a Boolean value 0, the multilayer of RRAM crossbar array is used to perform a dot product operation of a Boolean vector A and a Boolean vector B, A and B each indicate an N-dimensional Boolean vector, N is a positive integer not less than 2, the first layer of RRAM crossbar array of the multilayer of RRAM crossbar array comprises a memristor array having N rows × N columns, for each row of the first layer of RRAM crossbar array, an input end of the memristors of the row are connected to a corresponding word line, for each column of the first layer of RRAM crossbar array, an output end of the memristors of the column are connected to a corresponding bit line, and the N bit lines of the first layer of RRAM crossbar array are respectively connected to other layers of RRAM crossbar array of the multilayer of RRAM crossbar array through N comparator circuits; and the method comprises:

generating, by the first layer of RRAM crossbar array, N current signals on the N bit lines, each of the currents on the corresponding bit line being generated according to voltage signals input by the N word lines of the first layer of RRAM crossbar array the resistance values of the corresponding memristors of the first layer of RRAM crossbar array and a corresponding resistor (Rs), wherein a voltage value of the voltage signal input by the jth word line in the N word lines is a voltage value corresponding to Bj, the resistance value of each memristors of the jth row at the first layer of RRAM crossbar array is a resistance value corresponding to Aj, Bj is the jth element of the Boolean vector B, Aj is the jth element of the Boolean vector A, and a value of j ranges from 0 to N-1;

converting, by the N comparator circuits, the N current signals into N voltage signals, and comparing the N voltage signals with voltage thresholds respectively corresponding to the N comparator circuits, so that output ends of the N bit lines which correspond to output ends of the N comparator circuits output a voltage signal corresponding to a first computing result, wherein the first computing result is an N-dimensional Boolean vector, first K elements of the first computing result are 1, remaining elements are 0, and K is an operation result of the dot product of A and B; and

receiving, by the other layers of RRAM crossbar array, the voltage signal corresponding to the first computing result from the output ends of the N bit lines, and generating, according to the voltage signal corresponding to the first computing result and the resistance values of a plurality of memristors of the other layers of RRAM crossbar array, a voltage signal (O3,0....O3,n) corresponding to a second computing result, wherein the second computing result is a binary representation of K.


 
8. The method according to claim 7, wherein the logic module comprises at least three layers of RRAM crossbar array, and the other layers of the RRAM crossbar array comprise the second layer of RRAM crossbar array and the third layer of RRAM crossbar array;
the second layer of RRAM crossbar array comprises a (2N-1) rows × N columns memristor array, for each row of the second layer of RRAM crossbar array, an input end of the memristors of the row are connected to a corresponding word line, for each column of the second layer of RRAM crossbar array, an output end of the memristors of the column are connected to a corresponding bit line, and word lines of the second layer of RRAM crossbar array are connected to the output ends of the bit lines of the first layer of RRAM crossbar array;
the third layer of RRAM crossbar array comprises an N rows × n columns memristor array, for each row of the third layer of RRAM crossbar array, an input end of the memristors of the row are connected to a corresponding word line, for each column of the third layer of RRAM crossbar array, an output end of the memristors of the column are connected to a corresponding bit line, and n is greater than or equal to a minimum quantity of bits required for expressing the integer N in binary; and
the receiving, by the other layers of the RRAM crossbar array, the voltage signal corresponding to the first computing result from the output ends of the N bit lines, and generating, according to the voltage signal corresponding to the first computing result and the resistance values of the plurality of memristors of the other layers of the RRAM crossbar array, a voltage signal (O3,0....O3,n) corresponding to a second computing result comprises:
receiving, by the second layer of RRAM crossbar array, the voltage signal corresponding to the first computing result from the output ends of the bit lines of the first layer of RRAM crossbar array through the 2N-1 word lines, and performing a logic operation according to the voltage signal corresponding to the first computing result and the resistance values of the memristors of the second layer of RRAM crossbar array so as to obtain a voltage signal corresponding to an intermediate computing result:

wherein O1,j is a negation of a Boolean value corresponding to the voltage signal output by the jth bit line of the first layer of RRAM crossbar array, O1,j+1 is a Boolean value corresponding to the a voltage signal output by the (j+1)th bit line of the first layer of RRAM crossbar array, and O2,j is a negation of a Boolean value corresponding to the voltage signal output by the jth bit line of the second layer of RRAM crossbar array; and

receiving, by the third layer of RRAM crossbar array, the voltage signal corresponding to the intermediate computing result from the N bit lines of the second layer of RRAM crossbar array through the N word lines of the third layer of RRAM crossbar array, and encoding the intermediate computing result according to the voltage signal corresponding to the intermediate computing result and the resistance values of the memristors of the third layer of RRAM crossbar array, so as to obtain the voltage signal (O3,0....O3,n) corresponding to the second computing result.


 
9. The method according to claim 7 or 8, wherein the jth comparator circuit of the N 5 comparator circuits comprises the corresponding resistor Rs of a constant resistance value and a comparator, one end of the resistor Rs is connected to the jth bit line in the N bit lines and the comparator, the other end of the resistor Rs is grounded, the corresponding voltage threshold of the jth comparator circuit is VrgonRs(2j+1)/2, Vr indicates a voltage value corresponding to a Boolean value 1, and gon indicates a reciprocal of Ron.
 


Ansprüche

1. Speichervorrichtung (40), wobei die Speichervorrichtung (40) einen Steuerbus und mehrere Speichereinheiten (42) aufweist, wobei die mehreren Speichereinheiten (42) miteinander über den Steuerbus verbunden sind und wobei jede der mehreren Speichereinheiten (42) Folgendes aufweist:

ein Steuermodul (45), wobei das Steuermodul über den Steuerbus mit einem Prozessor (47) verbindbar ist und ausgebildet ist zum Empfangen und Parsen einer Anweisung des Prozessors durch den Steuerbus, und wobei die Anweisung des Prozessors eine logische Operationsanweisung aufweist; und

ein Logikmodul (44), wobei das Logikmodul (44) mit dem Steuermodul (45) verbunden ist, wobei das Logikmodul (44) eine mehrschichtige RRAM-"Crossbar"-Anordnung (Resistive Random Access Memory, resistiver Direktzugriffsspeicher) aufweist, wobei für jeden Memristor der mehrschichtigen RRAM-"Crossbar"-Anordnung der entsprechende Widerstandswert Ron oder Roff ist,

wobei Ron einen Booleschen Wert 1 anzeigt, Roff einen Booleschen Wert 0 anzeigt und das Logikmodul (44) ein Speichermodul ist, das ausgebildet ist zum Durchführen einer Booleschen Operation unter Verwendung der mehrschichtigen RRAM-"Crossbar"-Anordnung entsprechend der logischen Operationsanweisung,

wobei das Logikmodul (44) ausgebildet ist zum, entsprechend der logischen Operationsanweisung, Durchführen einer Skalarproduktoperation eines Booleschen Vektors A und eines Booleschen Vektors B, wobei A und B jeweils einen N-dimensionalen Booleschen Vektor anzeigen und wobei N eine positive ganze Zahl nicht kleiner als 2 ist;

wobei die erste Schicht der RRAM-"Crossbar"-Anordnung der mehrschichtigen RRAM-"Crossbar"-Anordnung eine Memristor-Anordnung mit N Zeilen x N Spalten aufweist, wobei für jede Zeile der ersten Schicht der RRAM-"Crossbar"-Anordnung ein Eingangsende der Memristoren der Zeile mit einer entsprechenden Wortleitung verbunden ist, wobei für jede Spalte der ersten Schicht der RRAM-"Crossbar"-Anordnung ein Ausgangsende der Memristoren der Spalte mit einer entsprechenden Bitleitung verbunden ist, wobei die N Wortleitungen der ersten Schicht der RRAM-"Crossbar"-Anordnung mit dem Steuermodul (45) verbunden sind und die N Bitleitungen der ersten Schicht der RRAM-"Crossbar"-Anordnung entsprechend über N Vergleicherschaltungen mit anderen Schichten der RRAM-"Crossbar"-Anordnung der mehrschichtigen RRAM-"Crossbar"-Anordnung verbunden sind;

wobei das Logikmodul (44) die N Vergleicherschaltungen aufweist, die erste Schicht der RRAM-"Crossbar"-Anordnung ausgebildet ist zum Erzeugen von N Stromsignalen auf den N Bitleitungen, wobei jeder der Ströme auf der entsprechenden Bitleitung entsprechend durch die N Wortleitungen eingegebenen Spannungssignalen, den Widerstandswerten der entsprechenden Memristoren der ersten Schicht der RRAM-"Crossbar"-Anordnung und einem entsprechenden Widerstand (Rs) erzeugt wird, wobei ein Spannungswert des durch die j-te Wortleitung der N Wortleitungen eingegebenen Spannungssignals ein Spannungswert entsprechend Bj ist, wobei der Widerstandswert jedes Memristors der j-ten Zeile der ersten Schicht der RRAM-"Crossbar"-Anordnung ein Widerstandswert entsprechend Aj ist, Bj das j-te Element des Booleschen Vektors B ist, Aj das j-te Element des Booleschen Vektors A ist und ein Wert von j von 0 bis N-1 reicht;

wobei die N Vergleicherschaltungen entsprechend ausgebildet sind, um die N Stromsignale in N Spannungssignale umzuwandeln, und dazu ausgebildet sind, die N Spannungssignale mit Spannungsschwellen jeweils entsprechend den N Vergleicherschaltungen zu vergleichen, sodass Ausgangsenden der N Bitleitungen, die Ausgangsenden der N Vergleicherschaltungen entsprechen, ein Spannungssignal entsprechend einem ersten Berechnungsergebnis ausgeben, wobei das erste Berechnungsergebnis ein N-dimensionaler Boolescher Vektor ist, erste K Elemente des ersten Berechnungsergebnisses 1 sind, restliche Elemente 0 sind und K ein Operationsergebnis des Skalarprodukts von A und B ist; und

wobei die anderen Schichten der RRAM-"Crossbar"-Anordnung dazu ausgebildet sind, das Spannungssignal entsprechend dem ersten Berechnungsergebnis von den Ausgangsenden der N Bitleitungen zu empfangen und dazu ausgebildet sind, gemäß dem Spannungssignal entsprechend dem ersten Berechnungsergebnis und den Widerstandswerten der mehreren Memristoren der anderen Schichten der RRAM-"Crossbar"-Anordnung ein Spannungssignal (O3,0... O3,n) entsprechend einem zweiten Berechnungsergebnis zu erzeugen, wobei das zweite Berechnungsergebnis eine binäre Darstellung von K ist.


 
2. Speichervorrichtung (40) nach Anspruch 1, wobei die j-te Vergleicherschaltung der N Vergleicherschaltungen den entsprechenden Widerstand Rs eines konstanten Widerstandswerts und einen Vergleicher aufweist, wobei ein Ende des Widerstands Rs mit der j-ten Bitleitung in den N Bitleitungen und dem Vergleicher verbunden ist, wobei das andere Ende des Widerstands Rs geerdet ist, wobei die entsprechende Spannungsschwelle der j-ten Vergleicherschaltung VrgonRs(2j+1)/2 ist, wobei Vr einen Spannungswert entsprechend einem Booleschen Wert 1 anzeigt und gon ein Reziprokes von Ron anzeigt.
 
3. Speichervorrichtung (40) nach Anspruch 2, wobei das Logikmodul (44) mindestens drei Schichten der RRAM-"Crossbar"-Anordnung aufweist und die anderen Schichten der RRAM-"Crossbar"-Anordnung die zweite Schicht der RRAM-"Crossbar"-Anordnung und die dritte Schicht der RRAM-"Crossbar"-Anordnung aufweisen;
wobei die zweite Schicht der RRAM-"Crossbar"-Anordnung eine Memristor-Anordnung mit (2N-1) Zeilen x N Spalten aufweist, wobei für jede Zeile der zweiten Schicht der RRAM-"Crossbar"-Anordnung ein Eingangsende der Memristoren der Zeile mit einer entsprechenden Wortleitung verbunden ist, wobei für jede Spalte der zweiten Schicht der RRAM-"Crossbar"-Anordnung ein Ausgangsende der Memristoren der Spalte mit einer entsprechenden Bitleitung verbunden ist, und wobei Wortleitungen der zweiten Schicht der RRAM-"Crossbar"-Anordnung mit den Ausgangsenden der Bitleitungen der ersten Schicht der RRAM-"Crossbar"-Anordnung verbunden sind;
wobei die zweite Schicht der RRAM-"Crossbar"-Anordnung dazu ausgebildet ist, das Spannungssignal entsprechend dem ersten Berechnungsergebnis von den Ausgangsenden der Bitleitungen der ersten Schicht von RRAMs durch die 2N-1 Wortleitungen zu empfangen und eine logische Operation gemäß dem Spannungssignal entsprechend dem ersten Berechnungsergebnis und den Widerstandswerten der Memristoren der zweiten Schicht der RRAM-"Crossbar"-Anordnung durchzuführen, um so ein Spannungssignal entsprechend einem zwischenzeitlichen Berechnungsergebnis zu erhalten:

wobei O1,j eine Negation eines Booleschen Wertes entsprechend dem durch die j-te Bitleitung der ersten Schicht der RRAM-"Crossbar"-Anordnung ausgegebenen Spannungssignal ist, O1,j+1 ein Boolescher Wert entsprechend dem durch die (j+1)-te Bitleitung der ersten Schicht der RRAM-"Crossbar"-Anordnung ausgegebenen Spannungssignal ist, und O2,j eine Negation eines Booleschen Wertes entsprechend dem durch die j-te Bitleitung der zweiten Schicht der RRAM-"Crossbar"-Anordnung ausgegebenen Spannungssignal ist;

wobei die dritte Schicht der RRAM-"Crossbar"-Anordnung eine Memristor-Anordnung mit N Zeilen x n Spalten aufweist, wobei für jede Zeile der dritten Schicht der RRAM-"Crossbar"-Anordnung ein Eingangsende der Memristoren der Zeile mit einer entsprechenden Wortleitung verbunden ist, wobei für jede Spalte der dritten Schicht der RRAM-"Crossbar"-Anordnung ein Ausgangsende der Memristoren der Spalte mit einer entsprechenden Bitleitung verbunden ist, und wobei n größer als oder gleich einer minimalen Quantität von Bits ist, die erforderlich ist, um die ganze Zahl N in Binärform auszudrücken; und

wobei die dritte Schicht der RRAM-"Crossbar"-Anordnung dazu ausgebildet ist, das Spannungssignal entsprechend dem zwischenzeitlichen Berechnungsergebnis von den N Bitleitungen der zweiten Schicht der RRAM-"Crossbar"-Anordnung durch die N Wortleitungen der dritten Schicht der RRAM-"Crossbar"-Anordnung zu empfangen und das zwischenzeitliche Berechnungsergebnis gemäß dem Spannungssignal entsprechend dem zwischenzeitlichen Berechnungsergebnis und den Widerstandswerten der Memristoren der dritten Schicht der RRAM-"Crossbar"-Anordnung zu codieren, um so das Spannungssignal (O3,0... O3,n) entsprechend dem zweiten Berechnungsergebnis zu erhalten.


 
4. Speichervorrichtung (40) nach Anspruch 3, wobei die j-te Wortleitung der dritten Schicht der RRAM-"Crossbar"-Anordnung mit der j-ten Bitleitung der zweiten Schicht der RRAM-"Crossbar"-Anordnung verbunden ist und die Widerstandswerte der Memristoren der j-ten Zeile der dritten Schicht der RRAM-"Crossbar"-Anordnung einer binären Darstellung der ganzen Zahl j+1 entsprechen.
 
5. Speichervorrichtung (40) nach einem der Ansprüche 1 bis 4, wobei der Boolesche Vektor A ein beliebiger Zeilenvektor einer Booleschen Matrix Φ ist, der Boolesche Vektor B ein beliebiger Spaltenvektor einer Booleschen Matrix X ist, jedes der mehreren Logikmodule in der Speichervorrichtung für Skalarproduktoperationen von einigen Zeilenvektoren der Booleschen Matrix Φ und einigen Spaltenvektoren der Booleschen Matrix X verantwortlich ist und die mehreren Logikmodule gemeinsam eine Boolesche Matrixmultiplikationsoperation der Booleschen Matrix Φ und der Booleschen Matrix X umsetzen.
 
6. Speichervorrichtung (40) nach einem der Ansprüche 1 bis 5, wobei die Anweisung des Prozessors ferner eine Datenlese-/-schreibanweisung aufweist und wobei jede Speichereinheit ferner Folgendes aufweist: ein Speichermodul (43), wobei das Speichermodul (43) mit dem Steuermodul (45) verbindbar ist und wobei das Steuermodul (45) dazu ausgebildet ist, Datenlese-/-schreiboperationen unter Verwendung des Speichermoduls (43) entsprechend der Datenlese-/- schreibanweisung durchzuführen.
 
7. Datenverarbeitungsverfahren, basierend auf einer mehrschichtigen RRAM-"Crossbar"-Anordnung (Resistive Random Access Memory, resistiver Direktzugriffsspeicher), wobei für jeden Memristor der mehrschichtigen RRAM-"Crossbar"-Anordnung ein entsprechender Widerstandswert Ron oder Roff ist, wobei Ron einen Booleschen Wert 1 anzeigt, Roff einen Booleschen Wert 0 anzeigt, die mehrschichtige RRAM-"Crossbar"-Anordnung verwendet wird, um eine Skalarproduktoperation eines Booleschen Vektors A und eines Booleschen Vektors B durchzuführen, wobei A und B jeweils einen N-dimensionalen Booleschen Vektor anzeigen, N eine positive ganze Zahl nicht kleiner als 2 ist, die erste Schicht der RRAM-"Crossbar"-Anordnung der mehrschichtigen RRAM-"Crossbar"-Anordnung eine Memristor-Anordnung mit N Zeilen x N Spalten aufweist, wobei, für jede Zeile der ersten Schicht der RRAM-"Crossbar"-Anordnung, ein Eingangsende der Memristoren der Zeile mit einer entsprechenden Wortleitung verbunden ist, wobei, für jede Spalte der ersten Schicht der RRAM-"Crossbar"-Anordnung, ein Ausgangsende der Memristoren der Spalte mit einer entsprechenden Bitleitung verbunden ist, und wobei die N Bitleitungen der ersten Schicht der RRAM-"Crossbar"-Anordnung über N Vergleicherschaltungen entsprechend mit anderen Schichten der RRAM-"Crossbar"-Anordnung der mehrschichtigen RRAM-"Crossbar"-Anordnung verbunden sind; und
wobei das Verfahren Folgendes aufweist:

Erzeugen, durch die erste Schicht der RRAM-"Crossbar"-Anordnung, von N Stromsignalen auf den N Bitleitungen, wobei jeder der Ströme auf der entsprechenden Bitleitung entsprechend durch die N Wortleitungen der ersten Schicht der RRAM-"Crossbar"-Anordnung eingegebenen Spannungssignalen, den Widerstandswerten der entsprechenden Memristoren der ersten Schicht der RRAM-"Crossbar"-Anordnung und einem entsprechenden Widerstand (Rs) erzeugt wird, wobei ein Spannungswert des durch die j-te Wortleitung in den N Wortleitungen eingegebenen Spannungssignals ein Spannungswert entsprechend Bj ist, wobei der Widerstandswert jedes Memristors der j-ten Zeile der ersten Schicht der RRAM-"Crossbar"-Anordnung ein Widerstandswert entsprechend Aj ist, Bj das j-te Element des Booleschen Vektors B ist, Aj das j-te Element des Booleschen Vektors A ist und ein Wert von j von 0 bis N-1 reicht;

Umwandeln, durch die N Vergleicherschaltungen, der N Stromsignale in N Spannungssignale und Vergleichen der N Spannungssignale mit Spannungsschwellen jeweils entsprechend den N Vergleicherschaltungen, sodass Ausgangsenden der N Bitleitungen, die Ausgangsenden der N Vergleicherschaltungen entsprechen, ein Spannungssignal entsprechend einem ersten Berechnungsergebnis ausgeben, wobei das erste Berechnungsergebnis ein N-dimensionaler Boolescher Vektor ist, erste K Elemente des ersten Berechnungsergebnisses 1 sind, restliche Elemente 0 sind und K ein Operationsergebnis des Skalarprodukts von A und B ist; und

Empfangen, durch die anderen Schichten der RRAM-"Crossbar"-Anordnung, des Spannungssignals entsprechend dem ersten Berechnungsergebnis von den Ausgangsenden der N Bitleitungen und Erzeugen, gemäß dem Spannungssignal entsprechend dem ersten Berechnungsergebnis und den Widerstandswerten von mehreren Memristoren der anderen Schichten der RRAM-"Crossbar"-Anordnung, eines Spannungssignals (O3,0 ... O3,n) entsprechend einem zweiten Berechnungsergebnis, wobei das zweite Berechnungsergebnis eine binäre Darstellung von K ist.


 
8. Verfahren nach Anspruch 7, wobei das Logikmodul mindestens drei Schichten der RRAM-"Crossbar"-Anordnung aufweist und die anderen Schichten der RRAM-"Crossbar"-Anordnung die zweite Schicht der RRAM-"Crossbar"-Anordnung und die dritte Schicht der RRAM-"Crossbar"-Anordnung aufweisen;
wobei die zweite Schicht der RRAM-"Crossbar"-Anordnung eine Memristor-Anordnung mit (2N-1) Zeilen x N Spalten aufweist, wobei für jede Zeile der zweiten Schicht der RRAM-"Crossbar"-Anordnung ein Eingangsende der Memristoren der Zeile mit einer entsprechenden Wortleitung verbunden ist, wobei für jede Spalte der zweiten Schicht der RRAM-"Crossbar"-Anordnung ein Ausgangsende der Memristoren der Spalte mit einer entsprechenden Bitleitung verbunden ist, und wobei Wortleitungen der zweiten Schicht der RRAM-"Crossbar"-Anordnung mit den Ausgangsenden der Bitleitungen der ersten Schicht der RRAM-"Crossbar"-Anordnung verbunden sind;
wobei die dritte Schicht der RRAM-"Crossbar"-Anordnung eine Memristor-Anordnung mit N Zeilen x n Spalten aufweist, wobei für jede Zeile der dritten Schicht der RRAM-"Crossbar"-Anordnung ein Eingangsende der Memristoren der Zeile mit einer entsprechenden Wortleitung verbunden ist, wobei für jede Spalte der dritten Schicht der RRAM-"Crossbar"-Anordnung ein Ausgangsende der Memristoren der Spalte mit einer entsprechenden Bitleitung verbunden ist, und wobei n größer als oder gleich einer minimalen Quantität von Bits ist, die erforderlich ist, um die ganze Zahl N in Binärform auszudrücken; und
wobei das Empfangen, durch die anderen Schichten der RRAM-"Crossbar"-Anordnung, des Spannungssignals entsprechend dem ersten Berechnungsergebnis von den Ausgangsenden der N Bitleitungen und Erzeugen, gemäß dem Spannungssignal entsprechend dem ersten Berechnungsergebnis und den Widerstandswerten der mehreren Memristoren der anderen Schichten der RRAM-"Crossbar"-Anordnung, eines Spannungssignals (O3,0 ... O3,n) entsprechend einem zweiten Berechnungsergebnis Folgendes aufweist:
Empfangen, durch die zweite Schicht der RRAM-"Crossbar"-Anordnung, des Spannungssignals entsprechend dem ersten Berechnungsergebnis von den Ausgangsenden der Bitleitungen der ersten Schicht der RRAM-"Crossbar"-Anordnung durch die 2N-1 Wortleitungen und Durchführen einer logischen Operation gemäß dem Spannungssignal entsprechend dem ersten Berechnungsergebnis und den Widerstandswerten der Memristoren der zweiten Schicht der RRAM-"Crossbar"-Anordnung, um so ein Spannungssignal entsprechend einem zwischenzeitlichen Berechnungsergebnis zu erhalten:

wobei O1,j eine Negation eines Booleschen Wertes entsprechend dem durch die j-te Bitleitung der ersten Schicht der RRAM-"Crossbar"-Anordnung ausgegebenen Spannungssignal ist, O1,j+1 ein Boolescher Wert entsprechend dem durch die (j+1)-te Bitleitung der ersten Schicht der RRAM-"Crossbar"-Anordnung ausgegebenen Spannungssignal ist, und O2,j eine Negation eines Booleschen Wertes entsprechend dem durch die j-te Bitleitung der zweiten Schicht der RRAM-"Crossbar"-Anordnung ausgegebenen Spannungssignal ist; und

Empfangen, durch die dritte Schicht der RRAM-"Crossbar"-Anordnung, des Spannungssignals entsprechend dem zwischenzeitlichen Berechnungsergebnis von den N Bitleitungen der zweiten Schicht der RRAM-"Crossbar"-Anordnung durch die N Wortleitungen der dritten Schicht der RRAM-"Crossbar"-Anordnung und Codieren des zwischenzeitlichen Berechnungsergebnisses gemäß dem Spannungssignal entsprechend dem zwischenzeitlichen Berechnungsergebnis und den Widerstandswerten der Memristoren der dritten Schicht der RRAM-"Crossbar"-Anordnung, um so das Spannungssignal (O3,0... O3,n) entsprechend dem zweiten Berechnungsergebnis zu erhalten.


 
9. Verfahren nach Anspruch 7 oder 8, wobei die j-te Vergleicherschaltung der N Vergleicherschaltungen den entsprechenden Widerstand Rs eines konstanten Widerstandswerts und einen Vergleicher aufweist, wobei ein Ende des Widerstands Rs mit der j-ten Bitleitung in den N Bitleitungen und dem Vergleicher verbunden ist, wobei das andere Ende des Widerstands Rs geerdet ist, wobei die entsprechende Spannungsschwelle der j-ten Vergleicherschaltung VrgonRs(2j+1)/2 ist, wobei Vr einen Spannungswert entsprechend einem Booleschen Wert 1 anzeigt und gon ein Reziprokes von Ron anzeigt.
 


Revendications

1. Dispositif de mémoire (40), le dispositif de mémoire (40) comprenant un bus de commande et de multiples unités de mémoire (42), les multiples unités de mémoire (42) étant reliées les unes aux autres par le bus de commande, et chacune des multiples unités de mémoire (42) comprenant :

un module de commande (45), le module de commande pouvant être relié à un processeur (47) par le bus de commande, et étant configuré pour recevoir et analyser une instruction du processeur par le bus de commande, l'instruction du processeur comprenant une instruction d'opération logique ; et

un module logique (44), le module logique (44) étant relié au module de commande (45), le module logique (44) comprenant une multicouche de réseau crossbar de mémoire vive résistive, RRAM, pour chaque memristance de la multicouche de réseau crossbar RRAM la valeur de résistance correspondante étant Ron ou Roff,

Ron indiquant une valeur booléenne 1, Roff indiquant une valeur booléenne 0, et le module logique (44) étant un module de stockage configuré pour effectuer une opération booléenne en utilisant la multicouche de réseau crossbar RRAM selon l'instruction d'opération logique,

le module logique (44) étant configuré pour, selon l'instruction d'opération logique, effectuer une opération de produit scalaire d'un vecteur booléen A et d'un vecteur booléen B, A et B indiquant chacun un vecteur booléen N-dimensionnel, et N étant un entier positif non inférieur à 2 ;

dans lequel la première couche de réseau crossbar RRAM de la multicouche de réseau crossbar RRAM comprend un réseau de memristances possédant N lignes × N colonnes, pour chaque ligne de la première couche de réseau crossbar RRAM, une extrémité d'entrée des memristances de la ligne est reliée à une ligne de mots correspondante, pour chaque colonne de la première couche de réseau crossbar RRAM, une extrémité de sortie des memristances de la colonne est reliée à une ligne de bits correspondante, les N lignes de mots de la première couche de réseau crossbar RRAM étant reliées au module de commande (45), et les N lignes de bits de la première couche de réseau crossbar RRAM étant reliées respectivement aux autres couches de réseau crossbar RRAM de la multicouche de réseau crossbar RRAM par N circuits comparateurs ; le module logique (44) comprenant lesdits N circuits comparateurs,

la première couche de réseau crossbar RRAM étant configurée pour générer N signaux de courant sur les N lignes de bits, chacun des courants présents sur la ligne de bits correspondante étant généré selon les signaux de tension entrés par les N lignes de mots, les valeurs de résistance des memristances correspondantes de la première couche de réseau crossbar RRAM et une résistance correspondante (Rs), une valeur de tension du signal de tension entré par la j-ième ligne de mots des N lignes de mots étant une valeur de tension correspondant à Bj, la valeur de résistance de chaque memristance de la j-ième ligne de la première couche de réseau crossbar RRAM étant une valeur de résistance correspondant à Aj, Bj étant le j-ième élément du vecteur booléen B, Aj étant le j-ième élément du vecteur booléen A, et une valeur de j étant comprise entre 0 et N-1 ;

les N circuits comparateurs étant configurés respectivement pour convertir les N signaux de courant en N signaux de tension, et configurés pour comparer les N signaux de tension à des seuils de tension correspondant respectivement aux N circuits comparateurs, de sorte que les extrémités de sortie des N lignes de bits qui correspondent aux extrémités de sortie des N circuits comparateurs émettent un signal de tension correspondant à un premier résultat de calcul, le premier résultat de calcul étant un vecteur booléen N-dimensionnel, les K premiers éléments du premier résultat de calcul étant à 1, les autres éléments étant à 0, et K étant un résultat d'opération du produit scalaire de A et B ; et

les autres couches de réseau crossbar RRAM étant configurées pour recevoir le signal de tension correspondant au premier résultat de calcul provenant des extrémités de sortie des N lignes de bits, et configurées pour générer, selon le signal de tension correspondant au premier résultat de calcul et aux valeurs de résistance de la pluralité de memristances des autres couches de réseau crossbar RRAM, un signal de tension (O3,0 ... O3,n) correspondant à un deuxième résultat de calcul, le deuxième résultat de calcul étant une représentation binaire de K.


 
2. Dispositif de mémoire (40) selon la revendication 1, dans lequel le j-ième circuit comparateur des N circuits comparateurs comprend la résistance correspondante Rs d'une valeur de résistance constante et un comparateur, une extrémité de la résistance Rs étant reliée à la j-ième ligne de bits des N lignes de bits et au comparateur, l'autre extrémité de la résistance Rs étant reliée à la masse, le seuil de tension correspondant du j-ième circuit comparateur étant VrgonRs(2j+1)/2,
Vr indiquant une valeur de tension correspondant à une valeur booléenne 1, et gon indiquant un inverse de Ron.
 
3. Dispositif de mémoire (40) selon la revendication 2, dans lequel le module logique (44) comprend au moins trois couches de réseau crossbar RRAM, et les autres couches de réseau crossbar RRAM comprennent la deuxième couche de réseau crossbar RRAM et la troisième couche de réseau crossbar RRAM ;
la deuxième couche de réseau crossbar RRAM comprend un réseau de memristances de (2N-1) lignes × N colonnes, pour chaque ligne de la deuxième couche de réseau crossbar RRAM, une extrémité d'entrée des memristances de la ligne est reliée à une ligne de mots correspondante, pour chaque colonne de la deuxième couche de réseau crossbar RRAM, une extrémité de sortie des memristances de la colonne est reliée à une ligne de bits correspondante, et les lignes de mots de la deuxième couche de réseau crossbar RRAM sont reliées aux extrémités de sortie des lignes de bits de la première couche de réseau crossbar RRAM ;
la deuxième couche de réseau crossbar RRAM est configurée pour recevoir le signal de tension correspondant au premier résultat de calcul provenant des extrémités de sortie des lignes de bits de la première couche de RRAM par les 2N-1 lignes de mots, et effectuer une opération logique selon le signal de tension correspondant au premier résultat de calcul et aux valeurs de résistance des memristances de la deuxième couche de réseau crossbar RRAM afin d'obtenir un signal de tension correspondant à un résultat de calcul intermédiaire :

O1,j est une négation d'une valeur booléenne correspondant au signal de tension émis par la j-ième ligne de bits de la première couche de réseau crossbar RRAM, O1,j+1 est une valeur booléenne correspondant au signal de tension émis par la (j+1)-ième ligne de bits de la première couche de réseau crossbar RRAM, et O2,j étant une négation d'une valeur booléenne correspondant au signal de tension émis par la j-ième ligne de bits de la deuxième couche de réseau crossbar RRAM ;

la troisième couche de réseau crossbar RRAM comprend un réseau de memristances de N lignes × n colonnes, pour chaque ligne de la troisième couche de réseau crossbar RRAM, une extrémité d'entrée des memristances de la ligne est reliée à une ligne de mots correspondante, pour chaque colonne de la troisième couche de réseau crossbar RRAM, une extrémité de sortie des memristances de la colonne est reliée à une ligne de bits correspondante, et n est supérieur ou égal à une quantité minimale de bits nécessaires pour exprimer l'entier N en binaire ; et

la troisième couche de réseau crossbar RRAM est configurée pour recevoir le signal de tension correspondant au résultat de calcul intermédiaire provenant des N lignes de bits de la deuxième couche de réseau crossbar RRAM par les N lignes de mots de la troisième couche de réseau crossbar RRAM, et coder le résultat de calcul intermédiaire selon le signal de tension correspondant au résultat de calcul intermédiaire et aux valeurs de résistance des memristances de la troisième couche de réseau crossbar RRAM, afin d'obtenir le signal de tension (O3,0 ... O3,n) correspondant au deuxième résultat de calcul.


 
4. Dispositif de mémoire (40) selon la revendication 3, dans lequel la j-ième ligne de mots de la troisième couche de réseau crossbar RRAM est reliée à la j-ième ligne de bits de la deuxième couche de réseau crossbar RRAM, et les valeurs de résistance des memristances de la j-ième ligne de la troisième couche de réseau crossbar RRAM correspondent à une représentation binaire de l'entier j+1.
 
5. Dispositif de mémoire (40) selon l'une quelconque des revendications 1 à 4, dans lequel le vecteur booléen A est un vecteur de ligne quelconque d'une matrice booléenne φ, le vecteur booléen B est un vecteur de colonne quelconque d'une matrice booléenne X, chacun des multiples modules logiques du dispositif de mémoire est chargé des opérations de produit scalaire de certains vecteurs de ligne de la matrice booléenne φ et de certains vecteurs de colonne de la matrice booléenne X, et les multiples modules logiques mettent en œuvre conjointement une opération de multiplication matricielle booléenne de la matrice booléenne φ et de la matrice booléenne X.
 
6. Dispositif de mémoire (40) selon l'une quelconque des revendications 1 à 5, dans lequel l'instruction du processeur comprend également une instruction de lecture/écriture de données, et chaque unité de mémoire comprend également :
un module de stockage (43), le module de stockage (43) pouvant être relié au module de commande (45), et le module de commande (45) étant configuré pour effectuer une lecture/écriture de données en utilisant le module de stockage (43) selon l'instruction de lecture/écriture de données.
 
7. Procédé de traitement de données basé sur une multicouche de réseau crossbar de mémoire vive résistive, RRAM, dans lequel, pour chaque memristance du réseau crossbar RRAM, une valeur de résistance correspondante est Ron ou Roff, Ron indiquant une valeur booléenne 1, Roff indiquant une valeur booléenne 0, la multicouche de réseau crossbar RRAM sert à effectuer une opération de produit scalaire d'un vecteur booléen A et d'un vecteur booléen B, A et B indiquant chacun un vecteur booléen N-dimensionnel, N étant un entier positif non inférieur à 2, la première couche de réseau crossbar RRAM de la multicouche de réseau crossbar RRAM comprend un réseau de memristances possédant N lignes × N colonnes, pour chaque ligne de la première couche de réseau crossbar RRAM, une extrémité d'entrée des memristances de la ligne est reliée à une ligne de mots correspondante, pour chaque colonne de la première couche de réseau crossbar RRAM, une extrémité de sortie des memristances de la colonne est reliée à une ligne de bits correspondante, et les N lignes de bits de la première couche de réseau crossbar RRAM sont reliées respectivement aux autres couches de réseau crossbar RRAM de la multicouche de réseau crossbar RRAM par N circuits comparateurs ; et
le procédé comprenant les étapes consistant à :

générer, par la première couche de réseau crossbar RRAM, N signaux de courant sur les N lignes de bits, chacun des courants présents sur la ligne de bits correspondante étant généré selon les signaux de tension entrés par les N lignes de mots de la première couche de réseau crossbar RRAM, les valeurs de résistance des memristances correspondantes de la première couche de réseau crossbar RRAM et une résistance correspondante (Rs),

une valeur de tension du signal de tension entré par la j-ième ligne de mots des N lignes de mots étant une valeur de tension correspondant à Bj, la valeur de résistance de chaque memristance de la j-ième ligne de la première couche de réseau crossbar RRAM étant une valeur de résistance correspondant à Aj, Bj étant le j-ième élément du vecteur booléen B, Aj étant le j-ième élément du vecteur booléen A, et une valeur de j étant comprise entre 0 et N-1 ;

convertir, par les N circuits comparateurs, les N signaux de courant en N signaux de tension, et comparer les N signaux de tension à des seuils de tension correspondant respectivement aux N circuits comparateurs, de sorte que les extrémités de sortie des N lignes de bits qui correspondent aux extrémités de sortie des N circuits comparateurs émettent un signal de tension correspondant à un premier résultat de calcul, le premier résultat de calcul étant un vecteur booléen N-dimensionnel, les K premiers éléments du premier résultat de calcul étant à 1, les autres éléments étant à 0, et K étant un résultat d'opération du produit scalaire de A et B ; et

recevoir, par les autres couches de réseau crossbar RRAM, le signal de tension correspondant au premier résultat de calcul provenant des extrémités de sortie des N lignes de bits, et générer, selon le signal de tension correspondant au premier résultat de calcul et aux valeurs de résistance d'une pluralité de memristances des autres couches de réseau crossbar RRAM, un signal de tension (O3,0 ... O3,n) correspondant à un deuxième résultat de calcul, le deuxième résultat de calcul étant une représentation binaire de K.


 
8. Procédé selon la revendication 7, dans lequel le module logique comprend au moins trois couches de réseau crossbar RRAM, et les autres couches de réseau crossbar RRAM comprennent la deuxième couche de réseau crossbar RRAM et la troisième couche de réseau crossbar RRAM ;
la deuxième couche de réseau crossbar RRAM comprend un réseau de memristances de (2N-1) lignes × N colonnes, pour chaque ligne de la deuxième couche de réseau crossbar RRAM, une extrémité d'entrée des memristances de la ligne est reliée à une ligne de mots correspondante, pour chaque colonne de la deuxième couche de réseau crossbar RRAM, une extrémité de sortie des memristances de la colonne est reliée à une ligne de bits correspondante, et les lignes de mots de la deuxième couche de réseau crossbar RRAM sont reliées aux extrémités de sortie des lignes de bits de la première couche de réseau crossbar RRAM ;
la troisième couche de réseau crossbar RRAM comprend un réseau de memristances de N lignes × n colonnes, pour chaque ligne de la troisième couche de réseau crossbar RRAM, une extrémité d'entrée des memristances de la ligne est reliée à une ligne de mots correspondante, pour chaque colonne de la troisième couche de réseau crossbar RRAM, une extrémité de sortie des memristances de la colonne est reliée à une ligne de bits correspondante, et n est supérieur ou égal à une quantité minimale de bits nécessaires pour exprimer l'entier N en binaire ; et
la réception, par les autres couches du réseau crossbar RRAM, du signal de tension correspondant au premier résultat de calcul provenant des extrémités de sortie des N lignes de bits, et la génération, selon le signal de tension correspondant au premier résultat de calcul et aux valeurs de résistance de la pluralité de memristances des autres couches du réseau crossbar RRAM, d'un signal de tension (O3,0 ... O3,n) correspondant à un deuxième résultat de calcul, comprennent les étapes consistant à :
recevoir, par la deuxième couche de réseau crossbar RRAM, le signal de tension correspondant au premier résultat de calcul provenant des extrémités de sortie des lignes de bits de la première couche de réseau crossbar RRAM par les 2N-1 lignes de mots, et effectuer une opération logique selon le signal de tension correspondant au premier résultat de calcul et aux valeurs de résistance des memristances de la deuxième couche de réseau crossbar RRAM afin d'obtenir un signal de tension correspondant à un résultat de calcul intermédiaire :

O1,j est une négation d'une valeur booléenne correspondant au signal de tension émis par la j-ième ligne de bits de la première couche de réseau crossbar RRAM, O1,j+1 est une valeur booléenne correspondant au signal de tension émis par la (j+1)-ième ligne de bits de la première couche de réseau crossbar RRAM, et O2,j étant une négation d'une valeur booléenne correspondant au signal de tension émis par la j-ième ligne de bits de la deuxième couche de réseau crossbar RRAM ; et

recevoir, par la troisième couche de réseau crossbar RRAM, le signal de tension correspondant au résultat de calcul intermédiaire provenant des N lignes de bits de la deuxième couche de réseau crossbar RRAM par les N lignes de mots de la troisième couche de réseau crossbar RRAM, et coder le résultat de calcul intermédiaire selon le signal de tension correspondant au résultat de calcul intermédiaire et aux valeurs de résistance des memristances de la troisième couche de réseau crossbar RRAM, afin d'obtenir le signal de tension (O3,0 ... O3,n) correspondant au deuxième résultat de calcul.


 
9. Procédé selon la revendication 7 ou 8, dans lequel le j-ième circuit comparateur des N circuits comparateurs comprend la résistance correspondante Rs d'une valeur de résistance constante et un comparateur, une extrémité de la résistance Rs étant reliée à la j-ième ligne de bits des N lignes de bits et au comparateur, l'autre extrémité de la résistance Rs étant reliée à la masse, le seuil de tension correspondant du j-ième circuit comparateur étant Vr*gon*Rs*(2j+1)/2,
Vr indiquant une valeur de tension correspondant à une valeur booléenne 1, et gon indiquant un inverse de Ron.
 




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Cited references

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Patent documents cited in the description