(19)
(11)EP 3 389 188 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
20.07.2022 Bulletin 2022/29

(21)Application number: 18167344.3

(22)Date of filing:  13.04.2018
(51)International Patent Classification (IPC): 
H03M 1/50(2006.01)
H03K 7/08(2006.01)
H03M 1/34(2006.01)
H03M 1/48(2006.01)
(52)Cooperative Patent Classification (CPC):
H03K 7/08; H03M 1/504; H03M 1/34; H03M 1/485

(54)

ANALOG TO DIGITAL CONVERTERS

ANALOG-DIGITAL-WANDLER

CONVERTISSEURS ANALOGIQUE-NUMÉRIQUE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 13.04.2017 US 201715487055

(43)Date of publication of application:
17.10.2018 Bulletin 2018/42

(73)Proprietor: Hamilton Sundstrand Corporation
Charlotte, NC 28217-4578 (US)

(72)Inventors:
  • WILSON, Michael A.
    Scottsdale, AZ 85251 (US)
  • REYES, Harold J.
    Tempe, AZ 85281 (US)

(74)Representative: Dehns 
St. Bride's House 10 Salisbury Square
London EC4Y 8JD
London EC4Y 8JD (GB)


(56)References cited: : 
EP-A1- 3 015 872
US-A- 5 218 315
US-A1- 2016 248 381
WO-A2-2011/149866
US-A1- 2013 051 092
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    BACKGROUND OF THE INVENTION


    1. Field of the Invention



    [0001] The present disclosure relates to signal conversion, and more particularly to analog to digital signal conversion for analog signal health monitoring.

    2. Description of Related Art



    [0002] Sensors, such as those employed on aircraft, commonly employ excitation voltages to sensors for purposes of monitoring a sensed parameter. For example, in rotating machinery like generators and motors resolvers are commonly employed to sense the rotational position and/or speed of a shaft. Such resolvers generally receive an excitation voltage that varies according to a desired sinusoidal waveform and typically provide an output signal indicative of the rotational position and/or speed of the shaft.

    [0003] When providing a sinusoidal voltage excitation waveform it is often desirable to monitor the amplitude of the sinusoidal excitation voltage applied to the sensor. This is because the output of the sensor can change according to variation in the amplitude of the input excitation waveform, potentially changing output of the sensor for a given sensed parameter value. Monitoring the sinusoidal voltage excitation waveform generally involves feeding the sinusoidal signal through an analog-to-digital converter (ADC) device. ADC devices typically have a limited number of input channels, which can limit the number of parameters sensed in certain applications.

    [0004] Such conventional methods and systems have generally been considered satisfactory for their intended purpose. However, there is still a need in the art for improved systems and methods for sensor excitation signal monitoring. The present disclosure provides a solution for this need.

    [0005] Sensor excitation signal monitoring is discussed in EP 3015872, US 2013,051092, US 5,218,315, US 2016/248381 and WO 2011/149866.

    SUMMARY OF THE INVENTION



    [0006] A sensor interface is provided as defined by claim 1.

    [0007] In accordance with certain embodiments, the SADO circuit can include a plurality of interconnected discrete electronic components. A voltage divider circuit connected to the comparator input terminal to attenuate an input voltage received at the comparator input. A source resistor connected in series between a sine wave generator and the comparator input terminal. A ground resistor can be connected in series between ground and the comparator input terminal.

    [0008] In accordance with further embodiments, a half-wave rectifier circuit can be connected to the comparator input terminal to half-wave rectify and clamp the input voltage received at the comparator input terminal to ground. The half-wave rectifier can include a diode connected between ground and the comparator input terminal. The diode can be arranged to oppose current flow from the comparator input terminal and ground.

    [0009] A pull-up resistor can be connected in series between a pull-up voltage source and the comparator output.

    [0010] A method of monitoring amplitude and frequency of a sinusoidal voltage waveform is provided as defined by claim 5.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0011] So that those skilled in the art to which the subject disclosure appertains will readily understand how to make and use the devices and methods of the subject disclosure without undue experimentation, embodiments thereof will be described in detail herein below with reference to certain figures, wherein:

    Fig. 1 is a schematic view of an exemplary embodiment sensor interface with a sinusoidal-amplitude-to-digital-output (SADO) circuit constructed in accordance with the present disclosure, showing the sensor interface connected between a sine wave generator and a sensor;

    Fig. 2 is a circuit diagram of the sensor interface of Fig. 1, showing discrete electronic components of the SADO circuit interconnected with one another; and

    Figs. 3 and 4 are graphs of output of the SADO circuit of Fig. 1, showing digital output duty cycle percentage as a function of input voltage amplitude and digital output for an exemplary waveform, respectively; and

    Fig. 5 is a process flow diagram for a method of converting a sinusoidal waveform into a pulse-width modulated output waveform, showing steps of the method.


    DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS



    [0012] Reference will now be made to the drawings wherein like reference numerals identify similar structural features or aspects of the subject disclosure. For purposes of explanation and illustration, and not limitation, a partial view of an exemplary embodiment of a circuit to allow an amplitude and frequency of a sinusoidal voltage waveform to be digitally monitored in accordance with the disclosure is shown in Fig. 1 and is designated generally by reference character 100. Other embodiments of such circuits, sensors interfaces employing such circuits, and methods of monitoring amplitude and frequency of sinusoidal voltage waveforms in accordance with the disclosure, or aspects thereof, are provided in Figs. 2-5, as will be described. The systems and methods described herein can be used for monitoring excitation voltages applied to sensors, such as resolvers operably coupled to rotating machinery in aircraft, though the present disclosure is not limited to resolvers or to rotating machinery in general.

    [0013] Referring to Fig. 1, circuit 100 is shown. Circuit 100 generally includes an input 101 configured to receive a sinusoidal voltage waveform and an output 103 in operable communication with input 101. Output 103 is configured to provide a duty cycle having a nonlinear relationship to the amplitude of the sinusoidal voltage waveform such that an amplitude of the sinusoidal voltage waveform can be calculated from just the duty cycle.

    [0014] In the illustrated exemplary embodiment circuit 100 is sinusoidal amplitude-to-digital-output (SADO) circuit included in sensor interface 10. Sensor interface 10 is connected to a sensor 2 and includes a SADO circuit 100, a sine wave generator 102, a memory 104 with a lookup table 106, and field-programmable-gate-array (FPGA) device or processor 108. Sine wave generator 102 is connected to SADO circuit 100 and sensor 2. FPGA device or processor 108 is connected to SADO circuit 100 via a digital bus 110 and is disposed in communication with memory 104. Lookup table 106 includes an association of sinusoid voltage to amplitude digital output due cycle percentage for an input voltage provided by sine wave generator 102 to SADO circuit 100 and sensor 2. Sensor 2 in coupled to a sensed device 4 for determining a parameter of sensed device 4. Sensed device 4 is resolver arranged to generate signal indicative of rotational position of rotating machine 6 using an excitation voltage received at sensor 2 by sine wave generator 102. It is to be understood and appreciated that this is for explanation purposes only, and that sensor 2 can be any device employing an excitation voltage with a sinusoidal waveform.

    [0015] With reference to Fig. 2, a circuit diagram of SADO circuit 100 is shown. SADO circuit 100 includes a comparator 112 with an input terminal 114, a reference terminal 116, and an output terminal 118. Digital bus 110 is connected to output terminal 118. A reference voltage source 120 is connected to reference terminal 116. A feedback resistor 144 is connected in parallel between output terminal 118 and input terminal 114 to convert voltage, e.g., sinusoidal voltage shown in Fig. 1, received at input terminal 114 into a digital pulse-width modulated waveform (shown in Fig. 1) that varies non-linearly with amplitude of the voltage received at input terminal 114 (shown in Fig. 4). It is contemplated that SADO circuit 100 include a plurality of discrete electronic components interconnected with one, e.g., resistors and diodes less than fully implemented in silicon.

    [0016] SADO circuit 100 also includes a voltage divider circuit 124. Voltage divider circuit 124 is connected to input terminal 114 and has a source resistor 126 and a ground resistor 128. Source resistor 126 is connected in series between sine wave generator 102 and input terminal 114. Ground resistor 128 is connected in series between a ground terminal 129 and input terminal 114. A ground lead 131 connects ground resistor 128 to an input lead 130 at a location between source resistor 126 and input terminal 114. Voltage divider circuit 124 is arranged, e.g., via respective resistances of source resistor 126 and ground resistor 128, to attenuate voltage of the excitation waveform (shown in Fig. 1) applied to input terminal 114.

    [0017] SADO circuit 100 additionally includes a half-wave rectifier circuit 132. Half-wave rectifier circuit 132 is connected to input terminal 114 and includes a diode 134. Diode 134 is connected in series between a ground terminal 129 and input terminal 114, and further connected to input lead 130 at a location between the connection of ground lead 131 and input terminal 114 via a diode lead 138. Diode 134 is arranged to oppose current flow from input lead 130, i.e. from input terminal 114 and sine wave generator 102, to ground terminal 136 to half-wave rectify and clamp input voltage received at input terminal 114 to ground. In the illustrated exemplary embodiment diode 134 is a Schottky diode, which provides good efficiency at high switching speeds.

    [0018] SADO circuit 100 further includes a hysteresis circuit 140. Hysteresis circuit 140 is connected between output terminal 118 and reference terminal 116 and includes a reference resistor 142 and a feedback resistor 144. Reference resistor 142 is connected in series between a reference voltage source 146 and reference terminal 116. Reference voltage source 146 sets a trip threshold for comparator 112. Feedback resistor 144 is connected in parallel with comparator 112, interconnects output terminal 118 with reference terminal 116, and is connected to reference voltage lead 148 at a location between reference terminal 116 and reference resistor 142.

    [0019] It is contemplated that feedback resistor 144 be arranged to set a width of a hysteresis band (shown in Fig. 3) of SADO circuit 100, i.e. a voltage separation 174 (shown in Fig. 3) between a low-to-high switching threshold 172 (shown in Fig. 3) and a high-to-low switching threshold 170 (shown in Fig. 3). The width of the hysteresis band is established at least in part based upon resistance of a pull-up resistor 156 connecting a digital bus pull-up voltage source 158 in series to digital bus 110.

    [0020] With reference to Fig. 3, a graph 160 of an input waveform 162 and a digital output waveform 164 are shown. Time is indicated on x-axis 166. Voltage is indicted at y-axis 168. Input waveform 162 is provided to SADO circuit 100 (shown in Fig. 1) in a sampling arrangement, shown in an exemplary way in Fig. 1 with SADO circuit 100 being connected in parallel with an excitation lead extending between sine wave generator 102 and sensor 2, from sine wave generator 102 (shown in Fig. 1).

    [0021] As input waveform 162 arrives SADO circuit 100 converts input waveform 162 into digital output waveform 164, which SADO circuit 100 provides to digital bus 110. The above-described circuitry pulse width modulates digital output waveform 164 according to time interval, e.g., the low interval shown in Fig. 3, between a high-to-low threshold 170 (VH) and low-to-high threshold 172 (VL). High-to-low threshold 170 (VH) is greater than low-to-high threshold 172 (VL), a wide hysteresis band 174 of SADO circuit 100 separating high-to-low threshold 170 (VH) and low-to-high threshold 172 (VL).

    [0022] SADO circuit 100 compares voltage amplitude of input waveform 162 against high-to-low voltage threshold 170 during intervals when digital output waveform 164 is 'high', e.g., a '1', and further compares the voltage amplitude of input waveform 162 against low-to-high threshold 172 when digital output waveform 164 is 'low', e.g., is a zero. High-to-low voltage threshold 170 (VH) and low-to-high threshold 172 (VL) are separated in voltage magnitude by a wide hysteresis band 174, which is established by hysteresis circuit 140 (shown in Fig. 2) and operates to switch the reference voltage applied to reference terminal 116 (shown in Fig. 2) according to whether digital output waveform 164 is high or low. The proportion of time during which the digital output waveform 164 is high corresponds to the duty cycle modulated into digital output waveform 164, which is provided in real-time to FPGA device or processor 108 for determining health of input waveform 162.

    [0023] With reference to Fig. 4, a graph 176 of duty cycle D born by digital output wavefrom 164 (shown in Fig. 3) in association with amplitude A of input waveform 162 (shown in Fig. 3) is shown. Amplitude A is expressed in volts on x-axis 178. Duty cycle D is expressed as a percentage on y-axis 180. A duty cycle function 182 extends from 0 volts on the left-hand side of graph 176 to about 20 volts on the right-hand side of graph 176, duty cycle function 182 varying in a non-linear with amplitude A. As will be appreciated by those of skill in art in view of the present disclosure, the non-linearity of duty cycle function 182 allows FPGA device or processor 108 (shown in Fig. 1) to calculate both sinusoidal frequency and amplitude using only a single digital input, i.e., digital output waveform 164 (shown in Fig. 3).

    [0024] Frequency is calculated by measuring time intervals between rising and falling edges of digital output wavefrom 164. Amplitude of input waveform 162 is determined by referencing an observed duty cycle (via pulse-width modulation imparted to digital output waveform 164) with an associated amplitdue according to duty cycle function 182. In an exemplary implementation shown in Fig. 4, a duty cycle of 78% is cross-referenced in lookup table 106 (shown in Fig. 1) to recognize that amplitude of input wavefrom 162 is about 6 volts. This amplitude can then be compared against a selected voltage value, or minimum to maximum voltage range (i.e., AMIN to AMAX), to assess health of input waveform 162.

    [0025] Duty cycle function 182 is arrived at via SADO circuitry shown in Fig. 2 as follows. Input waveform 162 a sinusoidal waveform with amplitude A and an angular frequency ω, and generally conforms to Equation 1:



    [0026] Assuming comparator 112 (shown in Fig. 2) has a high-to-low threshold VH and a low-to-high threshold VL, then the time associated with input waveform 160 crossing high-to-low threshold VH is according to Equation 2:



    [0027] The time associated with input waveform 162 crossing low-to-high threshold VL is according to Equation 3:



    [0028] The duty cycle D of the input waveform is according to Equation 4:



    [0029] Substituting Equation 2 and Equation 3 into Equation 4, and accounting for the constraint imposed by the dome of the arcsine yields an expression that is independent of angular frequency according to Equation 5:

    which is illustrated graphically in Fig. 4 with duty cycle function 182.

    [0030] In certain embodiments, output of SADO circuit 100 (shown in Fig. 1) is not as accurate as output from a dedicated analog-to-digital converter. However, using discrete components, embodiments of SADO circuit 100 can realize amplitude measurement accuracy of about +/-10% of actual amplitude, which is generally sufficient for sensor interfaces, e.g., sensor interface 10 (shown in Fig. 1).

    [0031] With reference to Fig. 5, a method 200 of monitoring amplitude and frequency of a sinusoidal voltage waveform is shown. Method 200 includes generating a digital PWM signal whose duty cycle varies non-linearly with amplitude of the sinusoidal voltage waveform. The digital PWM is analyzed, and amplitude and frequency representative of the sinusoidal voltage waveform are calculated using just the digital PWM signal. In the illustrated exemplary embodiment a method of monitoring excitation voltage for a sensor, e.g., sensor 2 (shown in Fig. 1) is shown. It is to be understood and appreciated that this is for illustration purposes only and is non-limiting.

    [0032] Method 200 includes receiving an input voltage with a sinusoidal waveform (shown in Fig. 2) at a comparator input terminal, e.g., input terminal 114 (shown in Fig. 2), as shown with box 210. Method 200 also includes receiving a reference voltage (shown in Fig. 3) at a comparator reference terminal, e.g., reference terminal 116 (shown in Fig. 1), as shown with box 220. Amplitude of the input voltage is compared to the reference voltage, as shown with box 230. If the input voltage is not greater than the reference voltage then output of the SADO circuit remains the same and monitoring continues, as shown with arrow 250.

    [0033] When the comparison indicates that the input voltage is greater than the reference voltage then the output of the SADO circuit is toggled between high and low, as shown with arrow 260 and box 270. The reference voltage is then offset with the toggled output, as shown with box 280. The offsetting can change the reference from a high-to-low threshold to a low-to-high threshold, as shown with box 282. The offsetting can change the reference from a low-to-high threshold to a high-to-low threshold, as shown with box 284. The magnitude of the reference voltage changes according when the waveform is switched high or low. It is contemplated that monitoring can continue with output being toggled between high and low according a wide hysteresis defined between the low-to-high and high-to-low thresholds to synthesize a PWM digital output, as shown with arrow 290.

    [0034] When providing a sinusoidal voltage excitation waveform it can be desirable to monitor amplitude of the sinusoid. Usually this involves feeding the sinusoid back through an analog-to-digital converter (ADC). While generally satisfactory for its intended purpose, the number of ADC channels available in a given application may be such that no monitoring channel is available to receive the sinusoidal waveform.

    [0035] In embodiments described herein a SADO circuit is provided. The SADO circuit is configured to convert an input voltage varying according to a sinusoidal waveform to a digital pulse-width modulated (PWM) output, the PWM output duty cycle varying nonlinearly with amplitude of the sinusoidal waveform. Varying the PWM output duty cycle nonlinearly with the sinusoidal voltage amplitude allows a microprocessor or a field-programmable gate array (FPGA) to calculate both sinusoidal frequency and amplitude using only a single digital input, i.e., the SADO circuit output. This allows for sinusoidal amplitude and frequency monitoring using digital inputs instead of analog inputs, potentially reducing cost as digital inputs can be more readily implemented than analog inputs.

    [0036] The methods and systems of the present disclosure, as described above and shown in the drawings, provide for sensor interfaces with superior properties including the sinusoidal excitation voltage waveform amplitude and frequency monitoring with the use of an ADC. While the apparatus and methods of the subject disclosure have been shown and described with reference to preferred embodiments, those skilled in the art will readily appreciate that changes and/or modifications may be made thereto without departing from the scope of the subject disclosure.


    Claims

    1. A sensor interface, comprising:
    a circuit to allow an amplitude and frequency of a sinusoidal voltage waveform to be digitally monitored, comprising:
    a sinusoidal-amplitude-to-digital-output, SADO, circuit (100), comprising:

    a comparator (112) with an input terminal (114), a reference terminal (116), and an output terminal (118);

    a digital bus (110) connected to the output terminal;

    a reference voltage source (120) connected via a resistor (142) to the reference terminal; and

    a feedback resistor (144) connected in parallel with the comparator (112) between the output terminal and the reference terminal to provide hysteresis and convert an input voltage received at the input terminal into a digital pulse-width modulated, PWM, waveform that varies non-linearly with amplitude of the input voltage;

    said sensor interface further comprising:

    a sine wave generator (102), for applying a sinusoidal voltage waveform to a sensor, connected to the input terminal of the comparator to provide the input voltage as a sinusoidal voltage waveform; and

    a field programmable gate array, FPGA, (108) or microprocessor device connected to the digital bus and configured to calculate the frequency of the sinusoidal voltage waveform using the PWM waveform received at the comparator output terminal, and to calculate the amplitude of the waveform by referencing, from a lookup table, an observed duty cycle of the PWM waveform .with an associated amplitude according to a duty cycle function.


     
    2. The sensor interface as recited in claim 1, further comprising a voltage divider circuit (124) connected to the comparator input terminal to attenuate the input voltage; and/or further comprising a half-wave rectifier circuit (130) connected to the comparator input terminal, configured to half-wave rectify and clamp the input voltage.
     
    3. The sensor interface as recited in claim 1 or 2, further comprising a pull-up resistor connected in series between the digital bus and a digital bus voltage source.
     
    4. The sensor interface as recited in any preceding claim, further comprising the lookup table (106) accessible by the FPGA or microprocessor device with voltage amplitude associated with duty cycle.
     
    5. A method of monitoring amplitude and frequency of a sinusoidal voltage waveform using a sensor interface as claimed in any preceding claim.
     
    6. The method as recited in claim 5, wherein the sinusoidal waveform is an excitation voltage for a sensor.
     
    7. The method as recited in claim 5 or 6, further comprising:

    switching the output voltage received at the comparator output terminal from a first voltage to a second voltage when amplitude of the input voltage crosses a low-to-high threshold; and

    switching the output voltage applied at the comparator output terminal from the second voltage to the first voltage when amplitude of the input voltage crosses a high-to-low threshold.


     
    8. The method as recited in claim 7, wherein the high-to-low threshold is greater than the low-to-high threshold.
     
    9. The method as recited in claim 7 or 8, further comprising generating the low-to-high threshold by offsetting the reference voltage by the first voltage subsequent to switching from the second voltage to the first voltage.
     
    10. The method as recited in claim 7, 8, or 9, further comprising generating the high-to-low threshold by offsetting the reference voltage offset by the second voltage subsequent to switching from the first voltage to the second voltage.
     


    Ansprüche

    1. Sensorschnittstelle, umfassend:
    eine Schaltung zum Ermöglichen, dass eine Amplitude und Frequenz einer sinusförmigen Spannungswellenform digital überwacht wird, umfassend:
    eine Sinus-Amplitude-an-Digital-Ausgabe-, SADO-, Schaltung (100), umfassend:

    einen Komparator (112) mit einem Eingangsanschluss (114), einem Referenzanschluss (116) und einem Ausgangsanschluss (118);

    einen Digitalbus (110), der mit dem Ausgangsanschluss verbunden ist;

    eine Referenzspannungsquelle (120), die über einen Widerstand (142) mit dem Referenzanschluss verbunden ist; und

    einen Rückkopplungswiderstand (144), der zwischen dem Ausgangsanschluss und dem Referenzanschluss parallel mit dem Komparator (112) geschaltet ist, um Hysterese bereitzustellen und eine Eingangsspannung, die am Eingangsanschluss aufgenommen wird, in eine digitale pulsweitenmodulierte, PWM, Wellenform umzuwandeln, die nichtlinear mit der Amplitude der Eingangsspannung variiert;

    wobei die Sensorschnittstelle ferner umfasst:

    einen Sinuswellengenerator (102) zum Anlegen einer sinusförmigen Spannungswellenform an einen Sensor, der mit dem Eingangsanschluss des Komparators verbunden ist, um die Eingangsspannung als eine sinusförmige Spannungswellenform bereitzustellen; und

    ein feldprogrammierbares Gate-Array, FPGA, (108) oder eine Mikroprozessorvorrichtung, das bzw. die mit dem Digitalbus verbunden und dazu konfiguriert ist, die Frequenz der sinusförmigen Spannungswellenform unter Verwendung der an dem Komparatorausgangsanschluss empfangenen PWM-Wellenform zu berechnen und die Amplitude der Wellenform zu berechnen, indem aus einer Nachschlagtabelle ein beobachtetes Tastverhältnisses der PWM-Wellenform mit einer zugeordneten Amplitude gemäß einer Tastverhältnisfunktion referenziert wird.


     
    2. Sensorschnittstelle nach Anspruch 1, ferner umfassend eine Spannungsteilerschaltung (124), die mit dem Komparatoreingangsanschluss verbunden ist, um die Eingangsspannung abzuschwächen; und/oder ferner umfassend eine Halbwellengleichrichterschaltung (130), die mit dem Komparatoreingangsanschluss verbunden und dazu konfiguriert ist, die Eingangsspannung einer Halbwellengleichrichtung und Clamping zu unterziehen.
     
    3. Sensorschnittstelle nach Anspruch 1 oder 2, ferner umfassend einen Pull-up-Widerstand, der in Reihe zwischen den Digitalbus und eine Digitalbusspannungsquelle geschaltet ist.
     
    4. Sensorschnittstelle nach einem vorangehenden Anspruch, ferner umfassend die für das FPGA oder die Mikroprozessorvorrichtung zugängliche Nachschlagtabelle (106) mit dem Tastverhältnis zugeordneter Spannungsamplitude.
     
    5. Verfahren zum Überwachen von Amplitude und Frequenz einer sinusförmigen Spannungswellenform unter Verwendung einer Sensorschnittstelle nach einem der vorangehenden Ansprüche.
     
    6. Verfahren nach Anspruch 5, wobei die sinusförmige Spannungswellenform eine Erregungsspannung für einen Sensor ist.
     
    7. Verfahren nach Anspruch 5 oder 6, ferner umfassend:

    Umschalten der an dem Komparatorausgangsanschluss aufgenommenen Spannung von einer ersten Spannung auf eine zweite Spannung, wenn die Amplitude der Eingangsspannung einen Niedrig-zu-hoch-Schwellenwert überschreitet; und

    Umschalten der an den Komparatorausgangsanschluss angelegten Spannung von der zweiten Spannung auf die erste Spannung, wenn die Amplitude der Eingangsspannung einen Hoch-zu-niedrig-Schwellenwert überschreitet.


     
    8. Verfahren nach Anspruch 7, wobei der Hoch-zu-niedrig-Schwellenwert größer als der Niedrig-zu-hoch-Schwellenwert ist.
     
    9. Verfahren nach Anspruch 7 oder 8, ferner umfassend Erzeugen des Niedrig-zu-hoch-Schwellenwerts durch Versetzen der Referenzspannung um die erste Spannung im Anschluss an das Umschalten von der zweiten Spannung auf die erste Spannung.
     
    10. Verfahren nach Anspruch 7, 8 oder 9, ferner umfassend Erzeugen des Hoch-zu-niedrig-Schwellenwerts durch Versetzen der versetzten Referenzspannung um die zweite Spannung im Anschluss an das Umschalten von der ersten Spannung auf die zweite Spannung.
     


    Revendications

    1. Interface de capteur, comprenant :
    un circuit pour permettre la surveillance numérique d'une amplitude et d'une fréquence d'une forme d'onde de tension sinusoïdale, comprenant :
    un circuit d'amplitude sinusoïdale à sortie numérique, SADO, (100), comprenant :

    un comparateur (112) avec une borne d'entrée (114), une borne de référence (116) et une borne de sortie (118) ;

    un bus numérique (110) connecté à la borne de sortie ;

    une source de tension de référence (120) connectée via une résistance (142) à la borne de référence ; et

    une résistance de rétroaction (144) connectée en parallèle avec le comparateur (112) entre la borne de sortie et la borne de référence pour fournir une hystérésis et convertir une tension d'entrée reçue à la borne d'entrée en une forme d'onde numérique modulée en largeur d'impulsion, PWM, qui varie de manière non linéaire avec l'amplitude de la tension d'entrée ;

    ladite interface de capteur comprenant en outre :

    un générateur d'onde sinusoïdale (102), pour appliquer une forme d'onde de tension sinusoïdale à un capteur, connecté à la borne d'entrée du comparateur afin de fournir la tension d'entrée en tant que forme d'onde de tension sinusoïdale ; et

    un réseau prédiffusé programmable, FPGA, (108) ou un dispositif à microprocesseur connecté au bus numérique et configuré pour calculer la fréquence de la forme d'onde de tension sinusoïdale à l'aide de la forme d'onde PWM reçue à la borne de sortie de comparateur, et pour calculer l'amplitude de la forme d'onde en référençant, à partir d'une table de consultation, un cycle d'utilisation observé de la forme d'onde PWM avec une amplitude associée selon une fonction de cycle d'utilisation.


     
    2. Interface de capteur selon la revendication 1, comprenant en outre un circuit diviseur de tension (124) connecté à la borne d'entrée de comparateur pour atténuer la tension d'entrée ; et/ou comprenant en outre un circuit redresseur demi-onde (130) connecté à la borne d'entrée de comparateur, configuré pour effectuer un redressement demi-onde et un blocage de la tension d'entrée.
     
    3. Interface de capteur selon la revendication 1 ou 2, comprenant en outre une résistance de rappel vers le niveau haut connectée en série entre le bus numérique et une source de tension de bus numérique.
     
    4. Interface de capteur selon une quelconque revendication précédente, comprenant en outre la table de consultation (106) accessible par le FPGA ou un dispositif à microprocesseur avec une amplitude de tension associée au cycle d'utilisation.
     
    5. Procédé de surveillance d'une amplitude et d'une fréquence d'une forme d'onde de tension sinusoïdale à l'aide d'une interface de capteur selon une quelconque revendication précédente.
     
    6. Procédé selon la revendication 5, dans lequel la forme d'onde sinusoïdale est une tension d'excitation pour un capteur.
     
    7. Procédé selon la revendication 5 ou 6, comprenant en outre :

    la commutation de la tension de sortie reçue à la borne de sortie de comparateur d'une première tension à une seconde tension lorsqu'une amplitude de la tension d'entrée franchit un seuil faible à élevé ; et

    la commutation de la tension de sortie appliquée à la borne de sortie de comparateur de la seconde tension à la première tension lorsque l'amplitude de la tension d'entrée franchit un seuil élevé à faible.


     
    8. Procédé selon la revendication 7, dans lequel le seuil élevé à faible est supérieur au seuil faible à élevé.
     
    9. Procédé selon la revendication 7 ou 8, comprenant en outre la génération du seuil faible à élevé en compensant la tension de référence par la première tension après la commutation de la seconde tension à la première tension.
     
    10. Procédé selon la revendication 7, 8 ou 9, comprenant en outre la génération du seuil élevé à faible en compensant la tension de référence compensée par la seconde tension après la commutation de la première tension à la seconde tension.
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description