(19)
(11)EP 3 398 206 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
11.12.2019 Bulletin 2019/50

(21)Application number: 17705143.0

(22)Date of filing:  15.02.2017
(51)International Patent Classification (IPC): 
H01L 23/66(2006.01)
H01L 23/498(2006.01)
H05K 1/11(2006.01)
H01L 23/13(2006.01)
H05K 1/02(2006.01)
H05K 1/16(2006.01)
(86)International application number:
PCT/EP2017/053424
(87)International publication number:
WO 2017/140737 (24.08.2017 Gazette  2017/34)

(54)

PCB BASED SEMICONDUCTOR PACKAGE WITH IMPEDANCE MATCHING NETWORK ELEMENTS INTEGRATED IN THE PCB

HALBLEITERPACKAGE, WELCHES EINE LEITERPLATTE AUFWEIST, DIE MIT INTEGRIERTEN IMPEDANZABGLEICHENDEN NETZWERKELEMENTEN VERSEHEN IST

BOÎTIER SEMI-CONDUCTEUR INCLUANT UN CIRCUIT IMPRIMÉ DANS LEQUEL DES ÉLÉMENTS DE RÉSEAU D'ADAPTATION D'IMPÉDANCE SONT INTÉGRÉS


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 18.02.2016 US 201615046923

(43)Date of publication of application:
07.11.2018 Bulletin 2018/45

(60)Divisional application:
19207270.0

(73)Proprietor: Cree, Inc.
Durham, NC 27703 (US)

(72)Inventors:
  • DANI, Asmita
    San Jose California 95123 (US)
  • GOZZI, Cristian
    Santa Clara, California 95051 (US)
  • MU, Qianli
    San Jose California 95124 (US)

(74)Representative: Appleyard Lees IP LLP 
15 Clare Road
Halifax HX1 2HY
Halifax HX1 2HY (GB)


(56)References cited: : 
EP-A2- 0 563 873
US-A1- 2004 012 938
WO-A1-03/037048
US-A1- 2013 256 858
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    TECHNICAL FIELD



    [0001] The present application relates to RF power packages, in particular PCB (printed circuit board) based packages for RF power applications.

    BACKGROUND



    [0002] Ceramic air-cavity and plastic air-cavity/overmold packages are widely used for RF/microwave discrete power transistors. Both types of packages provide a reliable and easy-to-handle handle mechanical design. However, ceramic air-cavity and plastic air-cavity/overmold packages are difficult to design in an electrical sense due to their stack-up and predetermined physical dimensions.

    [0003] RF transistors are commonly packaged with input and output matching networks. These input and output matching networks are typically provided by discrete reactive components, i.e., capacitors and inductors. For example, an output matching network for an RF transistor may be provided from a discrete capacitor that is mounted to the package substrate. The RF transistor is connected to the capacitor by inductive bond wires. The parameters of the output matching network can be tailored to match the output impedance of the packaged device to a fixed value (e.g., 50 ohms). In a ceramic open cavity RF package, one common approach for the output matching network is a high pass topology, which is designed to propagate higher frequency signals and to shunt lower frequency signals.

    [0004] Parasitic capacitances, inductances, and resistances in the conventional input/output matching network configurations described above detrimentally impact the performance and/or power consumption of the packaged RF device. These parasitic effects are attributed to mutual inductance and capacitive coupling between the bond wires and the associated bond pads. High-frequency effects also influence the behaviour of the input/output matching network. The physical arrangement of the bond wires can be altered to mitigate this phenomena, but only with limited success.

    [0005] In the background art, patent application document WO2003/037048A1 describes a multilayer RF amplifier module. Patent application document US2004/0012938A1 describes an interconnect module with reduced power distribution impedance.

    SUMMARY



    [0006] According to the present invention there is provided a semiconductor package according to claim 1, and a semiconductor assembly according to claim 14. Additional features will be appreciated from the dependent claims and the description herein. Any described embodiments which do not fall within the scope of the claims are to be interpreted as examples useful for understanding of the invention.

    [0007] A semiconductor package is disclosed. In one example, the semiconductor package includes a metal baseplate having a die attach region and a peripheral region, a transistor die having a reference terminal attached to the die attach region and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the peripheral region and a second side facing away from the baseplate. The multilayer circuit board includes two embedded electrically conductive layers that are separated from the first and second sides by layers of composite fiber, and an embedded dielectric layer disposed between the two embedded electrically conductive layers. The embedded dielectric layer has a higher dielectric constant than the layers of composite fiber.

    [0008] A semiconductor assembly is also disclosed. In one example, the semiconductor assembly includes a semiconductor package as described above and a global printed circuit board. The multilayer circuit board connects the RF terminal of the transistor die to the global printed circuit board.

    [0009] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

    BRIEF DESCRIPTION OF THE FIGURES



    [0010] The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.

    Figure 1 illustrates a partial sectional view of a semiconductor package including a multilayer circuit board, according to an embodiment.

    Figure 2, which includes Figs 2A and 2B, illustrates partial cross-sectional views of a multilayer circuit board, according to an embodiment.

    Figure 3 illustrates a circuit topology for a semiconductor package with a high-pass output matching network, according to an embodiment.

    Figure 4 illustrates a circuit topology for a semiconductor package with a high-pass output matching network, according to another embodiment.

    Figure 5 illustrates a physical layout of the semiconductor package of Fig. 4 with the high-pass output matching network integrated in a multilayer circuit board from a plan-view perspective, according to an embodiment.

    Figure 6 illustrates a physical layout of the semiconductor package of Fig. 4 with the high-pass output matching network integrated in a multilayer circuit board from an isometric view perspective, according to an embodiment.

    Figure 7 illustrates a circuit topology for a semiconductor package with a high-pass output matching network, according to another embodiment.

    Figure 8 illustrates a physical layout of the semiconductor package of Fig. 7 with the high-pass output matching network integrated in a multilayer circuit board from a plan-view perspective, according to an embodiment.

    Figure 9 illustrates a physical layout of the semiconductor package of Fig 7 with the high-pass output matching network integrated in a multilayer circuit board from an isometric view perspective, according to an embodiment.

    Figure 10 illustrates a circuit topology for a semiconductor package with a high-pass output matching network and low-frequency termination capacitor, according to an embodiment.

    Figure 11 illustrates a physical layout of the semiconductor package of Fig 10, with the high-pass output matching network integrated in a multilayer circuit board and a low-frequency termination capacitor mounted to an upper side of the multilayer circuit board, from a plan-view perspective, according to an embodiment.

    Figure 12 illustrates a physical layout of the semiconductor package of Fig 10, with the high-pass output matching network integrated in a multilayer circuit board and a low-frequency termination capacitor mounted to an upper side of the multilayer circuit board, from an isometric view perspective, according to an embodiment.

    Figure 13 illustrates a side-view of a multilayer circuit board with a thin surface-mount capacitor embedded within the multilayer circuit board, according to an embodiment.


    DETAILED DESCRIPTION



    [0011] By way of introduction, post-published patent application US2017/0034913 A1 describes various embodiments of a package design for, e.g., RF power transistors. To briefly summarize these embodiments, the package design is treated as part of the electrical design of the system instead of a just a mechanical component. To this end, the package includes a multilayer printed circuit board. The multi-layer circuit board can include a minimum of four layers, two of which are ground layers and two of which are signal layers. The signal and ground layers can be interleaved with one another to reduce interference and improve performance. Various RF components can be embedded within the multi-layer circuit board using the embedded signal layer. Examples of these RF components include integrated harmonics resonators, balanced power combiner networks, etc. In this way, fewer external components are needed and space efficiency of the package is improved.

    [0012] Embodiments of a multilayer circuit board described herein include an embedded dielectric layer that is disposed between embedded signal and ground layers. This design allows for the formation of embedded RF components with advantageous electrical characteristics. The embedded dielectric layer has a substantially higher dielectric constant than typical PCB materials that are used to separate and insulate the various layers. For example, the embedded dielectric layer may be formed from a polymer laminate material with a dielectric constant of between 4 and 30 and a thickness from 2 µm to 24 µm. By way of comparison, typical PCB dielectric layers, have a dielectric constant of 3.7 and a typical minimum thickness of 100 µm. As a result, the performance and/or space utilization of the integrated RF components formed in the presently disclosed multilayer circuit board compares favorably to the RF components that are formed using typical PCB dielectric layers. According to one embodiment, an embedded capacitor with a capacitance value of at least 100 pF (picofarads) is formed in the multilayer circuit board. A capacitor of this magnitude is not achievable using conventionally known PCB materials (e.g., composite fiber) as the interlayer dielectric while maintaining typical package size constraints, e.g., 10 mm x 7 mm.

    [0013] Figure 1 illustrates a partial sectional view of a semiconductor package, according to an embodiment. The semiconductor package includes a metal baseplate 100 having a die attach region 102 and a peripheral region 104, a transistor die 106 attached to the die attach region 102 of the baseplate 100, a multilayer circuit board 108 such as a PCB for providing electrical connections to the transistor die 106, and an optional lid 110 for enclosing the transistor die 106. The baseplate 100 is made of an electrically and thermally conductive material such as Cu, CPC (copper, copper-molybendum, copper laminate structure), CuW, etc. In some cases, the transistor die 106 attached to the baseplate 100 is a power transistor die such as an RF amplifier die. For example, the transistor die 106 can be an LDMOS (laterally diffused metal oxide semiconductor), vertical power MOSFET (metal oxide semiconductor field effect transistor) or GaN RF power transistor die. The transistor die 106 has a reference terminal 112 such as a source or emitter terminal attached to the die attach region 102 and an RF terminal 114 such as a drain or collector terminal facing away from the baseplate 100. The control (gate) terminal of the transistor die is out of view in Figure 1. More than one transistor die can be attached to the baseplate 100, e.g., in the case of a Doherty amplifier in which a main and one or more peaking amplifiers can be attached to the baseplate 100

    [0014] The multilayer circuit board 108 has a first side 116 attached to the peripheral region 104 of the baseplate 100 and a second side 118 facing away from the baseplate 100. The multilayer circuit board 108 extends beyond an exterior sidewall 120 of the baseplate 100 for attachment to another circuit board 122.

    [0015] The semiconductor package is connected to a global printed circuit board 122. The global printed circuit board 122 is part of a sub-system or system that incorporates the semiconductor package as a constituent component. Other semiconductor devices that are part of this sub-system or system can be connected to the global printed circuit board 122 as well. This global printed circuit board 122 can have a recessed region for receiving the baseplate 100 of the semiconductor package. A metal slug 124 can be disposed in the recess for enhancing the thermal and electrical conduction between the global printed circuit board 122 and the multilayer circuit board 108. The global printed circuit board 122 may include a heatsink 126 containing aluminium or copper, for example, which attaches to the baseplate 100 of the semiconductor package.

    [0016] The RF terminal 114 of the transistor die 106 is electrically connected to the multilayer circuit board 108, which in turn is connected to the global printed circuit board 122. As shown in Fig. 1, an electrically conductive bond wire 128 forms a direct electrical connection between the RF terminal 114 of the transistor die 106 and a first bond pad 130 that is disposed on the second side 118 of the multilayer circuit board 108. The multilayer circuit board 108 further includes two pads 132, 134 disposed on the first side 116 of the multilayer circuit board. The first pad 132 directly faces and electrically connects to a signal pad of the global printed circuit board 122, and thus forms a signal connection between the two. The second pad 134 directly faces and electrically connects to a ground pad of the global printed circuit board 122 (as well as the baseplate 100), and thus forms a ground connection between the two. The multilayer circuit board 108 contains conductive signal layers and via structures that connect the first bond pad 130 and the second bond pad 132. Using these conductive layers, the multilayer circuit board 108 connects the RF terminal 114 of the transistor die 106 to the global printed circuit board 122. Moreover, an RF impedance matching network can be embedded in the multilayer circuit board 108 and coupled to the RF terminal 114 of the transistor die 106 so as to match the impedance of the packaged device to a desired value (e.g., 50 ohms).

    [0017] Referring to Figs. 2A and 2B, the interior structure of the multilayer circuit board 108 is depicted, according to an embodiment. The multilayer circuit board 108 includes a number of conductive layers. According to an embodiment, the multilayer circuit board 108 has four electrically conductive layers: a first signal layer 136; a first ground layer 138; a second signal layer 140; and a second ground layer 142. Each of these layers is formed from a standard conductive material, such as copper. The first signal layer 136 is disposed at the second side 118 of the multilayer circuit board 108 and the second ground layer 142 is disposed at the first side 116 of the multilayer circuit board 108. That is, the first signal layer 136 and the second ground layer 142 are disposed at outer, opposing sides of the multilayer circuit board 108. As used herein, "disposed at the first side" or "disposed at the second side," as the case may be, refers to the fact that outer side of the particular element is coextensive with the first or second side of the multilayer circuit board.

    [0018] The first ground layer 138 and the second signal layer 140 are embedded in the multilayer circuit board. As used herein, "embedded" refers to the fact that the particular element is incorporated into the structure of the multilayer circuit board 108 and is separated from both the first side 116 and the second side 118 by another element or layer. According to an embodiment, the multilayer circuit board 108 includes a first embedded layer 144 disposed between the first signal layer 136 and the first ground layer 138. The first embedded layer 144 and the first signal layer 136 separate the first ground layer 138 from the second surface 118. Likewise, the multilayer circuit board 108 includes a second embedded layer 146 disposed between the second signal layer 140 and the second ground layer 142. The second embedded layer 146 and the second ground layer 142 separate the second signal layer 140 from the first surface 116. According to the invention, the first embedded layer 144 and the second embedded layer 146 are formed from an insulative pre-impregnated composite fiber material, such as polytetrafluoroethylene, FR-1, FR-2, FR-3, FR-4, FR-5, FR-6, G-10, CEM-1, CEM-2, CEM-3, CEM-4, CEM-5, etc. The first and second embedded layers 144, 146 have a thickness of at least 75 µm and according to one embodiment, have a thickness of about 100 µm.

    [0019] The multilayer circuit board 108 further includes an embedded dielectric layer 148 disposed between the first ground layer 138 and the second signal layer 140. The first ground layer 138 and the second signal layer 140 are thus arranged in a parallel plate-capacitor configuration. According to an embodiment, the embedded dielectric layer 148 directly contacts the first ground layer 138 and the second signal layer 140.

    [0020] The capacitance (C) of a parallel plate-capacitor is given by equation 1 as follows:

    where ε0 = vacuum permittivity, εr = relative permittivity of the dielectric, A = plate area, and t = thickness of the dielectric.

    [0021] Applying equation 1, a package designer can form a parallel plate-capacitor from a section of the of the second signal layer 140 by defining a certain area of the second signal layer 140 to achieve a certain capacitance value. The other parameters of the equation, i.e., relative permittivity of the dielectric and thickness of the dielectric are fixed values that are dictated by the structure of the multilayer circuit board 108. According to an embodiment, the embedded dielectric layer 148 is formed from a polymer capacitance laminate material with a high dielectric constant, e.g., between 4 and 30, and more particularly above 10 in some embodiments. The embedded dielectric layer 148 may have a thickness of between 2 µm and 50 µm, and more particularly between 2 µm and 24 µm is some embodiments.

    [0022] The multilayer circuit board 108 also includes via structures for connecting and/or providing electrical access to various components. More particularly, Fig. 2A depicts an insulated signal via 150 for connecting sections of the first and second signal layers 136, 140 together. The insulated signal via 150 extends through the first embedded layer 144. Similar structures can be used to connect any two layers together. The insulated signal via 150 may include a cap 152 such as a copper cap in the case of a copper via and a top pad 154 adjacent the cap 152 in the first (uppermost) signal layer 136. The bottom of the insulated signal via 150 includes a conductive pad 156 that contacts a portion of the second signal layer 140.

    [0023] Figure 2B illustrates a sectional view of an insulated path via 158 that extends from the first side 116 to the second side 118 and extends through all of the layers disposed between. The insulated path via 158 electrically contacts the second ground layer 142 by a conductive pad 156 and the first ground layer 140 by another conductive pad 156. The insulated path via 158 extends to the second side 118 in a region of the multilayer circuit board 108 that is a devoid of the first signal layer 136. As a result, the first and second ground layers 140, 142 are connected together and are electrically accessible at the second side 118 of the multilayer circuit board 108 by one of the conductive pads 156. A ground terminal of the multilayer circuit board 108 can be formed by the caps 220 on both sides of the multilayer circuit board 108.

    [0024] Referring to Fig. 3, an exemplary circuit topology is depicted. The circuit includes the transistor die 106 previously discussed with reference to Fig. 1. The drain terminal of the transistor die 106 is electrically connected to the multilayer circuit board 108 by the electrically conductive bond wire 128 previously discussed with reference to Fig. 1. The bond wire 128 connects to a first bond pad 154 of the multilayer circuit board 108, which may be formed in the first signal layer 136 and is represented by a first transmission line TL1 in the circuit schematic.

    [0025] The bond wire 128 is connected, via the first bond pad 154, to a shunt LC network 160 that is provided by the multilayer circuit board 108. The shunt LC network 160 includes reactive components that are configured to transform the output impedance of the circuit to a desired matching value (e.g., 50 ohms). The shunt LC network 160 includes a second transmission line TL2, which schematically represents one of the insulated signal vias 150 previously described. The second transmission line TL2 electrically connects the first transmission line TL1 (i.e., the top level bond pad) to an embedded reactive component that is integrated in multilayer circuit board 108. According to an embodiment, this embedded reactive component is an embedded capacitor C1. The positive electrode of the embedded capacitor C1 is formed by a first isolated section of the second signal layer 140, and the ground electrode of the first capacitor is formed by a first isolated section of the first ground layer 138. The embedded dielectric layer 148 is disposed between the two electrodes, i.e., so as to form a parallel plate capacitor described with reference to Fig. 2

    [0026] The first transmission line TL1 and the second transmission line TL2 are connected to a third transmission line TL3, which may be provided by another isolated section of the first signal layer 136. The third transmission line TL3 connects to a package terminal, which in turn may be connected to the global circuit board 122 described with reference to Fig. 1.

    [0027] Referring to Fig. 4, an exemplary circuit topology is depicted, according to another embodiment. The circuit topology of Fig. 4 may be substantially similar or identical to that of Fig. 3 with the exception that the shunt LC network 160 is configured with a shunt inductor 162 and a radial stub 164. In the embodiment of Fig. 4, one of the insulated signal vias 150 connects the first transmission line TL1 (i.e., the top level bond pad) to a shunt inductor 162. The shunt inductor 162 may be provided by a linear strip of the second signal layer 140. The shunt inductor 162 connects to an open-circuit radial stub 164.

    [0028] Referring Figs. 5 and 6, a physical layout of the semiconductor package of Fig. 4 is depicted. In the drawings, similarly numbered elements refer to corresponding circuit elements schematically represented in Fig. 4. In the physical layout, a plurality of the bond wires 128 extend directly between the transistor die 106 and a plurality of bond pads 154 that are formed in the first signal layer 136. These bond pads 154 are electrically connected to the second signal layer 140 by insulated signal vias 150. The shunt inductor 162 and the open-circuit radial stub 164 are formed in the second signal layer 140 and connect to the bond pads 154 (and to the bond wires 128) by the insulated signal vias 150. Optionally, the multilayer circuit board 108 may include a plurality of insulated path vias 158 as described with reference to Fig. 2B of the present Specification. These insulated path vias 158 are electrically connected to the ground layers to provide improved electrical isolation.

    [0029] Generally speaking, radial stubs are used as open-circuit ¼ wave terminations in RF circuits and have enhanced broadband frequency response. In a conventional PCB 2 layer substrate, a radial stub can be formed on the top layer as a microstripline component (i.e., a thin flat conductor which is parallel to a ground plane). However, the relatively low equivalent dielectric constant in this kind of PCB 2 layer substrate means that compact radial stubs are not possible for certain frequency bands. That is, in conventional PCB 2 layer substrates, package area can become the gating factor for the radial stub. The presently configured multilayer circuit board 108 allows for the radial stub 164 to be configured as a stripline component (i.e., a flat strip of metal which is sandwiched between two parallel ground planes) with a relatively compact design. The embedded capacitance material substantially increases the capacitance per unit area of the stripline components and this leads a very compact radial stub layout. For example a layout of 2 mm2 for the embedded component provides a capacitance of 100 pF, and this layout can be easily integrated inside a typical package outline of 10 mm x 7 mm (i.e., 70 mm2). With a standard substrate formed from an insulative pre-impregnated composite fiber material, the radial stub layout area needed to achieve 100 pF is 200 mm2, and this size component cannot be integrated within a 10 mm x 7 mm package outline.

    [0030] Referring to Fig. 7, an exemplary circuit topology is depicted, according to another embodiment. The circuit of Fig. 7 differs from the circuit of Fig. 4 with respect to the configuration of the bond wires 128. More particularly, the bond wires 128 are configured with two separate branches. A first branch 166 of the bond wires 128 is directly connected between the RF terminal of the transistor die 106 and a first bond pad 168, which may be provided by a first isolated portion of the first signal layer 136 in the manner previously discussed. The first bond pad 168 is connected to an output node of the multilayer circuit board 108 by a length of microstripline 174. A second branch 170 of the bond wires 128 is directly connected between the RF terminal of the transistor die 106 and a second bond pad 172, which may be provided by a second isolated portion of the first signal layer 136 that is electrically disconnected from the first bond pad 168. An insulated signal via 150 connects the second bond pad 172 to the radial stub 164.

    [0031] Referring Figs. 8 and 9, a physical layout of the semiconductor package of Fig. 8 is depicted. A set of the first bond pads 168 may be arranged in a similar manner as the bond pads 154 shown in Figs. 5 and 6. Another set of the second bond pads 172 may be disposed on either side of the first bond pads 168. That is, the first bond pads 168 may be disposed between the second bond pads 172. Optionally, a plurality of insulated path vias 158 that are electrically grounded may be disposed between the first bond pads 168 and the second bond pads 172 to provide increased electrical shielding between the two.

    [0032] According to an embodiment, the first branch 166 of the bond wires 128 extends in a first direction D1 between the transistor die 106 and the first bond pads 168. From the perspective of Fig. 8, the first direction D1 extends left to right, and represents a direction of the shortest path between the RF terminal 114 of the transistor die 106 and the first bond pads 168. The second branch 170 of the bond wires 128 extends in a second direction that is non-parallel to the first direction. That is, the second direction is disposed at an angle relative first direction. In the embodiment of Fig. 8, the second branch 170 of the bond wires 128 form an acute angle with the first branch 166 of the bond wires 128. This arrangement increases the separation distance between the first and second branches 176, 170 and consequently reduces the mutual inductance between the various bonding wires. As a result, parasitic effects are mitigated. Different orientations may be achieved, depending on the positioning of the bond pads 154.

    [0033] Referring to Fig. 10, an exemplary circuit topology is depicted, according to another embodiment. The circuit of Fig. 10 has a substantially similar topology to the circuit of Fig. 4, with the exception that an additional capacitor 178 is incorporated into the output matching network to improve the linearity of the system by providing a low frequency termination. Conventionally, a low frequency termination capacitor can be provided outside of the package using a discrete component. However, this arrangement suffers from the drawback that the parasitic inductance and capacitance of the external electrical connections (e.g., bond wires) to the additional capacitor degrade the bandwidth of the low frequency termination by as much as 100 MHz to 200 MHz. Preferably, the capacitor is disposed as close to the transistor as possible to mitigate these parasitic effects. Advantageously, the multilayer circuit board 108 design described herein allows for the additional capacitor 178 to be implemented as a discrete capacitor formed on or in the multilayer circuit board 108 very close to the transistor die 106. That is, the low frequency capacitor can incorporated into the device package. As a result, the bandwidth of the low frequency termination is improved.

    [0034] Referring Figs. 11 and 12, a physical layout of the semiconductor package of Fig. 10 is depicted. In the embodiment of Figs. 11 and 12, the additional capacitor 178 is implemented as a surface-mount capacitor, i.e., a discrete capacitor with lower facing terminals that directly contact a bond pad, and is bonded to the second side 118 of the multilayer circuit board 108. The multilayer circuit board includes 108 a third bond pad 180 which is formed by a third isolated portion of the first signal layer 136. The third bond pad 180 is electrically disconnected from the other bond pads 154. A positive electrode of the low frequency termination capacitor 178 is electrically connected to at least one of the embedded reactive components (i.e., the shunt inductor 162 and the radial stub 164 in the embodiment of Figs. 11-12) by an insulated signal via 150. The negative electrode of the low frequency termination capacitor 178 is connected to electrical ground by one of the path vias 158. Advantageously, the multilayer circuit board 108 described herein provides the circuit topology of Fig. 10 in a space efficient manner by providing the radial stub 164 embedded within the multilayer circuit board 108 while using overlapping surface area on the top surface of the multilayer circuit board 108 for the low frequency termination capacitor 178.

    [0035] In the embodiment of Fig. 10, the low frequency termination capacitor 178 is combined with the circuit and corresponding layouts described with reference to Figs. 4-6. However, this is just one example. Alternatively, the low frequency termination capacitor 178 could be combined with different configurations, such as the circuit and corresponding layouts described with reference to Figs. 7-9.

    [0036] Referring to Fig. 13, partial sectional view of a multilayer circuit board 108 is depicted, according to an embodiment. The multilayer circuit board 108 may be configured similarly as the multilayer circuit board described with reference to Figs. 11 and 12, with the exception that the low frequency termination capacitor 178 is disposed inside of the multilayer circuit board108 instead of on the upper surface. According to an embodiment, the low frequency termination capacitor 178 is an ultra-thin surface mount device. These devices can be embedded into the multilayer circuit board 108 during the fabrication process. More particularly, an ultra-thin surface mount device can be embedded in one or both of the embedded layers 144, 146, during the lamination process that forms these layers. Isolated sections of the signal and/or ground layers can be formed to provide bonding locations for the ultra-thin surface mount device. The insulated signal vias 150 and path vias 158 described herein can be used to connect these bonding locations with external bond pads.

    [0037] Spatially relative terms such as "under," "below," "lower," "over," "upper" and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as "first," "second," and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.

    [0038] As used herein, the terms "having," "containing," "including," "comprising" and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles "a," "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

    [0039] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention as defined by the claims.


    Claims

    1. A semiconductor package, comprising:

    a metal baseplate (100) having a die attach region (102) and a peripheral region (104);

    a transistor die (106) having a reference terminal (112) attached to the die attach region (102) and an RF terminal (114) facing away from the baseplate (100); and

    a multilayer circuit board (108) having a first side (116) attached to the peripheral region (104) and a second side (118) facing away from the baseplate (100), the multilayer circuit board (108) comprising:

    a first embedded electrically conductive layer (138) that is separated from the second side (118) by a first layer of composite fiber (144);

    a second embedded electrically conductive layer (140) that is separated from the first side (116) by a second layer of composite fiber (146); and

    an embedded dielectric layer (148) disposed between the first and second embedded electrically conductive layers (138, 140),

    wherein the embedded dielectric layer (148) has a higher dielectric constant than each of the first and second layers of composite fiber (144, 146).


     
    2. The semiconductor package of claim 1, wherein the multilayer circuit board comprises:

    a first electrically conductive signal layer (136) disposed at the second side (118);

    the first embedded electrically conductive layer (138) as a first electrically conductive ground layer (138) embedded in the multilayer circuit board (108);

    the second embedded electrically conductive layer (140) as a second electrically conductive signal layer (140) embedded in the multilayer circuit board (108); and

    a second electrically conductive ground layer (142) disposed at the first side (116);

    wherein:

    the first layer of composite fibre (144) separates the first signal layer (136) from the first ground layer (138);

    the second layer of composite fibre (146) separates the second signal layer (140) from the second ground layer (142);

    the embedded dielectric layer (148) separates the first ground layer (138) from the second signal layer (140); and

    the embedded dielectric layer (148) has a thickness which is less than the thickness of each of the first and second composite fiber layers (144, 146).


     
    3. The semiconductor package of claim 2, wherein the embedded dielectric layer (148) has a dielectric constant of between 4 and 30, and wherein the first and second composite fiber layers (144, 146) have a dielectric constant of 3.7 or less.
     
    4. The semiconductor package of claim 3, wherein the embedded dielectric layer (148) is formed from a polymer laminate material, and wherein the first and second composite fiber layers (144, 146) are formed from at least one of: FR-1, FR-2, FR-3, FR-4, FR-5, FR-6, G-10, CEM-1, CEM-2, CEM-3, CEM-4, CEM-5.
     
    5. The semiconductor package of claim 3, wherein the embedded dielectric layer (148) has a thickness of between 4 µm and 50 µm, and wherein the first and second composite fiber layers (144, 146) each have a thickness of at least 75 µm.
     
    6. The semiconductor package of claim 2, wherein the multilayer circuit board (108) further comprises:

    a first electrically conductive via (150) extending through the first composite fiber layer (144) and connected to a first bonding pad (156), the first bonding pad (156) being formed by an isolated portion of the first signal layer (136); and

    one or more embedded reactive components (C1) electrically connected to the first via (150), each of the one or more embedded reactive components comprising an isolated section of the second signal layer (140).


     
    7. The semiconductor package of claim 6, wherein the one or more embedded reactive components comprise a first capacitor (CI), wherein a positive electrode of the first capacitor is formed by a first isolated section of the second signal layer (140), and wherein a ground electrode of the first capacitor is formed by a first isolated section of the first ground layer (138).
     
    8. The semiconductor package of claim 7, wherein the first capacitor (C1) has a capacitance of at least 100 picoFarads.
     
    9. The semiconductor package of claim 6, wherein the one or more embedded reactive components comprise:

    a shunt inductance (162) connected to the first electrically conductive via (150) and comprising a linear strip of the second signal layer (140); and

    an open-circuit radial stub (164) connected to the shunt inductance (162) and comprising a radially shaped section of the second signal layer (140).


     
    10. The semiconductor package of claim 9, further comprising:
    a first set (166) of bond wires (128) directly connected between the RF terminal (114) and the first bonding pad (154, 168).
     
    11. The semiconductor package of claim 10, further comprising:

    a second bonding pad (172) formed by an isolated portion of the first signal layer (136); and

    a second set (170) of bond wires (128) directly connected between the RF terminal (114) and the second bonding pad (172),

    wherein the first set (166) of bond wires (128) extends in a first direction between the RF terminal (114) and the first bonding pad (168),

    wherein the second set (170) of bond wires (128) extends in a second direction between the RF terminal (114) and the second bonding pad (172), and

    wherein the second direction is non-parallel to the first direction.


     
    12. The semiconductor package of claim 6, further comprising a discrete capacitor (178) formed on or in the baseplate (100) and connected to the one or more embedded reactive components (C1, L1).
     
    13. The semiconductor package of claim 12, wherein the multilayer circuit board (108) comprises a third bonding pad (180) formed by an isolated portion of the first signal layer (136), wherein the discrete capacitor (178) is a surface-mount capacitor that is directly mounted on the third bonding pad (180), and wherein the third bonding pad (180) is electrically connected to the one or more embedded reactive components (C1, L1) by a second electrically conductive via extending through the first composite fiber layer (144).
     
    14. A semiconductor assembly, comprising:

    the semiconductor package of any of claims 1-13;

    a global printed circuit board (122); and

    wherein the multilayer circuit board (108) connects the RF terminal (114) of the transistor die (106) to the global printed circuit board (122).


     


    Ansprüche

    1. Halbleiter-Package, umfassend:

    Metallgrundplatte (100) mit einem Die-Befestigungsbereich (102) und einem peripheren Bereich (104);

    Transistor-Die (106) mit einem Referenzanschluss (112), der am Die-Befestigungsbereich (102) befestigt ist, und einem HF-Anschluss (114), der von der Grundplatte (100) weg weist; und

    mehrschichtige Leiterplatte (108) mit einer ersten Seite (116), die am peripheren Bereich (104) befestigt ist, und einer zweiten Seite (118), die von der Grundplatte (100) weg weist, wobei die mehrschichtige Leiterplatte (108) umfasst:

    erste eingebettete elektrisch leitfähige Schicht (138), die von der zweiten Seite (118) durch eine erste Schicht aus Verbundfaser (144) getrennt ist;

    zweite eingebettete elektrisch leitfähige Schicht (140), die von der ersten Seite (116) durch eine zweite Schicht aus Verbundfaser (146) getrennt ist; und

    eingebettete dielektrische Schicht (148), die zwischen der ersten und der zweiten eingebetteten elektrisch leitfähigen Schicht (138, 140) eingerichtet ist,

    wobei die eingebettete dielektrische Schicht (148) eine höhere Dielektrizitätskonstante aufweist als jede von der ersten und zweiten Schicht aus Verbundfaser (144, 146).


     
    2. Halbleiter-Package nach Anspruch 1, wobei die mehrschichtige Leiterplatte umfasst:

    erste elektrisch leitfähige Signalschicht (136), die auf der zweiten Seite (118) eingerichtet ist;

    die erste eingebettete elektrisch leitfähige Schicht (138) als eine erste elektrisch leitfähige Masseschicht (138), die in die mehrschichtige Leiterplatte (108) eingebettet ist;

    die zweite eingebettete elektrisch leitfähige Schicht (140) als eine zweite elektrisch leitfähige Signalschicht (140), die in die mehrschichtige Leiterplatte (108) eingebettet ist; und

    zweite elektrisch leitfähige Masseschicht (142), die an der ersten Seite (116) eingerichtet ist;

    wobei:

    die erste Schicht aus Verbundfaser (144) die erste Signalschicht (136) von der ersten Masseschicht (138) trennt;

    die zweite Schicht aus Verbundfaser (146) die zweite Signalschicht (140) von der zweiten Masseschicht (142) trennt;

    die eingebettete dielektrische Schicht (148) die erste Masseschicht (138) von der zweiten Signalschicht (140) trennt; und

    die eingebettete dielektrische Schicht (148) eine Dicke aufweist, die geringer ist als die Dicke jeder von der ersten und zweiten Verbundfaserschicht (144, 146).


     
    3. Halbleiter-Package nach Anspruch 2, wobei die eingebettete dielektrische Schicht (148) eine Dielektrizitätskonstante zwischen 4 und 30 aufweist, und wobei die erste und die zweite Verbundfaserschicht (144, 146) eine Dielektrizitätskonstante von 3,7 oder weniger aufweist.
     
    4. Halbleiter-Package nach Anspruch 3, wobei die eingebettete dielektrische Schicht (148) aus einem Polymerlaminatmaterial gebildet ist, und wobei die erste und die zweite Verbundfaserschicht (144, 146) aus mindestens einem der Folgenden gebildet sind: FR-1, FR-2, FR-3, FR-4, FR-5, FR-6, G-10, CEM-1, CEM-2, CEM-3, CEM-4, CEM-5.
     
    5. Halbleiter-Package nach Anspruch 3, wobei die eingebettete dielektrische Schicht (148) eine Dicke zwischen 4 µm und 50 µm aufweist, und wobei die erste und die zweite Verbundfaserschicht (144, 146) jeweils eine Dicke von mindestens 75 µm aufweisen.
     
    6. Halbleiter-Package nach Anspruch 2, wobei die mehrschichtige Leiterplatte (108) ferner umfasst:

    erste elektrisch leitfähige Durchkontaktierung (150), die sich durch die erste Verbundfaserschicht (144) erstreckt und mit einem ersten Bondpad (156) verbunden ist, wobei das erste Bondpad (156) durch einen isolierten Abschnitt der ersten Signalschicht (136) gebildet wird; und

    eine oder mehrere eingebettete reaktive Komponenten (Cl), die elektrisch mit der ersten Durchkontaktierung (150) verbunden sind, wobei jede der einen oder der mehreren eingebetteten reaktiven Komponenten einen isolierten Abschnitt der zweiten Signalschicht (140) umfasst.


     
    7. Halbleiter-Package nach Anspruch 6, wobei die eine oder die mehreren eingebetteten reaktiven Komponenten einen ersten Kondensator (C1) umfassen, wobei eine positive Elektrode des ersten Kondensators durch einen ersten isolierten Abschnitt der zweiten Signalschicht (140) gebildet wird, und wobei eine Masseelektrode des ersten Kondensators durch einen ersten isolierten Abschnitt der ersten Masseschicht (138) gebildet wird.
     
    8. Halbleiter-Package nach Anspruch 7, wobei der erste Kondensator (C1) eine Kapazität von mindestens 100 Pikofarad aufweist.
     
    9. Halbleiter-Package nach Anspruch 6, wobei die eine oder die mehreren eingebetteten reaktiven Komponenten umfassen:

    Shunt-Induktivität (162), die mit der ersten elektrisch leitenden Durchkontaktierung (150) verbunden ist und einen linearen Streifen der zweiten Signalschicht (140) umfasst; und

    offenen radialen Stub (164), der mit der Shunt-Induktivität (162) verbunden ist und einen radial geformten Abschnitt der zweiten Signalschicht (140) umfasst.


     
    10. Halbleiter-Package nach Anspruch 9, ferner umfassend:
    ersten Satz (166) von Bonddrähten (128), die direkt zwischen dem HF-Anschluss (114) und dem ersten Bondpad (154, 168) verbunden sind.
     
    11. Halbleiter-Package nach Anspruch 10, ferner umfassend:

    zweites Bondpad (172), das durch einen isolierten Abschnitt der ersten Signalschicht (136) gebildet wird; und

    zweiten Satz (170) von Bonddrähten (128), die direkt zwischen dem HF-Anschluss (114) und dem zweiten Bondpad (172) verbunden sind,

    wobei sich der erste Satz (166) von Bonddrähten (128) in einer ersten Richtung zwischen dem HF-Anschluss (114) und dem ersten Bondpad (168) erstreckt,

    wobei sich der zweite Satz (170) von Bonddrähten (128) in einer zweiten Richtung zwischen dem HF-Anschluss (114) und dem zweiten Bondpad (172) erstreckt, und

    wobei die zweite Richtung nicht parallel zur ersten Richtung ist.


     
    12. Halbleiter-Package nach Anspruch 6, ferner umfassend einen diskreten Kondensator (178), der auf oder in der Grundplatte (100) ausgebildet und mit der einen oder den mehreren eingebetteten reaktiven Komponenten (C1, L1) verbunden ist.
     
    13. Halbleiter-Package nach Anspruch 12, wobei die mehrschichtige Leiterplatte (108) ein drittes Bondpad (180) umfasst, das durch einen isolierten Abschnitt der ersten Signalschicht (136) gebildet wird, wobei der diskrete Kondensator (178) ein oberflächenmontierter Kondensator ist, der direkt auf dem dritten Bondpad (180) montiert ist, und wobei das dritte Bondpad (180) elektrisch mit der einen oder den mehreren eingebetteten reaktiven Komponenten (C1, L1) durch eine zweite elektrisch leitfähige Durchkontaktierung verbunden ist, die sich durch die erste Verbundfaserschicht (144) erstreckt.
     
    14. Halbleiteranordnung, umfassend:

    Halbleiter-Package nach einem der Ansprüche 1-13;

    globale Leiterplatte (122); und

    wobei die mehrschichtige Leiterplatte (108) den HF-Anschluss (114) des Transistor-Dies (106) mit der globalen Leiterplatte (122) verbindet.


     


    Revendications

    1. Boîtier semi-conducteur, comprenant :

    une plaque de base métallique (100) ayant une région de fixation de puce (102) et une région périphérique (104) ;

    une puce à transistors (106) ayant une borne de référence (112) fixée à la région de fixation de puce (102) et une borne RF (114) tournant le dos à la plaque de base (100) ; et

    une carte de circuit multicouche (108) ayant un premier côté (116) fixé à la région périphérique (104) et un deuxième côté (118) tournant le dos à la plaque de base (100), la carte de circuit multicouche (108) comprenant :

    une première couche électriquement conductrice intégrée (138) qui est séparée du deuxième côté (118) par une première couche de fibre composite (144) ;

    une deuxième couche électriquement conductrice intégrée (140) qui est séparée du premier côté (116) par une deuxième couche de fibre composite (146) ; et

    une couche diélectrique intégrée (148) disposée entre les première et deuxième couches électriquement conductrices intégrées (138, 140),

    dans lequel la couche diélectrique intégrée (148) a une plus forte constante diélectrique que chacune des première et deuxième couches de fibre composite (144, 146) .


     
    2. Boîtier semi-conducteur de la revendication 1, dans lequel la carte de circuit multicouche comprend :

    une première couche de signal électriquement conductrice (136) disposée du deuxième côté (118) ;

    la première couche électriquement conductrice intégrée (138) en tant que première couche de masse électriquement conductrice (138) intégrée dans la carte de circuit multicouche (108) ;

    la deuxième couche électriquement conductrice intégrée (140) en tant que deuxième couche de signal électriquement conductrice (140) intégrée dans la carte de circuit multicouche (108) ; et

    une deuxième couche de masse électriquement conductrice (142) disposée du premier côté (116) ;

    dans lequel :

    la première couche de fibre composite (144) sépare la première couche de signal (136) de la première couche de masse (138) ;

    la deuxième couche de fibre composite (146) sépare la deuxième couche de signal (140) de la deuxième couche de masse (142) ;

    la couche diélectrique intégrée (148) sépare la première couche de masse (138) de la deuxième couche de signal (140) ; et

    la couche diélectrique intégrée (148) a une épaisseur qui est inférieure à l'épaisseur de chacune des première et deuxième couches de fibre composite (144, 146).


     
    3. Boîtier semi-conducteur de la revendication 2, dans lequel la couche diélectrique intégrée (148) a une constante diélectrique comprise entre 4 et 30, et dans lequel les première et deuxième couches de fibre composite (144, 146) ont une constante diélectrique de 3,7 ou moins.
     
    4. Boîtier semi-conducteur de la revendication 3, dans lequel la couche diélectrique intégrée (148) est formée à partir d'un matériau polymère stratifié, et dans lequel les première et deuxième couches de fibre composite (144, 146) sont formées à partir d'au moins un élément parmi : FR-1, FR-2, FR-3, FR-4, FR-5, FR-6, G-10, CEM-1, CEM-2, CEM-3, CEM-4, CEM-5.
     
    5. Boîtier semi-conducteur de la revendication 3, dans lequel la couche diélectrique intégrée (148) a une épaisseur comprise entre 4 µm et 50 µm, et dans lequel les première et deuxième couches de fibre composite (144, 146) ont chacune une épaisseur d'au moins 75 µm.
     
    6. Boîtier semi-conducteur de la revendication 2, dans lequel la carte de circuit multicouche (108) comprend en outre :

    un premier trou d'interconnexion électriquement conducteur (150) s'étendant à travers la première couche de fibre composite (144) et raccordé à un premier plot de connexion (156), le premier plot de connexion (156) étant formé par une partie isolée de la première couche de signal (136) ; et

    un ou plusieurs composants réactifs intégrés (C1) raccordés électriquement au premier trou d'interconnexion (150), le ou chacun des composants réactifs intégrés comprenant une section isolée de la deuxième couche de signal (140).


     
    7. Boîtier semi-conducteur de la revendication 6, dans lequel le ou les composants réactifs intégrés comprennent un premier condensateur (C1), dans lequel une électrode positive du premier condensateur est formée par une première section isolée de la deuxième couche de signal (140), et dans lequel une électrode de masse du premier condensateur est formée par une première section isolée de la première couche de masse (138) .
     
    8. Boîtier semi-conducteur de la revendication 7, dans lequel le premier condensateur (C1) a une capacité d'au moins 100 picofarads.
     
    9. Boîtier semi-conducteur de la revendication 6, dans lequel le ou les composants réactifs intégrés comprennent :

    une inductance de shunt (162) raccordée au premier trou d'interconnexion électriquement conducteur (150) et comprenant une bande linéaire de la deuxième couche de signal (140) ; et

    un bras de réactance radial en circuit ouvert (164) raccordé à l'inductance de shunt (162) et comprenant une section formée radialement de la deuxième couche de signal (140).


     
    10. Boîtier semi-conducteur de la revendication 9, comprenant en outre :
    un premier ensemble (166) de fils de connexion (128) directement branchés entre la borne RF (114) et le premier plot de connexion (154, 168).
     
    11. Boîtier semi-conducteur de la revendication 10, comprenant en outre :

    un deuxième plot de connexion (172) formé par une partie isolée de la première couche de signal (136) ; et

    un deuxième ensemble (170) de fils de connexion (128) directement branchés entre la borne RF (114) et le deuxième plot de connexion (172),

    dans lequel le premier ensemble (166) de fils de connexion (128) s'étend dans une première direction entre la borne RF (114) et le premier plot de connexion (168),

    dans lequel le deuxième ensemble (170) de fils de connexion (128) s'étend dans une deuxième direction entre la borne RF (114) et le deuxième plot de connexion (172), et

    dans lequel la deuxième direction n'est pas parallèle à la première direction.


     
    12. Boîtier semi-conducteur de la revendication 6, comprenant en outre un condensateur discret (178) formé sur ou dans la plaque de base (100) et raccordé au(x) composant(s) réactif(s) intégré(s) (C1, L1).
     
    13. Boîtier semi-conducteur de la revendication 12, dans lequel la carte de circuit multicouche (108) comprend un troisième plot de connexion (180) formé par une partie isolée de la première couche de signal (136), dans lequel le condensateur discret (178) est un condensateur pour montage en surface qui est directement monté sur le troisième plot de connexion (180), et dans lequel le troisième plot de connexion (180) est raccordé électriquement au(x) composant(s) réactif(s) intégré(s) (C1, L1) par un deuxième trou d'interconnexion électriquement conducteur s'étendant à travers la première couche de fibre composite (144).
     
    14. Ensemble semi-conducteur, comprenant :

    le boîtier semi-conducteur de l'une quelconque des revendications 1 à 13 ;

    une carte de circuit imprimé globale (122) ; et

    dans lequel la carte de circuit multicouche (108) raccorde la borne RF (114) de la puce à transistors (106) à la carte de circuit imprimé globale (122).


     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description